8 BIT MICRO CONTROLLER MB89051 Series HARDWARE ......Series products original ASIC (Application Specific IC) compatible, 8-bit one-chip microcontrollers. Their application is wide-ranging

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

F2MC-8L8 BIT MICRO CONTROLLER

MB89051 SeriesHARDWARE MANUAL

CM25-10148-XE

FUJITSU LIMITED

F2MC-8L8 BIT MICRO CONTROLLER

MB89051 SeriesHARDWARE MANUAL

PREFACE

Purpose of this document and intended reader

The MB89051 Series products were developed as the general-purpose version of the F2MC-8LSeries products original ASIC (Application Specific IC) compatible, 8-bit one-chipmicrocontrollers. Their application is wide-ranging from consumer equipment to industrialequipment.

This manual explains the functions and operations of the MB89051 Series Microcontrollers forengineers engaged in product development by actually using these microcontrollers. Please readthrough this manual.

For more information on each instruction, refer to the "F2MC-8L Programming Manual".

Trademarks

F2MC, the abbreviation of FUJITSU Flexible Microcontroller, is a registered trademark of FujitsuLimited.

Other system and product names in this manual are trademarks of respective companies ororganizations.

The symbols TM and (R) are sometimes omitted in the text.

Organization of this documentThis manual contains the following seventeen chapters and an appendix.

Chapter 1 Overview

This chapter describes the features and main specifications of the MB89051 series.

Chapter 2 Precautions when Handling Devices

This chapter explains handling precautions for USB general-purpose one-chipmicrocontrollers.

Chapter 3 CPU

This chapter explains the functions and operations of the CPU.

Chapter 4 I/O port

This chapter describes the functions and operations of I/O ports.

Chapter 5 Time-base Timer

This chapter explains the functions and operations of the time-base timer.

Chapter 6 Watchdog Timer

This chapter explains the functions and operations of the watchdog timer.

Chapter 7 2-ch 8-bit PWM Timer

This chapter explains the functions and operations of the 2-ch 8-bit PWM timer.

Chapter 8 External Interrupt Circuit

This chapter explains the functions and operations of the external interruption circuit (level).

Chapter 9 USB Hub

This chapter explains the functions and operations of the USB hub circuit.

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Chapter 10 USB Function

This chapter explains the functions and operations of the USB function circuit.

Chapter 11 UART/SIO

This chapter explains the functions and operations of the CPU.

Chapter 12 8-bit Serial I/O

This chapter describes the functions and operation of the 8-bit serial I/O.

Chapter 13 I2C

This chapter explains the functions and operations of the I2C bus interface.

Chapter 14 Clock Output Function

This chapter explains the clock output function and operation.

Chapter 15 Pull-up Option

This chapter explains pull-up options.

Chapter 16 Flash Memory

This chapter explains the functions and operations of flash memory.

Chapter 17 Connection Examples for MB89F051 Serial Writing

This chapter explains connection examples for serial writing.

APPENDIX

The appendices include an I/O map and a list of instructions.

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Copyright© 2004 FUJITSU LIMITED All rights reserved

• The contents of this document are subject to change without notice. Customers are advised to consult withFUJITSU sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presentedsolely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device;FUJITSU does not warrant proper operation of the device with respect to use based on such information. When youdevelop equipment incorporating the device based on such information, you must assume any responsibility arisingout of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of theuse of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not beconstrued as license of the use or exercise of any intellectual property right, such as patent right or copyright, orany other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party'sintellectual property right or other right by using such information. FUJITSU assumes no liability for anyinfringement of the intellectual property rights or other rights of third parties which would result from the use ofinformation contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for generaluse, including without limitation, ordinary industrial use, general office use, personal use, and household use, butare not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangersthat, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly todeath, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch controlin weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificialsatellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damagesarising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or lossfrom such failures by incorporating safety design measures into your facility and equipment such as redundancy,fire protection, and prevention of over-current levels and other abnormal operating conditions.

• If any products described in this document represent goods or technologies subject to certain restrictions on exportunder the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government willbe required for export of those products from Japan.

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CONTENTS

CHAPTER 1 Overview ..................................................................................................... 11.1 Feature of MB89051 series ................................................................................................................ 21.2 Product lineup of the MB89051 series ................................................................................................ 51.3 Differences between models .............................................................................................................. 61.4 Block diagram of the MB89051 series ................................................................................................ 71.5 Pin Assignment ................................................................................................................................... 81.6 Package Dimension ............................................................................................................................ 91.7 Pin Description .................................................................................................................................. 101.8 I/O Circuit .......................................................................................................................................... 13

CHAPTER 2 Precautions when Handling Devices ..................................................... 172.1 Precautions when Handling Devices ................................................................................................ 18

CHAPTER 3 CPU ........................................................................................................... 193.1 Memory Space .................................................................................................................................. 20

3.1.1 Area for specific usage ................................................................................................................ 223.1.2 Location of 16-bit data in memory ............................................................................................... 23

3.2 Dedicated Registers ......................................................................................................................... 243.2.1 Condition code register (CCR) .................................................................................................... 263.2.2 Register bank pointer (RP) .......................................................................................................... 29

3.3 General-purpose Register ................................................................................................................ 303.4 Interrupt ............................................................................................................................................ 32

3.4.1 Interrupt level setting registers (ILR1, 2, 3, 4) ............................................................................. 333.4.2 Interrupt processing ..................................................................................................................... 353.4.3 Multiple interrupts ........................................................................................................................ 373.4.4 Interrupt processing time ............................................................................................................. 383.4.5 Stack operation during interrupt handling .................................................................................... 393.4.6 Interrupt handling stack area ....................................................................................................... 40

3.5 Reset ................................................................................................................................................ 413.5.1 External Reset Pin ....................................................................................................................... 433.5.2 Reset Operation .......................................................................................................................... 443.5.3 State of Each Pin at Reset .......................................................................................................... 46

3.6 Clock ................................................................................................................................................. 473.6.1 Clock generation block ................................................................................................................ 493.6.2 Clock control block ...................................................................................................................... 503.6.3 System clock control register (SYCC) ........................................................................................ 523.6.4 Clock Mode .................................................................................................................................. 543.6.5 Oscillation Stabilization Wait Time .............................................................................................. 55

3.7 Standby mode (low power consumption) .......................................................................................... 573.7.1 Operation status in standby mode ............................................................................................... 583.7.2 Sleep mode ................................................................................................................................. 593.7.3 Stop mode ................................................................................................................................... 603.7.4 Standby control register (STBC) .................................................................................................. 61

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3.7.5 State Transition Diagram ............................................................................................................. 633.7.6 Notes on using the standby mode ............................................................................................... 65

3.8 Memory Access Mode ...................................................................................................................... 67

CHAPTER 4 I/O Port ...................................................................................................... 694.1 Overview of I/O Ports ........................................................................................................................ 704.2 Port 0 ................................................................................................................................................ 72

4.2.1 Port-0 registers (PDR0,DDR0) ................................................................................................... 74Table 4.2-3R/W: Read/Write ...................................................................................................................... 744.2.2 Operation of port 0 ....................................................................................................................... 75

4.3 Port 1 ................................................................................................................................................ 774.3.1 Registers for Port 1 (PDR1, DDR1) ............................................................................................. 794.3.2 Operation of Port 1 ...................................................................................................................... 80




4.7 Port 5 ................................................................................................................................................ 994.7.1 Port-5 registers (PDR5,DDR5) ................................................................................................. 1014.7.2 Operation of Port 5 .................................................................................................................... 102

4.8 I/O Port Programming Example ...................................................................................................... 104

CHAPTER 5 Time-base Timer .................................................................................... 1055.1 Overview of Time-base Timer ......................................................................................................... 1065.2 Configuration of Time-base Timer .................................................................................................. 1085.3 Time-base timer control register (TBTC) ........................................................................................ 1105.4 Interrupt of Time-base Timer .......................................................................................................... 1125.5 Explanation of Operations of Time-base Timer Functions .............................................................. 1135.6 Precautions when Using Time-base Timer ..................................................................................... 1155.7 Program Example of Time-base Timer ........................................................................................... 116

CHAPTER 6 Watchdog Timer ..................................................................................... 1176.1 Overview of Watchdog Timer ......................................................................................................... 1186.2 Configuration of Watchdog Timer ................................................................................................... 1196.3 Watchdog control register (WDTC) ................................................................................................. 1206.4 Explanation of Operations of Watchdog Timer Functions .............................................................. 1216.5 Precautions when Using Watchdog Timer ...................................................................................... 1226.6 Program Examples of Watchdog Timer .......................................................................................... 123

CHAPTER 7 2-ch 8-bit PWM Timer ............................................................................ 1257.1 Overview of 2-ch 8-bit PWM Timers (interval timer function) ......................................................... 1267.2 Overview of 2-ch 8-bit PWM Timers (PWM timer function) ............................................................ 129

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7.3 Configuration of 8-bit PPG Timer .................................................................................................... 1327.4 Pins of 2-ch 8-bit PWM Timer ......................................................................................................... 1347.5 Registers of 2-ch 8-bit PWM Timers ............................................................................................... 136

7.5.1 PWM Control Register 1(CNTR1) ............................................................................................ 1377.5.2 PWM Control Register 2(CNTR2) ............................................................................................ 1397.5.3 PWM Control Register 3(CNTR3) ............................................................................................ 1417.5.4 PWM Compare Register 1(COMR1) ........................................................................................ 1437.5.5 PWM Compare Register 2(COMR2) ........................................................................................ 145

7.6 Interrupts of 2-ch 8-bit PWM Timer ................................................................................................. 1477.7 Explanation of Operations of the Interval Timer Functions ............................................................. 1487.8 Explanation of the 8-bit PWM Mode Operation .............................................................................. 1507.9 Explanation of the 7-bit PWM Mode Operation .............................................................................. 1527.10 Explanation of CH12 PWM mode operation ................................................................................... 1547.11 Explanation of the Operation of the Prescaler of the 2-ch 8-bit PWM Timer .................................. 1567.12 States in Each Mode During Operation of 2-ch 8-bit PWM Timer .................................................. 1577.13 Precautions when Using 2-ch 8-bit PPG Timer .............................................................................. 1597.14 Program Example for 2-ch 8-bit PWM Timers (interval function) ................................................... 1607.15 Programming Example of the 2-ch 8-bit PWM Timer (PWM Timer Function) ................................ 164

CHAPTER 8 External Interrupt Circuit (level) ........................................................... 1678.1 Overview of External interrupt circuit (Level) .................................................................................. 1688.2 Configuration of external interrupt circuit ........................................................................................ 1698.3 Pins of external interrupt circuit ...................................................................................................... 1708.4 Register for external interrupt circuit ............................................................................................... 172

8.4.1 External interrupt control register (EIE) .................................................................................... 1738.4.2 External interrupt flag register (EIF) ......................................................................................... 175

8.5 Interrupt of external interrupt circuit ................................................................................................ 1768.6 Operation of external interrupt circuit .............................................................................................. 1778.7 Sample program for external interrupt circuit .................................................................................. 178

CHAPTER 9 USB Hub ................................................................................................. 1799.1 Overview of USB hub ..................................................................................................................... 1809.2 Configuration of USB hub ............................................................................................................... 1819.3 Pins in USB hub .............................................................................................................................. 1839.4 Register for a USB hub ................................................................................................................... 185

9.4.1 USB hub mode register (HMDR) ............................................................................................... 1869.4.2 Hub descriptor register (HDSR1, 2, 3, 4) ................................................................................... 1889.4.3 Hub status register (HSTR) ....................................................................................................... 1919.4.4 Over-current control register (OCCR) ........................................................................................ 1939.4.5 Descriptor ROM Address Register (DADR) ............................................................................... 1959.4.6 ROM setting for the standard descriptors supported by the hub ............................................... 196

9.5 Interrupt of USB hub ....................................................................................................................... 1989.6 Descriptor ....................................................................................................................................... 1999.7 Functional descriptions of USB hub ................................................................................................ 202

CHAPTER 10 USB Function ......................................................................................... 20510.1 Overview of the USB Function ........................................................................................................ 206

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10.2 Configuration of the USB Function Circuit ...................................................................................... 20710.3 USB Function Circuit Register ........................................................................................................ 209

10.3.1 USB Reset Mode Register (UMDR) .......................................................................................... 21410.3.2 DMA Base Address Register (DBAR) ....................................................................................... 21610.3.3 Transfer data count registers (TDCR0 to 3) ............................................................................. 21810.3.4 USB control register (UCTR) .................................................................................................... 22010.3.5 USB status register 1(USTR1) ................................................................................................. 22110.3.6 USB status register 2 (USTR2) ................................................................................................ 22410.3.7 USB Interruption Mask Register (UMSKR) ................................................................................ 22610.3.8 USB Frame Status Register (UFRMR) ...................................................................................... 22810.3.9 EndPoint Enable Register (EPER) ............................................................................................ 22910.3.10 EndPoint Setup Register (EPBR0,EPBRx1,x2) ........................................................................ 23010.3.11 Pull-up Control Register for USB (USBPC, USBP) ................................................................... 234

10.4 USB Function Interruptions ............................................................................................................. 23610.5 Function Description-USB Function ................................................................................................ 23810.6 Operation of the USB Function ....................................................................................................... 239

10.6.1 Each register operation when command responds ................................................................... 24210.6.2 Suspend function ....................................................................................................................... 24610.6.3 Wake-up function ....................................................................................................................... 247

CHAPTER 11 UART/SIO ................................................................................................ 24911.1 Overview of UART/SIO ................................................................................................................... 25011.2 Configuration of UART/SIO ............................................................................................................ 25111.3 UART/SIO pins ............................................................................................................................... 25311.4 Register of UART/SIO .................................................................................................................... 255

11.4.1 Serial Mode Control Register 1 (SMC1) .................................................................................... 25611.4.2 Serial Mode Control Register 2 (SMC2) ................................................................................... 25811.4.3 Serial Clock Switching Register (SCS) ...................................................................................... 26011.4.4 Serial Status and Data Register (SSD) ..................................................................................... 26111.4.5 Serial Input Data Register (SIDR) ............................................................................................. 26311.4.6 Serial Output Data Register (SODR) ......................................................................................... 26411.4.7 Serial Rate Control Register (SRC) ........................................................................................... 265

11.5 UART/SIO interrupt ......................................................................................................................... 26611.6 Explanation of Operation of UART/SIO .......................................................................................... 26711.7 Explanation of operating mode 0 .................................................................................................... 26811.8 Explanation of operation mode 1 .................................................................................................... 274

CHAPTER 12 8-bit Serial I/O ......................................................................................... 28112.1 Overview of 8-Bit Serial I/O ............................................................................................................ 28212.2 Configuration of 8-Bit Serial I/O ...................................................................................................... 28312.3 Pin of 8-Bit Serial I/O ...................................................................................................................... 28512.4 Registers of 8-Bit Serial I/O ............................................................................................................ 288

12.4.1 Serial mode register 1/2 (SMR1/SMR2) ................................................................................... 28912.4.2 Serial data register 1/2 (SDR1/SDR2) ...................................................................................... 292

12.5 8-Bit Serial I/O Interrupt .................................................................................................................. 29312.6 Explanation of Operations of Serial Output Functions .................................................................... 29412.7 Explanation of Operations of Serial Input Functions ....................................................................... 296

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12.8 Status under each mode during 8-bit serial I/O operation .............................................................. 29812.9 Notes on Using 8-Bit Serial I/O ....................................................................................................... 30112.10 Example of 8-Bit Serial I/O Connection .......................................................................................... 30312.11 Program Example for 8-Bit Serial I/O ............................................................................................. 305

CHAPTER 13 I2C ............................................................................................................ 30913.1 I2C Interface Outline ....................................................................................................................... 31013.2 I2C Interface Configuration ............................................................................................................. 31113.3 I2C Interface Terminal ..................................................................................................................... 31413.4 I2C Interface Register ..................................................................................................................... 315

13.4.1 I2C bus status register (IBSR) ................................................................................................... 31613.4.2 I2C bus control register (IBCR) .................................................................................................. 31813.4.3 I2C clock control register (ICCR) ............................................................................................... 32113.4.4 I2C address register (IADR) ....................................................................................................... 32313.4.5 I2C data register (IDAR) ............................................................................................................ 324

13.5 I2C Interface Interruption ................................................................................................................ 32513.6 I2C Interface Operation Explanation ............................................................................................... 32713.7 Instructions for use of the I2C interface .......................................................................................... 33013.8 I2C Interface Program Example ...................................................................................................... 331

CHAPTER 14 Clock Output Function .......................................................................... 33314.1 Overview of clock output ................................................................................................................. 33414.2 Pins of clock output (CLK1, CLK2) ................................................................................................. 33514.3 Clock output registers ..................................................................................................................... 336

CHAPTER 15 Pull-up Option ........................................................................................ 33715.1 Pull-up option outline ...................................................................................................................... 33815.2 Pull-up option setting register ........................................................................................................ 339

CHAPTER 16 Flash Memory ......................................................................................... 34116.1 Flash memory outline ..................................................................................................................... 34216.2 Sector configuration for flash memory ............................................................................................ 34316.3 Flash Memory Control Status Register (FMCS) ............................................................................. 34416.4 Flash memory auto algorithm start-up method ............................................................................... 34616.5 Check the Execution State of Automatic Algorithm ........................................................................ 347

16.5.1 Data polling flag (DQ7) .............................................................................................................. 34816.5.2 Toggle bit flag (DQ6) ................................................................................................................. 34916.5.3 Timing limit over flag (DQ5) ....................................................................................................... 35016.5.4 Sector erasing timer flag (DQ3) ................................................................................................. 35116.5.5 Toggle bit 2 flag (DQ2) .............................................................................................................. 352

16.6 Details of Programming/Erasing Flash Memory ............................................................................. 35316.6.1 Flash memory reading/reset status ........................................................................................... 35416.6.2 Programming of Flash memory ................................................................................................. 35516.6.3 All data deletion of flash memory (chip deletion) ....................................................................... 35716.6.4 Arbitrary data deletion of flash memory (sector deletion) .......................................................... 35816.6.5 Suspension of Flash memory sector erase ............................................................................... 36016.6.6 Resumption of Flash memory sector erase ............................................................................... 361

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16.7 Notes on using Flash memory ........................................................................................................ 362

CHAPTER 17 Connection Examples for MB89F051 Serial Writing ........................... 36317.1 Basic configuration for the MB89F051 serial writing connection .................................................... 36417.2 Connection example for serial writing (when user power is used) .................................................. 36717.3 Minimum connection example with the flash micon programmer (when user power is used): ....... 369

APPENDIX ......................................................................................................................... 371APPENDIX A I/O Map ................................................................................................................................ 372APPENDIX B Overview of Instructions ....................................................................................................... 376

B.1 Addressing ..................................................................................................................................... 378B.2 Special instruction .......................................................................................................................... 382B.3 Bit manipulation instructions (SETB,CLRB) .................................................................................. 385B.4 F2MC-8L Instruction List ................................................................................................................ 386B.5 Instruction Map ............................................................................................................................... 391

APPENDIX C MB89051series pin status .................................................................................................... 392

INDEX ................................................................................................................................. 399

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CHAPTER 1Overview

This chapter describes the features and basic specifications of MB89051 series.

1.1 Feature of MB89051 series

1.2 Product lineup of the MB89051 series

1.3 Differences between models

1.4 Block diagram of the MB89051 series

1.5 Pin Assignment

1.6 Package Dimension

1.7 Pin Description

1.8 I/O Circuit

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CHAPTER 1 Overview

1.1 Feature of MB89051 series

The MB89051 Series of general-purpose one-chip microcontrollers with a compact instruction set come with a diverse range of internal peripheral functions including PLL clock control, timers, serial interface, PWM timer, USB hub function and USB function. The USB hub function, in particular, supports five down ports (of which one port is fixed to an internal function), allowing them to interface with other USB devices. The microcontrollers also contain one USB function channel to support full speed mode.

Features

Packages

• 64-pin LQFP package (0.65 mm pitch)

High-speed operation at low voltage

• Minimum execution time: 0.33 µs (Automatically generates a 12 MHz main clock and a 48MHz USB interface synchronization clock with an externally supplied 6 MHz clock and theinternal PLL circuit.)

F2MC-8L CPU Core

• Instruction system optimized for controllers

- Multiplication and division instructions

- 16-bit operation

- Bit test branch instruction

- Bit manipulation instructions etc.

PLL clock control

• The internal PLL clock circuit allows the use of low-speed clocks with advantageous noisecharacteristics (externally supplied 6 MHz clock → internal 12 MHz system clock)

Timers

• 8-bit PWM timer (can be used as either an 8-bit PWM timer × 2 channels or a PPG timer × 1channel)

• Built-in 21-bit time-base timer

Internal USB transceiver circuit (operated in both full and low speed modes)

USB hub

• Based on USB Protocol Revision 1.0

• Downstream port: 5 channels (of which one is dedicated to an internal function)

2

3

CHAPTER 1 Overview

• Automatically responds to all USB protocols by hardware

• Descriptor configuration information is provided as ROM data for automatic respondinghardware (vendor ID and product ID)

Note

String data is not supported.

• Allows switching between BUS power supply and own power supply mode.

• Power supply to USB down ports is controlled on a port-by-port basis.

USB function

• Based on USB Protocol Revision 1.0

• Supports full speed mode: When using hubs

• Supports full and low speed modes: When using functions

• Up to four endpoints can be specified.

• Types of transfer supported: Control/Interrupt/Bulk/Isochronous transfer

• Built-in DMAC (Maps buffer for each endpoint into the internal RAM to allow direct access ofsend and receive data of each function to memory)

UART/SIO, SIO serial interface

• Built-in UART/SIO (selected by switching) ×1 channel

• Built-in SIO (supporting 3 V)×2ch

I2C interface *

• Phillips I2C bus specification

• Two-wire data transfer protocol specification

• Master and slave transmission/reception

*: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to

use, these components in an I2C system provided that the system conforms to the I2CStandard Specification as defined by Philips.

External interrupt

• External interruption (Level detection × 7 channels)

• Seven input channels are independent from one another and can be used to cancel the low-power consumption mode (L level detection function available)

Clock output function

• 12 MHz * and 6 MHz * clock output enabled (Dedicated, 3 V supported)

*: When the external supply clock is at 6 MHz

CHAPTER 1 Overview

Low power consumption (standby mode supported)

• Stop mode (Almost no current consumption occurs because oscillation stops.)

• Sleep mode (Mode for stopping the CPU)

General-purpose I/O port Max 41

• General-purpose I/O ports (CMOS): 37 (of which seven support 3 V)

• General-purpose I/O ports (Nch open drain): 4

Power supply

• Power supply voltage 3.3 V ± 0.3 V or 5.0 V ± 0.5 V

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CHAPTER 1 Overview

1.2 Product lineup of the MB89051 series

MB89051 series is available in two types. Table 1.2-1 shows the MB89051 Series model, CPUs and peripheral functions.

Product lineup of the MB89051 series

*:When the external supply clock is at 6 MHz

Table 1.2-1 Product lineup of the MB89051 series

Item MB89051 MB89F051

ROM Size 32KB 32KB(FLASH)

RAM Size 2KB

Package LQFP-64(FPT-64P-M09)

Others MASK products FLASH products/EVA products

CPU function Number of basic instructions: 136 instructionsInstruction bit length: 8 bitsInstruction length: 1 to 3 bytesData bit length: 1, 8, and 16 bitsMinimum execution time: 0.33 µs (6MHz)Interrupt processing time: 3ms (6MHz)

Per

iphe

ral f

unct

ion

General-purpose port General-purpose I/O ports (37: CMOS (of which seven support 3 V), 4: Nch open drain)

USB hub Upstream port: 1 channelDownstream port: 5 channels (of which one is fixed to the internal function)Port power supply control system: Power supply control on a port-by-port basisSelection between the own power supply and bus power supply allowed

USB function Supports full speed mode: When using hubsSupports full and low speed modes: When using functionsEnd point max 4 Built-in DMAC (DMA transfer to the internal RAM allowed)

PWM timer 8-bit PWM timer operation × 2 channels (can also be used as a PPG × 1 channel timer)

UART SIO Switching between UART (clock-synchronous/asynchronous data transfer allowed) andSIO (simple serial transfer) allowed.

SIO SIO (single serial) ×2ch(corresponding to 3V)

I2C interface 1 channel, compatible with the Phillips specification. A two-wire protocol used forcommunications with other devices. Master and slave transmission/reception

Time-base timer 21bit Time-base timer

Clock output 12 MHz * and 6 MHz * clock output enabled (3 V)

Standby Mode Sleep mode, stop mode

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CHAPTER 1 Overview

1.3 Differences between models

Describes points to note when selecting MB89051 series models.

Note on selecting product

Memory Space

If using, for example, FLASH products for assessment, be sure to carefully check the differenceswith the model that is to be actually used.

Current Consumption

• When operated at low speed, FLASH models will consume more current than mask ROMmodels. However, in sleep/stop mode the current consumption is the same.

• For detailed information on each package, see "1.6 Package Dimension".

USB pull-up resistor control

A high impedance state continues until an USB connection takes place. Before setting up an USBconnection, use the USBP terminal to perform software-based control of pull-up resistorconnection.

Figure 1.3-1 A Connection Example of an MB89051 Series Model

D+

D−

1.5 kΩ

3.3 V

Host PC MB89051 series

USBP pin

RPVP pin

RPVM pin

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CHAPTER 1 Overview

1.4 Block diagram of the MB89051 series

Figure 1.4-1 shows block diagram of all MB89051 series.

Block diagram of all MB89051 series

Figure 1.4-1 Block diagram of all MB89051 series

RPVP

RPVM

D2VP to D5VP

D2VM to D5VM

US

B D

RV

Rp

Dp5-4

Dp5

CM

OS

I/O P

ort3V

CM

OS

I/O P

ort

CM

OS

out Port

Nch I/O

Port

CM

OS

I/O P

ort

Nch I/O

Port

P40/POW5P41/POW2P42/POW3P43/POW4

DMAC

P53/SDA, P54/SCL

VSS VCC MOD0 MOD1 C

RAM 2 KByte

F2MC - 8L CPU

ROM 32 K / FLASH 32 KByte

P20 to P27 *

P45/UO

P44/UCK

P47/PWM2

P46/UI/PWM1

P00 to P07,P10 to P17

SIO

RST

X0X1

CLK2

3V C

LK P

ort

CLK1

I2C

SIO1

SIO2

P31/INT1P32/INT2/SI1

P33/INT3/SO1P34/INT4/SCK1P35/INT5/SCK2P36/INT6/SO2P37/INT7/SI2

MOD2 USBP

UART

Main clock oscillation circuit

Clock control circuit

PLL circuit

USB HUB circuit

USB Functioncircuit

Clock input

External interrupt (level)

Reset output

Power-ON reset circuit (Watchdog timer)

21-bit timebase timer

8-bit PWM timer

Other pins

Inte

rna

l bu

s

*: Port2 serves as an output-only terminal on the emulator.

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CHAPTER 1 Overview

1.5 Pin Assignment

Figure 1.5-1 are pinouts of the MB89051.

Terminal Assignment of the MB89051 Series

Figure 1.5-1 Pin assignment of MB89051

P34/INT4/SCK1P35/INT5/SCK2

P36/INT6/SO2P37/INT7/SI2

CLK1CLK2

P40/POW1P41/POW2P42/POW3P43/POW4

P44/UCKP45/UO

P46/UI/PWM1VSS

P47/PWM2MOD2

123456789

10111213141516

P00P01P02P03P04P05P06P07P10P11P12P13P14P15P16P17

48474645444342414039383736353433

P53

/SD

AP

54/S

CL

RS

TM

OD

0M

OD

1X

0X

1V

SS

P27

P26

P25

P24

P23

P22

P21

P20

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P33

/INT

3/S

O1

P32

/INT

2/S

I1P

31/IN

T1

D4V

MD

4VP

D3V

MD

3VP

D2V

MD

2VP

D1V

MD

1VP

US

BP

RP

VM

RP

VP

C VC

C

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

(FPT-64P-M09)

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CHAPTER 1 Overview

1.6 Package Dimension

MB89051 series is available in one type of package.

Package DimensionFigure 1.6-1 FPT-64P-M09 package dimension

64-pin plastic LQFP Lead pitch 0.65 mm

Package width × package length

12 × 12 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.70 mm MAX

64-pin plastic LQFP(FPT-64P-M03)

Note 1)*: These dimensions do not include resin protrusion.Note 2)Pins width and pins thickness include plating thickness.Note 3)Pins width do not include tie bar cutting remainder.

(FPT-64P-M09)

C 2003 FUJITSU LIMITED F64018S-c-3-5

0.65(.026)

0.10(.004)

1 16

17

3249

64

3348

12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05(.013±.002)

M0.13(.005)

0.145±0.055(.0057±.0022)

"A"

.059 –.004+.008

–0.10+0.20

1.50

0~8˚

0.25(.010)

(Mounting height)

0.50±0.20(.020±.008)0.60±0.15

(.024±.006)

0.10±0.10(.004±.004)

Details of "A" part

(Stand off)

0.10(.004)

*

Dimensions in mm (inches).Note: The values in parentheses are reference values

9

CHAPTER 1 Overview

1.7 Pin Description

Table 1.7-1 list the I/O pins and their functions.The alphabet letter in the I/O Circuit Type field corresponds to that in the I/O Circuit Category field in Table 1.8-1 .

Pin Description

Table 1.7-1 Pin description

Pin number

Pin Name Input/OutputCircuit Type

Functional description

1 P34/INT4/SCK1 E CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)Clock input/output at SIO1

2 P35/INT5/SCK2 E CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)Clock input/output at SIO2

3 P36/INT6/SO2 B CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)SIO2 serial data output

4 P37/INT7/SI2 E CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)SIO2 serial data input

5 CLK1 M 12MHz clock output pinExternal supply clock at 6MHz

6 CLK2 M 12MHz clock output pin (External supply clock at 6MHz)

7 P40/POW5 B CMOS general-purpose I/O pinAlso serves as the USB Down Port power control signal terminal.




11 P44/UCK E CMOS general-purpose I/O pinClock input/output at UART/SIO

12 P45/UO B CMOS general-purpose I/O pinUART/SIO serial data output

13 P46/UI/PWM1 N General-purpose Nch open drain I/O terminalUART/SIO serial data inputPWM timer

10

CHAPTER 1 Overview

14 VSS - Power supply pin (GND)

15 P47/PWM2 K General-purpose Nch open drain I/O terminalPWM timer

16 MOD2 F Operating mode specification pinConnect them directly to VSS.

17 P53/SDA K General-purpose Nch open drain I/O terminal

Also serves as the I2C interface data I/O terminal.

18 P54/SCL K General-purpose Nch open drain I/O terminal

Also serves as the I2C interface clock I/O terminal.

19 RST I Reset pin (Reset when low (negative logic))



22 X0 A Connection terminal for the crystal oscillator circuit (6MHz).

23 X1

24 VSS - Power supply pin (GND)

25 P27 B CMOS general-purpose I/O pin*








33 P17 B CMOS general-purpose I/O pin








Pin number



11

CHAPTER 1 Overview










49 VCC - Power supply pin

50 C - Connects an external 0.1 mF capacitor. When using a 3.3 V power supply,connect this terminal to the VCC terminal for 3.3 V input.

51 RPVP USBDRV USB route port + terminal

52 RPVM USBDRV USB route port-terminal

53 USBP L USB pull-up resistor connection terminal

54 D5VP USBDRV USB down port 5 + terminal

55 D5VM USBDRV USB down port 5 - terminal







62 P31/INT1 B CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)

63 P32/INT2/SI1 E CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)SIO1 serial data input

64 P33/INT3/SO1 B CMOS general-purpose I/O pinExternal interruption input (Hysteresis input) (Level detection)SIO1 serial data output

*: For output only on the emulator.


Pin number



12

13

CHAPTER 1 Overview

1.8 I/O Circuit

Table 1.8-1 lists the I/O circuit types.The alphabet letter in the Category field corresponds to that in the I/O Circuit Type field in Table 1.7-1 , which provides descriptions of terminal functions.

I/O Circuit

Table 1.8-1 I/O circuit types (Continued)

Classification Circuit Remark

A • Oscillation return resistance about1MΩ

B • CMOS Input/output

E • CMOS Input/output• TTL hysteresis input

F • CMOS input

X1

X0

Standby control signal

Nch

R

Pch

PchPull-up control register


Input

Pch

Pch

R

Nch

Pull-up control register

Port input

Resource input


Input

CHAPTER 1 Overview

I • Hysteresis I/O• Pull-up resistance

USBDRV • USB input/output

K • Nch open drain I/O

L • USB pull-up resistor connection



Pch

R

Nch

Input

D+

D−

D+ input

D− input

Differential input

Full D+ output

Full D− output

Low D+ output

Low D− output

Direction

Speed

Nch


Input

Pch

Nch

14

CHAPTER 1 Overview

M • Clock output

N • Nch open drain I/O• Hysteresis input



Pch

Nch

Nch

Port input

Resource input


15

CHAPTER 1 Overview

16

CHAPTER 2Precautions when Handling

Devices

This chapter explains handling precautions for USB general-purpose one-chip microcontrollers.

2.1 Precautions when Handling Devices

17

18

CHAPTER 2 Precautions when Handling Devices

2.1 Precautions when Handling Devices

This section describes the precautions against the power supply voltage of the device and processing of pin.

Precautions when Handling Devices

Be sure to perform operation within the maximum rated voltage (to prevent latch-up).

Latch-up may occur on CMOS ICs if voltage higher than Vcc or lower than Vss is applied to inputor output pins other than the medium-and high-voltage pins or if voltage higher than the rating isapplied between VCC and VSS.

When latch-up occurs, power supply current increases rapidly and might thermally damageelements. When using, take great care not to exceed the absolute maximum ratings.

Take great care in ensuring the stability of supply voltage.

Sudden changes in the supply voltage may cause misoperation, even if the VCC supply voltage

remains within the guaranteed operating range.

For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50Hz to 60 Hz) fall below 10 of the standard VCC supply

voltage and the coefficient of fluctuation does not exceed 0.1 V/ms.

About the processing of an unused input terminal

Leaving unused input terminals open may cause malfunctions or permanent damage due tolatch-up. Apply a pull-up or pull-down process to the unused terminals using a resistor of 2 kΩ ormore.

Place unused I/O terminals in output state to leave them open or apply the same process as thatfor unused input terminals to terminals in input state.

Precaution against noise to the external reset terminal (RST)

An input of a reset pulse below the specified level to the external reset terminal (RST) may causemalfunctions. Be sure not to allow an input of a reset pulse below the specified level to theexternal reset terminal (RST).

Note on the clock during operation

This microcontroller uses a PLL for generating the main clock signal. If the oscillator is removedor the clock input stops during operation, therefor, the microcontroller may keep on operating atthe free-running frequency of the self-oscillation circuit in the PLL. The operation is not howeverguaranteed.

About port 2 (P20 to P27)

Port 2 serves as an output-only terminal on the emulator.

CHAPTER 3CPU

This chapter explains the function and operation of the UART0.

3.1 Memory Space

3.2 Dedicated Registers

3.3 General-purpose Register

3.4 Interrupt

3.5 Reset

3.6 Clock

3.7 Standby mode (low power consumption)

3.8 Memory Access Mode

19

CHAPTER 3 CPU

3.1 Memory Space

The MB89051 Series models have a 64-Kbyte memory space that consists of the I/O, RAM and ROM areas. The memory space contains areas that are used for specific purposes, such as a general-purpose register and a vector table.

Configuration of Memory Space

I/O area (address:0000H to 007FH)

• The space is assigned, for example, to control and data registers for internal peripheralfunctions.

• The I/O area can be accessed like memory since the assigned I/O area is a part of memory.Direct addressing also enables faster access.

RAM Area

• Static RAM is contained as the internal data area.

• The capacity of the internal ROM depends on the product.

• Direct addressing enables high-speed access to addresses 80H to FFH.

• Addresses 100H to 1FFH can be used as a general-purpose register area (however, note that

there is a limit to the area that can be used depending on the model).

• Resetting causes the RAM data to become undefined.

ROM Area

• ROM is contained as the internal program area.

• The capacity of the internal ROM depends on the product.

• The area FFC0H to FFFFH should be used for a vector table, for example.

20

CHAPTER 3 CPU

Memory Map

Figure 3.1-1 Memory Map

MB89051

0000H

0080H

0100H

0200H

0880H

8000H

FFC0HFFFFH

ROM

I/O

RAM

MB89F051

0000H

0080H

0100H

0200H

0880H

8000H

FFC0HFFFFH

ROM

I/O

RAM

Register Register

Accessprohibited

Vector Table(Reset, Interrupt, Vector Call Instruction)

Accessprohibited

: FLASH ROM

21

CHAPTER 3 CPU

3.1.1 Area for specific usage

In addition to the I/O area, the general-purpose register and vector table areas are available, as areas for specific purposes.

General-purpose register area (address: 0100H to 01FFH)

• Contains the auxiliary registers used for 8-bit arithmetic or transfer operations.

• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.

• When the addresses are used as general-purpose registers, general-purpose registeraddressing enables high-speed access using short instructions.

Reference

See "3.2.2 Register bank pointer (RP)" and "3.3 General-purpose Register" for details.

Vector table area (address: FFCOH to FFFFH)

• Used as the vector table for the vector call instruction, interrupts, and resets.

• Located at the top of the ROM area. Set the entry addresses for the handler routines at theirrespective vector table addresses.

• Table 3.1-1 lists the vector table addresses referred by the vector call instruction, interrupts,and resets.

See "3.4 Interrupt", "3.5 Reset", and the "CALLV #vct" explanation in "Appendix B.2 SpecialInstruction" for details.

Table 3.1-1 Vector table

Vector Call Instruction

Address of vector table Interrupt name

Address of vector tableHigh Low High Low

CALLV #0 FFC0H FFC1H IRQC FFE2H FFE3H CALLV #1 FFC2H FFC3H IRQB FFE4H FFE5H CALLV #2 FFC4H FFC5H IRQA FFE6H FFE7H CALLV #3 FFC6H FFC7H IRQ9 FFE8H FFE9H CALLV #4 FFC8H FFC9H IRQ8 FFEAH FFEBH CALLV #5 FFCAH FFCBH IRQ7 FFECH FFEDH CALLV #6 FFCCH FFCDH IRQ6 FFEEH FFEFH CALLV #7 FFCEH FFCFH IRQ5 FFF0H FFF1H

IRQ4 FFF2H FFF3H IRQ3 FFF4H FFF5H IRQ2 FFF6H FFF7H IRQ1 FFF8H FFF9H IRQ0 FFFAH FFFBH Mode Data - * FFFDH Reset vector FFFEH FFFFH *:FFFCH is not allowed to use. Set FFH.

22

CHAPTER 3 CPU

3.1.2 Location of 16-bit data in memory

16-bit data and stack values are stored with the upper byte in the lower memory address.

Storage format for 16-bit data in RAMWhen 16-bit data is written to memory, the high order byte of the data will be stored in the loweraddress byte and the low order byte of the data will be stored in the next address byte. The sameapplies when reading. Figure 3.1-2 shows the format of 16-bit data in memory.

Figure 3.1-2 Location of 16-bit data in memory

How data is stored when using a 16-bit operandWhen making 16-bit specification using an active operand, the high order byte will be stored inthe address close to the operand code and the low order byte will be stored in the next address.

This equally applies to when the operand is a memory address and 16-bit immediate data.

Figure 3.1-3 shows the format of 16-bit data in instructions.

Figure 3.1-3 Location of 16-bit data in an instruction

Storage format for 16-bit data on the stack16-bit data pushed onto the stack by an interrupt or similar is also stored with the upper byte inthe location with the lower address value.

before execution

A 1 2 3 4 H

Memory

0080H

0081H

0082H

0083H

after execution

A 1 2 3 4

Memory

0080H

0081H

0082H

0083H

12 H34 H

MOVW 0081H, A

[Example] MOV A, 5678H ; Extended address

MOVW A, #1234H ; 16 bits Immediate data

After assembly

X X X 0 H XX XXX X X 2 H 60 56 78 ; Extended addressX X X 5 H E4 12 34 ; 16 bits Immediate dataX X X 8 H XX

23

CHAPTER 3 CPU

3.2 Dedicated Registers

The dedicated registers in the CPU consist of the program counter (PC), arithmetic registers (A and T), three address pointers (IX, EP, and SP), and the program status (PS). All registers are 16-bit.

Configuration of Dedicated RegistersThe special-purpose registers in the CPU consist of seven 16-bit registers. Of these, someregisters can only use the lower 8 bits.

Figure 3.2-1 shows the structure of the special-purpose registers.

Figure 3.2-1 Configuration of Dedicated Registers

Function of dedicated Registers

Program counter (PC)

The program counter is a 16-bit counter which holds the memory address of the instructioncurrently being executed by the CPU. The contents of the program counter are updated byinstruction execution, interrupts, resets, and similar. The initial value during a reset is the readaddress for the mode data (FFFDH).

Accumulator (A)

The accumulator is a 16-bit register for operation; it is used for a variety of arithmetic and transferoperations of data in memory or data in other registers such as the temporary accumulator (T).The data in the accumulator is treated either as word data (16-bit) or byte data (8-bit). Only the

Program status A register for storing a register bank pointer and condition code.

RP CCR

PS

I flag =0,IL1,0=11Other bits are undefined.

Stack pointer A register for indicating the current stack location.

Undefined

Extra pointer A pointer for indicating a memory address.

Undefined

Index register A register for indicating an index address.

Undefined

Temporary accumulator A register which performs arithmetic operations with the accumulator.

Undefined

Accumulator A temporary register for storing arithmetic operations or transfer instructions.

Undefined

PC

A

T

IX

EP

SP

:

:

:

:

:

:

:

Program counter A register for indicating the current instruction storage positions.

16 bits

FFFDH

Initial value

24

CHAPTER 3 CPU

lower 8 bits of the accumulator (AL) are used for byte-length arithmetic and transfer operationsand the upper 8 bits (AH) are not used. Initial data becomes undefined after reset.

Temporary accumulator (T)

The temporary accumulator is a 16-bit auxiliary arithmetic register used to perform arithmeticoperations with the data in the accumulator (A). The data in the temporary accumulator is treatedas word data for word-length (16-bit) operations with the accumulator (A) and as byte data forbyte (8-bit) operations. Only the lower 8 bits of the temporary accumulator (TL) are used for byte-length operations and the upper 8 bits (TH) are not used.

When a MOV instruction is used to transfer data to the accumulator (A), the previous contents ofthe accumulator are automatically transferred to the temporary accumulator. When transferringbyte-length data, the upper 8 bits of the temporary accumulator (TH) remain unchanged. Initialdata becomes undefined after reset.

Index register (IX)

The index register is a 16-bit register used to store the index address. The index register iscombined with a single-byte offset value (-128 to +127). The signed offset is added to the indexaddress to generate the memory address from which to access the data. Initial data becomesundefined after reset.

Extra pointer (EP)

The extra pointer is a 16-bit register and specifies a memory address for a data access. Initialdata becomes undefined after reset.

Stack pointer (SP)

The stack pointer (SP) is a 16-bit register and stores an address that is used when an interrupt orsubroutine call occurs and by the stack push and pop instructions. During program execution, thevalue of the stack pointer indicates the address of the most recent data to be pushed onto thestack. Initial data becomes undefined after reset.

Program status (PS)

The program status is a 16-bit control register. The upper 8 bits contain the register bank pointer(RP) which specifies the address of the general-purpose register bank.

The lower 8 bits contain the condition code register which consists of flags that represent thestate of the CPU. The 8-bit registers are part of the program status and cannot be accessedindependently. (The only instructions for accessing the program status are MOVW A, PS andMOVW PS, A.)

25

CHAPTER 3 CPU

3.2.1 Condition code register (CCR)

The condition code register (CCR) contained in the lower 8 bits of the program status (PS) contains bits with information about the arithmetic result or transfer data (C,V, Z, N, and H), and bits used to control interrupt handling (I, IL1, and IL0).

Configuration of Condition Code Register (CCR)

Figure 3.2-2 Structure of the condition code register

Bits that indicate information about the operation result

H-flag (H)

The flag is set to "1" when an arithmetic operation results in a carry from bit 3 to bit 4 or in aborrow from bit 4 to bit 3. The bit is cleared to "0" in other instances. The flag is for decimaladjustment instructions; do not use for other than additions and subtractions.

Negative flag (N)

The flag is set to "1" when an arithmetic operation results in setting of the MSB to "1" or is clearedto "0" when the MSB is set to "0".

Zero flag (Z)

The flag is set to 1 when an arithmetic operation results in "0" or is set to "0" in other instances.

Overflow flag (V)

The flag is set to "1" when an arithmetic operation results in two’s complement overflow or iscleared to 0 if no overflow occurs.

Carrying flag (C)

Set to "1" if a carry from bit 7 or a borrow to bit 7 occurs during an arithmetic operation. Clearedto "0" otherwise. In the case of a shift instruction, the flag is set to the shift-out value.

Figure 3.2-3 shows how the carry flag is modified by a shift instruction.

Negative flagInterrupt level bitInterrupt enable flagHalf carring flag

Carring flagOverflow flagZero flag

R4 R2 R1 R0R3

bit15bit14bit13bit12bit11bit10 bit 9 bit 8

H I IL1 IL0 N Z V C

CCR

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PS

RP

X011XXXXB

Initial valueCCR

X: Undefined

26

CHAPTER 3 CPU

Figure 3.2-3 Change in carry flag resulting from shift instruction

Note

The condition code register is part of the program status (PS) and therefore cannot be accessedindependently.

Reference

When flags are used, flag bits are rarely fetched for direct use. Normally used indirectly via a branchinstruction (such as BNZ) or a decimal adjusted instruction (DAA or DAS). Initial data becomesundefined after reset.

Bits used to control how interrupts are handled

I-flag (I)

When this flag is set to "1", an interruption is enabled and the CPU accepts the interruption.When this flag is set to "0", an interruption is disabled and the CPU accepts no interruptionrequest.

The initial value after a reset is "0".

Normally, set to "1" by the SETI instruction and cleared to "0" by the CLRI instruction.

Interrupt level bit (IL1, 0)

This bit indicates the level of the interruption currently accepted by the CPU and is compared withthe value for the interruption level setting register (ILR1 to 3) that corresponds with theinterruption request (IRQ0 to IRQB) of each peripheral function.

The CPU only processes interruption requests of levels defined by values smaller than the bitvalue when the interruption-enable flag is enabled (I=1). Table 3.2-1 lists their level priorities. Theinitial value after a reset is "11".

bit7 bit0

C

bit7 bit0

C

The case of left shift (ROLC) The case of right shift (RORC)

27

CHAPTER 3 CPU

Reference

The interrupt level bits (IL1, IL0) are usually "11" with the CPU not servicing an interrupt (with themain program running).

For details of interrupt, see "3.4 Interrupt".

Table 3.2-1 Interrupt level

IL1 IL0 Interrupt level High to Low

0 0 1 High

Low (no interrupt)

0 1

1 0 2

1 1 3

28

CHAPTER 3 CPU

3.2.2 Register bank pointer (RP)

The register bank pointer (RP), the upper 8 bit of program status (PS), indicates the address of the general-purpose register bank currently used and will be converted to a real address during general-purpose register addressing.

Configuration of Register Bank Pointer (RP)Figure 3.2-4 shows the structure of the register bank pointer.

Figure 3.2-4 Construction of register bank pointer

The register bank pointer specifies the address of the register bank currently being used. Figure

3.2-5 shows the relationship between the register bank pointer and actual address.

Figure 3.2-5 Rule for Conversion of Actual Addresses in the General-purpose Register Area

The register bank pointer is used to specify which memory block in RAM to use as the general-purpose registers (the register bank). There are a total of 32 register banks. The current registerbank is specified by setting a value between 0 and 31 in the upper 5 bits of the register bankpointer. One register bank consists of eight 8-bit general-purpose registers specified by the lower3 bits of the op-code.

The region between 0100H and 01FFH is used as a general-purpose register area using the

register bank pointer. However, it should be note that there is a limit to the area that can be useddepending on the model. Initial data becomes undefined after reset.

Note

• Ensure that you set the register bank pointer (RP) before using the general-purpose registers.

• The register bank pointer is part of the program status (PS) and cannot be accessedindependently.

R4 R2 R1 R0R3

bit15bit14bit13bit12bit11bit10 bit 9 bit 8

H I IL1 IL0 N Z V C

CCR

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

PS

RP

XXXXXXXXB

Initial valueRP

X: Undefined

"0" "0" "0" "1""0" "0" "0" "0" R0 b2 b1 b0R4 R3 R2 R1

A11A10 A9 A8A15A14A13A12 A3 A2 A1A7 A6 A5 A4 A0Generation address

RP higerOperation code lower

29

CHAPTER 3 CPU

3.3 General-purpose Register

The general-purpose registers are memory blocks consisting of 8 x 8-bit registers per bank.Register bank pointer (RP) is used to specify the register bank.Up to 32 banks can be used. However, all the banks may not be used when the internal RAM capacity is small.This applies during interrupt processing, vector call processing, and subroutine calls.

Configuration of General-purpose Register• The general-purpose registers are 8-bit registers and are located in register banks in the

general-purpose register area (in RAM).

• One bank contains eight registers (R0 to R7), and up to 32 banks can be used. However,when only using internal RAM, the number of banks actually available depends on the devicemodel.

• The register bank pointer (RP) specifies the register bank currently being used and the lower 3bits of the op-code specify general-purpose register 0 (R0) to general-purpose register 7 (R7).

Figure 3.3-1 shows the structure of the register banks.

Figure 3.3-1 Construction of register bank

For more information on the general-purpose register area that can be used by each model, referto "3.1.1 Area for specific usage".

: The top of the register bank = 0100H + 8 (Higher 5 bits of RP)

000

001

010

011

100

101

110

111

000

:

111

:::

000

:

111

Bank 31 (RP = "11111---B")

32 bank (RAM area)

Bank 1 (RP = "00001---B")

Bank 0 (RP = "00000---B")

Bank 2

Bank 30

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

R 0

:

R 7

:::

R 0

:

R 7

100H

108H

1F8H

1FFH

Operation codelower 3 bits

Bank number is limitedby usable RAM capacity.

30

CHAPTER 3 CPU

Features of General-purpose RegisterThe general-purpose registers have the following characteristics.

• High-speed access to RAM using short instructions (general-purpose register addressing)

• This region is divided into register bank blocks to make it easy to backup the contents andseparate by function.

Separate register banks can be allocated for use as general-purpose registers by specificinterrupt handler or vector call (CALLV #0 to #7) handler routines. An example of how a shortinstruction is used is "Use the 4th register bank for the 2nd interruption.

Unless a register bank dedicated to single interruption processing is accidentally overwritten byanother routine, simply specifying the register bank at the beginning of each interruption handlingroutine saves the pre-interruption general-purpose register. This saves the trouble of saving thegeneral-purpose register into a stack, for example, and enables smooth, high-speed acceptanceof interruption requests.

For subroutine calls, in addition to protecting the general-purpose registers, the register bankscan also be used to implement reentrant programs (programs that do not use fixed addresses forvariables and can be entered more than once) usually created with the index register (IX).

Note

To specify a register bank after overwriting the register bank pointer (RP) during an interruptionhandling routine, programming must ensure that no change is made to the interruption level bit(CCR: IL1, 0) value of the condition code register.

31

CHAPTER 3 CPU

3.4 Interrupt

The MB89051 series have 13 interrupt request inputs to the peripheral functions. Separate interrupt level settings can be specified for each interrupt.When a peripheral function generates an interrupt request and output of the interrupt request is enabled in the peripheral function, the interrupt controller compares the interrupt level. The CPU performs an interruption in accordance with the level of the interruption request accepted. The device is released from standby mode by an interrupt request. On recovering, the device performs interrupt processing or normal operation.

Interrupt request from peripheral functionTable 3.4-1 lists the interrupt requests for each peripheral function. When an interruption requestis accepted, the interruption vector table address from which the interruption request originated issent to the interruption handling routine as the branched destination address.

The priority for each interrupt request can be set to one of three levels using the interrupt levelsetting registers (ILR1, 2, 3, and 4).

If another interrupt request with the same or lower level occurs during execution of the interrupthandler, the interrupt is normally processed after the current interrupt handler completes. Ifanother request with the same interrupt level occurs simultaneously, the relative priority isdetermined such that IRQ0 has the highest priority.

*:FLASH interrupt is only for MB89F051.

Table 3.4-1 Interrupt requests and interrupt vectors

Interrupt request Address of vector table Setting of interrupt level bit name in a register

Same level Priority order (at simultaneous occurrence)High Low

IRQ0 (External interrupt) FFFAH FFFBH L01, L00 High

IRQ1 (Setting prohibited) FFF8H FFF9H L11, L10

IRQ2(USB HUB1) FFF6H FFF7H L21, L20

IRQ3(USB FUNCTION1) FFF4H FFF5H L31, L30

IRQ4(USB HUB2) FFF2H FFF3H L41, L40

IRQ5(USB FUNCTION2) FFF0H FFF1H L51, L50

IRQ6(UART/SIO) FFEEH FFEFH L61, L60

IRQ7(time base timer) FFECH FFEDH L71, L70

IRQ8 (8-bit PWM timer 1, 2) FFEAH FFEBH L81, L80

IRQ9(I2C) FFE8H FFE9H L91, L90

IRQA(FLASH *) FFE6H FFE7H LA1, LA0

IRQB(SIO1) FFE4H FFE5H LB1, LB0

IRQC(SIO2) FFE2H FFE3H LC1, LC0 Low

32

CHAPTER 3 CPU

3.4.1 Interrupt level setting registers (ILR1, 2, 3, 4)

The interrupt level setting registers (ILR1, 2, 3, and 4) contain 13 2-bit settings each of which corresponds to an interrupt request from a peripheral functions. The interrupt level can be set in these two bits (interrupt level setting bits).

Configuration of Interrupt level setting register (ILR1,2,3,4)

Figure 3.4-1 Configuration of Interrupt level setting register

The interrupt level setting registers contain separate 2-bit settings for each interrupt request. Theinterrupt level setting bit values set in these registers determine the interrupt processing priority(interrupt levels 1 to 3).

The interrupt level setting bits are compared with the interrupt level bits in the condition coderegister (CCR:IL1, 0).

When the interruption level is set to "3", the CPU accepts no interruption request.

Table 3.4-2 lists the relationship between the interrupt level setting bits and the interrupt level.

L31 L21 L20 L11 L10 L01 L00

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 0 7 BH

Address

11111111B

Initial value

L30

Register

ILR1

L71 L61 L60 L51 L50 L41 L400 0 7 CH 11111111BL70ILR2

LB1 LA1 LA0 L91 L90 L81 L800 0 7 DH 11111111BLB0ILR3

W: Write only

WW W W W WWW

WW W W W WWW

WW W W W WWW

Reserved bit LC1 LC00 0 7 EH XXXXXX11BILR4

WW

Table 3.4-2 Relationship between interrupt level and interrupt level setting bits

L01 to LC1 L00 to LC0 Interrupt request level High - Low

0 0 1 High0 11 0 21 1 3 Low (no interrupt)

33

CHAPTER 3 CPU

Reference

The value of the interrupt level bits in the condition code register (CCR:IL1, 0) is normally "11".

Note

As the ILR1, ILR2, ILR3, and ILR4 registers are write-only, the bit manipulation instructions (SETBand CLRB) cannot be used.

Be also sure to always set the reserved bit to "1".

34

CHAPTER 3 CPU

3.4.2 Interrupt processing

When an interrupt request is generated by a peripheral function, the interrupt controller passes the interrupt level to the CPU. When the CPU is in a state where it can accept interruption requests, it temporarily halts the program currently being executed and executes an interruption handling routine.

Interrupt processingInterrupts are handled as follows: interrupt condition occurs in peripheral function, set theinterrupt request flag bit (request F/F), check the interrupt request enable bit (enable F/F), checkthe interrupt level (ILR1, 2, 3, and 4 and CCR:IL1, 0), check the same level at the same time,check the interrupt enable flag (CCR: I).

Figure 3.4-2 shows the operation for interrupt processing.

Figure 3.4-2 Interrupt processing

Internal Bus

IPLA

Registerfile

IR

Check Comparator

RAM

Enable FF

Request FFAND

Each peripheralInterruptcontroller

F2MC-8L, CPU

(4)

(4)

(3)

(7)

5

PS I IL

(6)

Condition coderegister (CCR)

START

Is interrupt request present at the

peripheral?

Check the interrupt priority level and transfer the level to the CPU

Initialize Peripheral

NO Is interrupt request output enabled

for the peripheral?

NO

YES

Compare the level withthe IL bits in PS

Is the level higher than IL?

I flag = 1?

YES

YESNO

NO

Saving PC and PS to a stack

PC Interrupt vector

Renewal of IL in PS

YES(3)

(1)

(5)

(6)

Stop released

Sleep released

Interrupt processing routine

Interrupt request clear

Executing interrupt request

RETI

Return PC and PS(7)

ExecutingMain program(2)

Leve

l com

para

tor

35

CHAPTER 3 CPU

1. All interrupt requests are disabled after a reset. In the initialization program for the peripheralfunctions, initialize those peripheral functions that generate interrupt requests and set theinterrupt level in the appropriate interrupt level setting register (ILR1, 2, 3, or 4) before startingoperation of peripheral. The interrupt level can be set to 1, 2, or 3. Level 1 interruptionrequests have highest priority and Level 2 interruption requests have second highest priority.Setting level 3 specifies that the interrupt from the corresponding peripheral function isdisabled.

2. Execute the main program (or the interrupt handler routine in the case of multiple interrupts).

3. When an interruption factor has been caused by the peripheral function, the interruptionrequest flag bit (request FF) of the peripheral function will be set to "1". If the interrupt requestenable bit for the peripheral function is enabled (enable F/F = 1), the interrupt request is outputto the interrupt controller.

4. The interrupt controller always monitors interrupt requests from individual peripheral resourcesand transfers the highest interrupt level, to the CPU, among the interrupt levels of the currentlygenerated interrupt requests. The relative priority if another request with the same interruptlevel occurs simultaneously is also determined at this time.

5. When the CPU receives an interruption request of higher priority (expressed by lower levels)than the level to which the interruption level bit (CCR: IL1, 0) of the condition code register isset, it checks the interruption-enable flag (CCR: I) and accept the interruption during interruptenable (CCR: I=1).

6. The CPU saves the contents of the programmer counter (PC) and program status (PS) to thestack, fetches the start address of an interrupt handler from the corresponding interrupt vectortable, changes the value in the interrupt level bits (CCR: IL1, IL0) to the value of the receivedinterrupt level, and starts the execution of interrupt process routine.

7. Finally, use the RETI instruction to restore the program counter (PC) and program status (PS)from the stack and continue execution from the next instruction after the instruction executedprior to the interrupt.

Note

As the interrupt request flag bit for a peripheral resource is not cleared automatically even onacceptance of an interrupt request, the interrupt handler must be programmed to clear the bit(normally, by writing 0 to the interrupt request flag bit).

Standby mode (low power consumption) is released by interruption. Please refer to "3.5 Reset" fordetails.

Reference

Clearing the interrupt request flag at the start of the interrupt handler allows the peripheral function togenerate another interrupt while the interrupt handler is still executing (set the interrupt request flagagain). However, interrupt reception is not normally performed until the current interrupt handlerroutine returns.

36

CHAPTER 3 CPU

3.4.3 Multiple interrupts

When multiple interrupt requests are generated by the peripheral functions, this can be handled by setting different interrupt levels in the interrupt level setting registers (ILR1, 2, 3, and 4).

Multiple interruptsIf an interruption request of higher priority occurs while an interruption handling routine is beingexecuted, the CPU halts interruption processing currently underway and accepts the interruptionrequest of higher priority. Although the interruption level can be set to "1" to "3", the CPU acceptsno Level 3 interruption requests.

Example of multiple interrupts

In case higher priority is given to external interruptions over timer interruptions as an examplemultiple interruption processing, set the timer interruption to Level 2 and the external interruptionto Level 1. If an external interruption occurs while a timer interruption is being processed whenthis setting is used, the processing as shown in Figure 3.4-3 takes place.

Figure 3.4-3 Example of multiple interrupts

• While a timer interruption is being processed, the interruption level bit (CCR: IL1, 0) value ofthe condition code register becomes equal to the value of the interruption level setting register(ILR1, 2, 3, 4) for the timer interruption (2 in the example). If an interrupt request with a higherpriority interrupt level occurs (level 1 for example), the higher priority interrupt is processedfirst.

• To temporarily disable multiple interruptions while a timer interruption is being processed, setthe interruption-enable flag in the condition code register to interruption disable (CCR: I=0) orset the interruption level bit (IL1, 0) to "00".

• Executing the interruption return instruction (RETI) after the interruption processing restoresthe program counter (PC) and program status (PS) values saved in a stack and the processingof the interruption program is resumed. Restoring the program status (PS) also restores thecondition code register (CCR) to its value prior to the interrupt.

(1)

(2)

(8)

(3)

(6)

(7)

(4)

(5)

Timer interrupt processingMain program External interrupt processing

Interrupt leve 2CCR:IL1, 0=10Initialize

peripheralTimer interrupt

generation

Resume Main

Resume

External interrupt generation

Timer interrupt processing

Timer interrupt return

Interrupt leve 1CCR:IL1, 0=01

External interrupt processing

External interrupt return

suspend

37

CHAPTER 3 CPU

3.4.4 Interrupt processing time

The time between an interrupt request being generated and control being passed to the interrupt handler is equal to the sum of the time until the currently executing instruction completes and the interrupt handling time (time required to initiate interruption). The maximum time is 30 instruction cycles.

Interrupt processing timeThe interruption request sample wait time and interruption handling time intervene between theoccurrence and acceptance of an interruption request and the execution of a interruption handlingroutine.

Interrupt request sampling delay time

Whether an interruption request has occurred is determined through the sampling of theinterruption request during the last cycle of each instruction. For this reason, the CPU is unable torecognize an interruption request while executing each instruction. This maximum length for thisdelay time occurs when the interrupt request is generated immediately after starting execution ofthe DIVU instruction which is the instruction with the longest execution time (21 instructioncycles).

Interrupt handling time

• Since the CPU performs the following interruption processing preparations after accepting aninterruption request, nine instruction cycles are required.

• Backup the program counter (PC) and program status (PS).

• Set the entry address for the interrupt handler in the PC.

• Updating the interrupt level bits in the program status (PS) (PS:CCR:IL1, 0)

Figure 3.4-4 shows the interrupt processing time.

Figure 3.4-4 Interrupt processing time

If an interrupt request is generated immediately after starting execution of the DIVU instructionwhich is the instruction with the longest execution time (21 instruction cycles), the interruptprocessing time is 21 + 9=30 instruction cycles. If the DIVU and MULU instructions are not usedin the program, the maximum interrupt processing time becomes 6 + 9 = 15 instruction cycles.

Normal Instruction execution Interrupt handlingCPU operation

Interrupt requestsample wait time

Interrupt handling time(9 instruction cycles)

Interrupt request generaiton

Interrupt wait time

: Instruction last cycle, Sampling interrupt request here

Interrupt processing routine

38

CHAPTER 3 CPU

3.4.5 Stack operation during interrupt handling

This explains how registers are saved and restored during interrupt processing.

Stack operation at the start of interrupt processingOnce the CPU accepts an interruption request, it automatically saves the current program counter(PC) and program status (PS) values into a stack.

Figure 3.4-5 shows how the stack is used at the start of interrupt processing.

Figure 3.4-5 Stack operation at the start of interrupt processing

Stack operation when returning from an interruptWhen the interrupt return instruction (RETI) is executed to end interrupt processing, the programstatus (PS) and then the program counter (PC) are restored from the stack (this is the opposite ofthe order in which they were saved to the stack during interruption). This restores PS and PC totheir states prior to starting interrupt processing.

Note

As the accumulator (A) and temporary accumulator (T) are not automatically saved on the stack, usethe PUSHW and POPW instructions to save and restore A and T on the stack.

immediately before interuption

SP 0280H

Memory

X XH

X XH

X XH

X XH

027CH

027DH

027EH

027FH

X XH

X XH

0280H

0281H

Address

PC E000H

PS 0870H

immediately afer interuption

PC E000H

Memory

0 8 H7 0 H

E 0 H

0 0 H

027CH

027DH

027EH

027FH

X XH

X XH

0280H

0281H

Address

PS 0870H

SP 027CH

PC

PS

39

CHAPTER 3 CPU

3.4.6 Interrupt handling stack area

The stack area in RAM is used when interrupt processing is executed. The stack pointer (SP) contains the address of the top of the stack area.

Interrupt handling stack areaThe stack area is used to store the program counter (PC) when a subroutine call instruction(CALL) or vector call instruction (CALLV) is executed, and also to backup registers temporarilyusing the PUSHW and POPW instructions.

• The stack area is located in RAM together with the data area.

• It is recommended that you initialize the stack pointer (SP) to the maximum RAM address andallocate data areas starting from the minimum RAM address.

Figure 3.4-6 shows an example of setting the stack area.

Figure 3.4-6 Interrupt handling stack area

Reference

New data is placed on the stack area by interrupts, subroutine calls, and the PUSHW instruction atprogressively lower addresses. Data is released from the stack by return instructions (RETI andRET) and the POPW instruction at progressively higher addresses. Ensure that the stack area in usedoes not overlap the data area containing other data or the general-purpose register area when thestack address is decreased by multiple interrupts or subroutine calls.

0000 H

0080 H

0100 H

0200 H

FFFF H

I/O

RAM

General- purpose register

ROM

0880 HStack area

Recommended set value for SP (When the top address of RAM is 0880H.)

Date area

Accessprohibited

40

CHAPTER 3 CPU

3.5 Reset

The four following reset factors are found.• External reset• Software reset• Watchdog reset• Power on reset

Reset Factor

External reset

An external reset is triggered by inputting an "L" level to the external reset pin (RST). Theexternal reset is released when the reset pin goes to the "H" level.

The external reset pin also serves as the reset output pin.

Software reset

Writing "0" to the software reset bit (STBC: RST) in the standby control register generates asoftware reset for four instruction cycles.

Watchdog reset

A watchdog reset generates a reset for 4 instruction cycles if data is not written to the watchdogcontrol register (WDTC) within the required time after the watchdog timer starts.

Power on reset

Power on reset generates reset by power-on.

Table 3.5-1 Reset Factor

Reset Factor Reset condition

External reset Set External Reset Pin to "L" level.

Software reset Write "0" to the software reset bit (STBC: RST) in the standby control register.

Watchdog reset Watchdog timer overflow

Power on reset Power on

41

CHAPTER 3 CPU

Reset factors and waiting for main clock oscillation stabilizationThe operation of the oscillation stabilization delay time is different depending on the operationmode when the reset was generated.

After a reset is performed, operation will start in normal main clock mode regardless of theoperation mode (clock mode or standby mode) before the reset or the reset factor. For thisreason, if a reset occurs while main clock oscillation is halted or during the main clock oscillationstabilization wait time, switching to the reset state will occur to wait for main clock oscillationstabilization.

When performing a software reset or watchdog reset, no oscillation stabilization wait time isrequired during the operation in the main clock mode.

Table 3.5-2 shows the relationship among reset factors, the wait time for main clock oscillationstabilization and reset operation (mode fetch).

Table 3.5-2 Reset Factors and Oscillation Stabilization Wait Times

Reset Factor Operating State Reset operation and Oscillation stabilization wait time of main clock

External reset*1 Power-on, stop mode If the external reset is released after the oscillation stabilization wait time,

the reset sequence is executed. *2

Software reset andwatchdog reset

Main clock mode A reset operation takes place after resets are generated for four instruction

cycles. *3

Power on reset A reset operation takes place when the main clock oscillation stabilization

wait time elapses after power-on. *2

*1: No waiting for oscillation stabilization is required when an external reset occurs during the operation in the main clock mode. The reset operation is performed after the external reset is released.

*2: During the main clock oscillation stabilization wait time, the "L" level output is made to the terminal.*3: The pin outputs an "L" level during the four instruction cycles.

42

CHAPTER 3 CPU

3.5.1 External Reset Pin

Inputting an "L" level to the external reset pin generates a reset.An internal reset factor causes the L level output.

Block Diagram of External Reset PinThe external reset terminal (RST) of the reset output ON models is set hysteresis input and Nchopen drain output with pull-up.

Figure 3.5-1 shows Block Diagram of External Reset Pin

Figure 3.5-1 Block Diagram of External Reset Pin

Function of External Reset PinInputting an "L" level to the external reset pin (RST) generates the internal reset signal.

An "L" level is output if an internal reset occurs and during the oscillation stabilization delay timefollowing a reset. Internal reset triggers include the software reset, watchdog reset, and power-onreset.

Note

An externally initiated reset is accepted asynchronously regardless of the internal clock.

Also, the clock is required to initialize the internal circuits.

An input of a reset pulse below the specified level to the external reset terminal (RST) may causemalfunctions. Be sure not to allow an input of a reset pulse below the specified level to the externalreset terminal (RST).

Pull - up resistanceApprox. 50 k (at 5V)

Pin

RST

Internal reset source

Pch

Nch

Input buffer

Internal reset signal

43

CHAPTER 3 CPU

3.5.2 Reset Operation

When a reset is cancelled, the CPU reads the mode data and reset vector from the internal ROM in accordance with the mode terminal setting (mode fetch). After power-on, mode fetch is performed to process a return from the stop mode using a reset after the oscillation stabilization wait time elapses. The contents of RAM are not guaranteed after a reset.

Overview of Reset Operation

Figure 3.5-2 Reset operation flow

External reset input

Capturing of mode data

Capturing of reset vector

Capture the instruction code from address

showed by reset vector and execute the instruction.

External reset release

YES

During reset

Mode fetch(Reset operation)

Normal operation(RUN state)

Power - on resetSoftware resetWatchdog reset

In powering on orduring stop mode

YES

Main clockoscillation stabilization

wait reset state

NO

NO

Main clockoscillation stabilization

wait reset state

Regulator recovery time

Regulatorrecovery time

Regulator stabilization time

44

CHAPTER 3 CPU

Mode PinMB89051: Only single-chip mode. Always set the mode pin (MOD0,MOD1,MOD2) to "VSS".

Select internal ROM as the location from which to read the mode data and reset vector. Do notchange the mode pin setting even after reset operation completes.

Mode FetchWhen a reset is cancelled, the mode data and reset vector are read from the internal ROM.

Mode data (address: FFFDH)

For mode data, be sure to set the single-chip mode (00H).

Reset vector (address: Upper FFFEH/Lower FFFFH)

Write the address from which execution is to restart after a reset. Instruction execution starts fromthe address specified here.

Oscillation Stabilization Waiting reset stateA reset during power-on and a reset initiated by an external reset during the stop mode takesplace after the oscillation stabilization wait time elapses. If the external reset input is not clearedat this time, the reset is not performed until the reset is cleared.

Since the oscillation stabilization wait time is needed, an external clock input is required during areset.

Oscillation stabilization waiting time of main clock is made by time base timer.

Regulator recovery timeThe MB89051 Series models have a built-in step-down circuit for operation at 3 volts. The step-down circuit consumes least power in the stop mode. The regulator recovery time, the timerequired before the step-down circuit resumes normal operation, is at least 20 ms.

Regulator stabilization timeThe regulator stabilization time in addition to the oscillation stabilization time is required during apower-on reset. The voltage supplied to the power supply terminal must reach the minimumoperating voltage within the regulator stabilization time. The regulator stabilization time must be at

least 219/FCH depending on the oscillation clock. FCH main clock oscillation.

Effect of a reset on RAM contentsAn external reset is not synchronized with the internal clock but directly initiates an internal reset.The RAM contents may be changed before and after the reset. Be sure, therefore, to initializeRAM before using it.

45

CHAPTER 3 CPU

3.5.3 State of Each Pin at Reset

The state of each pin is initialized by a reset.

Pin status during resetIf a reset factor occurs, all I/O terminals (resource terminals) with some exceptions switch to highimpedance state and the mode data are read into the internal ROM.

State of Pins after Mode Data ReadMost I/O terminals remain in high impedance state immediately after mode data reading.(terminals for which pull-up resistor was selected in the pull-up option setting register are set to"H" Level.)

Note

Ensure that any external devices connected to pins that go to high impedance when a reset ispresent do not misoperate in this case.

46

CHAPTER 3 CPU

3.6 Clock

A clock is generated by connecting a resonator externally. A clock is first input to the clock controller, then it is multiplied by the PLL circuit and divided into the CPU operation clock and peripheral circuit operation clock. The supply of these operation clocks is controlled in accordance with the operation mode setting and low power consumption mode setting.

Clock Supply MapThe oscillation of the clock and the supply of its signal to the CPU and peripheral circuits(resources) are controlled by the clock controller. The operation clocks of the CPU and peripheralcircuits are under the influence of the standby mode (sleep or stop).

The divided output of the free-run counter which operates using the peripheral circuit clock ispassed to the various peripheral functions. However, peripheral functions to which CLK1 andCLK2 clock output and divide-by-output of the time-base timer are supplied are not under theinfluence of the gear function.

The USB function section and the hub block section operate on a clock multiplied by 8 by the PLLcircuit (48 MHz) and the divide-by-four clock (12 MHz).

Figure 3.6-1 shows the clock supply map.

47

CHAPTER 3 CPU

Figure 3.6-1 Clock Supply Map

Divide by 4

Divide by 8

Divide by 16

Divide by 64

Timebase timer

Supply to CPU

Supply to

peripheral circuit

1tinst

1tinst

Freerun counter

SIO/UART

Oscillationstabilizationwait circuit

Watchdogtimer


Pin

Pin

X0

X1FCH

3

3

2

PinSCK

Clock control

Pripheral function

1

1, 3

FCH : Main clock oscillationFusb : USB clock oscillationtinst : Instruction cycle 1: Not affected by clock mode or gear function. 2: Operating speed is affected by clock mode or gear function. 3: Stops operation the moment the clock providing source oscillation stops. 4: Be sure to use gear at the highest speed.

Divide by 2

Gear function

Stoposcillation stabilization wait

Stop

PinCLK1

PinCLK2

2

8-multiplier

Fusb

USB-HUB4

8 bits serialI/O

2

2

2

2

2

1

USB-FUNCTION

4

Baud rate clockgenerating circuit

PinSCK1 SCK2

High-speed baud rate generating circuit

oscillatorcircuit

Oscillation

control

PLL

PinSCLI2C

Divide by 4

48

CHAPTER 3 CPU

3.6.1 Clock generation block

The stop mode is used to control the enabling and disabling of main clock oscillation.

Clock generation blockMake a connection as shown in Figure 3.6-2 when using a crystal resonator.

Figure 3.6-2 Example of connecting to crystal oscillation

X0 X1

C C

Main clockoscillator circuit

49

CHAPTER 3 CPU

3.6.2 Clock control block

The clock controller consists of the following six blocks:• Main clock oscillation circuit• System clock selector• Clock controller circuit• Oscillation stabilization wait time selector• System clock control register (SYCC)• Standby control register (STBC)

Block Diagram of clock control unitFigure 3.6-3 shows the block diagram of the clock controller.

Figure 3.6-3 Block Diagram of clock control unit

Standby control register (STBC)

System clock control register (SYCC)

oscillation stabilizationwait timeselector


Clock supply stopto CPU

Pin state

Stop

Sleep

Clock forTimebase timer

Supply to CPU

Supply toperipheral circuit

Prescaler

214 FCH

217 FCH

218 FCH

Divide by 4

Divide by 8

Divide by 16

Divide by 64

Selector

STP SLP SPL RST

CS1 CS0WT0WT1

System clock selectorMain clock control

2

FormTimebasetimer

FCH: Main clock oscillationtinst: Instruction cycle

clockcontroller circuit

Operationenable

1tinst

1tinst

Divide by 2

FCH

50

CHAPTER 3 CPU


Oscillation circuit in the main clock. Oscillation is stopped in main stop mode.

Clock controller circuit

Used to control the supply of the operation clocks of the CPU and each peripheral circuit inaccordance with the normal operation mode (RUN) setting and each standby mode setting (sleepor stop).

The clock supply to the CPU remains halted until the clock supply halt signal to the oscillationstabilization delay time selector is released.

Oscillation stabilization wait time selector

Used to select one of three clock oscillation stabilization wait time options created by the time-base timer in accordance with the standby mode and reset setting and to output it as the clocksupply stop signal to the CPU.

System clock control register (SYCC)

Used to select the speed and the oscillation stabilization wait time of the main clock.


Used to switch from the normal operation mode (RUN) to the standby mode, to set the terminalstate during the stop mode and to perform a software reset.

System clock selector

Used to select one of four clocks created by dividing the main clock oscillation and to supply theclock to the clock control circuit.

51

CHAPTER 3 CPU

3.6.3 System clock control register (SYCC)

The system clock control register (SYCC) is used to select the main clock speed and the oscillation stabilization wait time.

Structure of system clock control register (STBC)

Figure 3.6-4 Structure of system clock control register (STBC)


0 0 0 7H

Address

XXX11X00B

Initial value

WT1 WT0 CS0CS1

R/W

WT1

Oscillation stabilization wait time select bit

Main clock Oscillation stabilizationwait time by Timebase timer output

(at FCH=12MHz)

0

0

1

1

WT0

0

1

0

1

Setting disabled

Approx. 214 /FCH (Approx.1.36ms)

Approx. 217/FCH (Approx.10.9ms)

Approx. 218 /FCH (Approx.21.8ms)

CS1Main clock speed selection bit

Instruction cycle(at FCH=12MHz)

CS0

64/FCH (5.3 µs)

16/FCH (1.3 µs)

8/FCH (0.6 µs)

4/FCH (0.3 µs)

FCH: Main clock Oscillation

R/W X

: Readable and Writable: Unused : Undefined: Initial value

R/W

0

0

1

1

0

1

0

1

R/W R/W

52

CHAPTER 3 CPU

tINST: Instruction cycle (tinst)The instruction cycle (minimum execution time) can be selected from 1/4, 1/8, 1/16 and 1/64 ofthe main clock frequency using the main clock selection bits (CS1 and CS0) of the SYCCregister.

The instruction cycle at the maximum speed (SYCC: CS1, CS0=11B) is 4/FCH = approx. 0.33 µs if

the main clock oscillation (FCH) is set to 12 MHz.

Be sure to set the instruction cycle to 1/4 of the frequency before enabling the USB circuitfunction.

Table 3.6-1 Bit functional description of system clock control register (SYCC)

Bit name Function

Bit7 Bit6 Bit5

Unused bit • This bit is undefined when it is read.• Nothing is affected when it is written.

Bit4 Bit3

WT1, WT0: Oscillation stabilization wait timeselect bit

• This is a bit to select Clock Oscillation Stabilization Wait Time of themain clock.

• The oscillation stabilization wait time option selected by these bits isused to make a return from the main stop mode to the normal operationmode using an external interruption.

• The initial values of these bits are WT1=1 and WT0=1.

Bit2 Unused bit Note: Be sure to always set them to "1".

Bit1Bit0

CS1, CS0: Clock speed selection bit

• These bits are used for selecting the clock speed.• Four different operating clock speeds can be selected for the CPU and

each peripheral resource. (Gear function) However, it should be notedthat the clock using the time-base timer is not influenced by these bits.

53

CHAPTER 3 CPU

3.6.4 Clock Mode

The main clock speed can be switched by selecting a clock from among four clocks created by dividing the source oscillation frequency.

Operation states in clock modes

The device can change to the respective standby modes from each clock mode. Refer to "3.5

Reset" about standby mode.

Operation of the main clock modeSpecifying the standby mode causes a transition to the sleep mode or the stop mode.

When a reset of any type occurs, the operation always starts in the main RUN mode (cancellationof each operation mode by a reset).

Table 3.6-2 Operation states in clock modes

Clock mode

Main clock speed SYCC register (CS1, CS0)

StandbyMode

Clock Operation Clock Standby mode release source (Excluding Reset)

CPU Time-base timer

Each resource

Main Clock mode

(1.1) Fast RUN Oscillation FCH /4 FCH /2 FCH /4 Interrupt requests

Sleep Stop

Stop Stop Stop Stop External interrupt, USB interrupt

(1.0) RUN Oscillation FCH /8 FCH /2 FCH /8 Interrupt requests

Sleep Stop



Sleep Stop



Sleep Stop

Slow Stop Stop Stop Stop External interrupt, USB interrupt

FCH: main clock oscillation

54

CHAPTER 3 CPU

3.6.5 Oscillation Stabilization Wait Time

The main clock oscillation stabilization wait time is required to switch to the main RUN mode during power-on, during the main stop mode or while the main clock is stopped.

Oscillation Stabilization Wait TimeTransducers such as quartz crystal generally require several milliseconds to several dozenmilliseconds to stabilize at the specified frequency (oscillation frequency) after oscillation starts.

Accordingly, CPU operation is disabled immediately after the oscillation restarts and the clocksupply to the CPU is not re-enabled until the oscillation stabilization delay time has elapsed. Thisgives the oscillation time to stabilize.

As the time required for the oscillation to stabilize depends on the type of resonator (crystal orceramic, etc.) connected to the oscillator (clock generator), select an oscillation stabilization delaytime that is suitable for the using resonator.

Figure 3.6-5 shows the operation of the oscillation immediately after starting the oscillation.

Figure 3.6-5 Operation of oscillator immediately after oscillation starts

Main Clock Oscillation Stabilization Wait TimeTo start operation in the main clock mode from the state in which the main clock oscillation isstopped, the main clock stabilization wait time is required.

The oscillation stabilization delay time of main clock is the time from the time-base timer startingto count up after the counter being cleared until the specified bit overflows.

Oscillation Stabilization Wait Time during operation

One of three oscillation stabilization wait time options can be selected using the oscillationstabilization wait time selection bits of the system clock control register (SYCC: WT1 and WT0) toreturn to the main RUN mode from the main stop mode using an external interruption.

Oscillation Stabilization Wait Time when resetting

The oscillation stabilization wait time (initial value of WT1 and WT0) to be taken at resets is fixed.

The oscillation stabilization wait time is required for a power-on reset and the cancellation of thestop mode using an external reset.

Oscillation stabilizationwait time

Normal operatingRecovery from stop modeor reset operation

Oscillation start

X1

Oscillation Stabilization

Oscillationr time of resonator

55

CHAPTER 3 CPU

Table 3.6-3 Conditions for Starting the Operation in the Main Clock Mode and Required Oscillation Stabilization Wait Time

Main clock mode operation startcondition

At power on Cancellation of stop modes

External reset External interrupt

USB Interrupt

Select oscillation Stabilization Wait Time SYCC:WT1=1, WT0=1* SYCC:WT1, WT0*

*: Oscillation stabilization wait time selection bit of system clock control register

56

CHAPTER 3 CPU

3.7 Standby mode (low power consumption)

Standby mode includes sleep mode and stop mode.Use the standby control register (STBC) to change to a standby mode.In the main clock mode, a transition can be made to two modes; the sleep and stop modes.The standby modes reduce power consumption by halting the CPU and peripheral functions.This describes the relationship between the standby modes and clock modes, and the operation of each block during standby mode.

Standby ModeIn the standby mode, power consumption is reduced by the clock control section by stopping thesupply of the clock to the CPU (sleep mode) or by stopping the source oscillation (stop mode).

Sleep mode

The sleep mode halts the CPU and watchdog timer operation but peripheral functions areoperated using the main clock.

Stop mode

The stop mode halts the CPU and peripheral function operations as well as all functions with theexceptions of the external interruption and USB interruption.

57

CHAPTER 3 CPU

3.7.1 Operation status in standby mode

This describes the operation of the CPU and peripheral functions during standby mode.

Operation status in standby mode

State of pins in standby mode

Regardless of the clock mode, almost all I/O terminals can retain the state that immediatelypreceded a transition to the stop mode or can be set in high impedance state using the terminalstate specification bit of the standby control register (STBC: SPL).

Table 3.7-1 Operation of the CPU and peripheral functions during standby mode

Operating mode Main clock mode

Function RUN Sleep Stop (SPL = 0) Stop (SPL = 1)

Main clock Operation Operation Stop Stop

CPU Instruction Operation Stop Stop Stop

ROM Operation Hold Hold Hold

RAM Operation Hold Hold Hold

Resource I/O port Operation Hold Hold Hold

Time-base timer Operation Operation Stop Stop

Watchdog timer Operation Stop Stop Stop

8-bit PWM timer 1, 2 Operation Operation Stop Stop

UART/SIO Operation Operation Stop Stop

8-bit serial input/output

Operation Operation Stop Stop

External interrupt Operation Operation Operation Operation

USB hub functions Operation Operation Stop Stop

Pin Operation Hold Hold Hi-Z

Setting disabled Reset Interrupt Reset Interrupt Reset Interrupt Reset Interrupt

58

CHAPTER 3 CPU

3.7.2 Sleep mode

Operations Relating to Sleep Mode are explained.

Operations Relating to Sleep Mode

Transition to Sleep Mode

The sleep mode stops the operating clock for the CPU. In sleep mode, the operating clock forCPU is stopped. Although the CPU stops storing data in the registers and RAM used immediatelybefore transition to sleep mode, peripheral functions, excepting the watchdog timer, continue tooperate.

Writing "1" to the sleep bit in the standby control register (STBC:SLP) changes to sleep mode. If"1" is written to the SLP bit when an interrupt request is present, the write is ignored andinstruction execution continues without changing to sleep mode (does not change to sleep modeeven after handling the interrupt).

Cancellation of sleep modes

The sleep mode is canceled by a reset or an interrupt from a peripheral resource.

No oscillation stabilization wait time is required for a reset in the sleep mode.

Pin states are initialized by the reset operation.

If an interrupt request with an interrupt level higher than "11" occurs from a peripheral function oran external interrupt circuit during sleep mode, the CPU wakes up from sleep mode, regardless ofthe interrupt enable flag (CCR: I) and interrupt level bits (CCR: IL1 and IL0) in the CPU.

Normal interruption operation is performed after the cancellation of the sleep mode. If interruptionrequests are accepted, interruption processing is executed. If interruption requests are notaccepted, the instruction that comes after the instruction executed immediately preceding atransition to the sleep mode is executed.

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CHAPTER 3 CPU

3.7.3 Stop mode

This section describes the stop mode.

Operation in stop mode

Transition to stop mode

Stop mode halts the source oscillation. In stop mode, the source oscillation is stopped. Mostfunctions stop storing data in the registers and RAM used immediately before transition to stopmode.

In the main clock mode, the main clock oscillation stops. Peripheral function units and the CPUstop the operation excluding the operation of the external interruption circuit and the USBinterruption circuit. Therefore, power consumption for data retention can be minimized.

Writing "1" to the stop bit in the standby control register (STBC:STP) changes to stop mode. If theterminal state specification bit (STBC: SPL) is set to Åg0Åh, the external terminal state isretained. If it is set to Åg1Åh, on the other hand, the external terminal is switched to highimpedance state (H Level for the terminals for which pull-up resistor was selected in the pull-upsetting register).

If an interrupt request is generated when "1" is written to the STP bit, the write to the bit isignored, and the CPU continues the instruction execution without change to stop mode. (TheCPU does not assume stop mode even after completion of the interrupt processing.)

For a transition to stop mode, prohibit the time base timer interrupt request output (TBTC: TBIE =0) when necessary.

Cancellation of stop modes

The stop mode is canceled using a reset, external interruption or USB interruption.

If a reset occurs in the stop mode, a reset operation takes place when the main clock oscillationstabilization wait time elapses.

Pin states are initialized by the reset operation.

When an interrupt request with an interrupt level higher than 11 is generated in an externalinterrupt circuit in stop mode, stop mode is cancelled regardless of the CPU interrupt enable flag(CCR: I) or interrupt bit level (CCR: IL1 and IL0). Since peripheral function units are stopped inthe stop mode, no interruption requests other than external interruptions and USB interruptionsoccur.

Normal interruption operation is performed when the oscillation stabilization wait time elapsesafter the cancellation of the stop mode. If interruption requests are accepted, interruptionprocessing is executed. If interruption requests are not accepted.

When an external interrupt cancels stop mode, part of the peripheral functions are restarted withdata stored before the beginning of stop mode. Therefore, the initial interval of the interval timerand other similar settings are rendered unknown. The peripheral functions must be initialized afterreturning from stop mode.

Reference

The stop mode can only be cancelled using the interruption request from the external interruptioncircuit and the USB interruption circuit.

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CHAPTER 3 CPU

3.7.4 Standby control register (STBC)

The standby control register (STBC) controls transition to sleep/stop modes, pin state settings in stop mode, and software reset.


Figure 3.7-1 Standby control register (STBC)

STP


0 0 0 8H

Address

0001XXXXB

Initial value

SPL

W R/W

SLP RST

STPStop bit

"0" is always read. No effect for operating

Shift to stop mode

0

1

Read Write

W W

SLPSleep bit

"0" is always read. No effect for operating

Shift to sleep mode

0

1

Read Write

SPL Pin state specification bit

External pins hold their status prior to entering stop mode.

External pins go to high-impedance state on entering stop mode.

0

1

RSTSoftware reset bit

"1" is always read.

Generate the reset signalof 4-instruction cycle

No effect for operating1

Read Write

0

R/WW

X

: Readable and Writable: Write only: Unused: Undefined: Initial value

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CHAPTER 3 CPU

Table 3.7-2 Bit functional description of standby control register (STBC)

Bit name Function

Bit7 STP: Stop Bit

• This bit specifies transition to stop mode.• Writing "1" to the bit places the CPU in stop mode.• Writing "0" has no effect.• Reading operations always return "0" for this bit.

Bit6 SLP: Sleep bit

• This is a bit to specify a transition to Sleep Mode.• Writing "1" to the bit places the CPU in sleep mode.• Writing "0" has no effect.• Reading operations always return "0" for this bit.

Bit5 SPL: Pin statespecificationbit

• This bit specifies external pin states in stop mode.• Writing "0" to the bit specifies that external pin states (levels) are held when the CPU enters

the stop mode.• When this bit is set to "1", the external terminal is switched to high impedance state during a

transition to the stop mode ("H" Level for the terminals for which pull-up resistor was selectedin the pull-up setting register).

• This bit becomes "0" after a reset.

Bit4 RST: Softwarereset bit

• This bit specifies software reset.• Writing "0" to the bit generates an internal reset source for four instruction cycles.• Writing "1" has no effect.• Reading operations always return "0" for this bit.

Bit3 Bit2Bit1Bit0

Unused bit • Be sure to always set it to "1".• This bit is undefined when it is read.• Nothing is affected when it is written.

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CHAPTER 3 CPU

3.7.5 State Transition Diagram

Figure 3.7-2 shows the state transition diagram.This shows the transition to and the reset and cancellation of the each state.

State Transition Diagram

Figure 3.7-2 State Transition Diagram

Main clock mode

Main sleepstate

Main RUNstate

Main stopstate

Main clockoscillation

stabilizationwait

Reset stateOscillation

stabilization waitreset state

Power on

Power - on reset

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CHAPTER 3 CPU

Transition to and reset of the normal state (RUN)

Transition to and cancellation of standby mode

Table 3.7-3 Transition to and Reset of the Main Clock Mode RUN State

State transition Transition conditions (Figure 3.7-2 )

Normal after power onMove to (RUN)

[1] End of oscillation stabilization wait time of main clock (Time base timer output) [2] Cancellation of reset input

Reset in RUN mode [3] External reset, software reset Watchdog reset

Table 3.7-4 Transition to and cancellation of standby mode

State transition Transition conditions (Figure 3.7-2 )

Transition to Sleep Mode [1] STBC:SLP=1

Cancellation of sleep modes [2] Interrupt (each type)[3] External reset

Transition to stop mode [4] STBC:STP=1

Cancellation of stop modes [5] External interrupt, USB interrupt[6] End of oscillation stabilization wait time of main clock (Time base timer)[7] External reset[8] External reset (Oscillation stabilization waiting)

STBC: Standby control register (STBC)

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CHAPTER 3 CPU

3.7.6 Notes on using the standby mode

The CPU does not change to a standby mode if an interrupt request occurs from a peripheral function when a standby mode is set in the standby control register (STBC). When an interruption causes a return from the standby mode to the normal operation state, the operation that follows varies depending on whether interruption requests can be accepted.

Transition to Standby Mode and InterruptIf an interrupt request with an interrupt level higher than "11" occurs from a peripheral function tothe CPU, writing "1" to the stop bit (STP), or sleep bit (SLP) in the standby control register(STBC) is ignored. Therefore, the CPU does not change to a standby mode. (The CPU also doesnot change to the standby mode after completing interrupt processing.)

This has nothing to do with whether the CPU accepts interruptions.

Even when the CPU is currently performing interrupt processing, the device can go to the standbymode if no other interrupt request is present with the interrupt flag bit cleared.

Cancellation of Standby Mode by InterruptThe standby mode is canceled if an interrupt request with an interrupt level higher than "11"occurs from a peripheral resource in sleep or stop mode. This has nothing to do with whether theCPU accepts interruptions.

The normal interruption operation after the cancellation is as follows. If the priority of theinterruption level setting register (ILR1 to ILR3) for an interruption request is higher than theinterruption level bit value of the condition code register (CCR: IL1, 0) and the interruption-enableflag is set to enable (CCR: I=1), a branching to the interruption processing routine takes place.However if the interruption request is not accepted, the operation restarts from the instruction thatcomes after the instruction that activated the standby mode.

To prohibit a branch to the interrupt processing routine immediately after return, interrupts mustbe prohibited before standby mode is set.

Notes on Setting Standby ModeUse the standby control register (STBC) settings listed in Table 3.7-5 to change to standby mode.Although the order of precedence as to which mode will be activated if more than one bit is set to1 is stop mode and sleep mode, it is best to set just one bit to "1".

Table 3.7-5 Using the standby control register (STBC) to change to a low power consumption mode.

STBC register Mode

STP(bit7) SLP(bit6)

0 0 Normally

0 1 Sleep

1 0 Stop

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CHAPTER 3 CPU

Oscillation Stabilization Wait TimeThe oscillator for source oscillation stops in stop mode, thus oscillation stabilization wait timemust be applied after the oscillator is activated.

One of three main clock oscillation stabilization wait time options created by the time-base timeris selected.

If the interval selected for the time base timer is shorter than the oscillation stabilization wait time,an interval timer interrupt request is generated during oscillation stabilization wait time. Beforeswitching to the stop mode from the main clock mode, disable the output of the interruptionrequest from the time-base timer, if necessary (TBTC: TBIE=0).

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CHAPTER 3 CPU

3.8 Memory Access Mode

Only the single-chip mode is related to memory access. No other operation modes are related.

Single-chip modeIn single-chip mode, only internal RAM and ROM are used. Therefore, the CPU can only access(internal access) the internal I/O area, RAM area and ROM area.

Mode pin (MOD0,MOD1,MOD2) Be sure to set the mode pin (MOD0,MOD1) to "VSS".

Mode data and reset vector are read from internal ROM at a reset.

Do not change the settings for mode pins even after the reset operation is completed (or beingperformed). Table 3.8-1 lists the mode pin settings.

Mode DataSet 00H into the mode data in internal ROM to select single-chip mode.

Figure 3.8-1 shows the mode data configuration.

Figure 3.8-1 Construction of mode data

Operations for Selecting Memory Access ModeOnly single-chip mode is selectable.

Table 3.8-2 shows mode pin and mode data and Figure 3.8-2 shows operating of memory access

Table 3.8-1 Setting of Mode Pins

Pin state Description

MOD0 MOD1 MOD2

VSS VSS VSS Read the mode data and reset vector from the internal ROM.

Combinations other than those shown above Setting disabled

Data

00H

Other than 00H

Operation

Single - chip mode selection

Reserved, not to set

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0AddressF F F DH

67

CHAPTER 3 CPU

selection.

Figure 3.8-2 Operation of memory access selection

Table 3.8-2 Mode pin and mode data

Memory Access Mode Mode Pin (MOD0, MOD1, MOD2) Mode Data

Single-chip mode VSS, VSS, VSS 00H

Other modes Setting disabled Setting disabled

Reset factor generation

Mode pin(MOD1,0,2)

Other

Check mode pin

Reset factor release wait

Set I/O pin functions for program execution (RUN) state.

Mode fetch

Check mode data

Settingprohibited

Settingprohibited

Vss,Vss,Vss

Mode data is read to internal ROM

Single - chip mode

I/O pinhigh impedance

During reset

Capture the mode data andreset vector from internal ROM

Single - chip mode (00H)

Mode data

I/O setting of I/O pin by port direction register(DDR) etc.

Using enabled I/O pin as port

Other

External reset oroscillation stabilization wait time

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CHAPTER 4I/O Port

This chapter describes the function and operation of the I/O port.

4.1 Overview of I/O Ports

4.2 Port 0

4.3 Port 1

4.4 Port 2

4.5 Port 3

4.6 Port 4

4.7 Port 5

4.8 I/O Port Programming Example

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CHAPTER 4 I/O Port

4.1 Overview of I/O Ports

The I/O ports can be used as five (37 channels) general-purpose I/O ports.Port 3 also serves as a resource terminal (I/O terminal for various peripheral function units).

Functions of I/O PortsThe I/O ports function to output data from the CPU to I/O pins via their port data register (PDR)and send signals input to I/O pins to the CPU. For some ports, the I/O direction of I/O pins can beset by optionally setting the bits of the port data direction register (DDR), with the bitscorresponding to the pins.

The functions of the ports and peripherals for which the ports may serve are summarized below.

• Port 0: General-purpose I/O ports



• Port 3: Serves as a general-purpose I/O port/resource (external interruption, SIO1, SIO2)

• Port 4: Serves as a general-purpose I/O port/resource (UART/SIO, PWM, and power control)


Table 4.1-1 shows list of each port function. Table 4.1-2 shows registers of each port.

Table 4.1-1 List of Each Port Functions (Continued)

PortName

Pin Name Input Type OutputType

Function Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Port 0 P00 to P07 CMOS CMOSpush-pull

General-purpose I/O ports

P07 P06 P05 P04 P03 P02 P01 P00

Port 1 P10 to P17 General-purpose I/O ports

P17 P16 P15 P14 P13 P12 P11 P10

Port 2 P20 to P27 General-purpose I/O ports

P27 P26 P25 P24 P23 P22 P21 P20-

Port 3 P31/INT1to P37/INT7

CMOS Resource isHysteresis.


P37 P36 P35 P34 P33 P32 P31 -

External interrupt INT7 INT6 INT5 INT4 INT3 INT2 INT1 -

SIO1, SIO2 SI2 SO2 SCK2 SCK1 SO1 SI1 - -

Port 4 P40/POW5to P47/PWM2

CMOS *1, *2


P47 P46 P45 P44 P43 P42 P41 P40

UART/SIO - UI UO UCK POW4 POW3 POW2 POW5

PWM PWM2 PWM1 - - - - - -

Port 5 P53, P54 CMOS CMOS *2

push-pull


- - - P54 P53 - - -

*1: Resource of P44 and P46 is hysteresis input.*2: Nch open drain output at P46, P47, P53, P54.

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CHAPTER 4 I/O Port

Table 4.1-2 Registers of Each Port

Register Name Read/Write Address Initial value

Port 0 data register (PDR0) R/W 0000H XXXXXXXXB

Port 0 direction register (DDR0) * W 0001H 00000000B


Port 1 direction register (DDR1) * W 0003H 00000000B


Port 2 direction register (DDR2) R/W 0006H 00000000B

Port 3 data register (PDR3) R/W 000CH XXXXXXXXB

Port 3 direction register (DDR3) R/W 000DH 00000000B


Port 4 direction register (DDR4) R/W 0011H 00000000B

Port 5 data register (PDR5) R/W 0012H XXX11XXXB

R/W: Readable and WritableW : Write onlyX: Undefined*: DDR0 and DDR1 cannot be used for bit operation instruction.

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CHAPTER 4 I/O Port

4.2 Port 0

Port 0 is a general-purpose I/O port.This section also describes the structure, pins, and associated registers of port 0 and provides a block diagram of pins.

Configuration of Port 0Port 0 is comprised of the three elements shown below.

Port 0

• I/O pins (P00 to P07)

• Port 0 data register (PDR0)

• Port 0 direction register (DDR0)

A pin at port 0Port 0 has eight CMOS I/O terminals.

Table 4.2-1 lists the port 0 pins.

Refer to "1.7 Pin Description" about circuit types.

Table 4.2-1 A pin at port 0

Port Name Pin Name Function I/O Type Circuit Form

Input Output

Port 0 P00 P00 General-purpose I/O CMOS CMOS B

P01 P01 General-purpose I/O







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CHAPTER 4 I/O Port

Block Diagram of Port 0

Figure 4.2-1 Block Diagram of Pins of Port 0

Port-0 registers (PDR0, DDR0)Port 0 has two related registers, PDR0 and DDR0.

The bits of these registers correspond to the pins of port 0 in one-to-one correspondence.

Table 4.2-2 shows the correspondence between the registers and pins of port 0.

PDR read (for a bit manipulation instruction)

PDR write

Output latch

Stop (SPL=1)

PDR (Port data register)

Pin

Pch

Nch

PDR read

Stop mode

SPL: Pin state specification bit of the standby control register (STBC)

Internal Data B

us

Pch

DDR

DDR write(Port direction register)

(Pull-up option setting register)

Table 4.2-2 Relation between port 0 registers and pins

PortName

Bits of Related Registers and Corresponding Pins

Port 0 PDR0, DDR0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00

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CHAPTER 4 I/O Port

4.2.1 Port-0 registers (PDR0,DDR0)

This section describes the registers associated with port 0.

Port 0 register function

Port 0 data register (PDR0)

The PDR0 register shows the terminal state. For this reason, although the terminal designated asan output port can read out the same value as the output latch value ("0" or "1"), it cannot readout the output latch value when it is designated as an input port.

Reference

Since the bit operation instruction (SETB and CLRB) reads out the output latch value, not theterminal value, the output latch values of the bits other than the bits used for operation will notchange.

Port 0 direction register (DDR0)

The DDR0 register sets the I/O direction of each pin per bit.

When a bit of the DDR0 corresponding to a pin of port 0 is set to "1", the pin functions as anoutput port. When the bit is set to 0, the pin functions as an input port.

Table 4.2-3 shows the functions of the registers for port 0.

R/W: Read/WriteX: UndefinedW: Write only

Table 4.2-3 Port 0 register function

Register Name Data Whenbeing read

When being written Read/Write

Address Initial value

Port 0 dataregister (PDR0)

0 Pin state is "L" level

Output latch of "0" is set and "L" level isoutput to the pin in output port mode.

R/W 0000H XXXXXXXXB

1 Pin state is "H" level

Output latch of "1" is set and "H" level isoutput to the pin in output port mode.

Port 0 directionregister (DDR0)

0 Input portState

The pin is set to function as input pin withoutput transistor operation disabled.

W 0001H 00000000B

1 Output portState

The pin is set to function as output pin withoutput transistor operation enabled.

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CHAPTER 4 I/O Port

4.2.2 Operation of port 0

This section describes the operation of port 0.

Operation of Port 0

Operation in output port mode

When "1" is written for a bit of the DDR0 register, the bit corresponding to a pin of port 0, the pinfunctions as an output port.

In output port mode, the output transistor operation is enabled and the output latch data is outputto the pin.

Once data has been written into the PDR0 register, the written data is held in the output latch andoutput to the pin as is.

The terminal value can be read out by reading out the PDR0 register.

Operation in input port mode

When "0" is written for a bit of the DDR0 register, the bit corresponding to a pin of port 0, the pinfunctions as an input port.

When the pin serves as an input port, the output transistor is "OFF" and the pin remains in a highimpedance state.

Once data has been written into the PDR0 register, the written data is held in the output latch butis not output to the pin.

The terminal value can be read out by reading out the PDR0 register.

Operation when a reset is performed

• When the CPU is reset, the bits of the DDR0 register are initialized to "0". Accordingly, theoutput transistor turns "OFF" (input port) and the pin goes to high impedance.

• CPU resets do not initialize the PDR0 register. For this reason, to use Port 0 as an output port,setting output data in the PDR0 register is required before setting the corresponding DDR0register as the output.


If the pin state bit in the standby control register (STBC:SPL) is set to "1" when the device goes tostop mode, the pins go to high impedance. because the output transistor is turned OFFregardless of the value existing on the DDR0 register in the bit position corresponding to the pin.Input remains fixed to prevent leaks by input open.

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CHAPTER 4 I/O Port

Table 4.2-4 shows the state of the port 0 pins.

Reference

When pull-up resistor was selected in the pull-up option setting register, the terminal state in the stopmode (SPL=1) switches to "H" Level (pull-up state), but not to high impedance state. However, itshould be noted that the pull-up process during a reset will be disabled and becomes Hi-Z.

Table 4.2-4 Port 0 pin status

Pin Name Normal OperationSleepStop (SPL = 0)

Stop (SPL = 1) At a reset

P00 to P07 Pin state designating bit of standby control register

General-purpose I/O ports Hi-Z Hi-Z

STBC: SPLHi-Z: High impedance

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CHAPTER 4 I/O Port

4.3 Port 1

Port 1 is a general-purpose I/O port and also works as an input pin.This section also describes the structure, pins, and associated registers of port 1 and provides a block diagram of pins.


• General-purpose I/O pins (P10 to P17)







PortName

PinName

Function I/O Type Circuit Type

Input Output









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CHAPTER 4 I/O Port



Port-1 registersPort 1 has two related registers, PDR1 and DDR1.



PDR read

PDR write

Output latch

Stop (SPL=1)


Pin

Pch

NchDDR

PDR read

Stop mode

DDR write

Pch

(Port direction register)


From Pull - up option setting register

Internal Data B

us

(for a bit manipulation instruction)

Table 4.3-2 The correspondence between the registers and pins of port 1

PortName




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CHAPTER 4 I/O Port

4.3.1 Registers for Port 1 (PDR1, DDR1)


Function of Registers for Port 1



Reference




When a bit of the DDR1 corresponding to a pin of port "0" is set to "1", the pin functions as anoutput port. When the bit is set to 0, the pin functions as an input port.


Table 4.3-3 Function of Registers for Port 1

Register Name Data Whenbeing read



Port 1 dataregister (PDR1)

0 Pin state"L" level


R/W 0002H XXXXXXXXB

1 Pin state"H" level


Port 1 directionregister (DDR1)

0 Input portstate


W 0003 H 00000000B

1 Output portstate


R/W: Read/WriteX: UndefinedW: Write only enable

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CHAPTER 4 I/O Port

4.3.2 Operation of Port 1

The operation of port 1 is explained.

Operation of Port 1


• When "1" is written for a bit of the DDR1 register, the bit corresponding to a pin of port 1, thepin functions as an output port.

• In output port mode, the output transistor operation is enabled and the output latch data isoutput to the pin.

• Once data has been written into the PDR1 register, the written data is held in the output latchand output to the pin.

• The terminal value can be read out by reading out the PDR1 register.


• When "0" is written for a bit of the DDR1 register, the bit corresponding to a pin of port 1, thepin functions as an input port.

• When the pin serves as an input port, the output transistor is "OFF" and the pin remains in ahigh impedance state.

• Once data has been written into the PDR1 register, the written data is held in the output latchbut is not output to the pin.






If the pin state bit in the standby control register (STBC:SPL) is set to "1" when the device goes tostop mode, the pins go to high impedance. because the output transistor is turned "OFF"regardless of the value existing on the DDR1 register in the bit position corresponding to the pin.Input remains fixed to prevent leaks by input open.

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CHAPTER 4 I/O Port


Reference


Table 4.3-4 State of Port 1 Pins



P10 to P17 General-purpose I/O ports Hi-Z Hi-Z

SPL: Pin state designating bit of standby control register (STBC: SPL)Hi-Z: High impedance

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CHAPTER 4 I/O Port

4.4 Port 2

Port 2 is a general-purpose I/O port.This section also describes the structure, pins, and associated registers of port 2 and provides a block diagram of pins.


• General-purpose I/O pins (P20 to P27)







PortName

PinName

Function I/O Type Circuit Type

Input Output









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CHAPTER 4 I/O Port


Figure 4.4-1 Block Diagram of Pins of Port 2 (P20 to 27)

Registers for Port 2There registers PDR2 and DDR2 are associated with port 2.


Table 4.4-2 Correspondence between Registers and Pins for Port 2 shows the correspondencebetween the registers and pins of port 2.

Pin

Pch

Nch

Pch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop, Clock Mode(SPL=1)


DDR

Stop, Clock Mode(SPL=1)


Pull - up control register

Internal Data B

us

DDR read



Table 4.4-2 The correspondence between the registers and pins of port 2.

PortName




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CHAPTER 4 I/O Port





The PDR2 register indicates the state of the output latch. For this reason, the terminal statecannot be read.



When a bit of the DDR0 corresponding to a pin of port "0" is set to "1", the pin functions as anoutput port. When the bit is set to 0, the pin functions as an input port.

Reference


Table 4.4-3 Function of Registers for Port 2 shows the functions of the registers for port 2.


RegisterName

Data Whenbeing read



Port 2 dataregister(PDR2)


Set the output latch to "0" and apply the "L" leveloutput to the terminal.

R/W 0004 H 00000000B


Set the output latch to "1" and apply the "H" leveloutput to the terminal.

Port 2 directionregister(DDR2)

0 Input port state

The pin is set to function as input pin with outputtransistor operation disabled.

R/W 0006 H 00000000B

1 Output port status

The pin is set to function as output pin with outputtransistor operation enabled.

R/W: Readable and Writable

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CHAPTER 4 I/O Port



Operation of Port 2


Data written into the PDR2 register will be retained by the output latch and output to the terminalthrough the output buffer.







Resetting the CPU initializes the PDR2 register value to "0". However, the terminal switches tohigh impedance state during a reset and "L" level output is applied to the terminal after thecancellation of the reset.


If the terminal state specification bit of the standby control register (STBC: SPL) is set to "1" whena transition has been made to the stop mode, the output transistor is forced to turn "OFF" and theterminal switches to high impedance state.



Table 4.4-4 The state of the port 2 pins


Stop (SPL = 1) During resetting

P20 to P27 General-purpose I/Oports

Hi-Z Hi-Z

85

CHAPTER 4 I/O Port

Reference


86

CHAPTER 4 I/O Port

4.5 Port 3

Port 3 serves as a general-purpose I/O port. Each terminal is used as a resource terminal and as a port. The terminal function is switched by bit.This section mainly explains the general-purpose I/O function of the port.This section also describes port 3 concerning to the structure, pins, a block diagram of pins, and associated registers.


• General-purpose I/O pins and resource I/O pins (P31/INT1 to P37/INT7)



A pin at port 3Port 3 has 7 CMOS I/O terminals.

These pins cannot be used as a general-purpose I/O port when being used for peripherals


*: Hysteresis input is used for resource input.



PortName

Pin Name Function Peripherals for which a pinmay serve

I/O Type CircuitType

Input Output

Port 3 P31/INT1 P31 General-purpose I/O External interrupt input INT1 CMOS CMOS B

P32/INT2/SI1 P32 General-purpose I/O External interrupt input INT2SI1 input

CMOS* E

P33/INT3/SO1 P33 General-purpose I/O External interrupt input INT3SO1 output

CMOS B

P34/INT4/SCK1 P34 General-purpose I/O External interrupt input INT4SCK1 external clock input

CMOS* E

P35/INT5/SCK2 P35 General-purpose I/O External interrupt input INT5SCK2 external clock input

CMOS* E

P36/INT6/SO2 P36 General-purpose I/O External interrupt input INT6SO2 output

CMOS B

P37/INT7/SI2 P37 General-purpose I/O External interrupt input INT7SI1 input

CMOS* E

87

CHAPTER 4 I/O Port



Registers for Port 3Port 3 has two related registers, PDR3 and DDR3.


Table 4.5-2 Correspondence between Registers and Pins for Port 3 shows the correspondencebetween the registers and pins of port 3.

*1: Bit 0 is used to control the USB terminal. For more information, refer to "10.3.11 USB Pull-upControl Register for USB (USBPC and USBP)".

Pin

Pch

Nch

Pch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop (SPL=1)

from resource outputfrom resourceoutput enable


DDR

Stop mode


DDR read

DDR (Port direction register)

to External interrup circuit

only P34 to P36

External interrupt input enable bit

Internal Data B

us

toPeripheral resourceinput

Only P32,P34,P35,P37

From Pull - up option settingregister



Table 4.5-2 Correspondence between Registers and Pins for Port 3

PortName



Corresponding pin P37 P36 P35 P34 P33 P32 P31 USBPC/USBP *1

88

CHAPTER 4 I/O Port








When a bit of the DDR3 corresponding to a pin of port "0" is set to "1", the pin functions as anoutput port. When the bit is set to "0", the pin functions as an input port.

Reference


Setting the output from a peripheral enable

If a peripheral with an output pin is used, set the output enable bit for the peripheral enable.

Since the resource output takes priority, the set PDR3 register value for the resource outputterminal has no meaning since it has no relation to the resource output value or enabled output.

Setting the input to a peripheral enable

If a peripheral with an input pin is used, set the pin of port 0 for the input to the peripheral tofunction as an input port. In this mode, the corresponding output latch value has no significance.When the pin is set in this mode, its output latch value has no significance.

Table 4.5-3 Function of Registers for Port 3 shows the functions of the registers for port 3.

89

CHAPTER 4 I/O Port


RegisterName

Data Whenbeing read






R/W 000C H

XXXXXXXXB

*




0 Input portstate


R/W 000D H 00000000H *

1 Output portstatus


R/W: Readable and WritableX: Undefined*: Bit 0 is used to control the USBP terminal. For more information, refer to "10.3.11 Pull-up Control Register for USB(USBPC and USBP)".

90

CHAPTER 4 I/O Port



Operation of Port 3


• When "1" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, thepin functions as an output port.3


• Once data has been written into the PDR3 register, the written data is held in the output latchand output to the pin as is.

• The output latch value is always read out by reading out the PDR3 register.






Operation in mode enabling the output from a peripheral

• When the output enable bit for a peripheral is set to enable, the corresponding pin is set toserve the output from the peripheral.

Operation in mode enabling the input to a peripheral

• Set the DDR3 register bits corresponding to the resource input pins to "0" to set as input ports.

• The terminal value is always input for resource input.

• Regardless of whether the resource uses an input terminal, the terminal value can be read outby reading out the PDR3 register.


• When the CPU is reset, the bits of the DDR3 register are initialized to "0". All the outputtransistors are then turned "OFF" (input port setting), placing the pin in a high impedancestate.


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CHAPTER 4 I/O Port


If the terminal state specification bit of the standby control register (STBC: SPL) is set to "1" whena transition has been made to the stop mode, the output transistor is forced to turn off and theterminal switches to high impedance state. Input remains fixed to prevent leaks by input open.


Reference

When pull-up resistor was selected in the pull-up option setting register, the terminal state in the stopmode (SPL=1) switches to "H" Level (pull-up state), but not to high impedance state.

However, it should be noted that the pull-up process during a reset will be disabled and becomes Hi-z.

Note

Bit 0 of the PDR3 and DDR3 register is used to control the USB terminal. For more information, referto "10.3.11 Pull-up Control Register for USB (USBPC and USBP)".




P31 to P37 General-purpose I/O portsResource input/output

Hi-Z (External interrupt input) Hi-Z


92

CHAPTER 4 I/O Port

4.6 Port 4

Port 4 is a general-purpose I/O port and also works as a release I/O pin. Each terminal is used as a resource terminal and as a port. The terminal function is switched by bit.This section shows the Port 4 configuration and terminals, terminal block diagram and related registers with focus on its functions as a general-purpose I/O port.


• General-purpose I/O pins and resource I/O pins (P40/POW5 to P47/PWM2)



A pin at port 4Port 4 has six CMOS I/O terminals and two Nch open drain I/O terminals.

These pins cannot be used as a general-purpose I/O port when being used for peripherals.


*: Resource is hysteresis input



PortName

Pin Name Function Peripherals for which a pinmay serve


Input Output

Port 4 P40/POW5 P40 General-purpose I/O HUB power control POW1 CMOS CMOS B

P41/POW2 P41 General-purpose I/O HUB power control POW2



P44/UCK P44General-purpose I/O UCK 8-bit serial I/O clock I/O CMOS* E

P45/UO P45 General-purpose I/O UO 8-bit serial data output CMOS B

P46/UI/PWM1 P46 General-purpose I/O UI 8-bit serial data inputPWM1 PWM timer output

CMOS * Nch Opendrain

N

P47/PWM2 P47 General-purpose I/O PWM2 PWM timer output CMOS K

93

CHAPTER 4 I/O Port

Block Diagram of Pins of Port 4

Figure 4.6-1 Block Diagram of Pins of Port 4(P40 to P47)

Reference

Since P46 and P47 are Nch open drain terminals, pull-up resistor must be applied to the externalterminals when using them as output terminals.

Registers for Port 4Port 4 has two related registers, PDR4 and DDR4.



Pin

Pch

Nch

Pch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop mode (SPL=1)

fromresource output

from resourceoutput enable


DDR

Stop mode


DDR read


Pull-up control register

to resource

only P44,P46

to resource

Internal Data B

us

only P40 to P45




PortName




94

CHAPTER 4 I/O Port






Reference




When a bit of the DDR4 corresponding to a pin of port "0" is set to "1", the pin functions as anoutput port. When the bit is set to "0", the pin functions as an input port.





If a peripheral with an input pin is used, set the pin of port 0 for the input to the peripheral tofunction as an input port. In this mode, the corresponding output latch value has no significance.


95

CHAPTER 4 I/O Port


RegisterName

Data Whenbeing read





Output latch of "0" is set and "L" level is outputto the pin in output port mode.

R/W 0010H XXXXXXXXB


Output latch of "1" is set and "H" level is outputto the pin in output port mode.

Port 4directionregister(DDR4)

0 Input portstate


R/W 0011H 00000000B

1 Output portstatus


R/W: Readable and WritableX: Undefined

96

CHAPTER 4 I/O Port



Operation of Port 4


• When "1" is written for a bit of the DDR4 register, the bit corresponding to a pin of port 4, thepin functions as an output port.






• Output transistor is the "OFF" state at an input port and the pin enters a high impedance state.





• Even if the output from each resource is enabled, the resource output value can be read outbecause the terminal value can be read out by reading the PDR4 register.



• The value state of the pin is always input to the peripheral (except during stop mode).




• The PDR4 register bits are not initialized by a reset. For this reason, to use Port 0 as an outputport, setting output data in the PDR4 register is required before setting the correspondingDDR4 register as the output.

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CHAPTER 4 I/O Port


If the pin state bit in the standby control register (STBC:SPL) is set to "1" when the device goes to

stop mode, the pins go to high impedance*1. because the output transistor is turned OFFregardless of the value existing on the DDR4 register in the bit position corresponding to the pin.Input remains fixed to prevent leaks by input open.


Reference


It should be noted, however, that this does not apply to P46 or P47.




P40/POW5 to P47/PWM2 General-purpose I/O port and may also serve the input/output for peripherals

Hi-Z * Hi-Z *

SPL: Pin state designating bit of standby control register (STBC: SPL)Hi-Z: High impedance*: Since P46 and P47 are Nch open drain terminals, they are set to "1" when external pull-up resistor is applied.

98

CHAPTER 4 I/O Port

4.7 Port 5

Port 5 is a general-purpose I/O port. Each terminal is used as a resource terminal and as a port. The terminal function is switched by bit.This section shows the Port 5 configuration and terminals, terminal block diagram and related registers with focus on its functions as a general-purpose I/O port.

Configuration of Port 5Port 5 is comprised of the two elements shown below.

• Nch open drain type I/O terminal/resource I/O terminal (P53/SDA and P54/SCL)


A pin at port 5Port 5 has two Nch open drain output I/O terminals. These terminals cannot be used as general-purpose I/O ports when using a resource.




PortName

Pin Name Function Used in twoways release


Input Output

Port 5 P53/SDA P53 General-purpose I/O

SDA data input/output pin for I2C interfacefor I2CData pin

CMOS Nch Open drain

K

P54/SCL P54 General-purpose I/O

SCL clock input/output pin for I2C interfacefor I2CClock pin

99

CHAPTER 4 I/O Port

Block Diagram of Pins of Port 5

Figure 4.7-1 Block Diagram of Pins of Port 5 P53, 54

Reference

To use P53 and P54 as I2C output terminals or as Nch open drain output terminals, external terminalpull-up resistor must be applied.

Registers for Port 5A register PDR5 is associated with port 5.

The bits of this register correspond to the pins of port 5 in one-to-one correspondence.


PDR read

PDR write

Output latch

Stop (SPL=1)


Pin

Nch

PDR read

Stop mode


Internal Data B

us

fromresource output


to resource



PortName


Port 5 PDR5 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Corresponding pin - - - P54 P53 - - -

100

CHAPTER 4 I/O Port

4.7.1 Port-5 registers (PDR5,DDR5)




The PDR5 register shows the terminal state. For this reason, although the terminal designated asan output port can read out the same value as the output latch value ("0" or "1"), it cannot readout the output latch value when it is designated as an input port. Be also sure to always setunused bits (bit 0 to 2 and bit 5 to 7) to "1".

Reference




As is clear from the block diagram, the use as the resource output terminal takes priority to theuse as the general-purpose port.



If a peripheral with an input pin is used, set the pin of port 0 for the input to the peripheral tofunction as an input port. In this mode, the corresponding output latch value has no significance.When the pin is set in this mode, its output latch value has no significance.


RegisterName

Data Whenbeing read





Output latch of "0" is set and "L"level is output to the pin in outputport mode.

R/W 0012H XXX11XXXB


Output latch of "1" is set and "H"level is output to the pin in outputport mode.

R/W: Readable and WritableX: Undefined

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CHAPTER 4 I/O Port



Operation of Port 5


• When the output latch value is set to "0", the output transistor turns "ON" and "L" level output isapplied to the terminal. On the other hand, when the value is set to "1", the output transistorturns "OFF" and the terminal switches to high impedance state. When a pull-up process isapplied to the output terminal, if the output latch value is "1", the terminal switches to pull-upstate.






• Even if the output from each resource is enabled, the resource output value can be read outbecause the terminal value can be read out by reading the PDR5 register.





• When the CPU is reset, the bit 3 and bit 4 values of the PDR5 register are initialized to "1".Accordingly, the output transistor turns "OFF" (input port) and the pin goes to high impedance.

• Bits other than bit 3 and bit 4 of the PDR5 register are not initialized by a reset.


If the terminal state specification bit of the standby control register (STBC: SPL) is set to "1" whena transition has been made to the stop mode, the terminal switches to high impedance state.because the output transistor is turned "OFF" regardless of the value existing on the DDR5register in the bit position corresponding to the pin. Input remains fixed to prevent leaks by inputopen.

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CHAPTER 4 I/O Port





P53, P54 General-purpose I/O portsResource input/output

Hi-Z Hi-Z


103

CHAPTER 4 I/O Port

4.8 I/O Port Programming Example

This section provides an example of programming with I/O ports.

I/O Port Programming Example

Processing specification

• Ports 0 and 1 are used to light all seven segments of LED (eight segments if Dp are included).

• Pin P00 is connected to the anode common pin of LED and pins P10 to P17 are connected tothe pins of the segments.

Figure 4.8-1 shows an example connection for an 8-segment LCD.

Figure 4.8-1 Example of 8-segment LED connection

Coding examples (Pursuant to Softune V1)

P00

P17

P16

P10

MB89051 series

PDR0 EQU 0000H ; Port 0 data register address DDR0 EQU 0001H ; Port 0 direction register address PDR1 EQU 0002H ; Port 1 data register address DDR1 EQU 0003H ; Port 1 direction register address ; ---------- Main probram ----------------------------------------------------------------------------

CSEG ; CODE SEGMENT : CLRB PDR0:0 ; Set P00 to "L" level. MOV PDR1, #11111111B ; Set all port 1 to "H" level. MOV DDR0, #11111111B ; Set P00 to output, enabled in #XXXXXXX1B MOV DDR1, #11111111B ; Set port 1 to all bit output : ENDS ; --------------------------------------------------------------------------------------------------------------

END

104

CHAPTER 5Time-base Timer

This chapter describes the function and operation of the time-base timer.

5.1 Overview of Time-base Timer

5.2 Configuration of Time-base Timer

5.3 Time-base timer control register (TBTC)

5.4 Interrupt of Time-base Timer

5.5 Explanation of Operations of Time-base Timer Functions

5.6 Precautions when Using Time-base Timer

5.7 Program Example of Time-base Timer

105

CHAPTER 5 Time-base Timer

5.1 Overview of Time-base Timer

The time-base timer has interval timer function that enables interval time selection (four internal time options are available), using the 21-bit free-run counter that increments in synchronization with the internal count clock (1/2 main clock oscillation). In addition, it provides timer output for oscillation stabilization time and an operation clock for the watchdog timer.The time-base timer stops operating in the mode in which main clock oscillation stops.

Interval Timer FunctionThe interval timer function is designed to repeatedly generate an interruption at certain timeintervals.

• An overflow of the interval timer bit of the time-base timer counter causes the generation of aninterruption.

• You can select one of four bits (time intervals) for the interval timer.

Table 5.1-1 shows Interval Times of Time-base Timer.

Table 5.1-1 Interval Times of Time-base Timer

Internal count clock cycle Interval Time

2/FCH (0.167 m s) 213/FCH (Approx. 0.68 ms)

215/FCH (Approx. 2.73 ms)



FCH: main clock oscillation

The figure in ( ) shows the value during the operation at 12 MHz main clock oscillation.

106


Function of Clock SupplyClock supply function: The clock supply function is designed to output timer (four options) for themain clock oscillation stabilization wait time and to supply an operation clock to some peripheralfunction units.

Table 5.1-2 lists the periods of the clock supplied by the time-base timer to the various peripheralfunctions.

Note

Because oscillation cycles vary immediately after oscillation starts, the oscillation stabilization time islisted for reference.

Table 5.1-2 Clock signal supplied from the time-base timer

Where to Supply Clock Clock Cycle Remark

Main clockOscillation StabilizationWait Time

214/FCH (Approx. 1.37 ms) Selected using the oscillationstabilization wait time selection bit(SYCC: WT1, WT0) of the systemclock control register.



Watchdog timer 222/FCH (Approx. 349.53 ms) Watchdog timer count up clock

FCH: main clock oscillationThe figure in ( ) shows the value during the operation at 12 MHz main clock oscillation.

107


5.2 Configuration of Time-base Timer

The time-base timer consists of the following four function blocks.• Time-base counter• Counter clear circuit• Interval timer selector• Time-base timer control register (TBTC)

Block Diagram of Time-base Timer

Figure 5.2-1 Block Diagram of Time-base Timer

Time-base timer counter

A 21-bit up counter that uses 1/2 main oscillation clock as the count clock. It stops operatingwhen oscillation stops.

Counter clear circuit

Clears the counter when the TBTC register is set (TBR = 0), stop mode is entered (STBC: STP =1), or a power-on reset occurs.

Divided by 2 of FCH x21 x23 x214 x215 x216 x217 x220x213x212x211x22

Timebasetimer counter to Watchdog timer

Intervaltimer selector

toClock controlOscillation Stabilization Waittime selector

Counterclear circuit

Power - on reset

Stop mode start

IRQ7Timebase timerInterrupt

OFOF OF

OF

TBC0 TBRTBC1TBOF TBIE

Watchdog timerclear

OF: OverflowFCH : Main clock oscillation

x210x29x28x27

Counter clear

x26

Timebase timer control register (TBTC)

x221

108


Interval timer selector

Selects one bit for the interval timer from four bits in the time-base counter. When the specified bitoverflows, an interrupt occurs.

Time-base timer control register (TBTC)

Selects a time interval, clears the counter, controls interrupts, or checks the status.

109


5.3 Time-base timer control register (TBTC)

The time-base timer control register (TBTC) selects a time interval, clears the counter, controls interrupts, or checks the status.

Time-base timer control register (TBTC)

Figure 5.3-1 Time-base timer control register (TBTC)

TBIE

0

1

TBC1

0

0

1

1

213/FCH

215/FCH

218/FCH

222/FCH

TBC0

0

1

0

1


0 0 0 AH

Address

00XXX000B

Initial value

TBC0 TBRTBC1

R/W R/W WR/WR/W

TBIE

Interrupt request enable bit

Disable Interrupt request output

Enable Interrupt request output

TBOFOverflow interrupt request flag bit

Without overflow ofspecified bit

Clearing this bit.

No change, no effection to others

0

1

Interval time selection bit

Read Write

FCH: Main clock oscillation

TBOF

R/WW

X

: Readable and Writable: Write only: Unused: Undefined: Initial value

With overflow ofspecified bit

TBRTimebase timer initialization bit

Clearing Timebase timercounter

0

1

Read Write

"1" is always read. No change, no effection to others

110


Table 5.3-1 Functional description of each bit in time-base timer control register (TBTC)

Bit name Function

Bit7 TBOF: Overflow interruptrequest flag bit

• Set to "1" when an overflow of the time-base timer counter specification bit occurs.• When this bit and the interruption request enable bit (TBIE) are set to "1" an

interruption request is output.• Setting the bit to "0" clears the data during writing and setting the bit to "1" causes no

changes.

Bit6 TBIE: Interrupt requestenable bit

• This bit is used to allow and prohibit interrupt request output to the CPU. When thisbit and the overflow interruption request flag bit (TBOF) are set to "1", an interruptionrequest is output.

Bit5 Bit4 Bit3


Bit2Bit1

TBC1, TBC0: Interval time selectbits

• These bits specify a time interval for the interval timer.• Specifies the interval timer bit of the time-base timer counter.• One of four time intervals can be selected.

Bit0 TBR: Time-base timerinitialization bit

• This bit clears the time-base timer counter.• Setting this bit to "0" clears the counter to "000000H" and setting the bit to "1" causes

no changes.Reference:Reading value is always "1".

111


5.4 Interrupt of Time-base Timer

The time-base timer counter generates an interrupt when the specified bit of the counter overflows (interval timer function).

Interrupts when the Interval Timer Function is EnabledThe counter counts up on the internal count clock and sets the overflow interrupt request flag bit(TBTC:TBOF) to "1" when an overflow occurs on the selected interval timer bit. Then if theinterrupt request enable bit is enabled (TBTC: TBIE = 1), an interrupt request (IRQ7) is sent tothe CPU. Write "0" to the TBOF bit using the interrupt handling routine to clear the interruptrequest. The TBOF bit is set to "1" when the specified bit overflows regardless of the value of theTBIE bit.

Note

• When the interrupt request is allowed to be output (TBIE = 1) after a reset is released, clear theTBOF bit (TBOF = 0) at the same time.When the TBOF bit is "1", if the TBIE bit is changed from disabled to enabled (changed from 0 to1), an interrupt request occurs immediately.

• When the counter is cleared (TBTC: TBR = 0) and the specified bit overflows at the same time,the TBOF bit is not set.

Oscillation Stabilization Time and Time-base Timer InterruptsThe interval interrupt request (TBTC: TBOF = 1) is generated from the time-base timer upon thestart of normal mode. In this case, be sure to disable the time-base timer interruption (TBTC:TBIE=0) before switching to the mode (stop mode) in which the clock oscillation stops.

Register and Vector Table Related to Interrupts from Time-base Timer

For interrupt operation, see "3.4.2 Interrupt processing".

Table 5.4-1 Register and Vector Table Related to Interrupts from Time-base Timer

Interruptname

Interrupt level setting register Address of vector table

Register Register Bits High Low

IRQ7 ILR2(007DH) L71(bit7) L70(bit6) FFECH FFEDH

112


5.5 Explanation of Operations of Time-base Timer Functions

The time-base timer functions as an interval timer or supplies clocks to some peripherals.

Operations of Interval Timer Function (time-base timer)The settings shown in Figure 5.5-1 are required to use the interval timer function.

Figure 5.5-1 Settings of Interval Timer Function

The time-base timer counter continues to increment in synchronization with the internal countclock (main clock oscillation) as long as the clock continues oscillating.

The counter counts from "0" upon being cleared (TBR = 0). When the interval timer bit overflows,the overflow interrupt request flag bit (TBOF) is set to "1". In other words, interrupts are generatedat specified intervals, starting from when the counter is cleared.

Operations of Clock Supply FunctionThe time-base timer can also be used to create the clock oscillation stabilization wait time. Theoscillation stabilization time is measured from when the time-base timer counter is cleared towhen the oscillation stabilization time bit overflows. One of three oscillation stabilization times canbe selected by the oscillation stabilization time selection bits of the system clock control register(SYCC: WT1, WT0).

Operations of Time-base TimerFigure 5.5-2 shows the operation when:

• When power-on reset generated

• When having changed to the sleep mode during operations of the Interval Timer Functions

• When it stopped mode

• A request to clear the counter is issued.

In stop mode, the time-base timer is cleared and stops operating. When returning from stopmode, the time-base timer counts the oscillation stabilization time.


TBTC TBC0 TBRTBC1

1 00

TBIETBOF : Used bit: Set to 1: Set to 0

113


Figure 5.5-2 Operations of Time-base Timer

TBOF bit

1 FFFFFH

00000H

Counter value

Oscillation stabilization waitoverflow

CPU operationstart

Power - on reset(Option)

Interval cycle(TBTC : TBC1, TBC0=11H)

Clearing by interruption handling routine

Sleep

StopSLP bit(STBC register)

STP bit(STBC register)

Counter clear(TBTC : TBR=0)

Clear by transmission to main stop mode

: Indicates the Oscillation Stabilization Wait Time

Sleep release by IRQ7

TBIE bit

Stop release by external interrupt

When setting "11" to interval time select bit (TBTC TBC1, TBC0) of timebase timer control register (221/FCH)

114


5.6 Precautions when Using Time-base Timer

Notes on using the time-base timer are shown below.

Precautions when Using Time-base Timer

Notes on using programs to set time-base timer

When the interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit isenabled (TBTC: TBIE = 1), a return from interrupt handling is not possible. The TBOF bit must becleared.

Clearing time-base timer

The time-base timer is cleared when the clock oscillation stabilization wait time is required inaddition to when it is cleared by the time-base timer initialization bit (TBTC: TBR=0).

Using time-base timer as oscillation stabilization time timer

Since the clock source oscillation is stopped in the stop mode during power-on, the time-basetimer creates a clock oscillation stabilization wait time following the activation of the resonator.

The appropriate oscillation stabilization time must be selected according to the type of resonatorconnected to the oscillator (clock generator).

Please refer to "3.6.5 Oscillation Stabilization Wait Time".

Notes on peripheral functions the time-base timer supplies to the clock

When entering the modes in which oscillation stops, the counter is cleared and the time-basetimer stops operating. The clock from the time-base timer may have a shorter high-level period orlonger low-level period (up to half the clock cycle) when the counter of the time-base timer iscleared because the clock starts operating from the initial state. The clock for the watchdog timeralso starts operating from the initial state, but the watchdog timer operates at a normal cyclebecause the watchdog timer counter is cleared at the same time.

115


5.7 Program Example of Time-base Timer

Programming examples for the time-base timer are shown below.

Program Example of Time-base Timer


The interval timer interruption of 218/FCH (FCH: main clock oscillation: 12 MHz) is repeatedly

generated. The time interval is approximately 21.85 ms (operating at 12 MHz).


TBTC EQU 0000AH ; Timebase timer control register addressTBOF EQU TBTC:7 ; Interrupt request flag bit definition ILR2 EQU 007DH ; Interrupt level settinng register addressINT_V DSEG ABS ; DATA SEGMENT ORG 0FFECH IRQ7 DW WARI ; Interrupt vector setting INT_V ENDS ; ---------- Main program ---------------------------------------------------------- CSEG ; CODE SEGMENT ; Stack pointer (SP) etc. are already initialized. : CLRI ; Interrupt disable MOV ILR2,#01111111B ; Interrupt level setting (Level 1) MOV TBTC,#01000100B ; Interrupt request flag clear, Interrupt request output enable,

2 18/F CH selection, Timebase timer clear SETI ; Interrupt enable : ; ---------- Interrupt program ----------------------------------------------------- WARI CLRB TBOF ; Interrupt request flag clear PUSHW A XCHW A,T PUSHW A : User processing : POPW A XCHW A,T POPW A RETI ENDS ; ------------------------------------------------------------------------------- END

116

CHAPTER 6Watchdog Timer

This chapter describes the function and operation of the watchdog timer.

6.1 Overview of Watchdog Timer

6.2 Configuration of Watchdog Timer

6.3 Watchdog control register (WDTC)

6.4 Explanation of Operations of Watchdog Timer Functions

6.5 Precautions when Using Watchdog Timer

6.6 Program Examples of Watchdog Timer

117

CHAPTER 6 Watchdog Timer

6.1 Overview of Watchdog Timer

The watchdog timer resets the CPU when the 1-bit counter that uses the time-base timer output as the count clock is not cleared after a certain time interval following a startup.

Functions of Watchdog TimerThe watchdog timer is a counter for preventing programs from hanging up. The timer must becleared at specified intervals after being activated. If the timer is not cleared within a specifiedperiod of time because, for example, a program goes into an endless loop, the timer sends to theCPU a watchdog reset having a period of four instruction cycles.

Interval Time of Watchdog Timer is shown in Table 6.1-1 . When the watchdog timer is notcleared, a watchdog reset occurs following the time between the minimum time interval and themaximum time interval. The counter must be cleared before the time of the minimum timeinterval. Clear the counter within the minimum time given in Table 6.1-1 .

See "6.4 Explanation of Operations of Watchdog Timer Functions" for details of the minimum andmaximum interval times for the watchdog timer.

Note

• Since the watchdog timer counter uses the time-base timer output as the count clock, it is clearedsimultaneously when the time-base timer is cleared (TBTC: TBR=0). For this reason, if thecounter (time-base timer) used as the count clock is repeatedly cleared during the interval time ofthe watchdog timer, the watchdog timer stops functioning.

• On changing to sleep or stop mode, the counter for the watchdog timer is cleared and remainshalted until returning to normal operation (RUN mode).

• During USB data transfer, the watchdog timer counter is cleared and is resumed after the datatransfer.

Table 6.1-1 Time intervals of watchdog timer

Count Clock

- Time-base timer output (Main clock oscillation of 12 MHz)

Minimum time Approx. 349.5ms *

Maximum time Approx. 699.1ms

*: 1/2 main clock oscillation (FCH) × time-base timer count value (221)

118


6.2 Configuration of Watchdog Timer

The watchdog timer consists of the following four blocks:• Watchdog timer counter• Reset control circuit• Counter clear control circuit• Watchdog control register (WDTC)

Block Diagram of Watchdog Timer

Figure 6.2-1 Block Diagram of Watchdog Timer

Watchdog timer counter (1-bit counter)

A 1-bit counter that operates by accepting output from the time-base timer as the count clock.

Reset control circuit

Sends the reset signal to the CPU when the watchdog timer counter overflows.

Counter clear control circuit

Controls the clearing and stopping of the watchdog timer counter.

Watchdog control register (WDTC)

Chooses the count clock and activates and clears the watchdog timer counter. Because thisregister is write-only, bit manipulation instructions cannot be used.

Resetcontrol circuit

1 - bit counter OverflowRST

Watchdog control register(WDTC)

Watchdog timer

222/FCH

(Timebase timer output)

Counter clearcontrol circuitSleep mode start

Stop mode start

Clear signal fromTimebase timer

WTE0WTE3 WTE2 WTE1

Clear Activate

FCH: Main clock oscillation

119


6.3 Watchdog control register (WDTC)

The watchdog control register (WDTC) activates and clears the watchdog timer.

Watchdog control register (WDTC)

Figure 6.3-1 Watchdog control register (WDTC)

Table 6.3-1 Functional description of each bit in watchdog control register (WDTC)

Bit name Function

Bit7 Unused bit • Be sure to write "0".

Bit6 Bit5 Bit4


Bit3 Bit2Bit1Bit0

WTE3, WTE2, WTE1, WTE0: Watchdog timer control bit

• Writing "0101B" starts (when writing for the first time after a reset) orclears (second and subsequent writes) the watchdog timer.

• Writing other than "0101B" does not affect operation.Note:Reading value is "1111B". Bit manipulation instructions cannot be used.

WTE3

0

Other than the above


0 0 0 9H

Address

WTE0

Watchdog control bit

No operation

Start Watchdog timer(When writing for the first timeafter a reset)Clear Watchdog timer(When writing for the second and subsequent times after a reset)

WTE3 WTE2 WTE1

W W W W

WTE2

1

WTE1

0

WTE0

1

XXXXXXXXB

Initial value

: Write only: Unused: Undefined

W

X(Note) Because this register is write - only, bit manipulation instructions cannot be used.

120


6.4 Explanation of Operations of Watchdog Timer Functions

The watchdog timer generates a watchdog reset when a watchdog timer counter overflow occurs.

Operations of Watchdog Timer

Activating watchdog timer

• When the watchdog control bit (WDTC: WTE3 to 0) of the watchdog control register is set to"0101B" for the first time after a reset, the counter is activated.

• The watchdog timer cannot be stopped without accepting a reset upon activation.

Clearing watchdog timer

• The watchdog timer counter is cleared the second or subsequent time "0101B" is written to the

watchdog control bits (WDTC: WTE3-0) of the watchdog control register.

• If the counter is not cleared within the watchdog timer interval time, a counter overflow occursand an internal reset signal is generated for 4 instruction cycles.

Time intervals of watchdog timer

The interval time varies with the timing of clearing the watchdog timer. Figure 6.4-1 shows therelationship between the clearing timing and the interval time of the watchdog timer that uses thetime-base timer output as the count clock (main clock oscillation of 12 MHz).

Figure 6.4-1 Clearing watchdog timer and interval time

Timebase timerCount clock output

Maximum time

Watchdog reset

Watchdog clear

Watchdog1 - bit counter

Timebase timerCount clock output

Minimum time

Watchdog reset

Watchdog1 - bit counter

349.5ms

699.1ms

Overflow

Overflow

Watchdog clear

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6.5 Precautions when Using Watchdog Timer

Notes on using the watchdog timer are provided below.

Precautions when Using Watchdog Timer

Stopping watchdog timer

The watchdog timer cannot be stopped without accepting a reset upon activation.

Clearing watchdog timer

• Clearing the time-base timer counter that supplies the count clock to the watchdog timer alsoclears the watchdog timer counter at the same time.

• Switching to sleep or stop mode clears the watchdog timer counter.

Precautions when creating program

When creating a program that will repeatedly clear the watchdog timer in the main loop, be sureto keep the main loop processing time that includes the interruption processing time within theminimum watchdog timer interval time.

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6.6 Program Examples of Watchdog Timer

Watchdog timer programming examples are provided below.

Program Examples of Watchdog Timer


• Start the watchdog timer immediately after starting the program.

• The watchdog timer is cleared each time in loop of the main program.

• The execution time for each iteration of the main loop (including interrupt processing) must beless than the minimum interval time for the watchdog timer (approximately 349.5ms @12MHz).


WDTC EQU 00009H ; Watchdog control register address WDT_CLR EQU 00000101B VECT DSEG ABS ; DATA SEGMENT ORG 0FFFEH RST_V DW PROG ; Reset vector setting VECT ENDS ; ---------- Main program -------------------------------------------------------------------------------------- CSEG ; CODE SEGMENT PROG ; Initialized routine at reset MOVW SP,#0280H ; Initial value setting of stack pointer

(for interrupt process) :

Initialization of peripheral function (interrupt) etc. : INIT MOV WDTC,#WDT_CLR ; Activate Watchdog timer : MAIN MOV WDTC,#WDT_CLR ; Clear Watchdog timer : User processing ( interrupt processing may occur during this cycle) : JMP MAIN ; The loop must be executed in less than

the minimum interval time of the watchdog timer. ; ENDS ; --------------------------------------------------------------------------------------------------------------------

END

123


124

CHAPTER 72-ch 8-bit PWM Timer

This section describes the functions and operations of the 2-ch 8-bit PPG timer.

7.1 Overview of 2-ch 8-bit PWM Timers (interval timer function)

7.2 Overview of 2-ch 8-bit PWM Timers (PWM timer function)

7.3 Configuration of 8-bit PPG Timer

7.4 Pins of 2-ch 8-bit PWM Timer

7.5 Registers of 2-ch 8-bit PWM Timers

7.6 Interrupts of 2-ch 8-bit PWM Timer

7.7 Explanation of Operations of the Interval Timer Functions

7.8 Explanation of the 8-bit PWM Mode Operation


7.10 Explanation of CH12 PWM mode operation

7.11 Explanation of the Operation of the Prescaler of the 2-ch 8-bit PWM Timer

7.12 States in Each Mode During Operation of 2-ch 8-bit PWM Timer

7.13 Precautions when Using 2-ch 8-bit PPG Timer

7.14 Program Example for 2-ch 8-bit PWM Timers (interval function)

7.15 Programming Example of the 2-ch 8-bit PWM Timer (PWM Timer Function)

125

CHAPTER 7 2-ch 8-bit PWM Timer

7.1 Overview of 2-ch 8-bit PWM Timers (interval timer function)

The 2-ch 8-bit PWM timer is comprised of two 8-bit PWM timers (CH1 and CH2) that increment in synchronization with four internal count clocks. CH1 and CH2 can select either the interval timer function that can output square waves or the PWM timer function with 8-bit or 7-bit resolution. The interval timer function has the 8-bit timer mode that uses CH1 and CH2 separately and the CK12 mode that uses CH1 and CH2 together.

Interval Timer Functions (Functions to Output the Square Wave)The interval timer function is designed to repeatedly generate an interruption at given timeintervals.

Because the output level of the pin (PWM pin) can be inverted for each interrupt, the square waveof any frequency can also be output.

8-bit timer mode

In the 8-bit timer mode, the CH1 and CH2 8-bit PWM timer can be operated separately.

• The interval timer can operate with an interval time ranging from the count clock period up to

count clock x 28.

• The count clock can be selected from four different clocks.

Table 7.1-1 lists the interval times and square wave output ranges.

Table 7.1-1 Interval time and square wave output range (CH1,CH2)

Count Clock Cycle Interval Time Square wave output (Hz)

Internal countClock

1tinst 1tinst to 28 tinst 1/(2tinst) to 1/(29 tinst)

8tinst 23 tinst to 211 tinst 1/(24 tinst) to 1/(212 tinst)



tinst: Instruction cycle (Affected by the clock mode and others.)

126


Reference

Calculation example of intervals and square wave frequency

In this example, the main clock oscillation frequency (FCH) is 12 MHz, the PWM compare register(COMR) value is set to "DDH (221)", and the count clock cycle is set to 1 tinst. In this case, theinterval time and the frequency of the square wave output from the PWM pin (where the PWM timeroperates continuously and the value of the COMR register is constant) are calculated as follows.

However, this shows the value when the system clock control register (SYCC) selects the maximumspeed clock (CS1, CS0=11B, 1 instruction cycle=4/FCH) of the clock mode (SCS=1).

Interval Time = (1 x 4/FCH) x (COMR register value + 1)

= (4/12MHz)×(221+1)

= 74 µs

CH1 output frequency = FCH/(1×8× (COMR1 register value + 1))

= 12MHz/(8×(221+1))

≅ 6.76 kHz

CK12 Mode

The CK12 mode uses CH1 and CH2 together. The CH1 square wave output is used as the CH2count clock.

• On CH1 and CH2, the interval timer can operate with an interval time ranging from the count

clock period up to count clock x 28.

• CH1 selects one of four count clocks available.

• The CH2 count clock uses the CH1 square wave output.

Table 7.1-2 lists the interval times and square wave output ranges.

Table 7.1-2 Interval time and square wave output range

Count Clock Cycle Interval Time Square wave output (Hz)

CH1 Inside count clock 1t inst 1t inst to 28 t inst 1/(2t inst ) to 1/(29 t inst )

8t inst 23 t inst to 211 t inst 1/(24 t inst ) to 1/(212 t inst )



CH2 CH1 square wave output 2t inst to 215 t inst 2t inst to 223 t inst 1/(22 t inst ) to 1/(224 t inst )


127


Reference

Calculation example of intervals and square wave frequency

When the PWM compare register 1 and 2 (COMR1, COMR2) values are both set to "DDH (221)" atmain clock oscillation (FCH) of 12 MHz, the interval time when the CH1 count clock cycle is set toÅg1tinstÅh and the frequency of the square wave that is output from the PWM terminal duringcontinuous operation using the COMR register value unchanged are calculated as follows. However,this shows the value when the system clock control register (SYCC) selects the maximum speedclock (CS1, CS0=11B, 1 instruction cycle=4/FCH) of the clock mode (SCS=1).

CH1 Interval Time = (1 x 4/FCH) x (COMR1 register value + 1)

=(4/12MHz)×(221+1)

= 74 µs

CH1 output frequency = FCH/(1×8× (COMR1 register value + 1))

= 12MHz/(8×(221+1))

≅ 6.76kHz

CH2 interval time = (1/CH1 output frequency) × (COMR2 register value + 1)

=(1/6.76kHz)×(221+1)

≅ 32.8ms

CH2 output frequency = CH1 output frequency/(COMR2 register value + 1)

= 6.76kHz/(221+1)

≅ 30.45Hz

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7.2 Overview of 2-ch 8-bit PWM Timers (PWM timer function)

The 2-ch 8-bit PWM timer is comprised of two 8-bit PWM timers (CH1 and CH2) that increment in synchronization with four internal count clocks.

Overview of 2-ch 8-bit PWM Timers (PWM timer function)The 2-ch 8-bit PWM timer is comprised of two 8-bit PWM timers (CH1 and CH2) that increment insynchronization with four internal count clocks. CH1 and CH2 can select either the interval timerfunction that can output square waves or the PWM timer function with 8-bit or 7-bit resolution.The PWM timer function has the 7-or 8-bit PWM mode that uses CH1 and CH2 separately (highspeed mode) and the CH12 PWM mode that generates the PWM wave using CH1 for "L" widthand CH2 for frequency. It is also possible to operate CH1 in the 8-bit timer mode and use thesquare wave output as the CH2 count clock (CK12 PWM mode). The connection of a lowpassfilter to the PWM output enables its use as a D/A converter.

Figure 7.2-1 Example configuration for a D/A converter consisting of the PWM output and a low pass filter.

Analog output waveform

PWM output waveform

PWM pinPWM output

R C

Analog output (Va)

Tr

Va Vcc

TH TL

T

Va

t

Vcc

0

Relation between analog output voltage and PWM output waveformVa/Vcc = TH/TTr shows the time until output stabilization.

129


Reference

• Calculation examples of PWM wave (CH12PWM mode)

When the PWM compare registers have the following setting: COMR1=01H and COMR2=03H andeach count clock is set to "1t inst" at main clock oscillation (FCH) of 12 MHz, the PWM wave iscalculated as follows.

However, this shows the value when the system clock control register (SYCC) selects the maximumspeed clock (CS1, CS0=11B, 1 instruction cycle=4/FCH) of the clock mode (SCS=1).

"L" width = (1×4/FCH)×(COMR1register value + 1)

= (4/12 MHz)×(1+1)

≅ 0.67 µs

1 cycle width = (1×4/FCH)×(COMR2 register value + 1)

= (4/12MHz)×(3+1)

≅ 1.34 µs

No interruption request can be generated by PWM timer operations other than the CH12 PWM modeof operation.

PWM Timer FunctionsThe PWM timer function outputs the PWM wave to the PWM terminal by controlling the singlecycle "H" width or by controlling the "L" width and the cycle separately. The low pass filter can beconnected to the output and used as the D/A converter.

When using CH1 and CH2 separately, either the 8-bit PWM mode or the 7-bit PWM mode (highspeed mode) can be selected.

8-bit PWM mode

• Since the single cycle "H" width can be controlled with a 1/256 resolution, the PWM output isprovided at a duty ratio of 0 to 99.6.

• The PWM wave cycle, 28 times the count clock cycle, can be selected from four options.

7-bit PWM mode (High speed mode)

• Since the single cycle "H" width can be controlled with a 1/128 resolution, the PWM output isprovided at a duty ratio of 0 to 99.2.

• The PWM wave cycle, 27 times the count clock cycle (1/2 8-bit PWM mode), can be selectedfrom four options.

CK12PWM mode (8-bit PWM, 7-bit PWM)

• CH2 can select either the 8-bit PWM mode or the 7-bit PWM mode. However, the CH1 squarewave output is used as the count clock.

• CH1, operated in the 8-bit timer mode, controls the PWM wave cycle.

CH12PWM Mode

• The "L" width of the PWM wave can be changed from the width of each of the four count clock

130


cycles of CH1 to 28 times the width of each of the four cycles.

• The PWM wave cycle can be changed from the cycle of each of the four count clocks of CH2

to 28 times the cycle of each of the four count clocks.

• The PWM wave resolution can be changed to a minimum of 1/214 but this places a limit to theduty ratio.

A cycle of PWM wave in each mode

Table 7.2-1 PWM waveform periods able to be set on the PWM timer function.

Count Clock Cycle Separate use of CH1 and CH2 (Normal mode)

CH12PWM Mode

8-bit PWMmode cycle

7-bit PWM modeCycle of a high-speed

"L" width (CH1)

1 cycle width (CH2)

CH2 except for CH1 andCK12PWM mode

Inside countclock

1t inst 28 t inst 27 t inst 1t inst to 28 t inst 1t inst to 28 t inst

8t inst 211 t inst 210 t inst 23 t inst to 211 t inst 23 t inst to 211 t inst



CK12PWM CH2 in mode

CH1 Square wave output

2t inst to 215 t inst 29 t inst to 223 t inst 28 t inst to 222 t inst -


-: (Setting prohibited)

131


7.3 Configuration of 8-bit PPG Timer

The 2-ch 8-bit PPG timer comprises the following seven blocks:• Prescaler• 8-bit PWM timer 1(CH1)• 8-bit PWM timer 2(CH2)• PWM compare register 1,2(COMR1,COMR2)• PWM compare register 1,2,3(CNTR1,CNTR2,CNTR3)• CK12 selector• CH12PWM Output controller

2-ch 8-bit PWM timer 1 block diagram

Figure 7.3-1 2-ch 8-bit PWM timer 1 block diagram

PrescalerA circuit to divide the operation clock for the peripheral circuits.

When one of the counter operation enable bits (TPE1 and TPE2) of the PWM control register(CNTR2) is set to "1", the prescaler is activated to output one of four internal count clocks.

8-bit PWM timer 1 (CH1) and 8-bit PWM timer 2 (CH2)

Count clock selector

This circuit, used to select one of four internal count clocks, serves as the count-up clock for the8-bit counter.

PTX1 PTX2 P7M1 P7M2 SC11 SC10 SC21 SC20TPE1 TPE2 CK12 TIR1 TIR2 TIE1 TIE2

PWM control register 1(CNTR1)



COMR1 COMR2

Internal Data Bus

Start

CLK

7MOD

7MOD

7MODOUT

OUT

CLEAR

OVER FLOW

8 - bitcounter

IRQ8

IRQ8

1tinst

1tinst : instruction cycle

8 - bit PWMtimer 1 (CH1)

8 - bit PWMtimer 2 (CH2)

X 1

X 8

X 16

X 64

STOP

CLK

Prescaler

PWM compare register 1

Selector

Selector

Selector

Selector

P47/PWM2

P46/PWM1/UI

Comparison circuit

Start

CLK

7MOD

7MOD

OUT

CLEAR

OVER FLOW

8 - bitcounter

PWM compare register 2

Comparison circuit

RESET

SET

OUT2CH PWM

Output control circuit

2 2

OE3OE2 CH12

PWM generationand


7MOD

OUT

PWM generationand


Pin

Pin

CK12

4

132


8-bit counter

This counter is incremented by the count clock selected by the count clock selector.

Comparator

A latch in the comparator holds the COMR register value when the value of the 8-bit counter is"00H". And then compares the 8-bit counter with the COMR register value latched and detects amatch.

PWM generation and output control circuit

During the interval timer operation, the detection of a match causes the generation of aninterruption request, and when the output terminal control bit 2 or 3 (CNTR3: OE2 or OE3) is setto Åg1Åh, the output control circuit reverses the output level of the PWM terminal. And then the 8-bit counter is cleared.

During the PWM timer operation, once a match is detected, the output level of the P50/PWM pinis changed from "H" level to L level by the PWM generation circuit. Thereafter, when the 8-bitcounter overflows, the output level is returned to "H" level.

PWM compare register 1,2,(COMR1,COMR2) This register is used to set a value for comparison with the counter value of the 8-bit counter.

PWM control register 1,2,3(CNTR1,CNTR2,CNTR3) This register is used to select the operation mode, enable and disable operations, set the countclock, control interrupts, and check status.

When the operation mode is the PWM timer mode (P/TX = 1), the 8-bit counter cannot be cleared(by the match detection signal from the comparator) and the interrupt request (IRQ9) is disabled.

CK12 selectorThe input clock switching circuit switches the 8-bit PWM timer 2 (CH2) input clock to the countclock selector output or the 8-bit PWM timer 1 (CH1) square wave output.

CH12PWM Output controllerThe CH12 PWM mode controls the "L" width (L to H) and the cycle (H to L) of the PWM waveusing the CH1 and CH2 timer output.

Interruption related to 2-ch 8-bit PWM timerIRQ8: If the interruption request output is enabled (CNTR2: TIE1=1) when a match between thecounter value and the set COMR1 or COMR2 register value is detected by the CH1 interval timerfunction, an interruption request occurs (No interruption request occurs during normal operationof the PWM function.)

IRQ8: If the interruption request output is enabled (CNTR2: TIE2=1) when a match between thecounter value and the set COMR1 or COMR2 register value is detected by the CH2 interval timerfunction or in the CH12 PWM mode, an interruption request occurs (No interruption requestoccurs during normal operation of the PWM function.)

133

134


7.4 Pins of 2-ch 8-bit PWM Timer

This section describes the pin associated with the 2-ch 8-bit PWM timer and illustrates a block diagram of circuitry terminating at the pin.

Pin related to the 2-ch 8-bit PWM TimersThe pin related to the 2-ch 8-bit PWM timers is the P46/UI/PWM1, P47/PWM2 pin.

P46/UI/PWM1,P47/PWM2 pin

These terminals serve dual functions as the general-purpose I/O port (P46 and P47) and as theinterval timer/PWM timer output terminal (PWM1 and PWM2).

PWM1 and PWM2: Square waves are output to these terminals during the operation of theinterval timer function.

PWM waves are output to these terminals during the operation of the PWM timer function.

When the bit to control the output pin is set to the dedicated pin (CNTR3: OE=1), the P46/UI/PWM1, P47/PWM2 pin automatically functions as an output pin, regardless of the value of theport 5 data direction register (DDR5: bit 0), and as the PWM1, PWM2 pin.

Block Diagram of the Pin related to the 2-ch 8-bit PWM Timers

Figure 7.4-1 Block Diagram of the Pin related to the 2-ch 8-bit PWM Timers

Pin

Nch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop (SPL=1)


DDR

Stop mode


DDR read


P46/PWM1/UIP47/PWM2

Internal Data B

us



from resource outputfrom resourceoutput enable


Reference

A pull-up resistor must be applied to external terminals when they are used as PWM outputterminals.

135


7.5 Registers of 2-ch 8-bit PWM Timers

This section describes the registers related to the 2-ch 8-bit PWM timers.

2-ch 8-bit PPG timer registers

Figure 7.5-1 2-ch 8-bit PWM timer registers

Note

Because the PWM compare register 1,2 (COMR1, COMR2) is a write-only register, an instruction tooperate bits cannot be used.


0 0 2 7H

Address

00000000B

Initial value


0 0 2 8H

Address

000X0000B

Initial value

R/WR/W R/W R/WR/WR/W R/W

R/WR/W R/W R/WR/WR/W R/WR/W

CK12TPE1

SC20

TIE2TIE1

PTX1 PTX2 P7M1 P7M2 SC11 SC10

TPE2

SC21

TIR2TIR1

CNTR1


0 0 2 9H

Address

X000XXXXB

Initial value

R/WR/W

W

R/W

OE2 OE3 CH12CNTR3

CNTR2


0 0 2 AH

Address

XXXXXXXXB

Initial value

WW W WWW W


0 0 2 BH

Address

XXXXXXXXB

Initial value

WW W WWW WW

COMR2

COMR1

CNTR1,2,3 (PWM control register 1,2,3)

COMR1,2 (PWM compare register 1,2)

R/WW

X

: Readable and Writable: Write only: Unused: Undefined

136


7.5.1 PWM Control Register 1(CNTR1)

The PWM control register 1 (CNTR1) is used to select an operation mode (interval timer operation or PWM timer operation) of the 1CH and 2-ch 8-bit PWM timer, switch the resolution of the PWM timer function and select a count clock.


Figure 7.5-2 PWM control register 1(CNTR1)

PTX1 P7M1 P7M2


CNTR1 0 0 2 7H

Address

00000000B

Initial value

R/W

PTX2

PTX2

0

1

Operation as interval timer

Operation as PWM timer

P7M1

0

1

8 - bit PWM mode

7 - bit PWM mode (high speed mode)

SC11 SC21 SC20SC10

R/WR/W R/WR/W R/W R/WR/W

CH1 PWM resolution switching bit

CH2 operation mode selection bit

P7M2

0

1

8 - bit PWM mode

7 - bit PWM mode (high speed mode)

CH2 PWM resolution switching bit

R/W

SC21

0

0

1

1

SC20

0

1

0

1

CH2 clock selection bit

1tinst

8tinst

16tinst

64tinst

SC11

0

0

1

1

SC10

0

1

0

1

CH1 clock selection bit

1tinst

8tinst

16tinst

64tinst

PTX1

0

1

Operation as interval timer

Operation as PWM timer

CH1 operation mode selection bit

tinst : Instruction cycle: Readable and Writable: Initial value

137


Table 7.5-1 Functional description of each bit in PWM control register 1 (CNTR1)

Bit name Function

Bit7 PTX1: CH1 Operation modeselection bit

• A bit used to select the CH1 interval timer operation and PWM timer operation.• When this bit is set to "0", the interval timer operation takes place and when it is set to

"1", the PWM timer operation takes place.Note:Before setting this bit, be sure to stop the counter operation (TPE2=0), disable theinterruption (TIE2=0) and clear the interruption request flag bit (TIR2=0). This bit has no meaning during the CH12 PWM mode (CNTR3: CH12=1).

Bit6 PTX2: CH2 Operation modeselection bit

• A bit used to select the CH2 interval timer operation and PWM timer operation.• When this bit is set to "0", the interval timer operation takes place and when it is set to

"1", the PWM timer operation takes place.Note:Before setting this bit, be sure to stop the counter operation (TPE2=0), disable theinterruption (TIE2=0) and clear the interruption request flag bit (TIR2=0). This bit hasno meaning during the CH12 PWM mode (CNTR3: CH12=1).

Bit5 P7M1: CH1PWM resolution switching bit

• This bit is used to switch between the 8-bit PWM mode and the 7-bit PWM mode(high speed mode) during the CH1 PWM timer operation.

• When this bit is set to "0", the mode switches to the 8-bit PWM mode and when it isset to "1", the mode switches to the 7-bit PWM mode.

Note:Do not write "1" at operating of interval timer.

Bit4 P7M2: CH2PWM resolution switching bit

• This bit is used to switch between the 8-bit PWM mode and the 7-bit PWM mode(high speed mode) during the CH2 PWM timer operation.

• When this bit is set to "0", the mode switches to the 8-bit PWM mode and when it isset to "1", the mode switches to the 7-bit PWM mode.

Note:Do not write "1" at operating of interval timer.

Bit3 Bit2

SC11, SC10: CH1 Clock selectionbits

• This bit is used to select the count clock of the interval timer functions or PWM timerfunctions.

• 4 kinds of internal count clock are selected.Note:Do not switch at operating of CH1 counter (TPE1=1).

Bit1Bit0

SC21, SC20: CH2 Clock selectionbits

• This bit is used to select the count clock of the interval timer functions or PWM timerfunctions.

• 4 kinds of internal count clock are selected.Note:Do not switch at operating of CH2 counter (TPE2=1)

138



The PWM control register 2 (CNTR2) is used to enable or disable the 1CH and 2-ch 8-bit PWM timer operation, select the CK12 mode, perform interruption control and check the operation state.



TPE1 CK12


CNTR2 0 0 2 8 H

Address

000X0000B

Initial value

R/W

TPE2

TIE2

0

1

Interrupt request output disable

Interrupt request output enable

At PWM timer functionWrite

Write

Clear this bit

No change, no effect to others

No change

(other than

CH12PWM mode)

TIR1 TIE1 TIE2TIR2

R/WR/W R/WR/W R/WR/W

CH2 interrupt request enable bit

TIE1

0

1



CH1 interupt request enable bit

TIR2

CH2 interrupt request flag bit

At interval timer function

Not maching counter value

and setting value

Matcing counter value and

setting value

CK12

0

1

Clock selected by SC21 and SC20 bit

CH1 square wave output (CH12 mode)

CH2 input clock switching bit

TPE2

0

1

Counter operation stop

Counter operation start

CH2 counter operation enable bit

TPE1

0

1

Counter operation stop

Counter operation start

CH1 counter operation enable bit

0

1

At PWM timer function

Clear this bit

No change, no effect to others

No change

(Other than

CH12PWM mode)

TIR1

CH1 interrupt request flag bit

At interval timer function

Not maching counter value

and setting value

Matcing counter value and

setting value

0

1

Read

Read

R/W

X

: Readable and Writable: Unused: Undefined: Initial value

139


Table 7.5-2 Functional description of each bit in PWM control register 2 (ADC2)

Bit name Function

Bit7 TPE1: CH1 CounterPPG1 operation enable bit

• A bit used to start or stop the CH1 interval timer operation and PWM timeroperation.

When this bit is set to "1", the counting operation starts and when it is set to "0",the counter value is cleared to "00H" and the operation stops.

Bit6 TPE2: CH2 CounterPPG1 operation enable bit

• A bit used to start or stop the CH2 interval timer operation and PWM timeroperation.

• When this bit is set to "1", the counting operation starts and when it is set to"0", the counter value is cleared to "00H" and the operation stops.

Bit5 CK12: CH2 CMOS inputClock switching bit

• A bit used to switch the CH2 input clock.• When this bit is set to "0", the clock selected by the SC21 and SC20 bits is

used as the input clock.• When this bit is set to "1", regardless of the SC21 and SC20 bit values, the

CH1 square wave output is used as the input clock in the CK12 mode.Note: Do not write "1" at CH12PWM mode (CNTR3:CH12=1). Also do not write "1", when CH1 is PWM timer operating (CNTR1:PTX1=1).

Bit4 Unused bit • This bit is undefined when it is read.• Nothing is affected when it is written.

Bit3 TIR1: CH1 interruption requestsflag bit

• The bit will be set to "1" when the count value and the PWM compare register1 (COMR1) value mach during the operation of the CH1 interval timerfunction.

• When this bit and the CH1 interruption request enable bit (TIE1) are set to "1",an interruption request to the CPU is output.

• While the PWM timer functions excluding CH12PWM are enabled, aninterrupt request does not occur.

• Setting the bit to "0" clears the data during writing and setting the bit to "1"causes no changes to this bit.

Bit2 TIR2: CH2 interrupt request flag bit

• The bit will be set to "1" when the count value and the PWM compare register2 (COMR2) value mach during the operation of the CH2 interval timerfunction and in the CH12 PWM mode.

• When this bit and the CH1 interruption request enable bit (TIE2) are set to "1",an interruption request to the CPU is output.

• While the PWM timer functions excluding CH12PWM are enabled, aninterrupt request does not occur.

Setting the bit to "0" clears the data during writing and setting the bit to "1"causes no changes to this bit.

Bit1 TIE1: CH1 interruption requestsenable bit

• This bit is used to allow and prohibit interrupt request output to the CPU inCH1.

• When this bit and the CH1 interruption request flag bit (TIR1) are set to "1",an interruption request is output.

Note: Disable (TIE1=0) interrupt output at CH12PWM mode (CNTR3:CH12=1).

Bit0 TIE2: CH2 interruption requestsenable bit

• This bit is used to allow and prohibit interrupt request output to the CPU inCH2.

• When this bit and the CH2 interruption request flag bit (TIR2) are set to "1",an interruption request is output.

140



The PWM control register 3 (CNTR3) is used to select the CH12 PWM mode of the 1CH and 2-ch 8-bit PWM timer and control the output terminal.



OE3 CH12


CNTR3 0 0 2 9H

Address

X000XXXXB

Initial value

R/W

OE2

CH12

0

1

Normal mode

CH12PWM mode

R/W R/W

CH12PWM mode setting bit

OE3

0 Use as general - purpose port (P46)

Use as CH12PWM mode, CH1 interval timer/

PWM output pin (PWM1)

Output pin control bit 3

1

OE2

0

1

Use as general - purpose port (P47)

Use as CH2 interval timer/PWM output pin (PWM2)

Output pin control bit 2

R/W

X


141


Table 7.5-3 Functional description of each bit in PWM control register 3 (CNTR3) (Continued)

Bit name Function

Bit7 Unused bit • This bit is undefined when it is read.• Nothing is affected when it is written.

Bit6 OE2: Output pincontrol bit 2

• A bit used to switch the P47/PWM2 terminal between the general-purpose port modeand the dedicated terminal mode.

• When this bit is set to "0", the terminal functions as a general-purpose port (P47) andwhen it is set to "1", the terminal functions as a dedicated terminal (PWM2).

• The PWM2 terminal when using CH2 outputs the square wave during the operation ofthe interval timer function and outputs the PWM wave during the operation of the PWMtimer function.

Bit5 OE3: Output pincontrol bit 3

• A bit used to switch the P46/PWM1/UI terminal between the general-purpose port modeand the dedicated terminal mode.

• Setting this bit to "0" will enable the function as the general-purpose port (P46) andwhen it is set to "1", the terminal functions as a dedicated terminal (PWM1).

• The PWM1 terminal when using CH1 outputs the square wave during the operation ofthe interval timer function and outputs the PWM wave during the operation of the PWMtimer function. The PWM wave is output in the CH12 PWM mode.

Bit4 CH12: PWM ModeRegister Bits

• A bit used to switch between the normal mode and the CH12 PWM mode.• Setting this bit to "0" allows CH1 and CH2 to be operated separately. Setting this bit to

"1", on the other hand, allows operation in the CH12 PWM mode that uses CH1 andCH2 for specifying the "L" width and the cycle, respectively.

• In the CH12 PWM mode, the operation mode selection bits (CNTR1: PTX1 and PTX2)have no meaning.

Note: Do not write "1" at CK12 mode setting (CNTR2:CK12=1). Also do not rewrite during operating counter of CH1 or CH2 (CNTR2:TIE1 or TIE2=1).

Bit3 Bit2Bit1Bit0


142


7.5.4 PWM Compare Register 1(COMR1)

The PWM compare register 1 (COMR1) is the CH1 data register. During the operation of the interval timer function, this register value represents the interval time and during the operation of the normal PWM timer function, this register value represents the pulse "H" width. This register value represents the pulse "L" width in the CH12 PWM mode.

PWM compare register 1(COMR1) Figure 7.5-5 shows the bit layout of the PWM compare register.

Because this register is write-only, bit manipulation instructions cannot be used.

Figure 7.5-5 PWM compare register 1(COMR1)

When the interval timer is operating (8-bit timer mode and CK12 mode)

This register, used to set a value that is compared with the counter value, specifies the intervaltime (square wave output frequency).

When the set value written in this register and the counter value match, the counter will becleared and the interruption request flag bit will be set to "1" (CNTR2: TIR1=1).

If a value is written to the COMR1 register during counter operation, the new value is not useduntil the next cycle (after the next compare match).

Reference

The set value of the COMR1 register during the 8-bit timer operation and during the CK12 modeoperation can be calculated using the following equation. However, the instruction cycle is affectedby the clock mode and gear function.

COMR1 register value = Interval time/(count clock period x instruction cycle) - 1


COMR1 0 0 2 AH

Address

XXXXXXXXB

Initial value

WW W W W WWW

WX

: Write only: Undefined: No meaning at 7-bit PWM mode (high speed mode).

143


During the PWM timer operation (8-bit PWM mode and 7-bit PWM mode)

Specify the "H"-level width of a pulse in the register to which the value that is compared with thecounter value is to be set.

Until the set value written in this register and the counter value match, the PWM1 terminalcontinuously makes "H" output. If a match is found, the terminal continuously makes "L" outputuntil the counter value overflows.

If a value is written to the COMR1 register while the counter is operating, the value takes effect atthe next cycle (after overflow).

Reference

The settings and cycle of the COMR1 register, while the PWM timer is operating, can be calculatedusing the following formula. However, the instruction cycle is affected by the clock mode and gearfunction.

• 8-bit PWM modeCOMR1 register value = duty ratio x 256PWM wave cycle = count clock cycle x instruction cycle x 256


In the CH12PWM mode operation

Specify the L-level width of a pulse in the register to which the value that is compared with thecounter value is to be set.

Until the counter value matches the set value written in this register, the PWM1 terminalcontinuously makes "L" output. If a match is found, the terminal makes "H" output.

If a value is written in the COMR1 register while the counter is operating, the value becomes validfrom the next cycle.

Reference

The set value of the COMR1 register during the CH12 PWM mode operation can be calculated usingthe following equation. However, the instruction cycle is affected by the clock mode and gearfunction.

COMR1 register value = "L" width duration of the PWM wave/(count clock cycle × instruction cycle) -1.

144


7.5.5 PWM Compare Register 2(COMR2)

The PWM compare register 2 (COMR2) is the CH2 data register. During the operation of the interval timer function, this register value represents the interval time and during the operation of the normal PWM timer function, this register value represents the pulse "H" width. The register value represents the PWM wave frequency in the CH12 PWM mode.

PWM compare register 2(COMR2) Figure 7.5-6 shows the bit layout of the PWM compare register.

Because this register is write-only, bit manipulation instructions cannot be used.

Figure 7.5-6 PWM compare register 2(COMR2)

When the interval timer is operating (8-bit timer mode and CK12 mode)

Specify an interval in the register to which the value compared with the counter value is to be set.

When the set value written in this register and the counter value match, the counter will becleared and the interruption request flag bit will be set to "1" (CNTR2: TIR2=1).

If a value is written to the COMR2 register during counter operation, the new value is not useduntil the next cycle (after the next compare match).

Reference

The settings of the COMR2 register, while the interval timer is operating, can be calculated using thefollowing formula. However, the instruction cycle is affected by the clock mode and gear function.

• 8-bit timer modeCOMR2 register value = Interval time/(count clock period x instruction cycle)-1

• CK12 ModeCOMR2 register value = Interval time/CH1 square wave output - 1


COMR2 0 0 2 BH

Address

XXXXXXXXB

Initial value

WW W W W WWW

WX

: Write only: Undefined: No meaning at 7-bit PWM mode (high speed mode)

145


During the PWM timer operation (8-bit PWM mode and 7-bit PWM mode)

Specify the H-level width of a pulse in the register to which the value that is compared with thecounter value is to be set.

Until the set value written in this register and the counter value match, the PWM2 terminalcontinuously makes "H" output. If a match is found, the terminal continuously makes L output untilthe counter value overflows.

If a value is written to the COMR2 register while the counter is operating, the value takes effect atthe next cycle (after overflow).

Reference

The settings and cycle of the COMR2 register, while the PWM timer is operating, can be calculatedusing the following formula. However, the instruction cycle is affected by the clock mode and gearfunction.


• 7-bit PWM modeCOMR2 register value = duty ratio x 128 PWM wave cycle = count clock cycle x instruction cycle x 128

In the CH12PWM mode operation

This register, used to set a value that is compared with the counter value, specifies the PWMwaveform frequency.

When the set value written in this register and the counter value match, the CH1 and CH2counters will be cleared simultaneously and the interruption request flag bit (CNTR2: TIR2) will beset to "1".

When this happens, the PWM1 terminal switches to the "L" level.

If a value is written in the COMR2 register while the counter is operating, the value becomes validfrom the next cycle.

Reference

The set value of the COMR2 register during the CH12 PWM mode operation can be calculated usingthe following equation. However, it should be noted that the instruction cycle will be influenced by theclock and gear function.

COMR 2 register value = Single cycle time of the PWM wave/(count clock cycle × instruction cycle) -1

146


7.6 Interrupts of 2-ch 8-bit PWM Timer

An interrupt factor of an 2-ch 8-bit PWM timer can be a match between the counter value and the PWM compare register value while interval timer functions are operating. No interrupt request is generated when the PWM timer function excluding the CH12PWM mode is working.

Interruptions during the operation of the interval timer function and during the CH12 PWM mode operation

When the counter value is incremented from "00H" using the selected count clock and matches

the PWM compare register (COMR) value, "1" is set to the corresponding interrupt request flag bit(CNTR2: TIR1, TIR2).Then if the interrupt request enable bit is enabled (CNTR2:TIE1=1,TIE2=1), an interrupt request(IRQ8) is sent to the CPU. Write "0" to the TIR bit using the interrupt handling routine to clear theinterrupt request.The TIR bit is set to "1" when the counter value matches the settings regardless of the value ofthe TIE1, TIE2 bit.

NoteTo use interruptions in the CH12 PWM mode, do not use CH1 by setting it to interruption-disabled(CNTR2:TIE1=0). Possible to use CH2 while the interval timer functions are enabled:

ReferenceWhen a match is found between the counter value and the COMR register value concurrently withthe stop of the counter (CNTR2:TPE1=0,TPE2=0), the TIR bit is not set.When the TIR bit is "1", if the TIE bit is changed from disabled to enabled (changed from 0 to 1), aninterrupt request occurs immediately.

Register and Vector Table related to the Interrupts of an 2-ch 8-bit PWM Timer

Reference


Table 7.6-1 Register and Vector Table related to the Interrupts of an 2-ch 8-bit PWM Timer

Interrupt name Interrupt level setting register Address of vector table


IRQ8 ILR3(007D H ) L81(bit1) L80(bit0) FFEA H FFEB H

147


7.7 Explanation of Operations of the Interval Timer Functions

This section explains the interval timer function of the 2-ch 8-bit PWM timers in the 8-bit timer mode and the CK12 mode.

Operations of the Interval Timer FunctionsTo use the 2-ch 8-bit PWM timers (CH1 and CH2) as the interval timer in each mode, the settingsshown in Figure 7.7-1 are required.

Figure 7.7-1 Settings of Interval Timer Function

When the counter is activated, the counter is incremented from "00H " at the start-up of the

selected count clock. When the counter value matches the value set in the COMR register(compare value), the PWM timer inverts the level of the PWM pin on the next rising edge of thecount clock, clears the counter, sets the interrupt request flag bit (CNTR2:TIR1,TIR2=1), andrestarts counting from "00H ".

In the CK12 mode, the CH1 square wave output is used as the CH2 count clock.

Figure 7.7-2 shows the operation of the 2-ch 8-bit PWM timer.


CNTR1

CH1

CH2

CK12

PTX1 P7M1 P7M2PTX2 SC11 SC21 SC20SC10


CNTR3

CH1

CH2

CK12

OE3 CH12OE2


CNTR2

CH1

CH2

CK12

TPE1 CK12TPE2 TIR1 TIE1 TIE2TIR2

COMR1 Setting CH1 interval timer (compare value)

COMR2 Setting CH2 interval timer (compare value)

: Used bit: Set to 1.: Set to 0.: Unused bit (set to 0)

CH1 : 8 - bit timer mode CH1CH2 : 8 - bit timer mode CH2CK12 : CK12 mode

148


Figure 7.7-2 2-ch 8-bit PPG timer operation

Reference

• When "00H " is set to the COMR register, the output of the PWM pin is inverted in the cycle of thecount clock.

• While interval timer functions are enabled, the output level of the PWM pin in the counter stopstate (CNTR2:TPE1=0, TPE2=0) is at "L" level.

Note

During the operation of the interval timer function (CNTR2:TPE1,TPE2=1), be sure not to change thecorresponding count clock cycle (CNTR1: SC11, SC10 or SC21, SC20). However, it should be notedthat SC21 and SC20 bits have no meaning in the CK12 mode.

TIR bit

TPE bit

OE bit

PWM pin

FFH

80H

00H

Timer cycle Changing COMR value (FFH 80H)Time

When output pin control bit (OE) is "0", it is general purpose I/O port.

Clear by program

Comparison value (FFH) Comparison value (80H)

: If changing the value of compare register (COMR) during counter operation, it is enabled from next cycle.

Counter value

COMR value (FFH)

149



This section explains the 8-bit PWM mode operation of the 2-ch 8-bit PWM timer.

Operation of PWM Timer FunctionsTo use the 2-ch 8-bit PWM timers (CH1 and CH2) as the PWM timer in the 8-bit PWM mode, thesettings shown in Figure 7.8-1 are required.

Figure 7.8-1 8-bit PWM Mode Settings

When the counter is activated, the counter is incremented from 00H at the start-up of the selected

count clock. The PWM terminal output (PWM waveform) remains in the "H" level until the countervalue matches the value set in the COMR register. Then, the output remains in the "L" level untilthe counter value overflows (FFH to 00H).

The CK12 PWM mode operation takes place when the CK12 bit is set to "1" and the CH1 andCH2 are operated in the 8-bit timer mode and the PWM mode, respectively.

Figure 7.8-2 shows the PWM waveform output from the PWM pin.


CNTR1

CH1

CH2



CNTR3

CH1

CH2

OE3 CH12OE2


CNTR2

CH1

CH2

TPE1 CK12TPE2 TIR1 TIE1 TIE2TIR2

COMR1 Setting CH1 pulse "H" width (compare value)


: Used bit: Set to 1: Set to 0: Unused bit (set to 0)

CH1 : 8 - bit timer mode CH1CH2 : 8 - bit timer mode CH2

150


Figure 7.8-2 An Example of PWM Waveform Output in the 8-bit PWM Mode

Reference

While PWM timer functions are enabled, the level immediately before the stop is held as the outputlevel of the PWM pin in the counter stop state (CNTR2:TPE1=1,TPE2=0)).

Note

During the operation of the PWM timer function (CNTR2: TPE1=1, TPE2=1), be sure not to changethe corresponding count clock cycle (CNTR1: SC11, SC10 or SC21, SC20).

When CH1 is in the PWM timer mode of operation, the CK12 mode (CNTR2: CK12=1) cannot beset.

Counter value FFH00H

HL

HL

HL

PWM waveform

00H

00H

00H

Counter value 80H FFH00H

PWM waveform

Counter value

PWM waveform

FFH00H

1 count

At COMR register value "00H" (Duty ratio 0%)


At COMR register value "FFH" (Duty ratio 99.6%)

151



This section explains the 7-bit PWM mode (high speed mode) operation of the 2-ch 8-bit PWM timer.

Operation of high-speed PWM Timer FunctionsTo use the 2-ch 8-bit PWM timers (CH1 and CH2) as the PWM timer in the 7-bit PWM mode, thesettings shown in Figure 7.9-1 are required.

Figure 7.9-1 7-bit PWM Mode Settings

When the counter is activated, the counter is incremented from 00H at the start-up of the selected

count clock. The PWM terminal output (PWM waveform) remains in the "H" level until the countervalue matches the value set in the COMR register. Then, the output remains in the "L" level untilthe counter value overflows (7FH to 00H).

Since the 7-bit PWM mode has one less counter bit than the 8-bit PWM mode, it enables highspeed operation with twice the PWM frequency (half a cycle).

The CK12 PWM mode operation takes place when the CK12 bit is set to "1" and the CH1 andCH2 are operated in the 8-bit timer mode and the PWM mode, respectively.

Figure 7.9-2 shows the PWM waveform output from the PWM pin.


CNTR1

CH1

CH2


bit7

bit7

bit7

bit6 bit5 bit4 bit3 bit2 bit1 bit0

CNTR3

CH1

CH2

OE3 CH12OE2


CNTR2

CH1

CH2

TPE1 CH12TPE2 TIR1 TIE1 TIE2TIR2




CH1 : 7 - bit timer mode CH1CH2 : 7 - bit timer mode CH2

152


Figure 7.9-2 An Example of PWM Waveform Output in the 7-bit PWM Mode

Reference

While PWM timer functions are enabled, the level immediately before the stop is held as the outputlevel of the PWM pin in the counter stop state (CNTR2:TPE1=1,TPE2=0).

Note

During the operation of the PWM timer function (CNTR2: TPE1=1, TPE2=1), be sure not to changethe corresponding count clock cycle (CNTR1: SC11, SC10 or SC21, SC20).

When CH1 is in the PWM timer mode of operation, the CK12 mode (CNTR2: CK12=1) cannot beset.

7FH00H

HL

HL

HL

40H 7FH00H

7FH00H

1 count

At COMR register value "00H" (Duty raito 0%)


At COMR register value "7FH" (Duty ratio 99.2%)

Counter value

PWM waveform

00H

Counter value

PWM waveform

00H

Counter value

PWM waveform

00H

153


7.10 Explanation of CH12 PWM mode operation

This section explains the CH12 PWM mode operation of the 2-ch 8-bit PWM timer.

Operation of CH12PWM modeTo use the 2-ch 8-bit PWM timers (CH1 and CH2) as the PWM timer in the CH12 PWM mode,the settings shown in Figure 7.10-1 are required.

Figure 7.10-1 CH12PWM mode setting

The CH1 and CH2 counters, when activated, start counting up from "00H " using the count clock

selected for each. The PWM terminal output (PWM waveform) remains in the L level until theCH1 counter value matches the value set in the COMR1 register. If a match is found, it switchesto the "H" level. When the CH2 counter value matches the value set in the COMR2 register, theCH1 and CH2 counters will be cleared simultaneously and then start counting from "00H" again.When this happens, the PWM terminal output switches to the "L" level and the interruptionrequest flag bit will be set (CNTR2: TIR2=1).

Be sure to simultaneously start the CH1 and CH2 counters (CNTR2: TPE1=1, TPE2=1). Startingthese counters separately may affect the "L" width of the first single cycle of the PWM wave orthe cycle.

When the CH1 timer value that represents the "L" width of the PWM wave becomes larger thanthe CH2 timer value that represents the PWM wave cycle, the PWM wave is no longer output.

Figure 7.10-2 shows the PWM waveform output to the PWM terminal when the same count clockcycle is selected for CH1 and CH2.


CNTR1 PTX1 P7M1 P7M2PTX2 SC11 SC21 SC20SC10


CNTR3 OE3 CH12OE2


CNTR2 TPE1 CK12TPE2 TIR1 TIE1 TIE2TIR2

COMR1 Setting PWM wave pulse "L" width (compare value)

COMR2 Setting PWM wave 1 cycle (compare value)


154


Figure 7.10-2 Example of PWM waveform (PWM pin) output

Reference

While PWM timer functions are enabled, the level immediately before the stop is held as the outputlevel of the PWM pin in the counter stop state (CNTR2:TPE1=1,TPE2=0).

Note

During the operation of the PWM timer function (CNTR2: TPE1=1, TPE2=1), be sure not to changethe count clock cycle (CNTR1:SC11, SC10 and SC21, SC20).

During the CH12 PWM mode operation, the CK12 mode (CNTR2: CK12=1) cannot be set. Be alsosure to disable the CH1 interruption request output (CNTR2: TIE1=0).

CH1 Counter value 00H

HL

PWM waveform

PWM waveform

PWM waveform



HL

HL


80H00H

80H00H

00H

80H00H80H00H

80H00H

80H00H

00H40H 40H

FFH00H

00H

1 count

At COMR1 register value "80H", COMR2 register value "80H" (Duty ratio 0%)

At COMR1 register value "40H", COMR 2 register value "80H" (Duty ratio 50%)

CH1 Counter value 00H CH2 Counter value 00H

At COMR1 register value "00H", COMR 2 register value "FFH" (Duty ratio 99.6%)

: The minimum value of "L" width can be reduced by setting the CH1 count clock at the high speed more than the CH2 count clock.

(CH1 Timer time CH2 Timer time)

155


7.11 Explanation of the Operation of the Prescaler of the 2-ch 8-bit PWM Timer

This section explains the prescaler operation of the 2-ch 8-bit PWM timer.

Operation of prescalerThe prescaler of the 2-ch 8-bit PWM timer is enabled when one of the counter operation enablebits (CNTR2: TPE1 and TPE2) of the PWM control register 2 is set to "1".

This means that if TPE1 are TPE2 are set to "1" at the same time, CH1 and CH2 operate exactlythe same way from the first cycle.

However, if TPE1 or TPE2 has already been set to Åg1Åh when the counter that does notcorrespond to the bit that has been set to Åg1Åh is enabled, a difference of less than one countclock cycle occurs during the first cycle because the counting does not start synchronously.

Figure 7.11-1 shows the prescaler operation and Figure 7.11-2 shows the prescaler output.

Figure 7.11-1 Prescaler Operation

Figure 7.11-2 Prescaler Output

: B generates the difference as A within 1 cycle of the counter clock cycle.

A B

TPE1

TPE2

Count clock

CH1 square wave outputCOMR1 value 01H

CH2 square wave outputCOMR2 value 01H

TPE

1tinst

8tinst

16tinst

64tinst

tinst : instruction cycle

156


7.12 States in Each Mode During Operation of 2-ch 8-bit PWM Timer

This section explains the operation to take place when a transition to the sleep mode or stop mode occurs or when a cancellation request is made during the 2-ch 8-bit PWM timer operation.

Operations in the Standby Mode and at a Suspension" Figure 7.12-1 Operation of the counter during standby mode and operation halt (for the intervaltimer function) " and " Figure 7.12-2 Operation in the Standby Mode and at a Suspension " showthe state of the counter value when a transition to the sleep mode or stop mode occurs and whena cancellation request is made during the operation of the interval timer function and the PWMtimer function.

When switched to the stop mode, the counter holds a value and stops. When the stop mode isreleased by an external interrupt, the counter starts operation from the held value. Therefore, thefirst interval and the first cycle of the PWM waveform are not the values that are set. After therelease of the stop mode, initialize the 8-bit PWM timer.

While the interval timer functions are enabled:

Figure 7.12-1 Operation of the counter during standby mode and operation halt (for the interval timer function)

TIR bit

TPE bit

PWM pinOE 1

FFH

00H

Timer cycleTime

SLP bit(STBC register)


Stop request

Sleep

Stop


Sleep release by IRQ8

Clearing by operation stopCOMR value (FFH)

Operation stop Operation restart

Clearing by program

"L" level during stop operation

When bit of specifying pin state (STBC: SPL) of standby control register is "1", PWM pin in stop mode is High impedance state.When SPL bit is "0", holding the value of immediately before transmission to stop mode.

:

Counter value

Oscillation stabilization wait time

157


At PWM timer function

Figure 7.12-2 Operations in the Standby Mode and at a Suspension

PWM pin(PWM waveform)

00H 00H 00H 00H 00H

TPE bit



Operation stop Operation restart

Sleep


Oscillation stabilization wait time

Holding level of immediately before stop

Sleep release by other than IRQ8(IRQ8 is not generated.)Stop

: When bit of specifying pin state (STBC: SPL) of standby control register is "1", PWM pin in stop mode is High impedance state.When SPL bit is "0", holding the value of immediately before transmission to stop mode.

158


7.13 Precautions when Using 2-ch 8-bit PPG Timer

This section provides notes on using the 2-ch 8-bit PPG timer.

Precautions when Using 2-ch 8-bit PPG Timer

Error

Activating the counter by program is not synchronized with the start of counting-up using theselected count clock. Therefore, the time from activating the counter until a match with the PWMcompare register (COMR) is detected may be shorter than the theoretical time by a maximum ofone cycle of the count clock. Figure 7.13-1 shows the error in the count operation start timing.

Figure 7.13-1 Error in count operation start time

Notes on using programs to set time-base timer

• During the operation of the interval timer function and the PWM timer function (CNTR2:TPE1=1, TPE2=1), be sure not to change the corresponding count clock cycle (CNTR1: SC11,SC10 or SC21, SC20).

• Stop the counter (CNTR2:TPE1=0, TPE2=0), disable interrupts (CNTR2:TIE1=0, TIE2=0), andclear the interrupt request (CNTR2:TIR1=0, TIR2=0) before switching between the intervaltimer function and PWM timer function (CNTR1:PTX1, PTX2).

• In the CK12 mode (CNTR2: CK12=1), be sure not to set the CH12 PWM mode (CNTR3:CH12=1) and the CH1 PWM timer operation (CNTR1: PTX1=1).

• In the CH12 PWM mode, disable the CH1 interruption request output (CNTR2: TIE1=0). Makealso sure not to set the CK12 mode.

• Execution cannot return from interrupt processing if interrupt requests are enabled(CNTR2:TIE1=1, TIE2=1) and the interrupt request flag bit (CNTR2:TIR1, TIR2) is "1". The TIRbit must be cleared.

• When a match is found between the counter value and the COMR register value concurrentlywith the stop of the counter (CNTR2:TPE1=0, TPE2=0), the TIR bit is not set.

1 cycle

Counter start

Error 00H cycle

Counter value

Counter clock

00H 01H 02H 03H 04H

159


7.14 Program Example for 2-ch 8-bit PWM Timers (interval function)

This section shows a programming example of the interval timer function of the 2-ch 8-bit PWM timers in the 8-bit timer mode and the CK12 mode.

Programming example of the 8-bit timer mode


• Use CH1 as the interval timer in the 8-bit timer mode.

• Generates repeated 3.2ms interval timer interrupts.

• Outputs a square wave from the PWM1 pin. The output inverts after each interval time.

• The COMR1 register value when the interval time is approx. 3.2 ms at the main clockoscillation of 12 MHz is shown below. Use the internal count clock cycle of "64t inst" as the

count clock cycle (t inst: maximum clock speed (gear)).

- Register value of COMR1=3.2mS/ (64×4/12 MHz) - 1=149(095H)

160



CNTR1 EQU 0027H ;PWM Control register 1 address CNTR2 EQU 0028H ;PWM Control register 2 address CNTR3 EQU 0029H ;PWM Control register 3 address COMR1 EQU 002AH ;PWM Compare register 1 address TPE1 EQU CNTR2:7 ;CH1 Counter operation enable bit definition TIR1 EQU CNTR2:3 ;CH1 Interrupt request flag bit definition ILR3 EQU 007D ;Interrupt level setting register address INT_V DSEG ABS ; DATA SEGMENT ORG 0FFEAH IRQ8 DW WARI1 ; Interrupt vector setting INT_V ENDS ; ---------- Main program ----------------------------------------------------- CSEG ; CODE SEGMENT ; Stack pointer (SP) etc. are already initialized. : CLRI ; Interrupt disable CLRB TPE1 ; Counter operation stop MOV ILR3,#11111101B ; Interrupt level setting (Level 1) MOV COMR1,#095H ; Set value (interval time) to which counter vale is compared

MOV CNTR1,#00001100B ; Interval timer operation, 64t inst selection MOV CNTR3,#00100000B ;PWM1 pin output enable MOV CNTR2,#10000010B ; Counter operation start, Interrupt request output SETI ; Interrupt enable : ; ---------- Interrupt program ------------------------------------------------------WARI1 CLRB TIR1 ; Interrupt request flag clear

PUSHW A XCHW A,T ;A,T return PUSHW A : User Processing :

POPW A XCHW A,T ;A,T return POPW A RETI ENDS

; -------------------------------------------------------------------------------------------------------------------

161


Programming example of the CH12 PWM mode


• Set the CH1 interval timer value to "3.2ms" (Square wave output cycle =6.4ms) without usingany interruption.

• CH2 repeatedly generates a 64ms interval timer interruption using CH1 as the count clock.

• Output the square wave that is reversed during the CH2 interval time to the PWM2 terminal.

• The COMR1 register value when the interval time of the CH1 timer is approx. 3.2 ms at themain clock oscillation of 12 MHz is shown below. Use the internal count clock cycle of "64t inst"

as the count clock cycle (tinst: maximum clock speed (gear)).

- Register value of COMR1=3.2ms/(64×4/12MHz)-1=149(095H)

The COMR2 register value when the interval time of the CH2 timer that uses the CH1 squarewave output is approx. 64 ms is shown below.

• Register value of COMR2=64ms/(3.2×2) ms=10(00AH)

162



CNTR1 EQU 0027H ;PWM Control register 1 addressCNTR2 EQU 0028H ;PWM Control register 2 addressCNTR3 EQU 0029H ;PWM Control register 3 addressCOMR1 EQU 002AH ;PWM Compare register 1 address COMR2 EQU 002BH ;PWM Compare register 2 address TPE1 EQU CNTR2:7 ;CH1 Counter operation enable bit definition TPE2 EQU CNTR2:6 ;CH2 Counter operation enable bit definition TIR2 EQU CNTR2:2 ;CH2 Interrupt request flag bit definiton ILR3 EQU 007D ; Interrupt level setting register address INT_V DSEG ABS ; DATA SEGMENT ORG 0FFEAH IRQ9 DW WARI ; Interrupt vector setting INT_V ENDS ; -------------- Main program ------------------------------------------------------------------------------------- CSEG ; CODE SEGMENT ;

: CLRI ; Interrupt disable CLRB TPE1 ; Counter operation stop CLRB TPE2 MOV ILR3,#11111101B ; Interrupt level setting (Level 1) MOV COMR1,#095H ; MOV COMR2,#00AH MOV CNTR1,#00001100B ; Interval timer operation, 64t MOV CNTR3,#01000000B ;PWM2 pin output enable

MOV CONT2,#11100001B ; Counter operation start, Interrupt request output

inst selection

Stack pointer (SP) etc. are already initialized.

Set value (interval time) to which counter vale is compared

SETI ; Interrupt enable : ; -------------- Interrupt processing ---------------------------------------------------------------------------- WARI CLRB TIR2 ; Interrupt request flag clear PUSHW A XCHW A,T ;A,T return PUSHW A : User processing : POPW A XCHW A,T ;A,T return POPW A RETI ENDS ; ---------------------------------------------------------------------------------------------------------------------

163


7.15 Programming Example of the 2-ch 8-bit PWM Timer (PWM Timer Function)

This section shows a programming example of the PWM timer function of the 2-ch 8-bit PWM timers in the 8-bit PWM mode, 7-bit PWM mode and CH12 PWM mode.

Program Example of PWM Timer Functions


• Use CH1 as the PWM timer in the 8-bit PWM mode and make output to the PWM1 terminal.

• Use CH2 as the PWM timer in the 7-bit PWM mode (high speed mode) and make output to thePWM2 terminal.

• Generates a PWM waveform with a 50 duty ratio, then changes the duty ratio to 25.

• Interrupt request does not occur.

• If each count clock is set as "16 tinst" (tinst: maximum clock speed (gear)) of the internal count

clock at the main clock oscillation of 12 MHz, the CH1 PWM wave cycle is 16 × 2/6 MHz ×256=1.365 ms and the CH2 PWM wave cycle is 16 × 4/12 MHz × 128=6.82 ms.

• The COMR register value when the duty ratio is 50 in the 8-bit PWM mode is shown below.

- Register value of COMR1=50/100×256=128(080H)

• The COMR register value when the duty ratio is 50 in the 7-bit PWM mode is shown below.


164



CNTR1 EQU 0027H ;PWM Control register 1 address CNTR2 EQU 0028H ;PWM Control register 2 address CNTR3 EQU 0029H ;PWM Control register 3 address COMR1 EQU 002AH ;PWM Compare register 1 address COMR2 EQU 002BH ;PWM Compare register 2 address TPE1 EQU CNTR2:7 ;CH1 Counter operation bit definition TPE2 EQU CNTR2:6 ;CH2 Counter operation bit definition ; -------------- Main program ----------------------------------------------------------------------------------------- CSEG ; CODE SEGMENT : CLRB TPE1 ; Counter operation stop CLRB TPE2 MOV COMR1,#80H ; Pulse "H" width setting, duty ratio 50%

; PWM timer operation, 8/7-bit PWM mode, 16t selection MOV COMR2,#40H MOV CNTR1,#11011010B inst

MOV CNTR3,#01100000B ;PWM1, PWM2 pin output enable MOV CNTR2,#11000000B ; Counter operation start, Interrupt request output disable : :

MOV COMR1,#40H ; Change duty ratio to 25% (Valid from the cycle of next PWM wave)

MOV COMR2,#20H : ENDS ; ------------------------------------------------------------------------------------------------------------------------

END

165


Programming example of the CH12 PWM mode


• Generates a PWM waveform with a 50 duty ratio, then changes the duty ratio to 25.

• No interruptions should be used.

• If each count clock is set as "16 tinst" (tinst: maximum clock speed (gear)) of the internal count

clock and COMR1 register value is set as 128 (80H) at the main clock oscillation of 12 MHz,the PWM wave cycle is 16 × 4/12 MHz × 128=682.6 ms.

• Set the COMR1 register as follows to set a 50 duty ratio.



CNTR1 EQU 0027H ;PWM Control register 1 addressCNTR2 EQU 0028H ;PWM Control register 2 addressCNTR3 EQU 0029H ;PWM Control register 3 addressCOMR1 EQU 002AH ;PWM Compare register 1 address COMR2 EQU 002BH ;PWM Compare register 2 address TPE1 EQU CNTR2:7 ;CH1 Counter operation bit definition TPE2 EQU CNTR2:6 ;CH2 Counter operation bit definition ; -------------- Main program --------------------------------------------------------------------------------------

CSEG ; CODE SEGMENT : CLRB TPE1 ; Counter operation stop CLRB TPE2 MOV COMR1,#40H ; Pulse "H" width setting, duty ratio 50 MOV COMR2,#80H ; 1 cycle of pulse setting MOV CNTR1,#00001010B ;16tinst selection MOV CNTR3,#01010000B ;PWM2 pin output enable MOV CNTR2,#11000000B ; Counter operation start, Interrupt request output disable : : MOV COMR1,#20H ; Change duty ratio to 25% (Valid from the cycle of

next PWM wave)

: ENDS ; ------------------------------------------------------------------------------------------------------------------------END

166

CHAPTER 8External Interrupt Circuit

(level)

This chapter explains the functions and operations of the external interruption circuit (level).

8.1 Overview of External interrupt circuit (Level)

8.2 Configuration of external interrupt circuit

8.3 Pins of external interrupt circuit

8.4 Register for external interrupt circuit

8.5 Interrupt of external interrupt circuit

8.6 Operation of external interrupt circuit

8.7 Sample program for external interrupt circuit

167

CHAPTER 8 External Interrupt Circuit (level)

8.1 Overview of External interrupt circuit (Level)

The external interruption circuit detects the level of the signal input to the seven external interruption terminals and generates a single interruption request to the CPU.

External interruption circuit function (Level detection)The external interruption circuit has the function to detect the "L" level signal input to the externalinterruption terminals and generate an interruption request to the CPU. This interruption enablesa return from the standby mode and a transition to the normal operation state.

• External interrupt pin:7 (P31/INT1 to P37/INT7)

• External interruption factor: Input of the "L" level signal to the external interruption terminal

• Interruption control: Enabling and disabling of the external interruption input by the externalinterruption control register (EIE)

• Interruption flag: Detection of the "L" level signal by the external interruption request flag bit ofthe external interruption flag register (EIF)

• Interruption request: Generated by OR of each external interruption factor (IRQ0)

168


8.2 Configuration of external interrupt circuit

The external interruption circuit is comprised of three blocks shown below.• Interrupt request generation circuit• External interrupt 1 control register (EIE) • External interrupt flag register (EIF)

Block diagram of the external interrupt circuitFigure 8.2-1 Block diagram of the external interrupt circuit

Interrupt request generation circuit

The interruption request generation circuit generates an interruption request signal using thesignal input to the external interruption terminal and the external interruption input enable bits.

External interrupt control register (EIE)

The external interruption input enable bits (IE1 to IE7) enable or disable the "L" level input fromthe corresponding external interruption terminals.

External interrupt flag register (EIF)

Holds or clears the interruption request signal generated by the external interruption request flagbit (IF0).

Interrupt request generating circuit

IRQ0: Generates an interruption request when the "L" level signal is input to one of the externalinterruption terminals and the external interruption input enable bit that corresponds to theterminal is set to "1".

Interrupt request generation circuit

IF0IE7 IE5 IE4 IE3 IE1 Reser-vedIE6 IE2

P31/INT1 Pin

P32/INT2 Pin

P33/INT3 Pin

P34/INT4 Pin

P35/INT5 Pin

P36/INT6 Pin

P37/INT7 Pin

External interrupt requestIRQ0

External Interrupt Control Register (EIE) External Interrupt Flag Register (EIF)

7

169


8.3 Pins of external interrupt circuit

Pins used by the external interrupt circuit

Pins used by the external interrupt circuitThe pins related to the external interrupt circuit are 7 external interrupt pins.

P31/INT1 to P37/INT7

These external interruption terminals serve dual functions as the external interruption input(hysteresis input) terminal and as the general-purpose I/O port.

P31/Å`P37/ These terminals set up the terminal that corresponds to the port orientation register(DDR3) as the input port and function as external interruption terminals when the externalinterruption input is enabled by the external interruption control register (EIE). The state of aterminal, if set up as an input port, can always be read out from the port data register (PDR3).

Table 8.3-1 lists the pins used by the external interrupt circuit.

Table 8.3-1 Pins used by the external interrupt circuit

External interrupt pin Use for external interrupt input(Interrupt input enable)

Used as General-purpose I/O ports(Interrupt input disable)

P31/INT1 INT1 (EIE:IE1=1, DDR3:bit1=0) P31(EIE:IE1=0)







170


Block diagram of the pins used by the external interrupt circuit

Figure 8.3-1 Block diagram of the pins related by the external interrupt circuit

Reference


Relationship between the interruption enable bit and the external interruption terminal of the external interruption circuit

The relationship between the interruption enable bit and the external interruption terminal isshown in Table 8.3-2 .

PDR read

PDR write

Output latch

Stop mode (SPL=1)


Pin

Pch

NchDDR

PDR read

Stop mode

DDR write

Pch


Pull - up option register

to External interrupt

circuit

DDR read


P31/INT1P32/INT2P33/INT3P34/INT4P35/INT5P36/INT6P37/INT7

Internal Data B

us



Table 8.3-2 Correspondence between the interruption Enable Bit and the external interruption terminal

Register Bit name External interrupt pin

EIE Bit1 IE1 INT1

Bit2 IE2 INT2

Bit3 IE3 INT3

Bit4 IE4 INT4

Bit5 IE5 INT5

Bit6 IE6 INT6

Bit7 IE7 INT7

171


8.4 Register for external interrupt circuit

This section describes the registers associated with external interrupt circuit.

Registers Associated with External Interrupt Circuit

Figure 8.4-1 External interrupt related registers

IE7 IE5IE6


0 0 3 CH

Address

00000000B

Initial value

R/W

IE1 Reserved

R/W R/W R/W

IE4 IE3 IE2

R/W


0 0 3 DH

Address

XXXXXXX0B

Initial value

IF0

R/W

EIE (External interrupt control register)

EIF (External interrupt flag register)

R/W R/W

R/W

X

: Readable and Writable: Unused: Undefined

172


8.4.1 External interrupt control register (EIE)

The external interruption control register (EIE) enables and disables the interruption input to the external interruption terminal.

External interrupt control register (EIE)

Figure 8.4-2 External interrupt control register (EIE)

R/W

IE7


0 0 3 CH

Address

00000000B

Initial value

IE1 ReservedIE5

R/W R/WR/W

IE6 IE2IE4 IE3

R/W R/WR/W


0

1

External interrupt input disable

External interrupt input enable

IE1

IE7

R/W : Readable and Writable: Initial value

Table 8.4-1 Correspondence between Each Bit of the external interruption Control Register (EIE) and the external interruption terminal

Bit name External interrupt pin

Bit7 IE7 INT7

Bit6 IE6 INT6

Bit5 IE5 INT5

Bit4 IE4 INT4

Bit3 IE3 INT3

Bit2 IE2 INT2

Bit1 IE1 INT1

173


Explanation of external interrupt control register (EIE) bits

Bit name Function

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2Bit1

IE1 to IE7: External interrupt input enable bit

• These bits are used to enable and disable the interruption input to theexternal interruption terminal.

• When these bits are set to "1", the corresponding external interruptionterminals function to accept the external interruption input.

• When these bits are set to "0", on the other hand, the correspondingexternal interruption terminals function as the general-purpose portand no external interruption input is accepted.

Reference:• When using the external interruption terminal, be sure to set the bit that

corresponds to the port orientation register (DDR3) to "0" and set upthe terminal for input.

Regardless of the state of the external interruption input enable bit, thestate of the external interruption terminal can directly be read out by theport data register (PDR3).

Bit0 Reserved bit Reserved bit Be sure to set this bit to "0".

174


8.4.2 External interrupt flag register (EIF)

The external interruption flag register (EIF) detects the level interruption and the clears the interruption request flag.

External interrupt flag register (EIF)

Figure 8.4-3 External interrupt flag register (EIF)

Table 8.4-2 Explanation of the Function of Each Bit of the external interruption Flag Register (EIF)

Bit name Function

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2Bit1


Bit0 IF0: Externalinterrupt requestflag bit

• When the "L" level signal is input to the external interruption terminal that is externalinterruption enabled, the corresponding bit will be set to "1".

• Setting the bit to "0" clears the data during writing and setting the bit to "1" causes nochanges to this bit or other bits.

Note:The external interruption input enable bits (EIE: IE0 to IE7) of the external interruptioncontrol register only disable the external interruption input. The interruption request willcontinuously be generated until the IF0 bit is cleared to "0".

External interrupt request flag bit


0 0 3 DH

Address

XXXXXXX0B

Initial value

IF0

R/W

IF0

0

1

No interrupt request (No "L" level detected)

Interrupt request generated ("L" level detected)

Read

Clear this bit

This bit remains unchanged and has no effect on any other part of the device.

WriteR/W

X


175


8.5 Interrupt of external interrupt circuit

The factors for the interruption generated by the external interruption circuit include the "L" level signal input to the external interruption terminal.

Interrupt During the Operation of External Interrupt CircuitWhen the "L" level signal is input to the external interruption terminal that is interruption inputenabled, the external interruption request flag bit (EIF: IF0) will be set to "1" and an interruptionrequest (IRQ0) will be generated to the CPU. Set the IF0 bit to "0" to clear the interruption requestduring the interruption handling routine.

If the external interruption request flag bit (IF0) is set to Åg1Åh, the interruption request willcontinuously be generated until the IF0 bit is cleared to Åg0Åh even though the externalinterruption input is disabled by the interruption enable bits (IE1 to IE7) of the external interruptioncontrol register (EIE). So, be sure to clear the IF0 bit.

Moreover, if the external interruption terminal remains in the "L" level, the IF0 bit will be set againeven when the IF0 bit is cleared in the state where the external interruption input is not disabled.Disable the external interruption input or remove the external interruption factor, if necessary.

ReferenceTo enable the CPU interruption after the cancellation of a reset, clear the IF0 bit first.

Note• The "L" level input to the external interruption terminal generates the same interruption request

(IRQ0). For this reason, which terminal corresponds to the external interruption input must bedetermined by reading out the port data register (PDR3) before the signal input switches to the"H" level.

• The external interruption circuit can be used to cancel the stop mode by an interruption.

Register Associated with Interrupt Generation by External Interrupt Circuit and Vector Table

ReferenceFor interrupt operation, see "3.4.2 Interrupt processing".

Table 8.5-1 Vector table and registers used by the external interrupts

Interruptname



IRQ0 ILR1(007B H ) L01(bit1) L00(bit0) FFFA H FFFB H

176


8.6 Operation of external interrupt circuit

The external interruption circuit detects the "L" level signal input to the external interruption terminals and generates an interruption request to the CPU.

Operation of External Interrupt CircuitThe settings shown in Figure 8.6-1 are required to use the external interrupt circuit.

Figure 8.6-1 External interrupt circuit setting

Generates an IRQ0 interruption request to the CPU when the "L" level signal is input to theexternal interruption terminal that corresponds to IE1 to IE7 in the state where the externalinterruption input is partly enabled.

Figure 8.6-2 shows the operation of the external interruption circuit (when using terminals).

Figure 8.6-2 External interrupt operation (INT1)

ReferenceEven when the external interruption terminal is used as the external interruption input, the state ofthe terminal can directly be read out by the port data register (PDR3).


EIF

Used bitSet the bi corresponding to the pin to be used to "0".

::

IF0

EIE IE7 IE6 ReservedIE1IE2IE3IE4IE5

DDR3

Input wave to INT1 pin(detect "L" level)

Operation of interrupthandler for IRQ0

EIF : IF0(Same as IRQ0 state)

EIE : IE1

PDR3 : bit1

Interrupt processing Interrupt processing

Clear within Interrupt processing routine

External interrupt input enable state

Readable at any point

RETI RETI

177


8.7 Sample program for external interrupt circuit

An example of programming external interrupt circuit is given below.

Sample program for external interrupt circuit


An interruption is generated by detecting the "L" level signal input to the INT1 terminal.


DDR3 EQU 000DH ; Port direction register address EIE EQU 003CH ; External interrupt control register address EIF EQU 003DH ; External interrupt flag register address IF0 EQU EIF0 ; External interrupt request flag bit definition ILR1 EQU 007BH ; Interrupt level setting register address INT_V DSEG ABS ; DATA SEGMENT ORG 0FFFAH IRQ0 DW WARI ; Interrupt veltor setting INT_V ENDS ; -------------- Main program ------------------------------------------------------------------------------- CSEG ; CODE SEGMENT ; Initialize stack pointer (SP) etc.

: ; CLRI ; Interrupt disable CLRB IF0 ; External interrupt request flag clear MOV ILR1 #11111110B ; Set interrupt level to 2.

MOV DDR3, #00000000B ; Set INT1 pin to input.

MOV EIE #00000010B ; INT1 pin external interrupt input enable SETI ; Interrupt enable

:

; -------------- interrupt processing routine -------------------------------------------------------------- WARI MOV EIE #00000000B ; INT1 pin external interrupt input disable

CLRB IF0 ; External interrupt request flag clear PUSHW A XCHW A T PUSHW A : User processing : POPW A XCHW A T POPW A RETI ENDS ; ----------------------------------------------------------------------------------------------------------------

END

178

CHAPTER 9USB Hub

This chapter explains the functions and operations of the USB hub circuit.

9.1 Overview of USB hub

9.2 Configuration of USB hub

9.3 Pins in USB hub

9.4 Register for a USB hub

9.5 Interrupt of USB hub

9.6 Descriptor

9.7 Functional descriptions of USB hub

179

CHAPTER 9 USB Hub

9.1 Overview of USB hub

The USB hub supports the USB (Universal Serial Bus) communication protocol and five downstream ports of the USB interface (of which one is used by the internal USB function). The hub function can specify the operation mode (own power supply mode/BUS power supply mode) and the over-current protection mode by configuring internal register settings.

Function of USB hub circuitThe USB hub circuit performs two-way serial signal transfer with the host controller that supportsthe USB protocol.

• Protocol: Supporting USB Protocol Revision1.0

• Speed: Supports both Full (12 Mbps)/Low (1.5 Mbps) speed.

• USB port: USB port: Built-in USB transceiver. UP_PORT "1",DOWN_PORT "5" (of which onedownstream port is connected to the internal function)

• Clock: Corrects data synchronization using the 48 MHz clock created by the PLL circuit fromthe 6 MHz external clock (synchronized to 1/4 48 MHz inside the USB)

• Power supply operation mode: Specification of the selection of the own power supply mode orthe bus power supply mode enabled.

• Port power supply control: Power supply control on a port-by-port basis

• Over-current protection mode: Down_port over-current detection/protection mode: Global over-current protection. Specification of the over-current protection mode for each port enabled.

• Data check: Automatic generation and checking of Bit Stripping, Bit Stuffing, CRC5 andCRC16

• Data synchronization bit: Retention of the data synchronization bit (DATA0/DATA1 toggle bit)

• USB standard instruction: Automatically responds to all standard instructions (Device class,Hub class)

• Class/Vendor command: Automatically responds to the Class/Vendor command using thevalue set in the hard register.

• Endpoint: Supports Endpoint0 and another Endpoint status change (interruption) endpoint.

• Interruption: Supports two channels for the detection of the suspend state of the USB bus andfor the recovery from the suspend state

• Interruption factor: UP_PORT (and DW-PORT) During the detection of the suspend state andduring the recovery from the suspend state (Since the recovery request from the suspendstate can be accepted in the stop mode, the request can also be used to cancel the stopmode.)

180

CHAPTER 9 USB Hub

9.2 Configuration of USB hub

The USB hub circuit is comprised of the three main elements shown below.• USB hub controller (HUBCTL)• USB repeater block (HUBRPT)• USB hub registers (HMDR, HDSR1 to HDSR4, HSTR, OCCR, DADR and SDSR)

Block Diagram of USB hub circuit

Figure 9.2-1 Block Diagram of USB hub circuit

Internal Data Bus

Downport1State

USBDRV

HUBRPT

HUB Repeater

Serial Interface

Frame Timer

Pll circuit

End point 0/1 config HubComand Interpreter

USBDRV SBDRV USBDRV USBDRV

POWER control

Downport4State

Downport3State

Downport2State

Downport5State

FunctionBLOCK

Interface (Internal)

HUBCTL HUBcontrol

DescripterRegister

Over_CurrentRegister

ROM(Internal)

DeviceDescriptor

DMADescripter

P40/POW 5 P41/POW 2 P42/POW 3 P43/POW 4

Pin

Pin Pin Pin Pin

D4VP

D4VM

D3VP

D3VM

D2VP

D2VM

D5VP

D5VM

Pin

RPVPRPVM

I RQ2

I RQ4

181

CHAPTER 9 USB Hub

USB hub mode register (HMDR)

A register to specify the power supply operation mode (own power supply/BUS power supply) ofthe USB hub and reset the USB hub circuit section.

Hub descriptor register (HDSR1, 2, 3, 4)

Sets the USB hub configuration information (HUB descriptor information).

Hub status register (HSTR)

A register for USB up port and down port status information.

Over-current control register (OCCR)

The over-current register is a control register to report to the host controller that the currentdetection has occurred in the down port.

Descriptor ROM Address Register (DADR)

An address register to specify the first address that stores the configuration values of thestandard descriptor supported by the hub.

182

CHAPTER 9 USB Hub

9.3 Pins in USB hub

Block Diagram of Pins and pins related to USB hubs are shown.

Pin related to USB hubUSB hub related terminals include route port connection signal (RPVP, RPVM) terminals of theUSB serial bus, USB down port connection signal (D2VP, D2VM, D3VP, D3VM, D4VP, D4VM,D5VP, D5VM) terminals and down port power supply control output signal (POW2-5) terminals. Itshould be noted that a general-purpose input port is used as the over-current detection input andthat the detection result will be set in the over-current register by software and reported to thehost controller. The USB bus interface signals, excluding the POWER control signal, has a built-inUSB driver/receiver, and have full and low speed electric characteristics of the USB interface.The route ports (RPVP, RPVM) are connected at full speed and the down ports automaticallyswitch between the full and low speed mode depending on the device they connect to.

• RPVM: Plus signal of the route port of the USB serial bus interface

• RPVM: Minus signal of the route port of the USB serial bus interface

• D2VM: Plus signal of the down port 2 of the USB serial bus

• D2VM: Minus signal of the down port 2 of the USB serial bus

• D3VP: Plus signal of the down port 3 of the USB serial bus






• POW2-5: Down port power supply enable output signal and the CMOS interface signal

• OVER_CURRENT INPUT: No dedicated input terminal is available for the reporting of over-current detection by the down port to the host controller. Input the over-current detection signalto the general-purpose input port terminal. Checks the over-current state of the input port byusing software polling or external interruption function, sets the result in the over-currentregister and reports to the host controller. (The over-current detection mode supports theglobal mode and the port specific mode) To perform over-current detection for each port, makeconnection to each down port input (Port 2 to 5).

Note

The hub supports five down ports. Port No. 1 is dedicated to the internal function.

183

CHAPTER 9 USB Hub

Block Diagram of Pins

Figure 9.3-1 Block Diagram of Pins related to a hub

Pin

Pch

Nch

Pch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop mode (SPL=1)

from resource output



DDR

Stop mode


DDR read


From Pull - up controlregister

P40/POW5P41/POW2P42/POW3P43/POW4P44 to P47

Internal Data B

us



Pin

Differentialinput

D-_IN

D+_IN

to USB HUB

Pin

SUSPEND,STOP mode FULL/LOW

D+_OUT

D-_OUT

IN/OUT

USB output driverD2VPD3VPD4VPD5VP

D5VM

D2VMD3VMD4VM

RPVP

RPVM

RPVP/RPVMFULL

from USB HUB

D+

D-

pull - up resistor(RPVP )

pin externalpull - down resistor

pin external pull - down resistor

184

CHAPTER 9 USB Hub

9.4 Register for a USB hub

This section shows USB hub related registers.

USB hub related registers

Figure 9.4-1 USB hub related registers


0 0 4 0H

Address

10XXXXXX0B

initial value


0 0 4 1H

Address

XXXXXXXXB

initial value

R/WR/W

R/W R/W

PWCHRSTHMDR


0 0 4 2H

Address

XXXXXXXXB

initial value

PGD0PGD7 PGD6 PGD5 PGD4 PGD3 PGD2 PGD1HDSR2

HDSR1


0 0 4 3H

Address

XXXXXXXXB

initial value


0 0 4 4H

Address initial value

HSTR

HBSR

HDSR3

HDSR1,2,3,4 (Hub descriptor register)

OVM0OVM1


R/WR/W

R/W

R/WR/WR/W R/WR/W

HC0HC7 HC6 HC5 HC4 HC3 HC2 HC1


0 0 4 EH

Address

00000101B

initial value

HDSR4


PTNM0CDS DRV5 DRV4 DRV3 DRV2 PTNM2 PTNM1

HMDR (USB hub mode register)

HSTR (Hub status register)

R RRR/W R

R

P5SUSRTSUS RTSM R4SUS P3SUS P2SUS


0 0 4 5H

Address initial value

OCCR

OCCR (overcurrent register)

R/W

OC5OC4 OC3 OC2

00000000B

POWE

0XXX0000B

DADR (Descriptor ROM address register)bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 0 4 6H

Address

XXXXXXXXB

initial value

DADR


AD8AD15 AD14 AD13 AD12 AD11 AD10 AD9

R/W R/WR/WR/W

R/W R/W

WKUP MWKUP

R/WR/W

R/WR

X

: Readable and Writable: Read only: Unused: Undefined

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9.4.1 USB hub mode register (HMDR)

The USB hub mode register specifies the hub operation power supply mode and controls the reset of the hub circuit block. The register also specifies the hub function power supply mode (self or bus). (When the hub is operated in the own power supply mode, the internal USB function is also operated in the own power supply mode. Write data to this register in byte unit.) However, make sure to always write "0" since Bit 1 to 5 are reserved.

USB hub mode register (HMDR)

BIT7:HRST(Hub Reset)

Individual reset signals for the USB hub circuit section. The reset of the hub circuit block andthe system reset during power-on is OR connected. The reset of the hub circuit block and thesystem reset during power-on is OR connected. When this bit is set to "1", the hub circuitsection is in a reset state during power-on. Writing "0" to this bit will cancel the reset and thehub function will be enabled.

BIT6:POWE(Power control Enable)

A bit used to switch the P40/POW5 to P43/POW4 terminal between the general-purpose portmode and the dedicated terminal mode. Setting this bit to "0" will enable the function as thegeneral-purpose port (P40 to P43) and setting this bit to "1" will enable the USB down ports 2to 5 to output the power supply enable output signal (POW2 to 5).

BIT5 to 1: Reserved bit

Be sure to always write 0 to the bit of this register.

BIT0:PWC(USB HUB/FUNCTION Power mode control)

Specifies the USB circuit (including the hub and function) operation power supply mode (ownpower supply mode, bus power supply mode).

This bit also controls the power supply operation mode of the internal function connected tothe USB hub down port 1. The power supply operation mode of the USB hub and USBfunction (internal) is determined by the setting of this bit. The setting of this bit is reflected on

Bit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7 Initial value

10XXXXX0B

R/W

HRST

R/W

PWCPOWE

R/W

Address

HMDR 0040 H

HRST Hub block reset bit

0 Cancels the reset of the USB hub circuit. / Not in a reset state.

1 Resets the USB hub circuit. / reset state

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CHAPTER 9 USB Hub

the Get Status command response of the hub/function.

PWC USB operation power supply mode

0 USB HUB/FUNCTION bus power supply type

1 USB HUB/FUNCTION own power supply type

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CHAPTER 9 USB Hub

9.4.2 Hub descriptor register (HDSR1, 2, 3, 4)

The hub descriptor register specifies the configuration information of the hub descriptor that responds to the USB command, Get HUB Descriptor. Be sure to perform initial setup before starting operation since the initial values have not been given.

Hub descriptor register (HDSR1, 2, 3, 4)

Hub descriptor register 1(HDSR1:Hub Characteristics)

Set the over-current protection mode in the "wHubCharacteristics" field of the hub descriptor.


Be sure to always write "1" to the bit of this register.

BIT3,2:OVM1,0(Over Current Protect Mode)

Specify the reporting mode of the over-current protection state detected by each hub port.Specify whether to report the sum total of over-current of all hub ports or to report the over-current of each port. (Since the function internally connected to hub port 1 is not equipped withthe over-current detection function, the internal function is not influenced by this mode.)




XXXXXXXXBOVM0OVM1

Address

HDSR1 0041H

R/WR/W

OVM1, 0 Over-current protection mode

0 0 Global over-current protection mode. The hub reports the sum total of over-current of allports but does not report the over-current of each port.

0 1 Port-specific over-current protection. The hub reports the over-current of each port. Eachport has an over-current indicator.

1 X No over-current protection. This setting is enabled for the bus power supply hub that doesnot implement over-current protection.

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CHAPTER 9 USB Hub

Hub descriptor register 2 (HDSR2:Power on Power Good time)

Specify the time it takes for a port to stabilize after the power-on sequence starts on the port in 2ms unit. The system software uses this value to determine how long it must wait before makingaccess to the port turned on. The register setting unit is ms. Specify values in 2 ms unit. (Registersetting range: Minimum 0 m to Maximum 255 ms)

Hub descriptor register 3 (HDSR3:HUB Control Current)

Specify the maximum current consumption of the USB hub controller. Specify the maximumcurrent consumption of this microcontroller LSI with the USB hub function. A set unit is "mA".

Hub descriptor register 4 (HDSR4:HUB Characteristics)

Make compound device settings in the "wHubCharacteristics" field of the Hub Descriptor,"DeviceRemovable" settings and "Bnbrports" settings.

BIT7:CDS(Compound Device Select)

Set the compound device identification. The bit settings will be reflected on bit 2 of the"WhubChar" field of the Hub Descriptor.

R/W

PGD4


XXXXXXXXB

R/W

PGD7

R/WR/WR/WR/WR/WR/W

PGD0PGD1PGD2PGD3PGD5PGD6

Address

HDSR2 0042H

R/W

HC4


XXXXXXXXB

R/W

HC7

R/WR/WR/WR/WR/WR/W

HC0HC1HC2HC3HC5HC6

Address

HDSR3 0043H

R/W

DRV3


00000101B

R/W

CDS

R/WR/WR/WR/WR/WR/W

PTNM0PTNM1PTNM2DRV2DRV4DRV5

Address

HDSR4 004EH

CDS Compound device selection bit

0 The hub is not part of a compound device.

1 The hub is part of a compound device.

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CHAPTER 9 USB Hub

BIT6 to 3:DRV5 to 2(Device RemoVable)

Specify whether a removable device can be connected to the hub down port. The bit settingswill be reflected on bit 5 to 2 of the "DeviceRemovable" field of the Hub Descriptor.

BIT2 to 0:PTNM2 to 0(PortNumber)

Specify the number of down ports that will be supported by the hub. The bit settings will bereflected on bit 2 to 0 of the "Bnbrports" field of the Hub Descriptor.

DRV n Device removable bit(n corresponds to the down port number.)

0 The device is detachable.

1 The device is permanently connected.

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CHAPTER 9 USB Hub

9.4.3 Hub status register (HSTR)

The hub status register indicates the status of each port. The status information includes the suspend state of the upstream and four downstream ports. The suspension of the upstream port will cause an interruption to the CPU. The interruption mask bit can be used to stop the interruption factor from reporting an interruption. If upstream ports are suspended, the STBC (standby control register) that stops the clock must be switched to the stop mode in order to reduce the current consumption to less than the level in the standby mode stipulated by the USB specification.

Hub status register (HSTR)

BIT7:RTsus(Root Port Suspend Status)

When the USB hub up port is suspended by the host, "1" will be indicated.

The hub will switch to the suspend state when it detects continuous idle state of 3.0 ms ormore on the route port. This status bit will cause an interruption to the CPU. The interruptionmask bit, RTSM bit, can be used to mask the interruption factor. Clearing of the interrupt factoris performed writing "0". Writing "1" to this bit has no meaning.

The hub will shift from the suspend state to the resumed state when the host cancels thesuspend (when the route port state changes from J state to K state) or wake-up starts whenthe enabled down ports switch to another bus state.

BIT6: RTSM (Root Port Suspend Interrupt Mask)

Controls the masking of the interruption to the CPU when the suspend bit (Bit7: Rtsus bit) ofthe hub route port is set to "1".

Initial value

00000000BMwkup

Bit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7

RTsus

RRRRR/WR/W

P5susP2susP4susWkupRTSM P3sus

R/W R/W

Address

HSTR 0044 H

Rtsus Hub suspend status bit

0 Shows that the USB hub is in normal state. Clear Interrupt cause

1 Shows that the USB hub has detected a condition that causes a transition to the suspend state on the routeport and has switched to the suspend state.

RTSM Interrupt enable bits of root port suspend

0 Route port suspend interruption disabled (Masked state)

1 Route port suspend interruption enabled (Unmasked state)

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CHAPTER 9 USB Hub

BIT5:WKUP(Wake UP Interrupt)

Indicates that a recovery from the suspend state has been made by the request of the routeport or the down port. This bit will be set by hardware when one of RTSUS, and P5SUS toP2SUS is set to "0" in the suspend state. Writing "1" to this bit has no meaning. If theinterruption is enabled by the MWKUP bit, an interruption to the CPU will occur.

BIT4:MWKUP(Mask Wake UP Interrupt)

Controls the masking of the interruption to the CPU when the recovery from the suspend state(Bit5:WKUP) is set to "1".

BIT3,2,1,0:P4sus,P3sus,P2sus,P5sus(Down Port 4,3,2,5 suspend status)

Indicates the suspend state of each down port of the hub. This bit will cause an interruption tothe CPU.

WKUP Wake UP status bit

0 No factor for causing a return to the suspend stateClear Interrupt cause

1 Factor for causing a return to the suspend state present

MWKUP Wake UP Interrupt enable bits

0 Wake UP interruption disabled (Masked state)

1 Wake UP interruption enabled (Unmasked state)

P4, 3, 2, 5SUS Down port suspend status bit

0 Communication is enabled for the down port.

1 The down port whose state is shown is suspended.

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CHAPTER 9 USB Hub

9.4.4 Over-current control register (OCCR)

The over-current register is a control register to report to the host controller that the current detection has occurred in the down port. BIT7 also has a status register to indicate the bus reset state of the route port. The over-current detection is reported to the USB host controller when the CPU writes to this register for the over-current ports detected by the input of the external input terminal (assigned to the general-purpose input port). If the over-current detection input from the external port is cancelled, the over-current bit of the port that corresponds to this register will be cleared to "0". If global over-current protection is set using the over-current protection mode, only one general-purpose input port will be used to set all the bits of the register to "1".

Over-current control register (OCCR)

BIT7:HBSR(Hub Usb Bus Reset)

Indicates that the route port has shifted to the bus reset state.



BIT3,2,1,0:OC4,3,2,5(Over Current Control 4,3,2,5)

Reports the over-current detection state of down ports 5 to 2 to the host controller. If the over-current protection mode is set in the global over-current protection mode, the reporting of thestate to the USB host controller will be reflected on the bits of the over-current indicator in thehub status field using the settings of this bit. In this case, all the bits, OC5 to 2, will be setduring the over-current detection (No port specific control).

If the over-current protection mode is set in the port-specific over-current protection mode, theover-current detection state of each port will be reflected on the over-current indicator bits inthe port status field (Port specific control available).

Note

The number attached to OC** corresponds to the port number used when the port-specific over-current protection mode is specified.


0XXX0000B

R/WR/WR/WR/W

OC5OC2OC4 OC3 HBSR

R

OCCR 0045 H

HBSR Hub and bus reset status bit

0 The route port bus is not in the reset state.

1 The route port bus is in the reset state.

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CHAPTER 9 USB Hub

When the global over-current protection mode is used (Hub descriptor: The over-current protection

mode is set)

When the present setting is the port-specific over-current protection mode (hub descriptor setting: over-

current protection mode)

Over-current DetectionThe notification of a detected over-current state to the CPU by the externally provided over-current detection circuit is made using a general-purpose port or an external interruption terminal.

When the present setting is the global over-current protection mode, the hub notifies the hostcontroller of all over-current states occurred and detected on downstream ports through the hubstatus field. The over-current detection notification to the external terminals is made using thesignal that detected the over-current status. In this case, input use 1 pin only.

When the present mode is the port-specific over-current protection mode, an over-currentdetection circuit is provided for each downstream port and each over-current detection signal isassigned to a general-purpose port terminal or interruption input terminal. When an over-currentstatus is detected on each port, "1" is entered for the over-current register bit that corresponds tothe port on which the over-current status has been detected, and a notification for that port ismade. This is done on a port-by-port basis.

OC4, 3, 2, 5 Over-current control bit

0 Indicates that the no hub over-current detection has occurred. If a recovery is made from the over-currentdetection state to the normal state, writing Åg0Åh will report the recovery of the state to the hostcontroller.

1 All the bits are set to "1" when the hub over-current detection has occurred. An over-current state occurson a downstream port and the total over-current status for the hub as a whole is reported. This state isreflected in the over-current indicator in the hub status field.

OC4, 3, 2, 5 Over-current control bit

0 During the recovery process from an over-current state, the recovery status is reported to the host byentering "0" for this bit.

1 Reflected in the over-current indicators for the individual ports (individual setting). The port over-current status setting is made for each port.

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CHAPTER 9 USB Hub

9.4.5 Descriptor ROM Address Register (DADR)

Specifies the top address in the ROM that has the configuration values for the standard descriptors (Device/Configuration/Interface/EndPoint/String) supported by the hub. The hub analyzes the "GET DESCRIPTOR" from the USB host controller to identify the descriptor, performs a DMA transfer from the ROM address storing that descriptor and returns the descriptor configuration values to the host controller.

Descriptor ROM Address Register (DADR)Specifies the top address in the built-in ROM area that stores the standard descriptors supportedby the hub. Standard descriptors (Device Configuration Interface EndPoint String) > setting in acontinuous area in the ROM. The address specified by this register specifies the top address ofthe area that has this descriptor.

The hub automatically reads, by means of DMA transfer, the descriptor requested by theGET_Descriptor command from the USB host from the specified address with the address offsetfor each descriptor added and responds to the USB host controller.

BIT 7 to 0:AD15 to AD8 Descriptor ROM address

Specifies the top address in the ROM area that has the USB hub standard descriptors.

Address: The highest 8 bits are specified. The lowest 8 bits are fixed to 00H.

The hub standard descriptors are normally deployed in the ROM, but it is possible to specify aRAM address. To specify a RAM address, it is necessary to write the descriptor configurationinformation (software) in advance.

R/W

AD12


XXXXXXXXB

R/W

AD15

R/WR/WR/WR/WR/WR/W

AD8AD9AD11 AD13AD14 AD10

Address

DADR 0046 H

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CHAPTER 9 USB Hub

9.4.6 ROM setting for the standard descriptors supported by the hub

The configuration values for the standard descriptors (Configuration descriptor/Interface descriptor/EndPoint descriptor) supported by the hub are prepared in the ROM as data. These standard descriptors automatically read (DMA read transfer to a fixed ROM address), after the analysis of the GET_Descriptor command from the USB host by the hardware, the appropriate descriptor (deployed in the ROM) and respond to the USB host controller. The configurations of the descriptors that are supported by the hub as standard and are deployed in the ROM are explained below.

Configuration of typical descriptorThe standard descriptors supported by the hub support the following configurations:

The transfer of individual descriptors by the GET_Descriptor command: The data deployed in theROM is automatically read by the hardware and a response to the USB host controller is made.

For the standard descriptors deployed in the ROM, make settings using the following values: Forthe shaded part of XX, any value can be used. Otherwise, use the specified fixed values becausethe configuration values are fixed to those values by the hardware.

The standard descriptors supported by the hub supports DEVICE/CONFIGURATION/INTERFACE/ ENDPOINT.

ROM Setting Values for the Hub Standard DescriptorsDevice Descriptor

address data Setting contents XX00 H 12 H :18Bytes XX01 H 01 H :DEVICE Descriptor XX02 H 00 H :USB Revision(Lower Byte) 00 XX03 H 01 H :USB Revision(Upper Byte) 01 XX04 H 09 H :Hub Class XX05 H 00 H :Hub Sub Class XX06 H 00 H :Hub Protocol XX07 H 08 H :MaxPaketSize for EndPoint0(08 Byte) XX08 H VendID_L H :Vendor ID(Lower Byte) XX09 H VendID_H H :Vendor ID(Upper Byte) XX0A H Prod_L H :Product ID(Lower Byte) XX0B H Prod_H H :Product ID(Upper Byte) XX0C H DevRel_L H :Device Release Number in BCD(Lower Byte) XX0D H DevRel_H H :Device Release Number in BCD(Upper Byte) XX0E H imanufact H :iManufacturer String Index XX0F H iproduct H :iProduct String Index XX10 H serialnum H :iSerialNumber String Index XX11 H 01 H :bNumber Configurations = 1

Configuration Descriptor address data Setting contents XX12 H 09 H :9Bytes XX13 H 02 H :CONFIGURATION Descriptor XX14 H 19 H :wTotalLength(Lower Byte) = 25 Byte XX15 H 00 H :wTotalLength(Upper Byte) XX16 H 01 H :bNumberInterfaces = 1 XX17 H 01 H :bConfigurationValue = 1

XX18 H 00 H :iConfiguration String Index

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CHAPTER 9 USB Hub

XX19 H Attribut H :bmAttributes XX1A H Maxpower H :Max Power

Interface Desc riptor (Hard fixed) address data Setting contents XX1B H 09 H :9Byte XX1C H 04 H :INTERFACE Descriptor XX1D H 00 H :bInterfaceNumber = 0 XX1E H 00 H :bAlternateSetting = 0 XX1F H 01 H :bNumberEndpoints = 1 XX20 H 09 H :Interface Class XX21 H 00 H :Interface Sub Class XX22 H 00 H :Interface Protocol XX23 H 00 H :String Index

EndPoint D escriptor (Hard fixed) address data Setting contents XX24 H 07 H :7 Bytes XX25 H 05 H :ENDPOINT Descriptor XX26 H 81 H :EndpointAddress IN Endpoint #=1 XX27 H 03 H :Interrupt EndPoint XX28 H 01 H :MaxPaketSize(Lower) 1Byte XX29 H 00 H :MaxPaketSize(Upper) XX2A H FF H :Interval in ms for polling EndPoint

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CHAPTER 9 USB Hub

9.5 Interrupt of USB hub

A USB hub interruption occurs either upon a USB upstream port state shift to the suspend state caused by the host or upon an exit of a USB upstream port from the suspend state. As an exit from the suspend state causes an interruption request even in the STOP state, it can also be considered as a STOP state cancellation factor.

Interrupt in the USB hub operationWhen an idle state continuing for 3msec. or more is detected, a shift to the suspend state occursand the corresponding interruption request flag bit (HSTR:RTSUS) is set to "1" (USB upstreamport).

Then if the interrupt request enable bit is enabled (HSTR:RTSM=1), an interrupt request (IRQ2) issent to the CPU. Set the IF0 bit to "0" to clear the interruption request during the interruptionhandling routine.

If a shift to the resumption state is detected from a USB upstream or downstream port when thehub is in the suspend state, the corresponding interruption request flag bit (HSTR:WKUP) is setto "1".

Then if the interrupt request enable bit is enabled (HSTR:MWKUP=1), an interrupt request (IRQ4)is sent to the CPU. Set the IF0 bit to "0" to clear the interruption request during the interruptionhandling routine. An interruption request (IRQ4) may occur when the CPU is in the STOP state aswell.

The RTSUS and WKUP bits are set to "1" when there is a relevant interruption-causing factorregardless of the values of the RTSM and MWKUP bits.

Reference

When the RTSUS and WKUP bit is "1", if the RTSM and MWKUP bit is changed from disabled toenabled (changed from 0 to 1), an interrupt request occurs immediately.

Registers and Vector Tables Relating to USB Hub Interruptions

Reference


Table 9.5-1 Registers and Vector Tables Relating to USB Hub Interruptions

Interruptname



IRQ2 ILR1(007B H ) L21(bit5) L20(bit4) FFF6 H FFF7 H

IRQ4 ILR2(007C H ) L41(bit1) L40(bit0) FFF2H FFF3 H

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CHAPTER 9 USB Hub

9.6 Descriptor

Indicates the configurations of the USB descriptors supported by the USB hub. The EndPoint descriptor, Interface descriptor, Config descriptor, standard USB device descriptor and hub descriptor unique to the hub class are supported.

USB Hub Support Descriptor Configuration

Table 9.6-1 HUB Descriptor (Get HUB Descriptor request)

Offset Field Size Value Setting Description

0 BdescLength 1 8'h09 FIX Bytes of this descriptor are 9 Bytes.

1 BdescType 1 8'h29 FIX Descriptor type

2 1 8'hXX Registersetting value

The number of downstream ports supported by the hub.

3 2 16'h00_XX Registersetting value

D1.D0:power supply switching mode01-Port-specific power supply switching

- HUB is not part of a compound device.1 - HUB is part of a compound device.

00 - Global over-current protection01 - Port-specific over-current protection1X-No over-current protection (bus power hub)D15.D5: reserved (0 fixed)


Power supply settling time (unit: 2ms)


Current consumption by the hub controller electronicscomponents(current consumption of this microcomputer; unit: mA)


Indicates whether a detachable device is connected to the port.D0: reserved (0 fixed)D1:Port1 (1 fixed)

0 - The device is detachable.1 - The device is permanently connected.D6.D7: reserved (0 fixed)

8 PortPwrCtrlMsk 1 8'h3F FIX Indicates whether the port is subject to the influence of asimultaneous mode power supply control request.D0: reserved (0 fixed)D1:Port1(1 fixed) D2:Port2(1 fixed) D3:Port3(1 fixed) D4:Port4(1 fixed) D5:Port5(1 fixed) D6.D7: reserved (0 fixed)

Note: The setting for the shading part is made through register setting.

BnbrPorts

WhubChar

BpwrOn2PwrGood

BhubContrCurr

DeviceRemovable

D2: distinction of multiple devices

D4..D3: Over-current protection mode

D2:Port2

D3:Port3D4:Port4D5:Port5

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CHAPTER 9 USB Hub

Table 9.6-2 Standard Device Descriptor (Get Descriptor (Device))


0 Blength 1 8'h12 FIX The number of bytes of this descriptor, includingthis byte.

1 BdescriptorType 1 8'h01 FIX Descriptor type (This indicates the Config.)

2 BcdUSB 2 16'h01_00 FIX USB Specification release version number(Revision 1.00)

4 BdeviceClass 1 8'h09 FIX Class code

5 BdeviceSubClass 1 8'h00 FIX Sub class code

6 BdeviceProtocol 1 8'h00 FIX Protocol code (vendor-specific protocol)

7 BmaxPktSize0 1 8'h08 FIX EndPoint 0 maximum packet size (8 bytes)

8 2 16'h04_c5 ROM Set value Vendor ID (For example:Fujitsu Ltd)

10 2 16'hff_c1 ROM Set value Product ID (For example: Fujifacom1)

12 2 16'h01_23 ROM Set value Device release number (e.g. function/workversion number)

14 1 8'h00 ROM Set value String descriptor index that indicates themanufacturer

15 1 8'h00 ROM Set value String descriptor index that indicates the product

16 1 8'h00 ROM Set value String descriptor index that indicates the deviceproduct number

17 BnumConfigs 1 8'h01 FIX The number of configurable devices

Table 9.6-3 Config Descriptor (Get Descriptor (Config))


0 Blength 1 8'h09 FIX The number of bytes of this descriptor, including thisbyte.

1 BDescriptorType 1 8'h02 FIX Descriptor type (This indicates the Config.)

2 WTotalLength 2 16'h00_19 FIX Total (25 bytes) of all the numbers of bytes(Configuration, Interface, EndPoint, Class, vendor-specific descriptor, etc.) and the number of bytes ofthis descriptor.

4 BNumInterfaces 1 8'h01 FIX Interface(One as a device)

5 BConfigValue 1 8'h01 FIX Indicates the configuration for configuration selection.

6 IConfiguration 1 8'h00 FIX The index to the string descriptor that indicates theconfiguration.

7 1 8'hX0 ROM Set value Configuration of power supplyD7: Bus powerD6: Self powerD5: Remote wake-up (support)D6.D7: reserved (0 fixed)

8 1 8'hXX Register settingvalue

Maximum current consumption during operation(unit: 2mA)

Note: The remote wake-up operation is supported by default.

IdVendor

IdProduct

BcdDevice

Imanufacturer

Iproduct

IserialNumber

BmAttributes

MaxPower

200

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CHAPTER 9 USB Hub

Table 9.6-4 Interface Descriptor (Get Configuration (Interface))


0 BLength 1 8'h09 FIX The number of bytes of the descriptor, including this byte.


2 BInterfaceNum 1 8'h00 FIX This interface value (the value for identifying this interface)

3 BAlternateSetng 1 8'h00 FIX The value used to select an alternative setting to the interfaceidentified by the previous bInterfaceNum.

4 BNumEndpoints 1 8'h01 FIX The number of EndPoints the interface can use (excludingEndPoint0)

5 BInterfaceClass 1 8'h09 FIX Class code (interface)

6 BIntfSubClass 1 8'h00 FIX Sub class code

7 BIntfProtocol 1 8'h00 FIX Protocol code

8 Interface 1 8'h00 FIX The index to the string descriptor that indicates this interface.

Table 9.6-5 EndPoint Descriptor (Get Descriptor request)


0 BLength 1 8'h07 FIX The number of bytes of the descriptor, including this byte.


2 BEndpointAdr 1 8'h81 FIX EndPoint address (the value for EndPoint identification)D0..D3:EndPoint Number (Endpoint 1)D4.D6: reserved (0 fixed)D7 : direction 0 Outbound EndPoint 1 Inbound EndPoint

3 BmAttributes 1 8'h03 FIX End point configurationD0.D1:transfer type 00 control 01 ISO 10 Bulk 11 InterruptD2.D7: reserved (0 fixed)

4 WMaxPktSize 2 16'h00_01 FIX The maximum packet size (in bytes) an EndPoint can use.1Byte

6 BInterval 1 8'hff FIX The interval of data transfer polling to EndPoint (unit: ms).

CHAPTER 9 USB Hub

9.7 Functional descriptions of USB hub

Explains the operation of the USB hub.

Operation of USB hubThe USB hub supports all of the commands necessary in relation to the USB Specification Rev.1.0 device standard commands and hub class commands. The hardware automatically respondsto these commands in the hub circuit section.

The hub circuit stores and decodes the 8-byte data received during setup transactions andperforms the corresponding processing. The hub distinguishes the status stage from the datastage of control transfer.

The responses to the individual USB commands are as follows:

Standard command

• Clear Feature

- Device remote wake-up and EndPoint stall clearing (EndPoint 0) are supported. All otherrequests are stalled.

• Get Configuration

- In IN transaction, response in relation to 1-byte configuration informations made with anappropriate data toggle bit added. Supports one configuration by adding the configurationvalue 0 that indicates there is no device configuration.

• Get Descriptor

- Responses in relation to standard descriptors are made according to the descriptor indexgiven by the setup packet. The hub responds to DEVICE, CONFIGURATION, INTERFACEand ENDPOINT.

• Get Interface

- On the part of the hub, only one Interface is supported. Therefore, the GetInterfacecommand is not supported. When a GetInterface command is given, a response is madeusing STALL handshake.

• Get Status

- 2-byte status information data from the receiving side that was specified is added with anappropriate data toggle bit and returned to the IN transaction.

• Set Address

- This command is supported and updates the logical address from the wValue field of theSETUP packet.

• Set Configuration

- On the part of the hub, only one configuration is supported. Therefore, a response is madeonly when the value given by the SETUP packet is 0 or 1. Otherwise, a response withSTALL is made.

• Set Feature

- Supports Set Feature of DEVICE_REMOTE_WAKEUP of the device and

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CHAPTER 9 USB Hub

ENDPOINT_STALL to Endpoint 0.

• Set Interface

- The hub supports a single Interface that is set by Alternate (fixed). Therefore, if a SetInterface command is given, a response is made with STALL.

• Set Descriptor

- This command is not supported. A STALL handshake response is made during the datastage of the response control transfer by this command. The data is ignored.

• SynchFrame

- The SynchFrame command is not supported. Response to this command: STALLhandshake response during the status stage of the control transfer.

Hub class command

• GetHubDescriptor

- A 9-byte hub descriptor is returned in response to this request. The hub decodes the 8-bytedata received in the SETUP packet, and responds to the host only when the bDescriptortype is hub and the descriptor index is 0. Otherwise, it responds to the host with STALLhandshake.

• SetHubDescriptor

- This command is not supported. Requests are responded with STALL handshake.

• GetBusStatus

- This command is not supported. Requests are responded with STALL handshake.

• GetHubStatus

- 4-byte information containing wHubStatus and the wHubCange register is returned duringthe data stage of the control transfer.

• GetPortStatus

- 4-byte information containing wHubStatus and the wHubCange register is returned duringthe data stage of the control transfer. If the defined port is an unsupported one, a STALLhandshake response is made during the data stage.

• SetHubFeature

- Responds to this command and sets the defined function. Responds to this command andclears the defined function.

• ClearHubFeature

- Responds to this command and if the defined function is an unsupported one, a STALLhandshake response is made.

• SetPortFeature

- Responds to this command and assigns the defined function to the defined port. If thedefined function is an unsupported one or the port is not supported, a STALL handshakeresponse is made.

• ClearPortFeature

- Responds to this command and clears the defined function of the defined port. If the definedfunction is an unsupported one or the port is not supported, a STALL handshake responseis made.

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CHAPTER 9 USB Hub

204

CHAPTER 10USB Function

This chapter explains the operation and function of the USB function circuit.

10.1 Overview of the USB Function

10.2 Configuration of the USB Function Circuit

10.3 USB Function Circuit Register

10.4 USB Function Interruptions

10.5 Function Description-USB Function

10.6 Operation of the USB Function

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CHAPTER 10 USB Function

10.1 Overview of the USB Function

The USB function circuit is an interface that supports the USB (Universal Serial Bus) communication protocol. The USB function circuit supports Full speed (12Mbps) transfers.

Function of USB Function CircuitThe USB function circuit performs 2-way serial transfers to and from a host controller thatsupports the USB protocol.

• Protocol: Supporting USB Protocol Revision1.0

• Speed: Full speed (12Mbps) only

• Device status: The device status response is automatically sent using the USB protocol.

• Clock: The USB interface uses a 48 MHz clock and digital PLL for data synchronizationcorrection (synchronization to the 4th sub-harmonic of 48 MHz is made within the function).

• Data check: Automatic generation and checking of Bit Stripping, Bit Stuffing, CRC5 andCRC16

• Data synchronization bit: Retention of the data synchronization bit (DATA0/DATA1 toggle bit)

• Standard USB commands: Automatic responses are made to all standard commands exceptthe Get/SetDescriptor and SynchFrame commands. For the Get/SetDescriptor andSynchFrame commands, the SETUP transaction status is displayed and output to the CPUbus as data.

• Class/Vendor command: For the Class/Vendor command, the SETUP transaction is output tothe CPU bus as data.

• EndPoint: Up to 4 EndPoints are supported. (EndPoint 0 is fixed to Control transfer)

• Interface/Alternate: Switching between Interface 0, 1 and Alternate is controlled by thesoftware.

• Interruption factor: An interruption occurs upon completion of an EndPoint transfer packet(when a handshake transmission to or from the USB host is received). An interruption alsooccurs upon receipt of a FrameStart (SOF) packet, during the setup stage, upon receipt of aSetInterface, during a shift to the suspend state and during an exit from the suspend state.

• DMA transfer: Equipped with a built-in DMA controller. Direct transfer to the RAM from theinternal FIFO data.

206

207


10.2 Configuration of the USB Function Circuit

The USB function circuit comprises the following 4 components:• USB device controller (UDC)• Transmit/receive buffer (IN/OUT_BUF)• CAN controller (DMAC) • USB control registers

(UMDR, DBAR, DTCR, UCTR, USTR1, USTR2, UMSKR, UFRM1, UFRM2, EPER, EPBR0, EPBRx1, 2)

Block Diagram of USB Function Circuit

Figure 10.2-1 Block Diagram of USB Function Circuit

CLK(48MHz)

UDC

PL EP

Block Block

SIE Block

PLL Block

USB interrupt mask register

EPINFO

IN/OUT_BUF

DMAC

DMA base address register

Transfer byte count rgister

USB control register

USB status register 1, 2frame status register

End point enable registerEnd point setup register

UBL Block

Internal Bus

FIFO(8 bit x 8)

USB reset mode register

IRQ3

HUB

IRQ5

PO

RT

5

208


USB Reset Mode Register

These registers are used to reset the USB function circuit section, switch the operation speed(Full/Low), connect to the hub and perform the RESUME operation.

DMA Base Address Register

Specifies the address to store the transfer data in the RAM.

Transfer byte count registers 0 to 3

Registers that count the numbers of transferred bytes in packets at the EndPoints (transmission-DMA byte count specified, receiving-byte count).


This is a USB protocol data transfer control register.

USB status register 1,2

This register indicates the completion status of USB transfer data and gives information on thecurrent transfer packets.

USB Interruption Mask Register

An interruption mask register for USB transfer data completion interruptions and SOF packetreceipt interruptions.

Frame Status Register

This register stores the frame number.

EndPoint Enable Register

This register specifies (enables) the EndPoints functions.

EndPoint Setup Register

A setup register that specifies the EndPoints configurations (Interface, Alternate, Direction andMax Packet Size).

Pull-up Control Register for USB

Controls the pull-up resistances connected to the USBP terminal.


10.3 USB Function Circuit Register

Indicates the registers associated with the USB function circuit.

Registers Associated with the USB Function Circuit

USB Reset Mode Register

DMA Base Address Register

AddressUMDR 0050H

Initial value

1000XX00BBFS

R/WR/WR/W R/W R/W R/W

SPRST RFBMHCONRESUM

Bit0Bit1Bit2Bit3Bit4Bit5Bit6Bit7

DBAR 0051H AD8


XXXXXXXXB

R/W

AD4AD5AD6AD7 AD9

R/W R/W R/W R/W R/W

Address

209


Transfer data count registers 0 to 3.

(end point 0 to 3)


TDCR0 (EndPoint 0)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial value

Address052H BC6 BC5 BC4 BC3 BC2 BC1 BC0 X0000000B

R/W R/W R/W R/W R/W R/W R/W

( EndPoint 1)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial value

TDCR1




TDCR2




TDCR3



Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

UCTR 0058H Bfok3 Bfok2 Bfok1 Bfok0 Stall3 Stall2 Stall1 Stall0 00000000B

R/W R/W R/W R/W R/W R/W R/W R/W

210


USB status register 1

USB status register 2

USB interrupt mask

USB Frame Status Register

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddressUSTR1 0059H PKend Setup SOF SETIF BUSR Wkup Susp NACK 00000000B

R/W R/W R/W R/W R R/W R/W R

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddressUSTR2 005AH I0AL1 I0AL0 I1AL1 I1AL0 SPK DIR EPC1 EPC0 XXXXXX00B

R R R R R R R R

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddressUMSKR 005BH MPKend MSetup MSOF Msetif MBUSR MWKUPMSUSP BUSRF 00000000B


UFRMR1 Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial valueAddress

005CH Frm7 Frm6 Frm5 Frm4 Frm3 Frm2 Frm1 Frm0 XXXXXXXXB

R R R R R R R R

UFRMR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

005DH Frm10 Frm9 Frm8 XXXXXXXXB

R R R

211


EndPoint Enable Register

EndPoint (0,1,2,3) Setup Register

(end point 0)

(end point 1)

EPER Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

005EH Epen3 Epen2 Epen1 Epen0 XXXX0001B

R/W R/W R/W R

EPBR0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

005FH MP6 MP5 MP4 MP3 MP2 MP1 MP0 X0000000B



0060H TYP1 TYP0 DIR1 DIR0 XX0000XXB

R/W R/W R/W R/W


0061H MP6 MP5 MP4 MP3 MP2 MP1 MP0 X0000000B


212


(end point 2)

(end point 3)

Pull-up Control Register for USB



R/W R/W R/W R/W




EPBR31



R/W R/W R/W R/W

EPBR32




USBP


000CH PDR3 XXXXXXXXBUSBP

USBPC


000DH DDR3 00000000BUSBPC

213


10.3.1 USB Reset Mode Register (UMDR)

The USB reset mode register is used to reset USB function circuit blocking and specify operation modes. BIT 2 to 3 are reserved bits. When performing writing, make sure that "0" is entered.

USB Reset Mode Register (UMDR)

BIT7:RST(Function Reset)

Signal for individual resetting of the USB function circuit section. Individual resetting of thefunction circuit section by this bit is not necessary during normal operation (except theinitialization process performed after the power is turned on). The function circuit section isreset by OR and the system reset process performed after the power is turned on.

As the initial value is "1" which means that the present state is the reset state, enter "0" tocancel.

BIT6:RESUM (Resume)

When the present state is the Remote WakeUP Enable state (the SET_FEATURE commandis used for the enabling) and the SUSP value of status register 1 is "1" (SUSPEND mode), theRESUME operation can be performed. Entering "1" for this bit changes the SUSP value to 0 tostart the RESUME operation. If you want the RESUME operation to be performed, set this bitto "1" and then give a time equal to or longer than 2 clocks of 12MHz (166nsec.) and have a"0 write clear" performed.

BIT5:HCON(USB HOST Connection)

This register is used to connect to the host controller via the USB interface. When used in a


UMDR 0050H RST RESUM HCON SP RFBM BFS 1000XX00B

R/W R/W R/W R/W R/W R/W

RST Function blocking reset bit

0 Cancels USB function circuit resetting.

1 Resets the USB function circuit.

RESUME USB RESUME bit

0 USB RESUME start instruction bit released

1 USB RESUME start

214


hybrid device (hub + function), the register is used to connect to downstream port 5 of the hub.

BIT4:SP(USB Speed)

Sets the USB interface transfer speed. This setting can be made only once in the initializationprocess performed after the power is turned on. After the Speed setting, cancel the functioncircuit section reset by using the BIT7"RST" bit. The initial value after power-on is "0Lowspeed".

(Note) When using it in a hybrid device (hub + function), make sure that FullSpeed is used.



BIT1:RFBM(Rate FeedBack Made)

Data toggle mode selection bit for USB Interrupt transfers.

BIT0:BFS(Buffer Size)

Specifies the sizes of the buffer memories for the individual EndPoints that are acquired in theRAM. The sizes of the memories acquired in the RAM for the specified EndPoints (4EndPoints; EndPoints 0 to 3) are all set to the value specified by this bit.

HCON USB connection

0 No connection to the USB host controller or hub port

1 Connected to the USB host controller or hub port

SP USB speed bit

0 USB Low Speed (1.5Mbps)

1 USB Full Speed (12Mbps)

RFBM Data toggle mode selection bits

0 Alternative data toggle modeThe PID of DATA0/DATA1 is toggled only when the transfer has been completedsuccessfully.

1 Data toggle mode Data toggle mode-The PID of DATA0/DATA1 is toggled regardless of whether the transfer

has been completed successfully*.

*: Can be used for rate feedback information for ISO transfers.

BFS Buffer(on RAM) size specification bit

0 8 Byte (for all EndPoints (0 to 3))

1 64 Byte (for all EndPoints (0 to 3))

215


10.3.2 DMA Base Address Register (DBAR)

The DMA base address register specifies the baseline destination address for the DMA transfers of the buffer memories (mapped in the RAM) for the End Points (0 to 3). The address specified by the base address register is used as the DMA transfer destination address for End point 0. The transfer destination addresses for End points 1 to 3 are defined in such a manner that the transfer destination address for End point 0 is followed continuously by the transfer destination address for End point 1 and the transfer destination address for the End point with the End point number (n) is followed continuously by the transfer destination address for the End point with the End point number (n + 1)(the address size is specified by the USB reset mode register BFS bit).

DMA Base Address Register (DBAR)



BIT5 to 0(DBAR):AD9 to AD4(DMA Base Address AD9 to AD4)

Specifies the baseline DMA transfer destination address for EndPoint0. The transferdestination addresses for EndPoints 1 to 3 are defined in such a manner that the transferdestination address for EndPoint 0 is followed continuously by the transfer destination addressfor EndPoint 1 and the transfer destination address for the EndPoint with the End pointnumber (n) is followed continuously by the transfer destination address for the EndPoint withthe End point number (n + 1)(the address size (buffer size) is specified by the USB reset moderegister BFS bit). The specified address is "0XX0" H (X: given value).

Although the DMA addresses can be specified within the range "0000" H - "03F0" H make sure

that the addresses are within the range covered by the built-in RAM (The I/O area "0000" H -

"007F" H cannot be specified).

DBAR

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Iniatial valueAddress

0051H AD9 AD8 AD7 AD6 AD5 AD4 XXXXXXXB

R/W R/W R/W R/W R/W R/W

216

217


Example) The case where DBAR=0Ah and UMDR BFS bit="0"(8Byte)

I/O register area 0000 h

0080 h

XXXX h

RAM area

00A0 h

( 8Byte)

( 8Byte)

( 8Byte)

( 8Byte)

00A8h

00B0h

00B8h

00C0h

End point 0

End point 1

End point 2

End point 3

End point 1 DMA Address

End point 0 Base Address Register



nd poi nt

: The maximum address on the RAM area.


10.3.3 Transfer data count registers (TDCR0 to 3)

The transfer data count registers indicate the byte count statuses for the received data for outbound USB protocol data transfers and specifies the DMA transmission transfer byte counts for inbound data transfers. Transfer data byte count register: Indication for each EndPoint (EndPoints 0 to 3). For inbound data transfers, a subtraction is made from the count when a DMA transfer occurs → Count → 0 → USB protocol packet transfer completion → Transfer completion The interruption is reported to the CPU if the interruption enable bit is set to "enable" upon transfer completion.

Transfer data count registers (TDCR0 to 3)

Transfer Data Count Registers (TDCR 0 to 3) The data count registers are configured forEndPoints 0 to 3, respectively. EndPoints 0 to 3 correspond to "TDCR 0 to 3", respectively. Up to64 bytes can be transferred.

Writing for the data count registers: Make sure that "0" is entered for bit 7.

TDCR0 (EndPoint 0)Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial value




TDCR1




TDCR2




TDCR3



218


TDCR0 to 3 (end point 0 to 3)

BIT6 to 0:BC6 to BC0 (Transfer Byte Counter)

Up to 64 bytes can be specified.

For outbound USB transfers (function = data reception), it serves as a status register thatindicates the number of bytes of data received in a packet. For outbound transfers, the TDCRsare read-only and writing is meaningless. When the transfer completion status "Pkend" is "1" andthe transfer direction status DIR is OUT, the number of bytes of data the function received fromthe host is displayed in the data count register for the corresponding EndPoint. (This is effectiveonly when "Pkend=1" and "DIR=1".)

Specifies the DMA transmission transfer byte count for USB IN direction transfers (from thefunction to the host) for each of the EndPoints supported with respect to IN direction transfers.For inbound transfers, the TDCRs are write-only and "read values" are meaningless. Up to 64bytes can be transmitted in a DMA transfer.

(example) 8Byte "08H"

64Byte "40H"

219


10.3.4 USB control register (UCTR)

The USB control register controls data transfers through the USB protocol interface.

USB Control Register (UCTR)

BIT7 to 4:BFOK3,2,1,0(Buffer OK)

A bit used to permit the transfer after the preparations to use the transmission/receivingbuffers for the transfer data have been completed. As this bit is cleared by the hardware(transfer completion status "PKend" (USB ACK/NACK response)), it is necessary to make thesetting before the transfer to permit that transfer.

The suffix to this bit indicates the corresponding EndPoint (Endpoint 0, 1, 2 or 3)

BIT3 to 0:STALL3,2,1,0(USB STALL Response)

By entering "1", the STALL state is specified for the EndPoint that has been accessed(EndPoint 3, 2, 1 or 0).

This is automatically cleared when an access is made by the host to the EndPoint for whichSTALL and BFOK have been set. This automatic cancellation does not occur in cases whereonly STALL has been set.


UCTR 0058H Bfok3 Bfok2 Bfok1 Bfok0 Stall3 Stall2 Sta111 Stall0 00000000B


BFOK BUFFER Ready OK bit

0 The transfer buffers have not been prepared.

1 The transfer buffers have been prepared and the DMA transfer is permitted.

STALL Stall response bit

0 No STALL response.

1 STALL response is made.

220


10.3.5 USB status register 1(USTR1)

USB status register 1 indicates the statuses of and relating to the current transfer packet (e.g. USB interface data transfer completion, setup transaction and SOF packets). If the masks for the interruption-causing factors for the status in question are in the "disable" state, an interruption notification to the CPU is made.

USB status register 1 (USTR1)

BIT7:Pkend(Transfer Packet end)

Indicates the current transfer packet completion status (This is set to "1" by a transfer packetresponse (ACK/NACK)). This bit is cleared by entering "0". "1" Writing does not have themeaning. If the value of the corresponding bit of the interruption mask register permitsinterruptions, an interruption notification to the CPU is made.

BIT6:Setup(Setup)

Indicates that the present stage is the Setup stage of a USB control transfer. This bit iscleared by entering "0". "1" Writing does not have the meaning. If the value of thecorresponding bit of the interruption mask register permits interruptions, an interruptionnotification to the CPU is made.

BIT5:SOF(Start Of Frame)

A status bit to indicate that an SOF packet has been received through the USB interface.When this bit is "1" the frame register frame number is effective. This bit is cleared by entering"0". "1" Writing does not have the meaning.

If the value of the corresponding bit of the interruption mask register permits interruptions, an


USTR1 0059H PKend Setup SOF SETIF BUSR Wkup Susp NACK 00000000B

R/W R/W R/W R/W R R/W R/W R

Pkend Transmission/receiving packet transfer completion bit

0 No transfer of USB protocol transmission/receiving packet.

1 USB protocol transmission/receiving packet transfer completed.

Setup Wake up Status bit

0 The present stage is not setup stage of a control transfer.

1 Control transfer set-up stage

221


interruption notification to the CPU is made.

BIT4:Setif(Set Interface)

A status bit that is set upon acceptance of a Set Interface of USB command. This bit is clearedby entering "0". "1" Writing does not have the meaning. If the value of the corresponding bit ofthe interruption mask register permits interruptions, an interruption notification to the CPU ismade. When this bit is set, the UCTR (BFOK3 to BFOK0) are automatically cleared.

BIT3:BUSR(Usb Bus Reset)

Indicates that the USB interface has shifted to the "Bus Reset" state.

This bit is automatically cleared by an exit from the "Bus Reset" state (BUSRF clearing).

BIT2:WKUP(WaKe UP)

Indicates that the USB interface has exited the suspend state. This bit is set by the hardwareupon a suspend state signal (SUSP) change from the "enabled" to "disabled" state. If thevalue of the corresponding bit of the interruption mask register permits interruptions, aninterruption notification to the CPU is made.

BIT1:SUSP(USB Suspend)

Indicates that the USB interface has shifted to the suspend state.

It is put out of the suspend state by a remote wake-up (the writing of "1" for the UMDR registerRESUM bit) or by the host controller. Clearing of the interrupt factor is performed writing "0"."1" Writing does not have the meaning. If the value of the corresponding bit of the interruption

SOF Start of frame Status bit

0 No SOF/bit clear

1 There was an SOF packet.

Setif SetInterface Status bit

0 No SetInterface command, clearing of the interruption-causing factors.

1 Acceptance of a SetInterface command

BUSR Usb Bus Reset Status bit

0 The USB bus is not in the "Reset" state.

1 The USB bus is in the "Reset" state.

WKUP WAKE UP Status bit

0 WAKE UP Without interrupt factorClear Interrupt cause

1 WAKE UP With interrupt factor

222


mask register permits interruptions, an interruption notification to the CPU is made.

BIT0:NACK(NACK)

Indicates that a "NACK" response has been sent to the USB host controller when an error(CRC, FIFO overrun, etc.) has been detected in relation to the current USB protocol transfer.This bit status is "effective" when the packet transfer completion status "PKEND" is "1". (Note)This bit does not constitute an interruption-causing factor.

If the current transfer has ended with a "NACK", the integrity of the transfer data is notguaranteed. Establishes the "ready for transfer" state (by putting the transfer data into thetransmission buffer and making the setting to permit transfers) and waits for the next (hostcontroller) transfer request.

SUSP Suspend Status bit

0 No suspend status interruptClear Interrupt cause

1 Generation of suspend status interrupt

NACK NACK response status bit

0 A normal completion response (ACK) was sent for the current transfer.

1 An abnormality was found in the current transfer and a NACK response was sent.

223


10.3.6 USB status register 2 (USTR2)

USB status register 2 provides information about the statuses at the time of USB interface transfer completion (transfer direction, short packet flag, EndPoint number). Indicates the EndPoint properties at the time of USB transfer completion.

USB status register 2 (USTR2)

BIT7,6:I0AL1,I0AL0(Interface 0 Alternate 1,0 Number)

Indicates the Alternate number of Interface 0 which is currently specified. Indicates theAlternate number that is currently specified by the "Set Interface" command (USB hostrequest). The software can confirm whether the Alternate number that is currently beingmanaged and the configuration from the host matches.

BIT5,4:I1AL1,I1AL0(Interface 1 Alternate 1,0 Number)

Indicates the Alternate number of Interface 1 which is currently specified. Indicates theAlternate number that is currently specified by the "Set Interface" command (USB hostrequest). The software can confirm whether the Alternate number that is currently beingmanaged and the configuration from the host matches.

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddressUSTR2 005AH I0AL1 I0AL0 I1AL1 I1AL0 SPK DIR EPC1 EPC0 XXXXXX00B

R R R R R R R R

I0AL1, I0AL0 Current Interface 0 Alternate number

0, 0 Alternate 0

0, 1 Alternate 1

1, 0 Alternate 2

1, 1 Alternate 3

I1AL1, I1AL0 Current Interface 1 Alternate number

0, 0 Alternate 0

0, 1 Alternate 1

1, 0 Alternate 2

1, 1 Alternate 3

224


BIT3:SPK(Short Packet)

When the number of data bytes of the packet transferred using the USB protocol is less thanthe Max Packet Size specified for the corresponding EndPoint Buffer (0, 1, 2 or 3), it isindicated as a status. This bit is effective when the packet transfer completion status Pkend is"1". (Note) This bit does not constitute an interruption-causing factor.

BIT2:DIR(Direction)

Indicates the direction at the time of transfer packet completion. This bit is effective when thetransfer packet completion status "Pkend" bit is "1".

BIT1,0:EPC1,0(EndPoint Number Code)

Indicates the EndPoint number for the current transfer packet. This bit is effective when thetransfer packet completion status "Pkend" bit is "1".

SPK Short packet Status bit

0 The size of the transfer packet was equal to the Max Packet Size.

1 The size of the transfer packet was less than the Max Packet Size.

DIR Transfer packet direction status bit

0 USB Out direction transfer

1 USB IN direction transfer

EPC 1, 0 EndPoint number status bit

0, 0 EndPoint 0

0, 1 EndPoint 1

1, 0 EndPoint 2

1, 1 EndPoint 3

225


10.3.7 USB Interruption Mask Register (UMSKR)

Mask control register for the USB status register interruption-causing factor bits (PKEND, SETUP, SOF, SETIF, WKUP, SUSP). Interruption mask setting can be made for each of the bits (for each interruption-causing factor).

USB Interruption Mask Register (UMSKR)

BIT7:MPKend(Mask Packet END Interruption)

Mask control of "Pkend" status interruption is made (transfer data completion status). After apower-on reset cancellation or a cancellation of resetting by the reset bit of the reset controlregister, interruption masking is active (i.e. no interruption is permitted).

BIT6:MSETUP(Mask SETUP Interruption)

Mask control of "Setup" interruption is made (control transfer setup stage status).

After a power-on reset cancellation or a cancellation of resetting by the reset bit of the resetcontrol register, interruption masking is active (i.e. no interruption is permitted).

BIT5:MSOF(Mask SOF Interruption)

(Mask cancellation) Mask control of SOF status interruption of frame start synchronizationsignal is made. After a power-on reset cancellation or a cancellation of resetting by the resetbit of the reset control register, interruption masking is active (i.e. no interruption is permitted).

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 initial valueAddressUMSKR 005BH MPKend MSetup MSOF Msetif MBUSR MWKUP MSUSP BUSRF 00000000B


MPKend Pkend Interrupt enable bits

0 Corresponding Pkend interruptions are prohibited. (Mask state)

1 Corresponding Pkend interruptions are permitted. (Mask released)

MSetup Setup Interrupt enable bits

0 Corresponding Setup interruptions are prohibited. (Mask state)

1 Corresponding Setup interruptions are permitted. (Mask released)

MSOF SOF Interrupt enable bits

0 Corresponding SOF interruptions are prohibited. (Mask state)

1 Corresponding SOF interruptions are permitted. (Mask released)

226


BIT4:MSETIF(Mask SET InterFace Interruption)

Mask control of Reception status interruption of host command "SET INTERFACE" is made.After a power-on reset cancellation or a cancellation of resetting by the reset bit of the resetcontrol register, interruption masking is active (i.e. no interruption is permitted).

BIT3:MBUSR(Mask usb BUS Reset)

Mask control of "BUSRF" status interruption of USB bus reset status indication signal is made.After a power-on reset cancellation or a cancellation of resetting by the reset bit of the resetcontrol register, interruption masking is active (i.e. no interruption is permitted).

BIT2:MWKUP(Mask WaKeUP Interruption)

Mask control of "WKUP" status interruption of SUSPEND exit signal is made.


BIT1:MSUSP(Mask SUSPend Interruption)

Mask control of "SUSP" status interruption of suspend state indication signal is made.


BIT0:BUSRF(BUS Reset Flag)

Indicates the starting of a USB bus reset. "1" Writing does not have the meaning. If the valueof the corresponding bit of the interruption mask register permits interruptions, an interruptionnotification to the CPU is made. This bit is set at the starting edge of a USB bus reset.

MSETIF SETIF Interrupt enable bits

0 Corresponding SETIF interruptions are prohibited. (Mask state)

1 Corresponding SETIF interruptions are permitted. (Mask released)

MBUSR BUSRF Interrupt enable bits

0 Corresponding BUSRF interruptions are prohibited. (Mask state)

1 Corresponding BUSRF interruptions are permitted. (Mask released)

MWKUP WKUP Interrupt enable bits

0 Corresponding WKUP interruptions are prohibited. (Mask state)

1 Corresponding WKUP interruptions are permitted. (Mask released)

MSUSP SUSP Interrupt enable bits

0 Corresponding SUSP interruptions are prohibited. (Mask state)

1 Corresponding SUSP interruptions are permitted. (Mask released)

BUSRF USB BUS Reset flag bit

0 There is no factor that causes a USB bus reset interruption. Clear Interrupt cause.

1 There is a factor that causes a USB bus reset interruption.

227


10.3.8 USB Frame Status Register (UFRMR)

The USB frame status register indicates the frame number when a frame synchronization signal has been received.

USB Frame Status Register (UFRMR)

BIT7 to 0(UFRMR1),BIT2 to 0(UFRMR2):FRM10 to 0(Frame Number)

Indicates the current frame number of the frame synchronization packet. The frame number iseffective when the "SOF" flag of status register 1 is "1".

BIT7 to 3(UFRMR2): Reserved bit


UFRMR1 Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial valueAddress

005CH Frm7 Frm6 Frm5 Frm4 Frm3 Frm2 Frm1 Frm0 XXXXXXXXB

R R R R R R R R

UFRMR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

005DH Frm10 Frm9 Frm8 XXXXXXXXB

R R R

228


10.3.9 EndPoint Enable Register (EPER)

This register specifies (enables) the EndPoints functions. Enabling setting is made for the individual Endpoints used (functions) on an EndPoint-by-EndPoint basis.

EndPoint Enable Register (EPER)This register is used to enable EndPoints (0, 1, 2 and 3). Enabling setting is made on anEndPoint-by-EndPoint basis.



BIT3,2,1,0(Epen 3,2,1,0):(End Point Enable 3,2,1,0)

Enables EndPoints (3, 2 and 1). EndPoint 0 is "effective" (in the "enabled" state) upon power-on by default. (The enable bit for EndPoint 0 is fixed to "1".)

The suffix numbers correspond to the EndPoint numbers.

This bit allows you to enable an EndPoint that has configuration information (Interface, Type,Dir and Max Packet Size (EndPoint setup register setting)).

EPER Bit 7 Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Initial valueAddress

005EH Epen3 Epen2 Epen1 Epen0 XXXX0001B

R/W R/W R/W R

Table 10.3-1 EPEN 3,2,1

EPENx End point 3,2,1 enable bits

0 End point 3 to 1 are invalid.

1 The EndPoint with the specified EndPoint number is enabled (EndPoint 3, 2 or 1).

229


10.3.10 EndPoint Setup Register (EPBR0,EPBRx1,x2)

The EndPoint 0 setup register is used for configuration information setting for EndPoint 0 (EndPoint Buffer). The configuration for EndPoint 0 is fixed to Control_IN and Control_out by default and is contained in all Interfaces and Alternates.The EndPoint setup register x1 and x2 are used for configuration information setting for individual EndPoints (1, 2 and 3). The EndPoint configuration specifies the transfer type, transfer direction and maximum packet size. Do not alter these register values during a packet transfer.

EndPoint Setup Register (EPBR0,EPBRn1,n2)n=1,2,3

EndPoint 0 Setup Register (EPBRO)

BIT7: Reserved bit

When writing into the above reserved bits, make sure that "0" is entered.

BIT6 to 0:MP6 to MP0(Max packet Size)

Specifies the maximum number of transferred bytes for EndPoint 0. The maximum number oftransferred bytes that can be specified for packets for EndPoint 0 is 64. Do not specify a valuelarger than 64. ALL"0" 0Byte setting is also prohibited.

Example: MP5-MP0:"40"H = > 64Byte (maximum allowable value)

"08"H = > 8Byte

EndPoint Setup 1 Register (EPBR11,12)

Specifies the configuration for EndPoint 1.

EPBR 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Intial valueAddress

005FH MP6 MP5 MP4 MP3 MP2 MP1 MP0 X0000000B

R/W R/W R/W R/W R/W R/W R

EPBR 11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress


R/W R/W R/W R/W




230


<EPBR11>

BIT 7,6,1,0: Reserved bit

When writing into this bit, make sure that "0" is entered.

BIT5,4(EPBR11):TYP1,TYP0 (End Point 1 Type)

Specifies the transfer type supported by EndPoint 1.

BIT3,2(EPBR11):DIR1,DIR0(EndPoint 1 Direction)

Specifies the transfer direction supported by EndPoint 1.

<EPBR12>

BIT7(EPBR12): Reserved bit


BIT6 to 0(EPBR12):MP6 to 0(Max Packet Size)

Specifies the maximum transfer packet size supported by EndPoint 1. The maximum numberof transfer bytes that can be specified for EndPoint 1 is 64. The specification of ALL"0" 0Byteis prohibited.

<a setting example>

MP6 to MP0: 40H => 64Byte (Max)

TYP1 TYP0 EndPoint 1 TYPE specification

0 0 Interrupt transfer

0 1 Bulk transfer

1 0 Isochronous transfer

1 1 (Specification prohibited)

DIR1 DIR0 EndPoint 1 Direction specification

0 0 OUT EndPoint

0 1 IN EndPoint

1 0 EndPoint that corresponds both OUT and IN


231


EndPoint 2 Setup Register (EPBR21,22)

Specifies the configuration for EndPoint 2. The setting items are the same as those for theEndPoint 1 setup register.

<EPBR21>

BIT7,6,1,0(EPBR21): Reserved bit


BIT5,4(EPBR21):TYP1,TYP0(EndPoint 2 Type)




<EPBR22>




Specifies the maximum transfer packet size supported by EndPoint 2. The maximum numberof transfer bytes that can be specified for EndPoint 2 is 64 (ALL"0" 0Byte setting is prohibited).

<a setting example>

MP6 to MP0: "40"H => 64Byte (Max)





R/W R/W R/W R/W R/W

R/W R/W R/W R/W

R/W R/W



0 1 Bulk transfer



DIR1 DIR0 EndPoint 2 Direction specification

0 0 OUT EndPoint

0 1 IN EndPoint

1 0 EndPoint that corresponds both IN and OUT


232


EndPoint 3 Setup Register (EPBR31,32)

Specifies the configuration for EndPoint 3. The setting items are the same as those for theEndPoint 1 setup register.

<EPBR31>

BIT7,6,1,0(EPBR31): Reserved bit


BIT5,4(EPBR31):TYP1,TYP0 (EndPoint 3 Type)




<EPBR31>




Specifies the maximum transfer packet size supported by EndPoint 3. The maximum transferpacket size that can be specified for EndPoint 3 is 64 bytes (ALL"0" setting is prohibited).

<a setting example>

MP6 to MP0: "40"H => 64Byte (Max)





R/W R/W R/W R/W R/W

R/W R/W R/W R/W

R/W R/W



0 1 Bulk transfer



DIR1 DIR0 End Point 3 Direction specification

0 0 OUT End Point

0 1 IN End Point

1 0 End Point that corresponds IN and OUT


233


10.3.11 Pull-up Control Register for USB (USBPC, USBP)

This register controls the pull-up resistances that are connected to the USBP terminal. This allows the connection to the host controller to be recognized (the RPVP and RPVM terminals are in the high-impedance state until the pull-up resistances are enabled).

Pull-up Control Register for USB (USBPC, USBP)

Pull-up Control Register for USB (USBPC)

BIT7 to 1:

Used as DDR3(Port 3 direction register). Refer to "4.5 Port 3 ".

BIT0:

Specifies whether the use of the USBPC terminal is permitted or prohibited.

USBPC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial valueAddress

000DH USBPC 00000000BDDR3

USBPC The use of the USBP terminal is permitted.

0 The use of the USBP terminal is prohibited.

1 Use permission

234


Pull-up Register for USB (USBP)

BIT7 to 1:

Used as PDR3(Port 3 data register). Refer to "4.5 Port 3".

BIT0:

Specifies the ON/OFF status of the pull-up when the use of the USBP terminal is permitted bythe USBPC register.

Reference

To set the pull-up resistances for USB to ON, set the USBP register to "1" (pull-up ON) and then setthe USBPC register to "1" (use permitted). During the Reset state, the USBP terminal is "Hi-Z".

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USBPPDR3

USBP Initial valueAddress

000CH XXXXXXXXB

USBP Selection of pull-up on/off

0 Pull-up OFF

1 Pull-up ON

235


10.4 USB Function Interruptions

A USB function interruption occurs upon completion of data reception from and data transmission to the USB port, during the SETUP stage of a control transfer, upon receipt of a frame start signal (SOF), upon receipt of a SET Interface command, during a USB port bus reset, upon a state change of a USB port to the suspend state caused by the host and upon an exit from the suspend state. As an exit from the suspend state causes an interruption request even in the STOP state, it can also be considered as a STOP state cancellation event.

Interruptions during Operation of the USB FunctionUpon completion of the current transfer packet in a USB transfer, the transfer completion flag bit(USTR1:PKEND) is set to "1". If the interruption request permission bit has been set by this pointto permit interruption requests (UMSKR:MPKEND=1), an interruption request (IRQ3) is sent tothe CPU. Set the PKEND bit to "0" to clear the interruption request during the interruptionhandling routine.

Upon a status shift to the setup stage during a USB transfer, the interruption request flag bit(USTR1:SETUP) is set to "1". If the interruption request permission bit has been set by this pointto permit interruption requests (UMSKR:MPKEND=1), an interruption request (IRQ3) is sent tothe CPU. Set the SETUP bit to "0" to clear the interruption request during the interruptionhandling routine.

Upon reception of an SOF packet from the host during a USB transfer, the interruption requestflag bit (USTR1:SOF) is set to "1". If the interruption request permission bit has been set by thispoint to permit interruption requests (UMSKR:MPKEND=1), an interruption request (IRQ3) is sentto the CPU. Set the SOF bit to "0" to clear the interruption request during the interruption handlingroutine.

Upon acceptance of a SetInterface command from the host during a USB transfer, theinterruption request flag bit (USTR1:SETIF) is set to "1". If the interruption request permission bithas been set by this point to permit interruption requests (UMSKR:MPKEND=1), an interruptionrequest (IRQ3) is sent to the CPU. Set the SETIF bit to "0" to clear the interruption request duringthe interruption handling routine.

If a USB bus reset is detected, the interruption request flag bit (UMSKR:BUSRF) is set to "1". Ifthe interruption request bit has been set by this point to permit interruption requests(UMSKR:MBUSR=1), an interruption request (IRQ3) is sent to the CPU. Enter "0" for theinterruption request flag bit BUSRF using the interruption processing routine and clear theinterruption request.

When an idle state continuing for 3msec. or more is detected, a shift to the suspend state occursand the interruption request flag bit (USTR1:SUSP) is set to "1" (USB upstream port). If theinterruption request permission bit has been set by this point to permit interruption requests(UMSKR:MPKEND=1), an interruption request (IRQ3) is sent to the CPU. Set the SUSP bit to "0"to clear the interruption request during the interruption handling routine.

If a shift to the resume state is detected (USB upstream port) while the function is in the suspendstate, the corresponding interruption request flag bit (USTR1:WKUP) is set to "1".

236


If the interruption request permission bit has been set by this point to permit interruption requests(UMSKR:MPKEND=1), an interruption request (IRQ5) is sent to the CPU. Set the WKUP bit to "0"to clear the interruption request during the interruption handling routine. An interruption request(IRQ5) may occur when the CPU is in the STOP state as well. The PKEND, SETUP, SOF,SETIF, BUSRF, SUSP and WKUP bits are set to "1" when there is a relevant interruption-causingfactor regardless of the values of the MPKEND, MSETUP, MSOF, MSETIF, MBUSR, MSUSPand MWKUP bits.

Reference

When the PKEND, SETUP, SOF, SETIF, BUSRF, SUSP, WKUP bit is "1", if the MPKEND,MSETUP,MSOF, MSETIF, MBUSR, MSUSP, MWKUP bit is changed from disabled to enabled(changed from 0 to 1), an interrupt request occurs immediately.

Registers and Vector Tables Relating to USB Function Interruptions


Table 10.4-1 Registers and Vector Tables Relating to USB Function Interruptions

Interruptname



IRQ3 ILR1(007B H ) L31(bit7) L30(bit6) FFF4 H FFF5 H

IRQ5 ILR2(007C H ) L51(bit3) L50(bit2) FFF0H FFF1H

237


10.5 Function Description-USB Function

The functions supported by the USB Function are explained below. The individual endpoint setting items and the DMA transfer function are explained below.

The Configuration Supported by the USB FunctionThe USB function supports the following configuration:

Config:1

Supports one device configuration.

Interface:1,0

Supports two interfaces as devices. The interface numbers supported by the current configurationare managed by the software.

Alternate:0,1,2,3

Up to 4 Alternates are supported. Alternates after configuration are managed by the software.The hardware does not perform Alternate property checks for the specified EndPoints. Thesoftware manages the current EndPoints Alternate properties. These Alternate properties allowEndPoint configuration definitions (the same interface) to be changed in the event that theAlternate configuration has been altered by SetInterface (standard device request).

EndPoint:0,1,2,3

The function supports 4 EndPoints (Endpoints 0, 1, 2 and 3) including Endpoints 0.

EndPoint 0:

This is used for the default pipes of the USB devices. Supports control transfers only. Thetransfer packet size supported by EndPoint 0 is specified through EndPoint setup register(EPBR0) setting. The maximum transfer packet size that can be specified is 64 bytes.

EndPoint 1:

EndPoint property setting is made by means of the EndPoint setup register (EPBR1). Thesetting items are the interface number of the interface to which EndPoint 1 belongs (0 or 1),the supported transfer type (Interrupt, Bulk or Isochronous transfer), the transfer direction (Inor Out) and the maximum packet size (max. 64 bytes). The maximum transfer packet size forDMA transfers of transfer packet data to the built-in RAM is 64 bytes.

EndPoint 2:


EndPoint 3:


238


10.6 Operation of the USB Function

The USB function supports the USB (Universal Serial Bus) communication protocol (Revision 1.0). As the USB function circuit achieves USB communication by means of the hardware, the built-in RAM can be accessed using the DMAC without taking into consideration the packet communication with the host PC.

Operation of USB FunctionThe USB function circuit provides 2-way packet transfer communication with a host PC thatsupports the USB protocol. After the connection between the host PC and the devices has beenestablished by the enumeration process, communication is performed through various types oftransfers using device drivers.

Figure 10.6-1 USB Function Circuit

This subsection explains the operation of the USB communication between the host PC anddevices using the enumeration process as an example. The operation of each of the registersand the USB packet flows are shown to help you understand the overall processing mechanism.

Host PC

CPU

UDC

DMAC

RAM

UDCDMACRAM

: USB function circuit: DMA controller: CPU built-in RAM (A capacity depends on product types.) Buffer for transmitting and receiving

Device

239


Enumeration process

This is the process that establishes the connection between the host PC and the devices to allowthe USB function to operate. The host PC perform checks to identify the devices connected onthe USB bus.

This is done by means of USB control transfers (that are performed in accordance with the USBSpecification). USB control transfer communication is a type of USB transfer communication. Thisuses EP0 (EndPoINt0) (USB Specification).

Figure 10.6-2 Enumeration process

Connection detection

Reporting to the host PC by the devices.

The host monitors the signals on the 2 signal lines (D +, D -) of the USB bus to detect theconnected devices (If there is a connected device, the signals on either of the signal linesbecome "H"-level signals.

• For MB89051 series products, the following processing is required:

- Initial setting (Total initialization including the USB function registers and hub registers)

- The function circuit section resetting is cancelled using the UMDR register.

- The hub circuit section resetting is cancelled using the HMDR register of the hub.

- The pull-up resistances are enabled (connection with the host controller) by the USBPterminal software control (see 1.3.11 "Pull-up Control Registers for USB (USBPC, USBP)."(The RPVP and RPVM terminals are in the high-impedance state until the pull-upresistances are enabled.)

- HCON of the UMDR register is made "effective" (connection with the hub circuit).

Scenario Transfer direction Operatin outlineConnection detection Host Device Any operation never starts without detection of connection.

USB bus reset Host DeviceGetting descriptor Host Device The descriptor data is returned to the HOST.Address setting Host Device The optional address is allocated by the HOST.Getting descriptor (device) Host Device The descriptor data is returned to the HOST.Getting descriptor (configuration) Host Device The descriptor data is returned to the HOST.Setting configuration Host Device The configuration number is allocated by HOST.

No execution until USB bus reset.

240


Figure 10.6-3 A Connection Example of an MB89051 Series Model

Note

When the hub is in the "disabled" state, no connection with the host PC is established.

USB bus reset

Reporting to the devices by the host PC.

The USB function circuit is initialized.

For the devices, the following processing is required:

• Configuration initialization (the process of resetting the configuration to the initial interfacenumber when two or more interface numbers are accommodated)

• If the transmission and receiving buffers for the DMAC transfer destination are ready, BFOK0of the UCTR register is made "effective" (DMAC transfer permitted).

Getting descriptor

The host PC sends requests to the devices and data is sent to the host.

Communication takes place in the following 3 stages:

Setup stage → data stage → status stage

In the setup stage, a check is made to confirm whether the packets from the host PC to thedevices have been received successfully and then the commands are decoded. The descriptorinformation to be returned in the next data stage is then put into the area of the RAM that isdedicated to transmitting data.

In the data stage, a check is made to confirm whether the data has been transmitted successfullyfrom the host PC.

In the status stage, the host PC transfers packets with no data and the completion process isperformed.

RPVP pin

RPVM pin

D+

D-

Host PC

MB89051 series

1.5K

USBP pin

241


10.6.1 Each register operation when command responds

This subsection explains the USB packet processing method (architecture) with reference to operation and control of the registers that are considered fundamental.

Each register operation when command responds

Figure 10.6-4 Each register operation when command responds

Set-up processing

Firmware processing is performed on a handshake-by-handshake basis. This is equal to thestage-by-stage processing of packets shown in Figure 10.6-4 . This is explained below using Figure10.6-4 as an example.

BFOK is set to "effective" before the setup stage setup packet comes in. The reception of thesetup stage packet that follows clears BFOK and sets PKEND.

Immediately after the setting of PKEND, checks are made to confirm, for the packet, whether theNACK flag has been cleared and whether SETUP is effective. Then the command is decodedand the appropriate setting processing is performed. If the NACK flag is set, the succeedingstages will not take place (automatic response (standard command)). SETUP is cleared so thatthe next setup stage will be recognized. PKEND is cleared and BFOK is set, to allow the datastage packet to be received.

Packet transmission confirmation:

When the data stage packet is received, BFOK is cleared and PKEND is set. Immediately afterthe setting of PKEND, a check is made to confirm whether the NACK flag has been cleared forthe packet. Then, a DMA transfer destination RAM data update, DMA address alteration, etc. aredone as necessary. PKEND is cleared and BFOK is set, to allow the status stage packet or a re-transmission of the data stage packet from the host to be received.

End processing

When the status stage packet is received successfully, BFOK is cleared and PKEND is set.

From the DIR value, it can be confirmed that the packet is the status stage packet (transferdirection change from IN to OUT). After this, the final packet completion processing is performed.

Setup Stage Data Stage Status Stage

SETUP

ACK

IN

DATA

ACK No OUT DATA

ACK

Host PC DeviceDevice Host PC

BUFOKPKEND

NACKDIRSETUP

: A broken line shows the operation in the standard command (except Get/SetDescripter, SynchFrame)

[Processing] Set - up processing Packet transmission confirmation

End processing

242


Responses to USB Commands in Each StageThe responses to USB commands in each stage are shown.

Table 10.6-1 Register Responses to Commands

Register value State

BUFOK

PKEND

NACK

DIR

SETUP

0 0 0 0 0 The Initial State

1 0 0 0 0 Waiting to receive the packet

0 1 1 0 1 SETUP packet receptionStandard command IN packets

0 1 0 0 1 SETUP packet receptionGet/SetDescripter, SynchFRAMe, non-standard class vendor commands

0 1 0 1 0 GetDescripter, SynchFRAMe, non-standard class vendor commands (IN packet reception)

0 1 0 0 0 GetDescripter, non-standard class vendor commands (OUT packet reception)

0 1 0 0 0 GetDescripter, SynchFRAMe, non-standard class vendor commands (OUT status reception)

0 1 0 1 0 GetDescripter, non-standard class vendor commands (IN status reception)

243


Responses to setup stage standard USB commandsThe response to a setup stage standard USB command is shown.

Table 10.6-2 Response to a Setup Stage Standard Command

bRequest

Value

Register Hardware operationFirmware processing

Host PC Handshake

NA

CK

DIR

SET

UP

GetStatus 0 1 0 1 Returns the current status tothe host PC. Status: Anautomatic response is madeby the UDC hardware.

BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

ClearFeature 1 1 0 1 The function selected byWValue is cleared in theUDC hardware.


ACK

- 2 1 0 1 Not supported BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

SetFeature 3 1 0 1 The function selected byWValue is enabled.


ACK

- 4 1 0 1 Not supported BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

SetAddress 5 1 0 1 A new address number isspecified. The numberspecified by the host PC isheld by the UDC hardware.


ACK

GetDescriptor 6 0 0 1 Returns the currentdescriptor data to the hostPC. Data: An automaticresponse is made by theDMAC (data prepared by thefirmware in the RAM).

The descriptor dataindicated by the functionselector number that wasobtained by interpreting thecommand is stored in thearea of the RAM which isindicated in DBAR,TDCR0. BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

SetDescriptor 7 0 0 1 Descriptor data comes infrom the host. The DMACautomatically writes the datain the RAM.


ACK

GetConfiguration 8 1 0 1 Returns the currentconfiguration number to thehost PC. Number: Anautomatic response is madeby the UDC hardware.


ACK

244


SetConfiguration 9 1 0 1 A new configuration numberis specified. The numberspecified by the host PC isheld by the UDC hardware.


ACK

GetINterface 10 1 0 1 Returns the current interfacenumber to the host PC.Number: An automaticresponse is made by theUDC hardware.


ACK

SetINterface 11 1 0 1 Changes the Alternatesetting for the specifiedinterface and sets the SETIFbit. The Alternate setting canbe confirmed by using theUSTR2 register.

Interface-by-interfaceAlternate settingmanagement allowsEndPoint configurations tobe altered dynamically.Processing changes aremade with respect to thevolume, content, etc. of thedata transmitted andreceived according to thespecified Alternate setting.The SETIF bit is cleared toallow the next SetINterfacecommand receptioninterruption to take place.BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

SynchFRAMe 12 0 0 1 Returns the number of theframe to be synchronizedwith the host. With theNumber, an automaticresponse relating to dataprepared by the firmware inthe RAM is made by theDMAC.

The number of the frame tobe synchronized is stored inthe area of the RAM that isindicated by DBAR,TDCR0. BUFOK0 is set to"effective" to allow the nextpacket to be received.

ACK

Table 10.6-2 Response to a Setup Stage Standard Command

bRequest

Value

Register Hardware operationFirmware processing

Host PC Handshake

NA

CK

DIR

SET

UP

245


10.6.2 Suspend function

Make sure that all USB devices are placed in the suspend state (low power consumption state) while they are not operating. It is necessary to limit the current consumption of each suspend state device to 500µµµµA (bus power device configuration (i.e. power is supplied via the USB cable)). To achieve this, it is necessary to specify the STOP mode (that stops the main clock), which is the least power-consuming mode among the standby modes (CPU operation).

Suspend processingWhen the USB device core detects a suspend state, SUSP of the USTR1 register is set. Thismakes it necessary to:

• Read and clear the SUSP status;

• In the case of a device that supports remote wake-up, wait for 2ms. (the value specified in theUSB Specification is 5ms. including the suspend time); (This is necessary to make sure that noremote wake-up occurs during this period.)

• The following may help reduce the current consumption of devices in the suspend state:(However, there may be cases where these are not necessary.)

- Input/output direction setting optimization for general-purpose ports

- Pull-up/pull-down voltage level optimization within the user system

- Reducing power consumption levels of user peripheral functions

• Enable the external interruption EIF and EIE registers

• Set the STBC register STP (STOP mode).

For details of the STOP mode, refer to "3.7.3 STOP Mode".

Figure 10.6-5 Suspend operation

Cancellation of the suspend stateSuspend state devices that are in the STOP mode only need the following signal inputs to startoperating again:

• USB bus 2 (D +, D -)

• External interrupt pin (INT0 to 7)

• External Reset Pin (RSTX)

When the USB function circuit detects a resumption signal (i.e. wake-up state), the USTR1register WKUP is set.

1ms 1ms 3ms Suspend state

SOFHost PC DeviceDevice Host PC

SUSP

WKUP

IFO

STP

[Processing] Suspend processing STOP processing

SOF SOF the state that no signal exists on the USB bus including SOF

246


10.6.3 Wake-up function

There are 2 ways to shift a USB device to the wake-up state from the suspend state (USB protocol).• Remote wake-up from a device• Wake-up from the host PC

Remote wake-up from a deviceResumption signal direction: host PC ← device

This makes it necessary to:

• Disable the EIF/EIE register as necessary using external interruptions.

• Enable RESUM in UMDR.

• Read and clear the WKUP status;

• Undo the changes to reduce current consumption levels that were made for suspend statedevices:

- Input/output direction setting optimization for general-purpose ports

- Pull-up/pull-down settings within the user system

- Normal consumption power operation of user peripheral functions

Figure 10.6-6 Remote Wake-up Operation from a Device

Suspend state 20ms 1ms 1ms

RESUM SOF

SUSPWKUPIFOSTPRESUMINTO-7

External interrupt

[Processing] External interrupt processingWake - up processing

SOFRESUM

Oscillation stabilization itme

10mS

Host PC DeviceDevice Host PC

247


Wake-up from the host PCResumption signal direction: host PC -> device

This makes it necessary to:

• The above-mentioned "Reading and Clearing the WKUP Status" step in "Remote Wake-upfrom a Device" and the succeeding steps.

Figure 10.6-7 Wake-up Operation from the Host

Suspend state longer than 20ms 1ms 1ms

RESUM SOF

SUSPWKUPIFOSTP

[Processing] Wake - up processing

SOFHost PC DeviceDevice Host PC

Oscillation stabilization itme

248

CHAPTER 11UART/SIO

This chapter explains the function and operation of the UART/SIO.

11.1 Overview of UART/SIO

11.2 Configuration of UART/SIO

11.3 UART/SIO pins

11.4 Register of UART/SIO

11.5 UART/SIO interrupt

11.6 Explanation of Operation of UART/SIO

11.7 Explanation of operating mode 0

11.8 Explanation of operation mode 1

249

CHAPTER 11 UART/SIO

11.1 Overview of UART/SIO

UART/SIO is a general-purpose serial data communication interface. Serial transfers of variable-length data can be made with a synchronous or asynchronous clock. The transfer format is NRZ and the transfer rate can be specified by means of a dedicated baud rate generator, an external clock or an internal timer.

UART/SIO functionUART/SIO has a serial data communication (serial input and output) function that allows data tobe transmitted to and received from other CPUs and peripheral devices.

• Equipped with a full-duplex double buffer that allows 2-way full-duplex communication.

• The synchronous or asynchronous transfer mode can be selected.

• The built-in baud rate generator allows an appropriate baud rate to be selected from 14different baud rates. It is also possible to specify any desired baud rate using an external clockinput source.

• The data length is variable. 7-bit or 8-bit can be specified when parity is not used and 8-bit or9-bit can be specified when parity is used (Table 11.1-1 ).

• The data transfer format is NRZ (Non-Return-to-Zero).

Table 11.1-1 UART/SIO operation modes

Operating mode Data length Synchronous mode Length of Stop Bit

No Parity With Parity

0 7 8 Asynchronous 1 bit or 2 bits

8 9

1 8 Synchronous -

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CHAPTER 11 UART/SIO

11.2 Configuration of UART/SIO

The UART/SIO consists of the following block.• Serial Clock Switching Register (SCS)• Serial Mode Control Register (SMC1)• Serial Mode Control Register (SMC2)• Serial Rate Control Register (SRC)• Serial Status and Data Register (SSD)• Serial Input Data Register (SIDR)• Serial Output Data Register (SODR)

UART/SIO block diagram

Figure 11.2-1 UART/SIO block diagram

Control Bus

Reload

Reload data register

BRGE

Selector

CS2 to CS0

0.66µs2.66µs

10.66µs

P44/UCK

1/8 clock

MD bit

Each register

Receiving

counter

Start bitdetection

Receivestate

decisioncircuit

Receivedata

register

ShifterPin

IRQ6

P46/UI/PW1

PEROVFFER

RDRFRIE

TDRETIE

CLSBLMD

Receiving

counter

Transmitstart

circuit

TDP,PEN

TXE Transmitdata

register

Shifter

SCKEP44/UCK

TXOEP45/UO

TDRE

MDBRGE EXBRE

0.923µs

EXBRE

8 - bit counter

EXBRE

1/4 clock

1/2 clock

P44/UCK

0.33ms(at 6MHz)

Paritygenerator

Parity

generator

251

CHAPTER 11 UART/SIO

Serial Clock Switching Register (SCS)

Serial Clock Switching Register (SCS): Used to switch the dedicated baud rate generator inputclock between the 4th sub-harmonic of the external clock and the input clock and to switch theclock selected when CS2/CS1/CS0 = 100B (selector circuit) between the external and internalclock.

Serial Mode Control Register (SMC1)

Used for UART/SIO operation mode control. Specifies whether parity is used or not, the stop bitlength, the operation mode (data length), whether the synchronous or asynchronous mode isused and the serial clock.

Serial Mode Control Register (SMC2)

Used for UART/SIO operation mode control. Specifies whether the serial clock output is enabledor disabled, whether the serial data output is enabled or disabled, whether the general-purpose orserial port is used and whether interruptions are permitted or prohibited.

Serial Rate Control Register (SRC)

This register is used for UART/SIO data transfer speed (baud rate) control.

Serial Status and Data Register (SSD)

Indicates the UART/SIO transmission/reception and error statuses.

Serial Input Data Register (SIDR)

The register retains the receive data. The serial input is converted and then stored in this register.

Serial Output Data Register (SODR)

The register sets the transmit data. Data written to this register is serial-converted and thenoutput.

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CHAPTER 11 UART/SIO

11.3 UART/SIO pins

Indicates the terminals associated with UART/SIO and provides a block diagram of the terminals.

Pin related to UART/SIOThe terminals associated with UART/SIO are the clock input and output terminal (P44/UCK),serial data output terminal (P45/UO) and serial data input terminal (P46/UI). These terminals areswitched by the port selection bit (TXOE:SCKE).

P44/UCK:

Serves as both a general-purpose input and output port (P44) and UART/SIO clock input andoutput terminal (hysteresis input) (UCK). When the clock output is enabled (SMC2:SCKE=1), itserves as a UART/SIO clock output terminal (UCK) regardless of the value of thecorresponding port direction register. In this case, make sure that the external clock is notselected (except for SMC1:CS2, CS1, CS0=100B). When it is to be used as a UART/SIO clock

input terminal, disable the clock output (SMC2:SCKE=0) and make sure that it is set as inputport (DDR4:bit4=0) by corresponding port direction register. In this case, make sure that theexternal clock is selected (SMC1:CS2, CS1, CS0=100B).

P45/UO:

Serves as both a general-purpose I/O port (P45) and UART/SIO serial data output terminal(UO). When the serial data output is enabled (SMC2:TXOE=1), it serves as a UART/SIO serialdata output terminal (UO) regardless of the value of the corresponding port direction register.

P46/UI/PW1:

Serves as both a general-purpose input and output port (P46) and UART/SIO serial data inputterminal (hysteresis input) (UI). When it is to be used as a UART/SIO serial data inputterminal, make sure that it is set as input port (DDR4:bit6=0) by corresponding port directionregister.

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CHAPTER 11 UART/SIO

Block Diagram of Pins related to UART/SIO

Figure 11.3-1 Block Diagram of Pins related to UART/SIO

Note

When pull-up resistor was selected in the pull-up option setting register, the terminal state in the stopmode (SPL=1) switches to "H" Level (pull-up state), but not to high impedance state. However, itshould be noted that the pull-up process during a reset will be disabled and becomes Hi-Z. (Note)P46 is not supported.

Pin

Pch

Nch

Pch

PDR read

PDR read

PDR write

DDR write

Output latch

Stop mode (SPL=1)

fromresource output



DDR

Stop mode


DDR read


From Pull - up controlregister

to resource

P44/UCKP45/UOP46/UI

Internal Data B

us

P46 does not exist.



254

CHAPTER 11 UART/SIO

11.4 Register of UART/SIO

Indicates the registers associated with UART/SIO.

Register related to UART/SIO

Figure 11.4-1 Register related to UART/SIO

MD TDP SBL


0 0 2 FH

Address

00000000B

Initial value

R/W

PEN CL CS1 CS0CS2

R/W R/W R/W R/W

RR R RR R

R/WR/W

BRGE


0 0 3 0H

Address

00000000B

Initial value

TXOE RIE TIESCKE

R/WR/W

RERC RXE TXE

PER OVE FER RDRF TDRE

R/WR/WWR/W

RR


0 0 3 1H

Address

00001XXXB

Initial value

R R


0 0 3 2H

Address

XXXXXXXXB

Initial value

SMC1 (Serial Mode Control Register 1)


0 0 3 2H

Address

XXXXXXXXB

Initial value

WW W WW W WW

SODR (Serial Output Data Register)

SIDR (Serial Input Data Register)

SMC2 (Serial Mode Control Register 2)

SSD (Serial Status and Data Register )


0 0 3 3H

Address

XXXXXXXXB

Initial value

SRC (Serial Rate Control Register)

R/W

R/WR/W R/W R/W R/W R/WR/WR/W

R/WR/W

RR R


0 0 2 DH


EXBRE

R/W

SCS (Serial Clock Switching Register)

XXXXXXX0B

R/WRW

X

: Readable and Writable: Read only: Write only: Unused: Undefined

255

CHAPTER 11 UART/SIO

11.4.1 Serial Mode Control Register 1 (SMC1)

Used for UART/SIO operation mode control. Specifies whether parity is used or not, the stop bit length, the operation mode (data length), whether the synchronous or asynchronous mode is used and the serial clock.

Serial Mode Control Register 1 (SMC1)

Figure 11.4-2 Serial mode register 1 (SMC1)

2 instruction cycle (0.66µs/source oscillation 6MHz)



Dedicated baud rate generator

External clock/3.25 instruction (1.08µs/source oscillation 6MHz)

MD

0

1

Asynchronous clock mode (UART)

Synchronous clock mode (SIO)

Mode control bit

SBL

0

1

1-bit length

2-bit length

Control Bit of Stop Bit Length

PEN

0

1

No Parity

With Parity

Parity Control Bit

MD TDP SBL


0 0 2 FH

Address

00000000B

Initial value

R/W

PEN CL CS1 CS0CS2

R/W R/W R/W R/WR/W R/WR/W

CS2

0

0

0

0

1

clock select bitCS1 CS0

0

0

1

1

0

0

1

0

1

0

CL

0

1

7-bit length

8-bit length

Control Bit of Character Bit Length

TDP

0

1

Even Parity

Odd Parity

Parity Polarity Bit

R/WX

: Readable and Writable: Undefined: Initial value

256

CHAPTER 11 UART/SIO

Table 11.4-1 Functions of the Individual Bits of Serial Mode Control Register 1 (SMC1)

Bit name Function

Bit7 MD: Mode control bit

Specifies the UART operation mode. In the asynchronous mode, the 1/8clock of the serial clock is used as the operation clock. In the synchronousclock mode, the selected serial clock is used as the operation clock.

Bit6 PEN: Parity Control Bit

Set parity On/Off at clock asynchronous mode.

Bit5 TDP: Parity Polarity Bit

Set appending parity data for serial transmitting at clock asynchronousmode. A parity data check is performed on each piece of serial-receptiondata during the receiving stage.

Bit4 SBL: Control Bit of Length of Stop Bit

Set stop bit length at clock asynchronous mode. A stop bit with thespecified bit length is added to each piece of serial-transmission dataduring the transmission stage. During the serial-reception of a piece ofdata, a stop bit check for one bit length is performed regardless of thesetting value.

Bit3 CL: Control Bit of Length of CharacterBit

Set character bit length at clock asynchronous mode.

Bit2 Bit1Bit0

CS2 CS1 CS0: Clock selection bits

Select serial clockSCS:EXBRE is used to specify whether the external or internal clock is tobe used when CS2, CS1, CS0=100B.

257

CHAPTER 11 UART/SIO

11.4.2 Serial Mode Control Register 2 (SMC2)

Serial Mode Control Register 2 (SMC2) provides UART/SIO operation mode control. Specifies whether the serial clock output is enabled or disabled, whether the serial data output is enabled or disabled, whether the general-purpose or serial port is used and whether interruptions are permitted or prohibited.

Serial Mode Control Register 2 (SMC2)

Figure 11.4-3 Serial mode register 2 (SMC2)

TXOE

0

1

Serial data output disable (possible to use as port)

Serial data output enable

Serial data output bit

SCKE

0

1

Clock input (possible to use as port)

Clock output enable

Serial clock output bit

BRGE

0

1

Baud rate generator stop

Baud rate generator start

Baud rate generator start bit

BRGE


0 0 3 0H

Address

00000000B

Initial value

TXOE RIE TIESCKE

R/WR/W

RERC RXE TXE

R/WR/WWR/WR/WR/W

TIE

0

1

Transmission interrupt disable

Transmission interrupt enable

Transmission interrupt enable bit

RIE

0

1

Reception interrupt disable

Reception interrupt enable

Reception interrupt enable bit

TXE

0

1

Transmit operation disable

Transmit operation enable

transmit operation enable bit

RXE

0

1

Receive operation disable

Receive operation enable

Receive operation enable bit

RERC

0

1

Each error flag is cleared.

No effect on this bit and others.

Receive error flag clear bit

R/WWX

: Readable and Writable: Write only: Undefined: Initial value

258

CHAPTER 11 UART/SIO

Table 11.4-2 Functions of the Individual Bits of Serial Mode Control Register 2 (SMC2)

Bit name Function

Bit7 RERC: Receive error flag clear bit

Entering "0" for this bit clears the SSD register error flag (PER/OVR/FER). When reading is performed, it always becomes "1".

Bit6 RXE: Reception enable bit

It is a bit which the serial data receiving is enabled. If "0" is entered for thisbit while data is being received, the receiving of data is prohibited aftercompletion of the current data reception.

Bit5 TXE: Transmit enable bit

It is a bit which the serial data transmitting is enabled. If "0" is entered forthis bit while data is being sent, the sending of data is prohibited aftercompletion of the current data transmission.

Bit4 BRGE: Baud rate generator start bit

This bit activate the baud rate generator.

Bit3 TXOE: serial data output bit Serial data output permission / prohibition is controlled by the bit.

Bit2 SCKE: serial clock output bit Serial clock I/O is controlled by the bit at clock synchronous mode.When an external clock is to be input to the P44/UCK terminal, make surethat the appropriate value is specified (input, DDR4 bit4=0).

Bit1 RIE: Receive interrupt enable bit Reception Interrupt is enabled. If the setting to permit receptioninterruptions is made when the RDRF bit is "1" or when the error flag is"1", reception interruptions will occur immediately.

Bit0 TIE: Send interrupt enable bit Transmission Interrupt is permitted. If the setting to permit transmissioninterruptions is made when the TDRE bit is "1", transmission interruptionsoccur immediately.

259

CHAPTER 11 UART/SIO

11.4.3 Serial Clock Switching Register (SCS)

The serial clock switching register (SCS) is used to switch the dedicated baud rate generator input clock and to switch the clock that is input to the selector circuit.

Serial Clock Switching Register (SCS)

Figure 11.4-4 Serial Clock Switching Register (SCS)

Table 11.4-3 Functions of the Bits of the Serial Clock Switching Register (SCS)

Bit name Function

Bit0 EXBRE: Clock switching bit

Specifies switching the dedicated baud rate generator input clock and set input by clockused to external or internal clock when SMC: CS2, CS1, CS0= 100B is selected (3.25

instruction cycle).


0 0 2 DH


EXBRE

R/W

SCS (Serial Clock Switching Register)

XXXXXXX0B

EXBRE

0

1

(SMC1 CS2,CS1,CS0=011B )



Select an external clock


Select an internal clock

Serial Clock Switching Register

R/W

X


260

CHAPTER 11 UART/SIO

11.4.4 Serial Status and Data Register (SSD)

Indicates the UART/SIO transmission/reception and error.

Serial Status and Data Register (SSD)

Figure 11.4-5 Serial Status and Data Register (SSD)

PER OVE FER RDRF TDRE

RR


0 0 3 1H

Address

00001XXXB

Initial value

RR R

OVE

0

1

No Overrun error

With Overrun error

Overrun error flag

FER

0

1

No Framing error

With Framing error

Framing error flag

TDRE

0

1

Transmission data

Empty

Transmit data register Empty

PER

0

1

No Parity error

With Parity error

Parity error flag bit

RDRF

0

1

Empty

Reception data

Receive data register full

R

X

: Read only: Unused: Undefined: Initial value

261

CHAPTER 11 UART/SIO

Table 11.4-4 Functions of the Bits of the Serial Status and Data Register (SSD)

Bit name Function

Bit7 PER: Parity error flag bit

This is set if a parity error occurs while data is being received, and is cleared when"0" is entered for the RERC bit of the SMC2 register. If this flag is set, the SIDRdata becomes invalid. If the FER bit is set when the RIE bit is "1", interruptions willoccur.

Bit6 OVE: Overrun error flag

This is set if an overrun error occurs while data is being received, and is clearedwhen "0" is entered for the RERC bit of the SMC2 register. If this flag is set, theSIDR data becomes invalid. If the FER bit is set when the RIE bit is "1",interruptions will occur.

Bit5 FER: Framing error flag

This is set if a framing error occurs while data is being received, and is cleared when"0" is entered for the RERC bit of the SMC2 register. If this flag is set, the SIDRdata becomes invalid If the FER bit is set when the RIE bit is "1", interruptions willoccur.

Bit4 RDRF: Receive data register full

The flag shows the state of the receive data register (SIDR). This is set whenreceived data is loaded into the SIDR register, and is cleared when the data is readfrom the SIDR register. If the RDRF bit is set when the RIE bit is "1", interruptionswill occur.

Bit3 TDRE: Transmit data registerEmpty

This flag indicates the status of SODR (serial transmission data register). This iscleared when data to be transmitted is written into the SODR register, and is setwhen the data is loaded into the transmission shiftier and transmission starts. If theTDRE bit is set when the TIE bit is "1", interruptions will occur.

262

CHAPTER 11 UART/SIO

11.4.5 Serial Input Data Register (SIDR)

The serial input data register (SIDR) is used to input (receive) serial data.

Serial Input Data Register (SIDR)Figure 11.4-6 shows the bit configuration of the serial input data register.

Figure 11.4-6 Serial Input Data Register (SIDR)

The SIDR stores received data. The serial data signals sent to the serial data input terminal (UIterminal) is converted by the shift register and stored in this register.

If the received data is successfully set into this register, the reception data flag bit (RDRF) is setto "1". If the setting to permit reception interruption requests has been made by this point,interruptions will occur. If an RDRF bit check by the program or using an interruption shows thatreceived data is stored in this register, the reading of the content of this register clears the RDRFflag.

RR R RR R R R


0 0 3 2H

Address

XXXXXXXXB

Initial value

R

X

: Read only: Unused: Undefined

263

CHAPTER 11 UART/SIO

11.4.6 Serial Output Data Register (SODR)

Serial output data register (SODR) is used to output (transmit) serial data.

Serial Output Data Register (SODR)Figure 11.4-7 shows the bit configuration of the serial output data register.

Figure 11.4-7 Serial Output Data Register (SODR)

If the data to be transmitted is written into this register after reading the SSD register when thesetting to permit transmissions has been made by this point, the data to be transmitted istransferred to the transmission shift register, converted into serial data and sent out from theserial data output terminal (UO terminal).

When the transmission data is written into the SODR register, the transmission data flag bit is setto "0". When the transfer of the transmission data to the transmission shift register is complete,the transmission data flag bit is set to "1" and the writing of the next data to be transmittedbecomes possible. If the setting to permit interruption requests has been made by this point,interruptions will occur. The writing of the next data to be transmitted must be done when thetransmission data flag bit is "1" or using an interruption.


0 0 3 2H

Address

XXXXXXXXB

Initial value

WW W WW W WWWX

: Write only: Undefined

264

CHAPTER 11 UART/SIO

11.4.7 Serial Rate Control Register (SRC)

This register is used for UART/SIO data transfer speed (baud rate) control.

Serial Rate Control Register (SRC)

Figure 11.4-8 Serial Rate Register (SRC)

When the clock selection bit (CS2-0) is 011, the dedicated baud rate generator is selected as theserial clock source. This register allows any desired baud rate clock to be specified. Make surethat the writing of data into this register is done when UART is not operating.


0 0 3 3H

Address

XXXXXXXXB

Initial value

R/WR/W R/W R/W R/W R/WR/WR/W

R/W

X


265

CHAPTER 11 UART/SIO

11.5 UART/SIO interrupt

UART/SIO has 3 flags; the error flag bit relating to interruptions (PER, OVE, FER), the "received data" flag bit (RDRF) and "transmission data" flag bit (TDRE). An interruption occurs in the following two cases;• Upon completion of the transfer of a piece of received data from the reception shift

register to the serial input data register (SIDR)• Upon completion of the transfer of a piece of transmission data from the serial output

data register (SODR) to the transmission shift register.

Transmission InterruptWhen the output data is written into the SODR register after the reading of the SSD register, thedata written into the SODR register is transferred to the internal transmission shift register. Whenit becomes ready for the writing of the next data, the TDRE bit is set to "1". If the setting to permittransmission interruptions (SMC2:TIE=1) has been made by this point, an interruption request tothe CPU (IRQ6) will occur.

Reception InterruptIf the data is input successfully up to the stop bit, the RDRF bit is set to "1". If an overrun/parity/framing error occurs, the corresponding error flag bit is set to "1".

These bits are set when a stop bit is detected. If the setting to permit reception interruptions(SSD:RIE=1) has been made by this point, an interruption request to the CPU (IRQ6) will occur.

Registers and Vector Table Addresses Relating to UART/SIO Interruptions

Reference


Table 11.5-1 Registers and Vector Table Addresses Relating to UART/SIO Interruptions

Interruptname



IRQ6 ILR2(007C H ) L61(bit5)

L60(bit4)

FFEE H FFEFH

266

CHAPTER 11 UART/SIO

11.6 Explanation of Operation of UART/SIO

This section explains operation of UART/SIO.UART/SIO has a standard serial communication function (operation modes 0 and 1).

Operation of UART/SIO

Operating mode

UART/SIO has two operation modes. Either the synchronous clock (SIO) mode or asynchronousclock (UART) mode can be selected (See "11.1 Overview of UART/SIO Table 11.1-1 UART/SIOoperation modes").

267

CHAPTER 11 UART/SIO

11.7 Explanation of operating mode 0

Operation mode 0 is the asynchronous clock mode.

Explanation of UART/SIO operating mode 0The CS2 to CS0 bits of the SMC1 register is used to select a serial clock out of the baud rategenerator, external clock and 3 internal clocks. When the selected clock is the external clock,make sure that clock signals are supplied constantly.

In the asynchronous clock mode, the 1/8 clock of the shift clock selected by the CS2 to CS0 bitsis used and transfers can be performed within the range between -2% to +2% of the selectedbaud rate. The baud rate calculation formula for the internal and external clocks and baud rategenerator is as follows:

Baud rate calculation formula by internal/external clock

When the EXBRE bit of the serial clock switching register (SCS) is 0 when CS2, CS1, CS0=100B

is specified and when SMC1(CS2, CS1, CS0 = 000B, 001B, 010B) is selected, the following

calculation formula is used.

Baud rate value1

[bps]

8 Clock cycles selectedat CS2 to CS0.

268

CHAPTER 11 UART/SIO

Baud rate calculation formula for the case where SMC1 (CS2, CS1, CS0 = 100B) is selected and

EXBRE is "1"

When CS2, CS1, CS0 = 100B is specified and the EXBRE bit is 1, the calculation formula is as

follows:

Baud rate calculation formula for using dedicated baud rate generator

When CS2, CS1, CS0 = 011B is specified and the EXBRE bit is "0", the calculation formula is as

follows:

Baud rate value1

[bps]

Fch: Main clock oscillation frequency

Baud rate value

8 13

1[bps]

1/12

<Example: Fch = at 12MHZ>

115384

8 13 1/Fch

Baud rate value

8 2 SRC register value(SRC)


64/FCH

16/FCH

8/FCH

4/FCH

clock gear select

1[bps]

269

CHAPTER 11 UART/SIO

Baud rate calculation formula for the case where the external clock is selected when the dedicated

baud rate generator is being used

When CS2, CS1, CS0 = 011B is specified and the EXBRE bit is "1", the calculation formula is as

follows:

Table 11.7-1 Rate for Asynchronous Transfers (Baud Rate Generator)

Using frequency 12MHz 10MHz 8MHz 7.3728MHz 4.9152MHz

Baud rate Numbers in parentheses

mean SRC register value.*2

- 78125(n=2) - - 76800(n=1)

- 39062(n=4) - 38400(n=3) 38400(n=2)

- 19531(n=8) - 19200(n=6) 19200(n=4)

- 9765(n=16) 9615(n=13) 9600(n=12) 9600(n=8)

4807(n=39) 4882(n=32) 4807(n=26) 4800(n=24) 4800(n=16)

2403(n=78) 2403(n=65) 2403(n=52) 2400(n=48) 2400(n=32)

1201(n=156) 1201(n=130) 1201(n=104) 1200(n=96) 1200(n=64)

- - 600(n=208) 600(n=192) 600(n=128)

*1: The clock frequencies used when the dedicated baud rate generator is used (Fch, Fex)*2: When the internal clock is selected: maximum speed (clock gear)

Baud rate value

8 4 SRC register value(SRC)

1[bps]

2

Fex: External clock frequency

1/Fex

270

CHAPTER 11 UART/SIO

Forwarding data formatUART can handle NRA (Non-Return-to-Zero) format data only. Figure 11.7-1 shows the dataformat. Indicates a case where the stop bit length is 2 bits.

As is shown in Figure 11.7-1 , transfer data always starts with a start bit ("L" level) and ends with astop bit ("H" level). Transfers are performed using the data bit length specified (LSB first). Whenthe state is the idle state, the level is the "H" level.

Figure 11.7-1 Forwarding data format

Receiving operation in the asynchronous clock modeThe baud rate clock is selected using the CS2 to CS0 bits of the SMC1 register. For the baud rateclock, refer to the clock selection. The receiving of data is permitted when the RXE bit of theSMC2 register is "1". The receiving operation starts at the first trailing edge of the input data(detection of the start bit). Upon completion of the receiving operation, the RDRF bit of the SSDregister is set to "1" and the received data is loaded into the SIDR register. If the RDRF bit is setto "1" when the RIE bit is "1", reception interruptions to the CPU will occur. If any of the 3 errorbits (PER/OVE/FER) shows that there is an error at the time of completion of the receivingoperation, the RDRF bit is not set to 1 and the received data is not loaded into SIDR, whichmeans that the SIDR register value shows the data received in the previous receiving session. Aslong as "0" is not set as the RXE bit, it will continue receiving if a start bit is detected even if thereis an error flag.

When "0" is written as the RXE bit in the SMC2 register while receiving, further reception isprohibited once data reception is terminated.

St D0 D1 D2 D3 D4 D5 D6 Sp Sp7-bit lengthNo ParityStop bit 2-bit

St D0 D1 D2 D3 D4 D5 D6 Sp Sp7-bit lengthWith ParityStop bit 2-bit

P

St D0 D1 D2 D3 D4 D5 D6 Sp Sp8-bit lengthNo ParityStop bit 2-bit

D7

St D0 D1 D2 D3 D4 D5 D6 Sp Sp8-bit lengthWith ParityStop bit 2-bit

D7 P

StD0 to D7PSp

: Start bit: Data bit: Parity bit: Stop bit

271

CHAPTER 11 UART/SIO

Figure 11.7-2 Receiving operation in the asynchronous clock mode

Reception error when CLK asynchronous mode is specified.Three errors are detected when CLK asynchronous mode is specified. The three errors are parity,over-run, and framing errors, and when such errors are detected, 1 is ascribed as each of thePER, OVE, and FER bits on the SSD register.

These errors are detected when reception ends as follows. If such errors are detected, the RDRFwill not be set, and received data will not be loaded onto the SIDR register, so the previouslyreceived data will remain as the value on the SIDR register. All three of these error flags can becleared by writing 0 as the RERC bit in the SCM2 register.

Figure 11.7-3 Setting the timing for receiving errors

Detection of start bit during receptionThe start bit is defined as the start bit that has "L" level for 4 clocks using the selected serial clock(i.e. generator output) after the first falling edge of input data. After the start bit is detected, data issampled at the rising edge of the 5th serial clock.

SI St D0 D1 D2 D3 D4 D5 D6 Sp SpD7 St D0 D1 D2

RXE

SIDRRead

RDRF

SI D5 D6 Sp SpD7

Error interrupt

PEROVEFER

272

CHAPTER 11 UART/SIO

Figure 11.7-4 Start bit detection

CLK asynchronous mode transmissionWhen the TXE bit in the SMC2 register is "1", by writing transmission data to the SODR register,the TDRE bit in the SSD register will be cleared and transmission started. When the SODRregister data is loaded to the shiftier and output of transmission data is started, the TDRE bit inthe SSD register will be set. If data is written into the SODR register during transmission (whenthe TDRE bit is "1"), the TDRE bit will be cleared and transmission will continue aftertransmission for the specified bit length ends.

When "0" is written as the TXE bit in the SMC2 register during transmission, transmission will beprohibited once transmission for the specified bit length ends if the SODR register is vacant(TDRE bit is "1"). When data exists in the SODR register (TDRE bit is "1"), transmission will beprohibited after transmitting the SODR register data.

Figure 11.7-5 CLK asynchronous mode transmission

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

D0

Serial clock

SI

4 clocks

detection of a start bit Sampling data

: Start bit: Data bit

StD0 to D7

SO St D0 D1 D2 D3 D4 D5 D6 Sp SpD7 St D0 D1 D2

TXE

SODRWrite

TDRE

Interrupt to CPU Interrupt to CPU

: Start bit: Data bit: Stop bit

StD0 to D7Sp

273

CHAPTER 11 UART/SIO

11.8 Explanation of operation mode 1

Operation mode 1 operates in clock synchronous mode.

Explanation of UART/SIO operating mode 1Under CLK synchronous mode, executes using the CS2 ~ CS0 bits in the SMC21 register, withselection being made from 3 types of output-namely internal clock, external clock, and baud rategenerator. Shifting is carried out using the selected clock as the shift clock. When an externalclock is input, set "0" as the SCK bit.

When internal clock or baud rate generator is output as the shift clock, set "1" as the SCKE bit.The baud rate calculation formula using internal/external clocks and baud rate generator is shownas follows.

Baud rate calculation formula by internal/external clock

When SMC1 (CS2, CS1, CS0=000B, 001B, 010B) is selected and when CS2, CS1, CS0=100B is

selected, if 0 is set as the EXBRE bit on the SCS (serial clock switching register), the calculationformula will be as follows.

The baud rate calculation formula when "1" is set as the EXBRE bit while SMC1 (CS2, CS1,

CS0=100B) is selected

Baud rate value1

[bps]Clock cycles selected at

CS2 to CS0

Baud rate value


1[bps]

13 1 / Fch

274

CHAPTER 11 UART/SIO

The baud rate calculation formula if the internal clock is selected when a dedicated baud rate generator

is used.

When CS2, CS1, CS0=011B is selected, if "0" is set as the EXBRE bit, the calculation formula will

be as follows.

Baud rate calculation formula for the case where the external clock is selected when the dedicated

baud rate generator is being used

When CS2, CS1, CS0=011B is selected, if "1" is set as the EXBRE bit, the calculation formula will

be as follows.

Baud rate value

2 SRC register value(SRC)


64/FCH

16/FCH

8/FCH

4/FCH

Clock gear select

1[bps]

Baud rate value

4 SRC register value(SRC)

Fex: External clock

1[bps]

2 1/Fex

275

CHAPTER 11 UART/SIO

8-bit ReceptionReception is enabled by specifying "11" as the TXE/RXE bit, and initiated by writing to the SODRregister, while reception is synchronized with the rising edge of the shift clock. Once 8-bit datareception ends, shiftier data is loaded to the SIDR register, and the RDRF flag is set as "1". WhenRIE="1", an interrupt request is issued to the CPU. If an over-run error occurs once receptionends, the data will not be loaded to the SIDR register. When "0" is written as the RXE bit duringreception, reception is suspended once 8 bits of data are received. The serial clock must alwaysbe input as "H" level while serial operation is suspended (regardless of the RXE bit value).

Figure 11.8-1 8-bit reception of CLK synchronous mode

SI D0 D1 D2 D3 D4 D5 D6 D7

SCK

SIDRread

RDRF

SODRWrite

Interrupt to CPU

276

CHAPTER 11 UART/SIO

Sequence reception operationUnder CLK synchronous mode, continuous reception is possible as well as 8-bit data reception.As regards the bits to be used, the TIE bit on the SMC2 register and the TDRE bit on the SSDregister are used as well as the bit used for 8-bit reception. Reception is enabled by specifying"11" as the TXE/RXE bit, and initiated by writing to the SODR register, while reception issynchronized with the rising edge of the shift clock. When shift operations are started, the TDREbit is set as "1", and if TIE="1", an interruption request is issued to the CPU. By writing to theSODR register before completing the 8-bit shift operation, the following shift operation is enabled,and reception can continue after 8-bit data reception as well. When 8-bit data reception ends,shiftier data is loaded to the SIDR register, the RDRF flag is set to "1", and if RIE ="1", aninterruption request is issued to the CPU. If an over-run error occurs once reception ends, thedata will not be loaded to the SIDR register, so the previously received data will remain as thecontents on the SIDR register. Receipt interruption (RDRF) is cleared by reading the SIDRregister. Reception is stopped by writing "0" to the RXE bit. When "0" is written as the RXE bitduring reception, reception is suspended once 8 bits of data are received.

Figure 11.8-2 Continuous reception under CLK synchronous mode

SI D0 D1 D2 D3 D4 D5 D6 D7

SCK

SIDRLoad

RDRF

SODRWrite

Interruptto CPU

D0 D1 D2 D3 D4 D5 D6 D7

TDRE

SIDR read Interruptto CPU

277

CHAPTER 11 UART/SIO

8-bit TransmissionTransmission is initiated by writing to the SODR register after setting the TXE/RXE bit to "11".When transmission is activated, shift operation is carried out after loading the data written in theSODR register to the shiftier. When SODR register data is loaded to the shiftier, the TDRE flag isset to "1", and if TIE="1", an interruption request is issued to the CPU. Serial data output isenabled by specifying TXOE="1", and output is carried out in synchronization with the falling edgeof the shift clock.

When "0" is written as the TXE bit during transmission, transmission is stopped after sending 8bits of data. After sending 8 bits, the RDRF bit is set to "1", and if RIE="1", interruption request isissued to the CPU. Transmission direction starts from bit 0 and ends at bit 7. The serial clockmust always be input as "H" level while serial operation is suspended (regardless of the RXE bitvalue).

Figure 11.8-3 8-bit transmission under CLK synchronous mode

SI D0 D1 D2 D3 D4 D5 D6 D7

SCK

RDRF

SODRWrite

Interrupt to CPU

TDRE

Interrupt to CPU

278

CHAPTER 11 UART/SIO

Sequence transmission operationUnder CLK synchronous mode, continuous transmission is possible as well as 8-bit datatransmission. Once "11" is set as the TXE/RXE bit, operation is carried out by writing data to theSODR register. When transmission is activated, shift operation is carried out after loading thedata written in the SODR register to the shiftier. When SODR register data is loaded to theshiftier, the TDRE flag is set to "1", and if TIE="1", an interruption request is issued to the CPU.

Continuous operation is carried out by writing the following transmission data to the SODRregister when the TDRE bit is "1" (SODR register is vacant) during transmission. The TDRE bit iscleared by writing to SODR, and after 1bit of data transmission, transmission is continued byloading the data written in the SODR register to the shiftier. Data transmission is stopped bywriting "0" to the TXE bit. When "0" is written to the TXE bit during transmission, if the SODRregister is vacant (TDRE bit is "1"), transmission is stopped after sending 8 bits of data. Whendata exists in the SODR register (TDRE bit is "0"), transmission is stopped after sending theSODR register data. When 8-bit data transmission ends, "1" is set as the RDRF bit, and ifRIE="1", interruption request is issued to the CPU.

Figure 11.8-4 Continuous transmission under CLK synchronous mode

SI D0 D1 D2 D3 D4 D5 D6 D7

SCK

RDRF

SODRWrite

Interrupt to CPU

TDRE

Interrupt to CPU

D0 D1 D2 D3

279

CHAPTER 11 UART/SIO

280

CHAPTER 128-bit Serial I/O

This chapter describes the functions and operation of the 8-bit serial I/O.

12.1 Overview of 8-Bit Serial I/O

12.2 Configuration of 8-Bit Serial I/O

12.3 Pin of 8-Bit Serial I/O

12.4 Registers of 8-Bit Serial I/O

12.5 8-Bit Serial I/O Interrupt

12.6 Explanation of Operations of Serial Output Functions

12.7 Explanation of Operations of Serial Input Functions

12.8 Status under each mode during 8-bit serial I/O operation

12.9 Notes on Using 8-Bit Serial I/O

12.10 Example of 8-Bit Serial I/O Connection

12.11 Program Example for 8-Bit Serial I/O

281

CHAPTER 12 8-bit Serial I/O

12.1 Overview of 8-Bit Serial I/O

The 8-bit serial I/O has a function that serially transfers 8-bit data in synchronization with a shift clock. It can select one shift clock from three internal shift clocks and one external shift clock. It can also select LSB first or MSB first as the data shift direction.

Serial I/O FunctionThe 8-bit serial I/O function serially inputs and outputs 8-bit data in synchronization with a shiftclock. 2 channels are featured on this model.

• Converts 8-bit parallel data to serial and outputs. Also inputs 8-bit serial data, converts thedata to 8-bit parallel data, and stores it.

• It can select one shift clock from three internal shift clocks and one external shift clock.

• The shift clock input and output can be controlled and the internal shift clock can be output.

• The data shift direction (transfer direction) can be set to either LSB-first or MSB-first.

Table 12.1-1 Shift clock frequency and transfer speed

Shift clock Clock Cycle Frequency (Hz) Transfer rate(FCH =12MHz, at Max speed)

Internal shift clock (Output) 2t inst 1/(2t inst ) 1500 Kbps

8t inst 1/(8t inst ) 375 Kbps

32t inst 1/(32t inst ) 93.7 Kbps

External shift clock (input) 2t inst or more under 1/(2t inst ) DC to 1500 Kbps

FCH: main clock source oscillationtinst: Instruction cycle (Affected by the clock mode and others.)* :When the quickest clock in the main clock mode (SOS=1) is selected (CS1, CS0=11B, 1 instruction cycle = 4/

FCH) using the system clock control register (SYCC);

282


12.2 Configuration of 8-Bit Serial I/O

Each 8-bit serial I/O channel consists of the following four blocks:• Shift clock control circuit• Shift clock counter• Serial data register 1/2 (SDR1/SDR2) • Serial mode register 1/2 (SMR1/SMR2)

Block Diagram of 8-bit Serial I/O

Figure 12.2-1 Block Diagram of 8-bit Serial I/O

Internal Data Bus

(shift direction)

Serial data register (SDR1 /SDR2 )

D0 to D7MSB first

D7 to D0LSB first

D7 to D0

2

SST

BDS

CKS0

CKS1

SOE

SCKE

SIOE

SIOF

Serial mode register(SMR1 /SMR2 )Shift clock

control circuit

Shift clock counter

Transferdirection select

P32/INT2/SI1P37/INT7/SI2

Output enable

Output enable

2tinst

Shift clock select

InterruptrequestIRQBIROC

tinst: instruction cycle

Overflow

8tinst

32tinst

Clear

Pin

Pin

Pin

Output buffer

Output buffer

P33/INT3/SO1P36/INT6/SO2

P34/INT4/SCK1P35/INT5/SCK2

: for 8 - bit serial I/O1: for 8 - bit serial I/O2

283


Shift clock control circuit

As a shift clock of the shift clock control circuit, one of three internal clocks and one external clockis selected.

Selecting an internal clock enables the shift clock to be output to the SCK1/SCK2 pins. Selectingan external clock enables the clock to be input from the SCK1/SCK2 pins to act as the shift clock.The SDR1/SDR2 register is shifted using this shift clock, and the value shifted out is output to theSO1/SO2 terminal. Input of the SI1/SI2 terminal is downloaded to the SDR1/SDR2 register whileshifting.

Shift clock counter

The number of shifts of the SDR1/SDR2 register using the shift clock is counted, and when 8-bitshifting ends, the counter overflows.

The serial I/O transfer start bit of the SMR1/SMR2 register is cleared (SMR1/SMR2:SST=0) bythis overflow, and an interruption request flag is set (SMR1/SMR2:SIOF=1). The shift clockcounter stops counting when serial transfer is stopped (SMR1/SMR2:SST=0), and is clearedupon start of serial transfer (SMR1/SMR2:SST=1).

Serial data register (SDR1/SDR2)

The SDR retains transfer data. Data written in this register is output after serial conversion, andalso serial input is stored after parallel conversion.

Serial mode register (SMR1/SMR2)

A control register for Serial I/O. It is used to allow and prohibit serial I/O operation, select shiftclocks, and set a transfer (shift) direction. It is also used to control interrupts and check interruptstates.

8-bit serial I/O interrupt factor

IRQB(8-bit serial I/O 1)/IRQC(8-bit serial I/O 2):

When input/output of 8-bit serial data using the input/output function ends, if interruption requestoutput is enabled (SMR1/SMR2:SIOE="1"), the 8-bit serial I/O issues the interruption request(IRQ8/IRQC).

284


12.3 Pin of 8-Bit Serial I/O

8-bit serial I/O-related terminals, block diagram of the terminals, and interruption causes of 8-bit serial I/O are shown.

Pin of 8-bit Serial I/OThe P32//SI1, P33//SO1, and P34//SCK1 terminals relate to 8-bit serial I/O1, and the P37//SI2,P36//SO2, and P35//SCK2 terminals relate to 8-bit serial I/O2.

Pin of 8-bit Serial I/O

P32/INT2/SI1 pin

The P32/INT2/SI1 terminal can perform the serial data input (hysteresis input) function (SI1) ofthe general-purpose input/output port (P32), external interruption INT2, or 8-bit serial I/O.

P33/INT3/SO1 pin

The P33/INT3/SO1 terminal functions as a general-purpose input/output port (P33) and also as aserial data output terminal (CMOS output) for external interruption (INT3) 8-bit serial I/O.

When serial data output is enabled (SMR1:SOE=1), it automatically becomes the output terminal,and functions as the SO1 terminal.

P34/INT4/SCK1 pin

The P34/INT4/SCK1 terminal functions as a general-purpose input/output port (P34) and also asa shift clock input/output terminal (hysteresis input) (SCK1) for external interruption (INT4) serial I/O.

• When SCK1 is used as an input terminal, set up (DDR3:bit4=0) to the input port using the portdirection register, and prohibit output of the shift clock (SMR1:SCKE=0). In this case, be sureto select the external shift clock (SMR1: CKS1, CKS0 = 11B).

• When using the P34/INT4/SCK1 pin as the shift clock output pin, when the shift clock output isallowed (SMR1: SCKE=1), the P34/INT4/SCK1 pin automatically becomes as output pinirrespective of the values in the port direction register (DDR3:bit4) and functions as the SCK1output pin. In this case, be sure to select an internal shift clock (when SMR: CKS1, CKS0 arenot 11B).

Pin of 8-bit Serial I/O2

P37/INT7/SI2

The P32/INT7/SI1 terminal can perform the serial data input (hysteresis input) function (SI1) ofthe general-purpose input/output port (P37), external interruption INT7, or 8-bit serial I/O.

285


P36/INT6/SO2 pin

The P33/INT6/SO1 terminal functions as a general-purpose input/output port (P36) and also as aserial data output terminal (CMOS output) for external interruption (INT6) 8-bit serial I/O.

When serial data output is enabled (SMR2:SOE=1), it automatically becomes the output terminal,and functions as the SO2 terminal.

P35/INT5/SCK2 pin

The P34/INT5/SCK1 terminal functions as a general-purpose input/output port (P35) and also asa shift clock input/output terminal (hysteresis input) (SCK2) for external interruption (INT5) serial I/O.

• When SCK2 is used as an input terminal, set up (DDR3:bit5=0) to the input port using the portdirection register, and prohibit output of the shift clock (SMR2:SCKE=0). In this case, be sureto select the external shift clock (SMR2: CKS1, CKS0 = 11B).

• When using the P34/INT4/SCK1 pin as the shift clock output pin, when the shift clock output isallowed (SMR2: SCKE=1), the P35/(GRAPHICS)/SCK2 pin automatically becomes as outputpin irrespective of the values in the port direction register (DDR3:bit5) and functions as theSCK2 output pin.

Block Diagram for 8-bit Serial I/O Pins

Figure 12.3-1 Block Diagram of SI1, SI2, SCK1, SCK2 Pins

Pin

Pch

Nch

Pch

PDR read

PDR write

DDR write

Output latch

Stop, Clock mode (SPL=1)


DDR



Port 3 pull - up resistancecontrol register

Internal Data B

us

to SI1,SI2,SCK1,

SCK2 inputpull - up resistance

Approx. 50k

PDR read

DDR read

SCK1,SCK2 output enable

SCK1,SCK2 output


External interrupt input enable

to External interrupt circuit

8 - bit serial I/O1P32/INT2/SI1P33/INT3/SO1P34/INT4/SCK1

8 - bit serial I/O2P37/INT7/SI2P36/INT6/SO2P35/INT7/SCK2



286


Reference

When pull-up resistance is selected for the port 3 pull up resistance control register, the terminalstatus for the stop mode or clock mode (STBC:SPL=1) will be "H" level (pull up status) instead ofhigh impedance.

However, it should be noted that the pull-up process during a reset will be disabled and becomes Hi-Z.

287


12.4 Registers of 8-Bit Serial I/O

Registers of 8-bit Serial I/O

Registers of 8-bit Serial I/O

Figure 12.4-1 Registers of 8-bit Serial I/O 1

Registers of 8-bit Serial I/O2

Figure 12.4-2 Registers of 8-bit Serial I/O2

SOE


00000000BSI0F SSTBDSCKS0CKS1SCKESI0E

Address

SMR1 003AH

R/WR/W R/WR/WR/WR/WR/WR/W


XXXXXXXXB

Address

SDR1 003BH


R/WX

: Readable and Writable: Undefined

SOE


00000000BSI0F SSTBDSCKS0CKS1SCKESI0E

Address

SMR2 004AH



XXXXXXXXB

Address

SDR2 004BH


R/WX


288


12.4.1 Serial mode register 1/2 (SMR1/SMR2)

Serial mode register 1/2 (SMR1/SMR2) enables and prohibits operation of 8-bit serial I/O, selects the shift clock, sets up the transfer direction, controls interruptions, and checks the status.

Serial mode register 1/2 (SMR1/SMR2)

Figure 12.4-3 Serial mode register (SMR1/SMR2)

SIOE

0

1

SOE


0 0 3 AH/0 0 4 AH

Address

00000000B

Initial value

CKS1 BDS SSTCKS0

Interrupt request enable bit



SIOFInterrupt request flag bit

Transfer does not finish. Clear this bit.

No change. No effect on others.

0

1

Read Write

SCKE Shift clock output enable bit

Use P34/INT4/SCK1 for SMR1 and P35/INT7/SCK2for SMR2 as general-purpose ports or shift clock input pins.

0

1

SIOF SIOE SCKE

Transfer finished.

SOE Serial data output enable bit

Use P33/INT3/SO1 for SMR1 and P36/INT6/SO2for SMR2 as general-purpose ports.0

1

CKS1

0

0

1

1

CKS0

0

1

0

1

Shift clock selection bit

External shift clock

2tinst

8tinst

32tinst

Internal shift clock

SCK1/SCK2 Pin

Output

Output

Output

Input

tinst: instruction cycle

Transfer direction select bit

LSB first(Start transfer from the lowest bit.)

MSB first(Start transfer from the highest bit.)

BDS

0

1

SSTSerial I/O transfer start bit

0

1

Read Write

Serial transfer stop

During serial transfer

Serial transfer stop/disable

Serial transfer start/enable


Use P33/INT3/SO1 for SMR1 and P36/INT6/SO2for SMR2 as serial data output pins.

Use P34/INT4/SCK1 for SMR1 and P35/INT7/SCK2for SMR2 as shift clock output pins.


289


Table 12.4-1 Functional description of each bit in Serial mode register (SMR1/SMR2)

Bit name Function

Bit7 SIOF: Interrupt requestflag bit

• Set to "1" by the serial I/O after 8 bits of serial data input or output completes. When this bit and the interruption request enable bit (SIOE) are set to "1", an interruption request is output.

• Cleared by specifying "0" during writing, and remains unchanged as the bit is unaffected by specifying "1".

Bit6 SIOE: Interrupt requestenable bit

This bit is used to enable and disable interrupt request output to the CPU. When this bitand the interrupt request enable bit (SIOF) are 1, an interrupt request is output.

Bit5 SCKE: Shift clock outputenable bit

• This bit is used to control shift clock I/O.• When this bit is "0", the P34/INT4/SCK1 (for SMR1), P35/INT5/SCK2 (for SMR2)

terminal will be the shift clock input terminal, and conversely will be the shift clock output terminal when it is "1".

Note:• In order to use as shift clock input, P34/INT4/SCK1 (for SMR1), or P35/INT5/SCK2

(for SMR2) terminal must be set as an input port. Also select the external shift clock with the shift clock selection bits (Set the CKS1 and CKS0 bits to 11B).

• For shift clock output (SCKE bit = 1), select an internal shift clock (do not set the CKS1 and CKS0 bits to 11B).

Reference:• When shift clock output is enabled (SCKE=1), functions as SCK1/SCK2 output

terminal regardless of the status of the general-purpose port (P34 (for SMR1)/P35 (for SMR2)).

• Select shift clock input (SCKE=0) when using as a general-purpose port (P34 (for SMR1)/P35 (for SMR1).

Bit4 SOE: Serial-data outputenable bit

When this bit is 0, the P33//SO1 (for SMR1), P36//SO2 (for SMR2) terminal will be ageneral-purpose port (P33 (for SMR1) / P36 (for SMR2)), otherwise it will be a serial dataoutput terminal 1 (SO1/SO2) when this bit is 1.Reference:When serial data output is enabled (SOE=1), functions as the SO1 (for SMR1) / SO2 (for SMR2) terminal regardless of the status of the general purpose port (P33 (for SMR1) / P36 (for SMR2)).

Bit3 Bit2

CKS1, CKS0: Clock select bit

• These bits are used to select three internal shift clocks or one external shift clock.• When these bits are other than "11B ", the internal shift clock is selected, and when the

shift clock output enabling bit (SCKE) is "1", the shift clock is output from the SCK1 (for SMR1)/SCK2 (for SMR2) output terminal.

• When it is 11B, an external shift clock is selected, and if the shift clock input is set, (SCKE=0, DDR3:bit4=0 (for SCK1) /DDR3:bit5 (for SCK2)), the SCK1 (for SMR1) / SCK2 (for SMR2) shift clock is input from the output terminal.

Bit1 BDS: Transfer directionselect bit

This bit is used to select whether to transfer serial data, starting at the lowest bit (LSB first,BDS=0) or the highest bit (MSB first, BDS=1).Note:After data is written to the SDR1 (for SMR1) or SDR 2 (for SMR2) register to replace upper and lower data when reading and writing to the serial data register 1 (SDR1: for SMR1) or serial data register 2 (SDR2: for SMR2), if this bit is rewritten, the data will be invalidated.

290


Bit0 SST: Serial I/O transferstart bit

• Controls transfer start and transfer enable for the serial I/O. The decision to terminate the transfer can be made using this bit as well.

• When the internal shift clock (CKS1, CKS0= other than 11 B) is specified, the shift

clock counter will be cleared and transfer will be started by writing "1" to this bit.• When external shift clock (CKS1, CKS0=11B) is specified, transfer is enabled by

writing "1" to this bit, the shift clock counter will be cleared and will adopt a standby status for the external shift clock input.

• When transfer ends, this bit will be cleared to "0" and the SIOF bit will be set to "1".• When "0" is written to this bit during transfer (SST=1), transfer will be suspended. If

transfer is suspended, the SDR1/SDR2 register at the data output side needs to be set up, and transfer at the data input side needs to be re-started (clearing the shift clock counter).

Table 12.4-1 Functional description of each bit in Serial mode register (SMR1/SMR2)

Bit name Function

291


12.4.2 Serial data register 1/2 (SDR1/SDR2)

The serial data register 1/2(SDR1/SDR2) holds 8-bit serial I/O transfer data.The SDR functions as a transmission data register at serial output operation. It functions as a reception data register at serial input operation.

Serial data register 1/2 (SDR1/SDR2) Figure 12.4-4 shows the bit layout of the serial data register.

Figure 12.4-4 Serial data register 1/2(SDR1/SDR2)

At serial output operation

When transfer of serial I/O is started (SMR1/SMR2:SST=1) using the register that functions as atransmit data register, data that is written into this register will be transferred serially.

Transmit data will not remain in the SDR1/SDR2 register as it is shifted out by this transfer.

At serial input operation

When transfer of serial I/O is started (SMR1/SMR2:SST=1) using the register that functions as areceipt data register, data that is serially transferred to this register will be stored.

During serial I/O transfer

While serial I/O is transferring, do not write data to the SDR1/SDR2 register. The read-out valuesare meaningless.

When serial output and serial input are allowed at the same time, serial I/O operation isperformed.


XXXXXXXXB

Address

003BH/004BH


R/WX


292


12.5 8-Bit Serial I/O Interrupt

An event triggering an 8-bit serial I/O interrupt is the completion of serial input or output of eight-bit data.

Interrupt at Serial I/O OperationIn the 8-bit serial I/O, serial output operation and serial input operation are performed at the sametime. When serial I/O transfers started, the value in the serial data register (SDR1/SDR2) areinput and output on a per bit basis in synchronization with the set shift clock cycle. Subsequently,when the shift clock at the 8th bit is started up, the interruption request flag bit (SMR1/SMR2:SIOF) will be set to "1".

In this case, if the interruption request output bit is enabled (SMR1/SMR2:SIOE=1), aninterruption request is issued to the CPU (IRQB (for SMR1)/IRQC (for SMR2)).

Write 0 to the SIOF bit using the interrupt handling routine to clear the interrupt request. When 8-bit serial output is completed, the SIOF bit is set irrespective of the SIOE bit value.

Reference

During serial input/output operation, if suspension of serial transfer (SMR1/SMR2:SST=0) andtermination of data transfer occur simultaneously, the interruption request flag bit setting (SMR1/SMR2:SIOF=1) will not be carried out. Also, an interrupt is generated if the SIOE bit is changed fromdisabled to enabled (0 to 1) when the SIOF bit is "1".

8-bit Serial I/O Interrupt Register and Vector Table


Table 12.5-1 8-bit Serial I/O Interrupt Register and Vector Table

Interrupt name Interrupt level setting register Address of vector table


IRQB(8-bit serial I/O 1) ILR3(007D H ) LLB(bit7) LLB(bit6) FFE4 H FFE5 H

IRQC(8-bit serial I/O 2) ILR4(007E H ) LC1(bit1) LC0(bit0) FFE2 H FFE3 H

293


12.6 Explanation of Operations of Serial Output Functions

8-bit serial I/O can execute serial output of 8-bit data in synchronization with the shift clock. In this section, 8-bit serial I/O1 is explained as an example.

Serial output operationFor serial output operation, the internal and external shift clocks can be used. When serial input/output operation is enabled, the SDR1 register details are output to the serial data output terminal(SO1) at the same time as the serial input.

For the internal shift clock:

Serial output operation based on the internal shift clock requires the settings shown in Figure 12.6-

1 .

Figure 12.6-1 Setup for serial output (when internal shift clock is used)

When serial output is activated, the SDR1 register details are output to the SO1 terminal insynchronization with the falling edge of the selected internal shift clock. In this case, the transferdestination (serial input side) must be in the external shift clock input wait state.

For external shift clock:

Serial output operation based on the external shift clock requires the settings shown in Figure

12.6-2 .

Figure 12.6-2 Setting serial output (with the external shift clock used)

When serial output is enabled, the SDR1 register details are output to the SO1 terminal insynchronization with the falling edge of the external shift clock. After serial output ends, the SDR1register needs to be re-set up immediately and operation needs to be enabled (SMR1: SST=1)promptly to be ready for the next data output.

: Used bit: Set to 1

SMR1

SDR1 Setting Transfer data

1

SIOF SIOE SSTBDSCKS0CKS1SOESCKE

11Other than 11


: Used bit: Unused bit: Set to 1: Set to 0

SMR1

SDR1 Setting Transfer data

DDR3

0

0


11 1 1

294


After serial input operation (rising edge) of the other end ends, while waiting for the next dataoutput (idle status), set the external shift clock to "H" level.

Figure 12.6-3 shows the operation of the 8-bit serial output.

Figure 12.6-3 8-bit serial output operation

Operation at Serial Output CompletionInterruption request flag bit is set (SMR1:SIOF=1) and serial I/O start bit is cleared (SMR1:SST=0) by the rising edge of the shift clock that input/output the serial data of the 8th bit.

#7 #5 #4SDR1

At LSB first

#6 #3 #1 #0#2

#0 #1 #2 #3 #4 #5 #6 #7

Shift clock

SIOF bit

SST bit

SO1 pin

Serialoutput data


0 1 2 3 4 5 6 7Clearing by program

Automatic clear at transfer end.

Transfer start Interrupt request

295


12.7 Explanation of Operations of Serial Input Functions

In the 8-bit serial I/O, 8-bit serial input operation synchronized with a shift clock is possible.

Serial input operationOperation using internal and external shift clocks is possible for serial input. When serial input/output operation is enabled, the SDR1 register details are output to the serial data output terminal(SO1) at the same time as the serial input.

For the internal shift clock:

Serial input operation based on the internal shift clock requires the settings shown in Figure 12.7-1 .

Figure 12.7-1 Setting serial input (with the internal shift clock used)

When serial input is activated, value of the serial data input terminal (SI1) is downloaded to theSDR1 register in synchronization with rising edge of the selected internal shift clock. In this case,the SDR1 register at the transfer destination (serial output side) must be set up and the externalshift clock input must be on standby status.

For external shift clock:

Serial input operation based on the external shift clock requires the settings shown in Figure 12.7-

2 .

DDR3


SMR1

SDR1 Reception data storage

1


1Other than 11 : Used bit: Unused bit: Set to 1: Set to 0

296


Figure 12.7-2 Setting serial input (with the external shift clock used)

When serial input is enabled, the value of the SI1 terminal is downloaded to the SDR1 register insynchronization with rising edge of the external shift clock. After serial input ends, the SDR1register needs to be read out immediately and operation needs to be enabled (SMR1:SST=1)promptly to be ready for the next data input.

In this case, the external shift clock should be set to "H" level while waiting for the next dataoutput (idle status).

Figure 12.7-3 shows the operation of the 8-bit serial input.

Figure 12.7-3 8-bit serial input operation

Operation of serial input completionInterruption request flag bit is set (SMR1:SIOF=1) and serial I/O start bit is cleared (SMR1:SST=0) by the rising edge of the shift clock that input/output the serial data of the 8th bit.

DDR3


SMR1

SDR1 Reception data storage

0

0


11 1: Used bit: Unused bit: Set to 1: Set to 0

#7 #5 #4SDR1

At MSB first

#6 #3 #1 #0#2

#7 #6 #5 #4 #3 #2 #1 #0

Shift clock

SIOF bit

SST bit

SI1 pin

Serialinput data


0 1 2 3 4 5 6

Automatic clear at transfer end.

7Clearing by program

Interrupt request

297


12.8 Status under each mode during 8-bit serial I/O operation

Actions during suspension and when shifting to sleep mode or stop mode during serial I/O operation are explained using 8-bit serial I/O1 as an example.

When the Internal Shift Clock is Used

Operation at sleep

In sleep mode, the device continues transfer without stopping serial I/O operation as shown inFigure 12.8-1 .

Figure 12.8-1 Operation in sleep mode (internal shift clock)

8-bit serial I/O operation in stop mode

During stop mode, serial input and output operation halts and any transfer is aborted, as shown inFigure 12.8-2 . After stop mode has been released, reinitialize the 8-bit serial I/O becauseoperation is resumed halfway.

Figure 12.8-2 Operation in stop mode (internal shift clock)

#0 #1 #2 #3 #4 #5 #6 #7

SCK1 pin output

SST bit

SIOF bit

SO1 pin output


Sleep

Sleep mode release via IRQB

Clearing by program

Interrupt request

#0 #1 #2 #3 #4 #5 #6 #7

SCK1 pin output

SST bit

SIOF bit

SO1 pin output


Stop mode release via external interrupt

Interrupt request

Clearing by program

Oscillation stabilizationwait timeStop mode request

Stop, Clock mode

298


8-bit serial I/O operation at issuance of stop request during operation

If operation is halted (SMR1:SST=0) while a transfer is in progress as shown in Figure 12.8-3 , thetransfer stops and the shift clock counter is cleared. For this reason, the transfer destination mustalso be initialized. During serial output operation, re-set the SDR1 register before re-starting.

Figure 12.8-3 Operation when halted while in operation (internal shift clock)

When the External Shift Clock is Used

Operation at sleep

In sleep mode, the device continues transfer without stopping serial I/O operation as shown inFigure 12.8-4 .

Figure 12.8-4 Operation in sleep mode (external shift clock)

8-bit serial I/O operation in stop mode

During stop mode, serial input and output operation halts and any transfer is aborted, as shown inFigure 12.8-5 . After stop mode has been released, a transfer destination error occurs becauseoperation is resumed halfway. Execute re-initialization.

Figure 12.8-5 Operation in stop mode (external shift clock)

#0 #1 #2 #3 #4 #0 #1

SCK1 pin output

SST bit

SIOF bit

SO1 pin output #5

RestartOperation stop

SDR1 register reset

#0 #1 #2 #3 #4 #5 #6 #7

SCK1 pin input

SST bit

SIOF bit

SO1 pin output


Sleep

Sleep mode release via IRQB

Next data clock

Clearing by progaram

Interrupt request

#0 #1 #2 #3 #4 #5 #6 #7

SCK1 pin input

SST bit

SIOF bit

SO1 pin output

STP bit(STBC register) Stop mode release via external interrupt

Interrupt request

Clearing by program

Transfer error occurrence

oscillation stabilization wait time

#6 #7

Next data clock

Stop mode request

Stop, Clock mode

299


8-bit serial I/O operation at issuance of stop request during operation

If operation is halted (SMR1:SST=0) while a transfer is in progress as shown in Figure 12.8-6 , thetransfer stops and the shift clock counter is cleared. For this reason, the transfer destination mustalso be initialized. During serial output operation, re-set the SDR1 register before re-starting. Inthis case, when the external clock is input, the SO1 pin output changes.

Figure 12.8-6 Operation when halted while in operation (external shift clock)

#0 #1 #2 #3 #4 #0 #1

SCK1 pin input

SST bit

SIOF bit

SO1 pin output #5

restartSDR register reset

Operation stop #6 #7

Next data clock

300


12.9 Notes on Using 8-Bit Serial I/O

This section provides notes on using the 8-bit serial I/O.

Notes on Using 8-Bit Serial I/O

Error in serial transfer start timing

As initiation of serial transfer using the program (SMR1/SMR2:SST=1) and length of time untilfalling edge (output) or rising edge (input) of the shift clock are not synchronized, so the time untilthe first serial data to be input/output will be delayed by up to 1 cycle of the shift clock that hasbeen set at most.

Malfunction due to noise

During serial data transfer, serial I/O may cause a malfunction if the shift clock signal involvesextra pulses (pulses exceeding the hysteresis width) due to external noise.

Note on setting program

• Writing to serial mode register 1/2 (SMR1/SMR2) and serial data register 1/2 (SDR1/SDR2)should be carried out while serial I/O is suspended (SMR1/SMR2:SST=0).

• When serial I/O transfer is started or enabled (SMR1/SMR2:SST=1), do not change other bitsin the SMR1/SMR2 register.

• If MSB first is set when a shift clock is used in external shift clock input, the highest bit level isoutput as the SO1/SO2 pin output level. If LSB first is set, the lowest bit level is output as theSO1/SO2 pin output level. MSB first and LSB first are set when the external shift clock is input.In this case, however, serial data output must be allowed (SMR1/SMR2:SOE=1) even if serialI/O transfer is stopped (SMR1/SMR2:SST=0).

• The interrupt request flag bit (SMR1/SMR2:SIOF) is not set if serial data transfer completes atthe same time as serial I/O transfer is halted (SMR1/SMR2:SST=0).

• Return from interruption processing is impossible under the status of interruption requestoutput enabled (SIOE=1) while the SIOF bit is "1". Be sure to clear the SIOF bit.

Transfer rate of serial I/O

The serial data output terminal (SO2) of serial I/O is not suitable for high speed transmission as itis Nch open drain output. Care must be taken when used for high speed shift clock.

301


Shift clock idle state

The external shift clock must maintain the H level during the wait time between one 8-bit datatransfer and another (idle state). When the internal shift clock (CKS1, CKS0 = not 11B) is used as

the shift clock output pin (SMR1/SMR2: SCKE = 1), data is output at the H level in the idle state.

Figure 12.9-1 shows shift clock idle state.

Figure 12.9-1 Shift clock idle state

External shift clock

Idle state Idle state Idle state8-bit data transfer 8-bit data transfer

302


12.10 Example of 8-Bit Serial I/O Connection

This shows an example in which two MB89051 series 8-bit I/O ports are connected and used for bi-directional serial I/O.

When Bidirectional Serial I/O Operation is Performed

Figure 12.10-1 Connection example of 8-bit serial I/O (interface in MB89051 series)

SCK1

SI1

SO1

SCK1

SO1

SI1

SIO-A SIO-B

Internal shift clock External shift clock

output input

303


Figure 12.10-2 Bi-directional serial I/O operation

START

Is SIO-Bserial transfer allowance

state?*1

YES

Set Output data

Transfer enable state

Set SI1 pin to Serial data input (input port)

Set SCK1 pin to Shift clockoutputSet SO1 pin to Serial dataoutputSelect Internal shift clockSet transmission data (shift) direction

NO

Serial transfer start(SST=1)

8 - bitTransfer termination

YES SST=0

Serial data transfer

Read Input data

Is next data available?

NO

NO

END

Stop SIO-A operation(SST=0)

SIO-A

START

Set Output data

Set SI1 pin to Serial datainput (input port)

Set SCK1 pin to Shift clock inputSet SO1 pin to Serialdata outputSelect external shift clockSet the same transmission data (shift) direction as SIO-A

Serial transfer enable(SST=1)

8 - bitTransfer termination

YES SST=0

NO

Read Input data

Stop SIO-B operationSST=0

SIO-B

Serial data output via SIO-A

Simultaneous data input via SIO-B

SST: The SST bit is the serial I/O transfer start bit of the serial mode register1 (SMR1).1 : If only the SO1, SI1, and SCK1 pins are connected, there is no method

for directly checking whether SIO-B is in the serial transfer allowance state. For this reason, a timer, etc., must be used to monitor the wait time period that lasts until SIO-B is allowed for transfer via software.2 : If SIO-B is not allowed for serial I/O transfer, data cannot be

transferred correctly even if SIO-A starts serial I/O transfer.3 : When 8-bit data transfer terminates, a interrupt request occurs.

SIO-A SIO-B

YES

Serial data transfer

304


12.11 Program Example for 8-Bit Serial I/O

This section provides program example for 8-bit serial I/O.

Program Example for 8-bit Serial Output


• Outputs the 8-bit serial data (55 H) from the SO pin used by serial I/O and generates an

interrupt when the transfer completes.

• Use the interrupt handler to reset the transfer data and continue output.

• Operates using the internal shift clock and outputs the shift clock from the SCK1 pin.

• Transfer rate and interruption generation cycle if the shift clock is set to 32tinst when the main

clock speed (gear) is highest (1 instruction cycle = 4/FCH) at 12 MHz are shown as follows.

Transfer rate = 12MHz/4/32 = 93.7kbps

Interruption cycle = 4×32×8/12 MHz = 85.33 µs

305



SMR1 EQU 003AH ; Serial mode 1 register address SDR1 EQU 003BH ; Serial data 1 register address SIOF EQU SMR1:7 ; Interupt request flag bit definition SST EQU SMR1:0 ; Serial I/O transfer start bit definition ILR3 EQU 007DH ; Interrupt level setting register address INT_V DSEG ABS ; DATA SEGMENT ORG 0FFE4H IRQB DW WARI ; Interrupt vector setting INT_V ENDS ; -------------- Main program ---------------------------------------------------------------------------------------- CSEG ; CODE SEGMENT ; The stack pointer (SP),etc., are already initialized.

: CLRI ; Interrupt disable CLRB SST ; Serial I/O transfer stop MOV ILR3,#01111111B ; Interrupt level setting (Level 1) MOV SDR1,#55H ; Transfer data (55H) setting

Interrupt request flag clear, Interrupt requestoutput enable, Shift clock output enable (SCK1),Serial data output enable (SO1), 32tinst selection,LSB first

MOV SMR1,#01111000B ;

SETB SST ; Serial I/O transfer start SETI ; Interrupt enable : ; ---------------Interrupt processing routine ------------------------------------------------------------------------WARI CLRB SIOF ; Interrupt request flag clear PUSHW A XCHW A,T ;A,T return PUSHW A MOV SDR1#55H ; Transfer data (55H) resetting SETB SST ; Serial I/O transfer start : User processing : POPW A XCHW A,T ;A,T return POPW A RETI ENDS ; ------------------------------------------------------------------------------------------------------------------------

END

306


Serial input programming example


• Inputs the 8-bit serial data from the SI1 pin used by serial I/O and generates an interrupt whenthe transfer completes.

• Use the interrupt handler to read the transferred data and continue input.

• Operates using the external shift clock, which is input from the SCK1 terminal.

307



DDR3 EQU 000DH SMR1 EQU 0070H ; Serial mode 1 register addressSDR1 EQU 0071H ; Serial data 1 register addressSIOF EQU SMR1:7 ; Interupt request flag bit definition SST EQU SMR1:0 ; Serial I/O transfer start bit definitionILR3 EQU 007DH ; Interrupt level setting register addressINT_V DSEG ABS ; DATA SEGMENT ORG 0FFE4H IRQB DW WARI ; Interrupt vector setting INT_V ENDS ; -------------- Main program --------------------------------------------------------------------------------------- CSEG ; CODE SEGMENT ;

:

MOV DDR3,#00000000B ;Set P34/INT4/SCK1 pin and P32/INT2/SI1 pin to input.

CLRI ; Interrupt disable CLRB SST ; Serial I/O transfer stop MOV ILR3,#01111111B ; Interrupt level setting (Level 1) MOV SMR1,#01001100B ; Interrupt request flag clear, Interrupt request

output enable, Shift clock output enable (SCK1),Serial data output disable (SO1), external clock selection,LSB first

SETB SST ; Serial I/O transfer start SETI ; Interrupt enable : ; -------------- Interrupt processing routine -----------------------------------------------------------------------WARI CLRB SIOF ; Interrupt request flag clear PUSHW A XCHW A,T PUSHW A MOV A,SDR1 ; Read transfer data SETB SST ; Serial I/O transfer enable : User processing : POPW A XCHW A,T POPW A RETI ENDS ; ----------------------------------------------------------------------------------------------------------------------

END

The stack pointer (SP),etc., are already initialized.

308

CHAPTER 13

I2C

This chapter explains the functions and operations of

the I2C bus interface.

13.1 I2C Interface Outline

13.2 I2C Interface Configuration

13.3 I2C Interface Terminal

13.4 I2C Interface Register

13.5 I2C Interface Interruption

13.6 I2C Interface Operation Explanation

13.7 Instructions for use of the I2C interface

13.8 I2C Interface Program Example

309

CHAPTER 13 I2C

13.1 I2C Interface Outline

The I2C interface that supports Phillips’s I2C bus specification provides master/slave transmission and reception, arbitration lost detection, slave address/general call address detection, generation and detection of start/stop conditions, and 5 types of buss error detection.

I2C interface function• Master and slave transmission/reception

• Automatic conversion from master to slave when arbitration lost is detected.

• Comparison between slave and general call addresses

• Detection of data transfer direction

• Generation and detection of start/stop conditions

• Bus error detection

• 32 types of shift clock frequencies can be selected using software.

• Acknowledge bit can be selected using software.

• Generation and detection of acknowledgement bit.

• Transfer of each byte data

• I2C interface input buffer

• Input spike noise can be eliminated to 20 ns.

• I2C interface circuit is built in per channel.

Outline of communication functions using I2C bus

I2C interface has a simple two-way function configured of two wires, namely the serial data line(SDA) and serial clock line (SCL). Open drain or open collector output is required for all devicesconnected to these serial buses. Two wires have two pull-up resistance, and can carry out logicalfunctions.

Each device connected to a bus has a unique address, and address specification for each deviceis possible using software. A simple master and slave relationship always exists betweendevices. The master functions as a master transmitting or receiving device.

It is a full-scale multi-master bus equipped with a collision detection function to prevent damageto data, and a communication adjustment procedure in case the master tries to initiatesimultaneous data transfer. 8-bit two-way serial data can be transferred at a maximum 100 Kbit/s.Any number of ICs can be connected to a bus provided that the capacitance of the bus does notexceed an upper limit of 400pF.

I2C interface can support Phillips I2C bus.

310

CHAPTER 13 I2C

13.2 I2C Interface Configuration

I2C interface is configured of the following 10 blocks.• Clock control block• Start stop condition detection circuit• Start stop condition generation circuit• Arbitration lost detection circuit• Slave address comparison circuit

• I2C bus status register (IBSR)

• I2C bus control register (IBCR)

• I2C clock control register (ICCR)

• I2C address register (IADR)

• I2C data register (IDAR)

311

CHAPTER 13 I2C

Block Diagram of I2C interface

Figure 13.2-1 Block Diagram of I2C interface

Clock control block

This circuit selects and transacts the shift clock of the I2C bus based on the internal clock.

Start stop condition generation circuit

Master starts communication by sending a start condition when the bus is released (when SCLand SDA are H level). Will be start condition when the SDA line is changed from "H" to "L" while

Inte

rnal

Dat

a B

us

SCC

BEIE

MSS

ACK

GCAA

INTE

INT

BER

AL

RSC

LRB

TRX

AAS

GCA

FBT

BB

IBSR

Start stopcondition

generaiton circuit

Counter clock selector 1

Clock selector 2

Clock divider 1

Clock divider 2

Shift clockgeneration

circuit

Error

Sync

StartMaster

ACK enable

GC-ACK enable

Bus busy

Repeat start

Last bit

Transfer/receive

Slave

Arbitration lost detection circuit

SDA line

SCL line

1st byte detection

I2C enable

Start stopcondition

detection circuit

IDAR register

IADR register

Slave addresscomparison circuit

ICCR

EN

CS4

CSL3

CSL2CS1

CS0

IBCR

IBCR

IBSR

Interrupt request

IRQ8

Finish

4 8 16 32 64 128 256 512

5 876

Input buffer select

Peripheral clock

Shift clockedge

general call

DMBP

IBS

Interrupt enable

Transfer completion flag

Clock control

312

CHAPTER 13 I2C

SCL=H. The master can terminate communication by raising the stop condition. Will be stopcondition when the SDA line is changed from "L" to "H" while SCL=H.

Start stop condition detection circuit

This circuit detects start stop condition for data transfer.

Arbitration lost detection circuit

This interface circuit supports the multi-master system. Arbitration lost occurs if a number ofmasters transmit simultaneously. When the SDA line is L-level, if logic level 1 is transferred, it isdefined as arbitration lost, the setting changes to (IBSR:AL=1) and the master becomes a slave.

Slave address comparison circuit

Slave address is sent after start condition is executed. This is a 7-bit length address added by the8th bit, which is the data direction bit (R/W). Only slaves with matching addresses returnacknowledgements.

I2C bus status register (IBSR)

The IBSR register expresses the I2C interface status. This is a read-only register.

I2C bus control register (IBCR)

The IBCR register is used to select the operating mode, and enable or prohibit interruptions,acknowledgements, and general call acknowledgements.

I2C clock control register (ICCR)

The ICCR register is used to enable I2C interface operations and select the shift clock frequency.

I2C address register (IADR)

The IADR register specifies the slave address.

I2C data register (IDAR)

This data register is used for serial transfers, and is transferred from the MSB. The data outputvalue will be "1" during data reception (IBSR: TRX=0).

I2C interface interrupt source

IRQ9: An interruption request is raised by the I2C interface when the bit is enabled (IBCR:BEIE=1, IBCR:INTE=1), a bus error is generated, and data transfer ends.

313

CHAPTER 13 I2C

13.3 I2C Interface Terminal

The I2C interface terminal, block diagram, register, and interruption functions are explained.

Terminals related to the I2C interface

The P53/SDA and P54/SCL terminals are related to the I2C interface.

P53/SDA pin

The P53/SDA terminal functions as an Nch open drain output port (P53), or data input/output

terminal (SDA). When I2C is enabled, the P53/SDA terminal will automatically be a data input/output terminal.

P54/SCL pin

The P54/SCL terminal functions as an Nch open drain output port (P54), or shift clock input/

output terminal (SCL). When I2C is enabled, the P54/SCL terminal will automatically be a shiftclock input/output terminal.

Noise canceller for P53/SDA and P54/SCLExternal signals to the P53/SDA and P54/SCL terminals are filtered before entering the internalinterface circuit. All spikes less than 20 ns are removed by the filter. The noise canceller cannotbe used while the ICCR:DMBP bit is enabled.

Block Diagram of Pins related to I2C interface

Figure 13.3-1 Block Diagram of Pins related to I2C interface

PDR read

PDR write

Output latch

Stop mode (SPL=1)


PinNch

PDR read

Stop mode


Internal Data B

us

from SDA, SCL output

form I2C enable bit

to SDA, SCL input

P53/SDAP54/SCL


314

CHAPTER 13 I2C

13.4 I2C Interface Register

The I2C interface-related registers are shown.

I2C interface register

Figure 13.4-1 I2C interface register

BB ALRSC


0 0 3 4H

Address

00000000B

Initial value

R

GCA FBT

R R R R

LRB TRX AAS

R

IBSR (I2C bus status register)

R R

DMBP ENReserved


0 0 3 6H

Address

0X0XXXXXB

Initial value

R/W

CS1 CS0

R/W R/W R/W R/W

CS4 CS3 CS2

R/W

ICCR (I2C clock control register)

R/W

A5A6


0 0 3 7H

Address

XXXXXXXXB

Initial value

R/W

A1 A0

R/W R/W R/W

A4 A3 A2

R/W

IADR (I2C address register)

R/W R/W

BER SCCBEIE


0 0 3 5H

Address

00011000B

Initial value

R/W

INTE INT

R/W R/W R/W R/W

MSS ACK GCAA

R/W

IBCR (I2C bus control register)

R/W R/W

D7 D5D6


0 0 3 8H

Address

XXXXXXXXB

Initial value

R/W

D1 D0

R/W R/W R/W R/W

D4 D3 D2

R/W

IDAR (I2C data register)

R/W R/W

R/WR

X

: Readable and Writable: Read only: Unused: Undefined

315

CHAPTER 13 I2C

13.4.1 I2C bus status register (IBSR)

The I2C bus status register (IBSR) checks the communication status of each interface.

I2C bus status register (IBSR)

Figure 13.4-2 I2C bus status register (IBSR)

R R RR

LRB


0 0 3 4H

Address

00000000B

Initial value

TRX AAS GCA FBT

R

TRX

0

1

Receive state

AAS

0

1

Addressing detection bit

GCA

0

1

In slave mode, the general call address is not received.

State bit of data transfer

General call address detection bit

FBT

0

1

The received data is a byte other than the first byte when data is received.

1st byte detection bit

RRR

BB RSC AL

The received data is the first dta (address data) when data is received.

In slave mode, the general call address is received.

Transfer state

LRB

0

1

An acknowledge was detected.

Acknowledge stored bit

An acknowledge has not been detected.

BB

0

1

Stop condition is detected.

Bus busy bit

Start condition is detected. (The bus is in use.)

RSC

0

1

Repeated start condition is not detected.

Start condition detection repeatedly bit

Start condition is detected again when the bus is in use.

AL

0 Arbitration lost is not detected.

Arbitration lost detection bit

Arbitration lost is generated while the master is transmitting data or

"1" is written to the IBCR MSS bit when another system is using the

bus.

1

R : Read only: Initial value

316

CHAPTER 13 I2C

Table 13.4-1 Functional explanation of each bit for I2C bus status register (IBSR)

Bit name CPU function

Bit7 BB: Bus busy bit This bit indicates the bus status. It is cleared when a stop condition isdetected, and set when a start condition is detected.

Bit6 RSC: It is a start conditiondetection repeatedly bit.

• This bit detects repeat start conditions. (RSD=1)• If this bit is "0", it indicates that a stop condition was detected, or if it is

"1", it indicates that a start condition has been detected again.• It is cleared under the following status.1) IBCR::"0" is written to the INT bit2) Is not addressed under slave status3) Start condition detected during bus suspension4) Detection of stop condition

Bit5 AL: Arbitration lost detection bit • This bit indicates that arbitration lost is detected.• It is set under the following status.1) When arbitration lost is generated during master transmission.2) When "1" is written to the IBSR:MSS bit while another system is usingthe bus.• It is cleared by writing "0" to the IBCR:INT bit.

Bit4 LRB: Acknowledge stored bit • This bit stores the SDA line value of the 9th clock into data bytetransfer.

• This bit is cleared when an acknowledgement bit is detected. (SDA=L)• This bit is set when an acknowledgement bit is not detected. (SDA=H)• It is cleared by specifying "0" during a start or stop condition.•

Bit3 TRX: State bit of data transfer This bit indicates whether data transfer is under reception mode or transfermode.

Bit2 AAS: Addressing detection bit • This bit indicates that data is set and addressed under slave mode.• It is cleared by specifying "0" during a start or stop condition.

Bit1 GCA: General call addressdetection bit

• When this bit is "1", it indicates that the general call address (00H) wasreceived during slave status.

• It is cleared by specifying "0" during a start or stop condition.

Bit0 FBT: 1st byte detection bit • This bit is set when the 1st byte reception data calling address isdetected.

• It is regularly set for the start condition.• It is set to "1" by detecting the start condition, and is cleared by writing

"0" to the IBCR:INT bit or not being addressed during slave status.

317

CHAPTER 13 I2C

13.4.2 I2C bus control register (IBCR)

The I2C bus control register (IBCR) is used to select the operating mode, and to enable or prohibit interruptions, acknowledgements, and general call acknowledgements.

I2C bus control register (IBCR)

Figure 13.4-3 I2C bus control register (IBCR)

MSS


0 0 3 5H

Address

00011000B

Initial value

ACK INTE INTGCAA

R/W R/W R/WR/WR/W

BEIEBER SCC

R/W R/W R/W

Transfer termination interrupt request flag bit

Data transfer not completed Set to 0

Read WriteINT

0

1

GCAA

0

1

General call address acknowledge generation enable bit

ACK Data acknowledge generation enable bit

Acknowledge is not generated.0

1

BEIE Bus error interrupt request enable bit

Bus error interrupt request output disable0

1

One by data transfer including acknowledge of the ninth clock completed.

No change

INTE Transfer termination interrupt request enable bit

Transfer termination interrupt request output disable

Transfer termination interrupt request output enable

0

1

Acknowledge is generated.

Acknowledge is not generated.

Acknowledge is generated.

MSS Master/slave selection bit

Slave mode selection0

1 Master mode selection

Bus error interrupt request output enable

Bus error Interrupt request bit

No bus error Set to 0

Read WriteBER

0

1 An illegal start or stop condition is detected.

No change

Start condition generation bit

always 0 No change

Read WriteSCC

0

1 Generates repeated start conditionin master mode.

R/W : Readable and Writable: Unused: Initial value

318

CHAPTER 13 I2C

Table 13.4-2 Each bit functional description of I2C bus control register (IBCR) (Continued)


Bit7 BER: Bus error interrupt requestflag bit

• This bit clears bus error interruptions, and also detects bus errors.• It is cleared by writing "0".• There is no change by writing "1", which has no effect on the others

either.• It is set when an incorrect start or stop condition is detected during

data transfer.

• When this bit is set, the I2C interface operation enabling bit (EN) of

the ICCR register will be cleared, the I2C interface will be stopped,and data transfer will be suspended.

Bit6 BEIE: Bus error interrupt requestenable bit

• This bit enables (BEIE=1) or prohibits ((BEIE=0) generation of buserror interruption requests.

• An interruption request is sent to the CPU when this bit is set andBER=1.

Bit5 SCC: It is a start conditiongeneration bit.

• When this bit is set, repeat start condition of the master mode is raised.(SCC=1)

• There is no change by writing "0".• The read-out value for this bit is always "0".Note:• SCC=1 and MSS=0 must not be written simultaneously.• When INT=0 and SCC=1 are set, the "1" written for the SCC bit is

treated as the priority and a start condition is raised.

Bit4 MSS: Master/slave selection bit • This bit selects slave mode (MSS=0) or master mode (MSS=1).• When "0" is specified for this bit, a stop condition is raised, and will

revert to slave mode upon completion of the transfer.• When "1" is specified for this bit, master mode is set, a start condition

is raised, and transfer is started.• It is cleared when arbitration lost is generated during master transfer,

and will revert to slave mode.Note:• SCC=1 and MSS=0 must not be written simultaneously.• When INT=0 and MSS=0 are set, the "0" written for the MSS bit is

treated as the priority, and a stop condition is raised.

Bit3 ACK: Data acknowledgegeneration enable bit

• This bit enables or prohibits acknowledgement bit output for the 9thclock when data is received.

• This bit will be invalid when address data is received during slavestatus. Acknowledgement will also be sent during addressing.

Bit2 GCAA: General call addressacknowledge generation enable bit

This bit sets enabling output of the general call address acknowledgementbit during slave reception.

Bit1 INTE: Transfer terminationinterrupt request enable bit

• This bit enables (INTE=1) or prohibits (INTE=0) interruption whentransfer is terminated.

• When this bit is set and INT is "1", a transfer terminating interruptionrequest is sent to the CPU.

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CHAPTER 13 I2C

Bit0 INT: Transfer terminationinterrupt request flag bit

• This bit clears the data transfer termination interruption request flagand indicates whether or not this interruption is detected.

• Transfer termination interruption request flag is cleared by writing"0".

• There is no change by writing "1".• It is set if the following condition applies when 1-byte transfer

including the acknowledgement bit ends.1) It is in bus master mode.2) It is the addressed slave.3) General call address was received.4) Arbitration lost was generated.5) Raising a start condition was attempted while another system wasusing the bus.• When this bit is "1", the SCL line will be maintained at L-level. When

this bit is set as "0", it is cleared. In this case, the I2C interface releasesthe SCL line, and transfers the following bytes.

• It is cleared to "0" by generating a start or stop condition duringmaster status.

Note:• When INT=0 and SCC=1 are set, the "1" written for the SCC bit is

treated as the priority and a start condition is raised.• When INT=0 and MSS=0 are set, the "0" written for the MSS bit is

treated as the priority, and a stop condition is raised.

Table 13.4-2 Each bit functional description of I2C bus control register (IBCR) (Continued)


320

CHAPTER 13 I2C

13.4.3 I2C clock control register (ICCR)

The I2C clock control register (ICCR) is used to enable I2C operation and select the shift clock frequency.

I2C clock control register (ICCR)

Figure 13.4-4 I2C clock control register (ICCR)

DMBP EN CS4


0 0 3 6H

Address

0X0XXXXXB

Initial value

R/W

Reserved

EN

0

1

Operation disable

CS3 CS1 CS0CS2

R/W R/WR/W R/W R/WR/W

I2C interface operation enabling bit

CS2

0

0

0

0

1

1

1

1

CS1

0

0

1

1

0

0

1

1

CS0

0

1

0

1

0

1

0

1

Divider n

4

8

16

32

64

128

256

512

Clock 2 selection bit

DMBP

0

1

Bypass disable

Divider m bypass bit

CS4

0

0

1

1

CS3

0

1

0

1

Divider m

5

6

7

8

Clock 1 selection bit

Operation enable

Bypass devider mR/W

X


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CHAPTER 13 I2C

Notes on setting the shift clock frequencyThe m, n, and DMBP values need to be known to calculate the shift clock frequency using theFsck formula shown in Table 13.4-3 .

DMBP values cannot be selected when the m value is 5 (ICCR:CS4=CS3=0)and when the nvalue is 4 (ICCR:CS2=CS1=CS0=0). There are no problems with other combinations.

Table 13.4-3 Function explanation for each bit on the I2C clock control register (ICCR)

Bit name Function

Bit7 DMBP: Divider m Bypass bit

• This bit is used to bypass the m divider to raise the shift clock frequency.• When "0" is written, the value selected for CS3 or CS4 will be the m

divider value.• When "1" is written, the m divider will be bypassed. This is the same as

m=1.• While reading, the current set value can be read out.• When "n=4 ", do not set this bit (CS2=CS1=CS0=0).

Bit6 Reserved bit Reserved bit. Be sure to write "0".

Bit5 EN:

I2C interfaceFace operation enable bits

• This bit enables I2C interface operation. (EN= "1")• When this bit is "0", operation is prohibited, and each bit on the IBSR

register and IBCR register (excluding the BER and BEIE bits) is clearedto "0".

• When the IBCR:BER bit is set, this bit will be cleared to "0".

• This bit must be enabled to write into all I2C registers.

Bit4 Bit3

CS4, CS3: Clock 1 selection bits

• This bit sets the shift clock frequency.• Shift clock frequency (Fsck) is set as shown by the following formula.

tinst indicates the instruction cycle. (It is the clock selected for the CS bitwithin the SYCC)When DMBP is "0", m will be selected by CS4 and CS3, and when DMBPis "1", m will be "1".n will be selected by CS2, CS1, and CS0.

Bit2Bit1Bit0

CS2, CS1, CS0: Clock 2 selection bits 2 / t inst

Fsck m n+ 4

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CHAPTER 13 I2C

13.4.4 I2C address register (IADR)

I2C address register (IADR) is used as saving slave address.

I2C address register (IADR)

Figure 13.4-5 I2C address register (IADR)

This register specifies effective slave address only during slave status. The address is 7-bit data,but is sent as 8-bit address data by adding the R/W bit as the last bit from the master.

During slave status, the IDAR register value is compared with the last 7 bits after receiving theaddress data from the master, and used to determine the address.

A5A6


0 0 3 7H

Address

XXXXXXXXB

Initial value

R/W

A1 A0

R/W R/W R/W

A4 A3 A2

R/W

IADR (I2C address register)

R/W R/W

R/W

X

: Readable and Writable: Unused: Undefined

323

CHAPTER 13 I2C

13.4.5 I2C data register (IDAR)

The I2C data register (IDAR) is used to save transmit shift data.

I2C data register (IDAR)

Figure 13.4-6 I2C data register (IDAR)

During master mode, data written to the register is shifted from the priority bit to the SDA line perbit.

The writing side of this register is double buffer, and if the bus is being used (IBSR:BB=1), writtendata is loaded to this 8-bit shift register once the current byte transfer ends. Shift register data isshifted to the SDA line per bit. Writing to this register does not have any effect on the current datatransfer. The same function can also be used for slave mode after determining the address.

When IBCR:INT=1 during data reception (IBSR:TRX=0), received data can be read out from thisregister. The read-out from this register is always "FFH ". However, shift register values can be

read out from the IDAR address during data transfers (IBSR:TRX=1).

D7 D5D6


0 0 3 8H

Address

XXXXXXXXB

Initial value

R/W

D1 D0

R/W R/W R/W R/W

D4 D3 D2

R/W

IDAR (I2C data register)

R/W R/W

R/WX


324

CHAPTER 13 I2C

13.5 I2C Interface Interruption

The I2C interface can raise interruption requests when data transfer ends or if a bus error is generated.

Interrupt at bus error

When the following conditions are met, a bus error is deemed to have occurred, and the I2Cinterface will be stopped. Bus error interruption request flag bit (IBCR:BER) is set to "1".

• Detecting violations of basic regulations on the I2C bus during data transfer (including ACK bit)

• Stop condition detection at master

• Detecting violations of basic regulations on the I2C bus while the bus is idle

• If the SCL line is "L" level when a start condition is generated

• When a re-transmission start condition is detected (IBSR:RSC=1) within the bus master

In this case, if bus error interruption request bit is enabled (IBCR:BETE=1), an interruptionrequest is output to the interruption controller. Clear interruption request by writing "0" to theIBCR:BER bit within the interruption processing routine.

The IBCR:BER bit will be set to "1", if a bus error is generated regardless of the BEIE bit value.

Interruption when data transfer ends

The I2C interface sends to and receives from the SDA line per bit. Each byte of data is fixed at 8bits. When SCL is "L", data can be amended, and when it is "H", the data needs to be stable. 1 bitof data with MSB at the head is transferred per clock pulse. For each byte of data, the SDA line ofthe 9th clock is drawn to "L", and needs to follow the acknowledgement received from thereception device. Thus, nine clock pulses are required for one complete byte of data to betransferred.

In this case, an interruption request is output to the interruption controller (IRQ9) when thetransfer termination interruption bit is enabled (IBCR:INTE=1). Clear interruption request bywriting "0" to the IBCR:INT bit during the interruption processing routine.

The IBCR:INT bit will be set to 1 when data transfer is terminated regardless of the IBCR:INTE bitvalue.

Table for register and vector in relation to I2C interface interruption

The table for register and vector in relation to I2C interface interruption is shown in Table 13.5-1 .

Table 13.5-1 Table for register and vector in relation to I2C interface interruption

Interruptname



IRQ9 ILR3(007D H ) L91(bit3) L90(bit2) FFE8 H FFE9 H

325

CHAPTER 13 I2C

Reference


326

CHAPTER 13 I2C

13.6 I2C Interface Operation Explanation

The I2C interface is an 8-bit data serial interface synchronized with the SCL clock.

I2C bus system

The I2C bus system uses the serial data line (SDA) and serial clock line (SCL) for data transfers.All connected devices need to be open drain or open collector output, and serial data line andserial clock line are used by connection to pull-up resistance.

Each device connected to the bus has a unique address, and can be set up using software. Asimple slave and master relationship always exists between devices, with the master functioningas a master transmitter or master receiver. This is a full-scale multi-master bus equipped withcollision detection function or arbitration function to prevent damage to data in the event that anumber of masters attempt to initiate data transfer simultaneously.

I2C bus protocols The formats required for data transfer are shown in Figure 13.6-1 .

Figure 13.6-1 Data transfer example

The slave address is sent after a start condition (S) is generated. For this address, the 8th bitdata direction bit (R/W) is added to the 7-bit length one. Data transfer is always terminated by thestop condition (P) using the master. However, addressing other slaves is also possible withoutraising a stop condition by repeatedly carrying out start conditions (Sr).

Start condition

When "1" is written to the I2C bus control register (IBCR:MSS) bit while the bus is open (IBSR:

BB=0, IBCR: MSS=0), the I2C interface will adopt a master mode and simultaneously raise a startcondition. As shown in Figure 13.6-1, a start condition will be raised by changing the SD line fromH to L when SCL=H, and this signal notifies the start of communication (hereafter bus busy) tothe bus connection device.

Conditions for raising start conditions are as follows.

• Writing "1" to the IBCR:MSS bit while the bus is not used. (IBCR:MSS=0, IBSR:BB=0,IBCR:INT=0, IBSR: AL=0) After that, IBSR:BB is set to "1", indicating that the bus is busy.

• Writing "1" to the IBCR:SCC bit during interruption status while a bus master (IBCR:MSS=1,IBSR:BB=1, IBCR:INT=1, IBSR: AL=0) This is repeated and a start condition will be raised.

1 1 10 0 1 10 1 1 10 0 1 10

SDA

SCL

Startcondition

7 - bit address 8 - bit addressR/W

Acknowledge bit No Acknowledge

Stopcondition

LSBMSBMSB LSB

327

CHAPTER 13 I2C

Writing "1" to the IBCR:MSS bit and IBCR:SCC bit under conditions other than these two will beignored. If "1" is written to the IBCR:MSS bit while another system is using the bus (during idlestatus), the IBSR:AL bit will be set to "1".

Addressing

Addressing of the master mode

Under master mode, after the start condition is raised, the I2C bus status register (IBSR: BB,

TRX) will be set to "11B", and the I2C data register (IDAR:D7~D1) details will be output from the

upper bit (MSB). This address data is configured of a 7-bit slave address plus the 8th bit wherebythe R/W bit (IDAR:D0) indicates the data transfer direction.

After the address data is sent, when an acknowledgement is received from the slave, bit0

transmission data (IDAR:DO after transmission) will revert and be stored in the I2C bus statusregister (IBSR:TRX). The SDA line of the 9th clock is drawn to "L", and indicates that theacknowledgement bit is received from the reception device.

Addressing slave mode

Under slave mode, after raising a start condition, the I2C bus status register (IBSR: BB, TRX) will

be set to "10B", and transmission data from the master will be received in the I2C data register

(IDAR). After receiving address data, the I2C data register (IDAR) and I2C address register

(IADR) are compared, and if they match, the I2C bus status register (IBSR:AAS) will be set to "1",and an acknowledgement will be sent to the master. After that, reception data bit0 (IDAR:D0 after

reception) will be stored as the I2C bus status register (IBSR:TRX) bit.

Data transferAfter determining the data transfer slave address, data transfers can be sent/received per byte inthe direction dictated per R/W bit sent from the master.

Each byte to be output on the SDA line is fixed at 8 bits. As shown in Figure 13.6-1 , set the SDAline to L-level for receiving device while the acknowledgement clock pulse is output.Acknowledgements can be reported to the sender by stabilizing the SDA line to L-level while thisclock pulse is "H". Data is transferred at 1 clock pulse per bit with MSB at the head. For eachbyte, the SDA line of the 9th clock is drawn to "L", and it must follow the acknowledgementreceived from the receiving device. Thus, nine clock pulses are required for one complete byte ofdata to be transferred.

Acknowledgement (acknowledgement signal)Acknowledgement is transmitted to the 9th clock of the sender data byte transfer from thereceiver.

When data is received, whether an acknowledgement is required can be selected using the I2Cbus control register (IBCR:ACK). When data is sent, acknowledgement from the receiver is stored

on the I2C bus status register (IBSR:LRB).

When a slave is sent after a 1-byte transfer, if acknowledgement is not received from the master

receiver, the I2C bus status register (IBSR: TRX) will be "0", and will adopt a slave receptionmode. By doing this, the master can raise a stop condition or repeat a start condition when aslave releases the SCL line.

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CHAPTER 13 I2C

Stop conditionBus can be released by raising a stop condition, and the master can terminate communications.The master can also raise a start condition continuously (repeat start condition) without raising astop condition.

When SCL is "H", if the SDA line is changed from "L" to "H", a stop condition is raised and thissignal notifies the bus connection device that communications have ended (hereafter bus free)under master mode.

A stop condition will be raised and slave mode adopted by writing 0 to the IBCR: MSS bit underinterruption status (IBCR: MSS=1, IBSR: BB=1, IBCR: INT=1, IBSR: AL=0) while a bus master.

Writing "0" onto the IBCR: MSS bit will be ignored for cases other than the above.

Arbitration (communication enabling procedure)

The I2C interface circuit is a fully-fledged multi-master bus that can connect a number of masters.Arbitration occurs when another master within the system simultaneously transfers data during amaster transfer.

Arbitration is generated with the SDA line when the SCL line is set to "H" level. When one owntransmission data is "1" and the data on the SDA line is "L" level, it is defined that arbitration lostoccurs, data output is turned off, and sets IBSR: AL=1. When IBSR: AL is set to 1, IBCR: MSSand IBSR: TRX will both be 0, and slave reception mode will be adopted.

Reference

As mentioned above, when the bus is used, if attempting to raise a start condition, IBSR: AL will beset to 1. However, IBCR: MSS will be 1.

329

CHAPTER 13 I2C

13.7 Instructions for use of the I2C interface

Instructions for use of the I2C interface are described.

Instructions for use of the I2C interface

Instructions for setting the I2C interface register

• The I2C interface must be enabled before writing the interface to the register (ICCR: EN)

• Transfer is started by setting the master slave selection bit (IBCR: MSS).

Instructions for priorities when next byte transfer, raising start condition, and raising stop condition

compete to write simultaneously.

• Competition between byte transfer and stop condition When IBCR:INT is cleared and 0 iswritten to IBCR:MSS, the MSS bit takes priority, and a stop condition will be raised.

• Competition between next byte transfer and start condition When IBCR:INT is cleared and 1 iswritten to IBCR:SCC, the SCC bit takes priority, and a start condition will be raised.

Instruction for set up using software

• Do not select repeat start condition (IBCR:SCC=1) and slave mode (IBCR:MSS=0)simultaneously.

• Execution cannot return from interrupt processing if interrupt requests are enabled(CNTR:TIE=1) and the interrupt request flag bit (CNTR:TIR) is "1". The IBCR:BER/IBCR:INTbit must be cleared.

• If I2C is not enabled, (ICCR:EN=0), all bits on the bus status register IBSR and bus controlregister IBCR (excluding bus error bit IBCR:BER and bus error enabling bit IBCR:BEIE) will becleared.

330

CHAPTER 13 I2C

13.8 I2C Interface Program Example

I2C interface program examples are introduced.

Master transfer mode program examples


• Transfer rate of 100 Kbit/s

• Set under master transfer mode

• 64H data transmission to the slave with address 19H

The m and n values of the ICCR register that will be the transfer rate (Fsck) of 100 Kbit/s whensource oscillation (FCH) of 12 MHz is used, are shown as follows.

1/t inst =12MHz/2/2=3.0MHz

m is selected by CS4 and CS3 of the ICCR register.

n is selected by CS2, CS1 and CS0 of the ICCR register.

m×n=12MHz/100KHz-8=112(7×8)

ICCR register value (bit0 to bit4) is 01001B.

ICCR:DMBP(bit7) is "0".

2/ t inst 2 (12MHz/2/2)Fsck 100Kbps

M × n + 4 7 × 8 + 4

331

CHAPTER 13 I2C


IBSR EQU 0034H ;I2C bus status register addressIBCR EQU 0035H ;I2C bus control register addressICCR EQU 0036H ;I2C clock control register addressIADR EQU 0037H ;I2C address register IDAR EQU 0038H ;I2C data register EN EQU ICCR:5 ;I2C enable bit definition BER EQU IBCR:7 ; Bus error interrupt request flag bit definitionINT EQU IBCR:0 ; Data transfer termination interruption

request flag bit definition ILR3 EQU 007DH ; Interrupt request setting register address INT_V DSEG ABS ; DATA SEGMENT ORG 0FFE8H IRQ9 DW WARI ; Interrupt vector setting INT_V ENDS ; -------------- Main program -----------------------------------------------------------------------------------

CSEG ; CODE SEGMENT

;

:

CLRI ; Interrupt disable

SETB EN ;I2C manipulation enable

MOV ILR3,#11110111B ; Interrupt level setting (Level 1)MOV ICCR,#031H ;I2C manipulation enable, Shift clock

frequency 100bps selection

The stack pointer (SP),etc., are already initialized.

332

CHAPTER 14Clock Output Function

In this chapter, clock output function and operation are explained.

14.1 Overview of clock output

14.2 Pins of clock output (CLK1, CLK2)

14.3 Clock output registers

333

CHAPTER 14 Clock Output Function

14.1 Overview of clock output

General clock output function of clock output multiplies the source oscillation clock using PLL, and outputs a cyclical waveform.

Clock output functionThe clock output function multiplies source oscillation clock using PLL, and outputs a cyclicalwaveform (with the same frequency as the source oscillation clock). Output terminals are asfollows.

• Divided waveform of source oscillation clock multiplication: CLK1, CLK2

334


14.2 Pins of clock output (CLK1, CLK2)

The clock output (CLK1,CLK2)-related terminals and the block diagram of pins are shown.

Clock output (CLK1, CLK2)-related terminalsThe clock output (CLK1, CLK2)-related terminals are CLK1 and CLK2 terminals.

CLK1:

A waveform with the same frequency as the source oscillation clock (CLK1) is output.

CLK2:

A waveform with double the frequency of the source oscillation clock (CLK2) is output.

Block Diagram of Pins related to clock output

Figure 14.2-1 Block Diagram of Pins related to clock output

Reference

"0" is output during reset.

Pin

Pch

NchStop

CLK1CLK2

CK1E,CK2E

CLK1,CLK2

335


14.3 Clock output registers

Clock output-related registers are shown.

Clock output control register (CKR)

Figure 14.3-1 Clock output control register (CKR)

Table 14.3-1 Function explanation for each bit on the clock output control register (CKR)

Bit name Function

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2

Unused bit • This bit is undefined when it is read.• Must be written "0" for writing.

Bit1 CK2E: Clock 2 output enable bit

• This bit enables output of clock 2 waveform.

Bit0 CK1E: Clock 1 output enable bit

• This bit enables output of clock 1 waveform.


0 0 2 C H

Address

CK1ECK2E XXXXXX00B

Initial value

CK1E

0

1

Clock 1 output enable bit

Clock 1 output disable

Clock 1 output enable

CK2E

0

1

Clock 2 output enable bit

Clock 2 output disable

Clock 2 output enable

R/WR/W

R/W

X


336

CHAPTER 15Pull-up Option

In this chapter, the pull-up option is explained.

15.1 Pull-up option outline

15.2 Pull-up option setting register

337

CHAPTER 15 Pull-up Option

15.1 Pull-up option outline

The pull-up option sets up the pull-up for ports 0, 1, 2, 3, and 4.

Pull-up optionPull-up option enables the terminals of ports 0, 1, 2, 3, and 4 to be pulled up. Set up is possibleper pin by setting up (writing) on the pull-up option register.

When pull-up resistor was selected in the pull-up option setting register, the terminal state in thestop mode (SPL=1) switches to "H" Level (pull-up state), but not to high impedance state.However, it should be noted that the pull-up process during a reset will be disabled and becomesHi-Z.

338


15.2 Pull-up option setting register

The register to set up the pull-up options is shown.

Pull-up option setting register (PURR0,1,2)

Figure 15.2-1 Pull-up option setting register (PURR0,1,2)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0Address Initial value

PURR1 0 0 2 2H 11111111B

R/W

PUR10


PUR11PUR14 PUR13 PUR12PUR17 PUR16 PUR15

PUR12 PUR13PUR10 PUR11

P10 pull-up ON

P10 pull-up OFF

P11 pull-up ON P12 pull-up ON P13 pull-up ON

P11 pull-up OFF P12 pull-up OFF P13 pull-up OFF


P14 pull-up ON

P14 pull-up OFF




PURR0 0 0 2 1H

Address

11111111B

Initial value

R/W

PUR00


PUR02


PUR03PUR00 PUR01

P00 pull-up ON

P00 pull-up OFF




P04 pull-up ON

P04 pull-up OFF




PURR2 0 0 2 3H

Address

111111111B

Initial value

R/W

PUR20


PUR22


PUR23PUR20 PUR21

P20 pull-up ON

P20 pull-up OFF




P24 pull-up ON

P24 pull-up OFF



0

1

0

1

0

1

0

1

0

1

0

1


339


Pull-up option setting register (PURR3,4)

Figure 15.2-2 Pull-up option setting register (PURR3,4)


PURR3 0 0 2 4H

Address

1111111XB

Initial value

R/W

Reserved

Reserved

Reserved Reserved

R/WR/W R/WR/W R/W R/W

PUR32


PUR33PUR31




P34 pull-up ON

P34 pull-up OFF




PURR4 0 0 2 5H

Address

11111111B

Initial value

R/W

PUR40

Reserved Reserved

R/WR/W R/W R/WR/W

PUR42

PUR41PUR44 PUR43 PUR42PUR45

PUR43PUR40 PUR41

P40 pull-up ON

P40 pull-up OFF



0

1

0

1

0

1

0

1

PUR44 PUR45

P44 pull-up ON

P44 pull-up OFF

P45 pull-up ON

P45 pull-up OFF

Set to "1".

Set to "1".Set to "1".

R/W

X


340

CHAPTER 16Flash Memory

In this chapter, the flash memory function and operations are explained.

There are three ways of programming and erasing flash memory as follows:1. Programming and erasing using parallel writer2. Writing and deletion using the serial writer3. Programming and erasing by executing programThis section explains "3 Programming and erasing by executing program"*: Please create a serial writer by yourself.

16.1 Flash memory outline

16.2 Sector configuration for flash memory

16.3 Flash Memory Control Status Register (FMCS)

16.4 Flash memory auto algorithm start-up method

16.5 Check the Execution State of Automatic Algorithm

16.6 Details of Programming/Erasing Flash Memory

16.7 Notes on using Flash memory

341

CHAPTER 16 Flash Memory

16.1 Flash memory outline

Flash memory is located at 8000H to FFFFH on the CPU memory map, and read access

and program access from the CPU are possible in the same way as a mask ROM using the flash memory interface circuit function. Writing to or deletion of flash memory can be carried out by receiving instructions from the CPU via the flash memory interface circuit. Thus, re-writing while mounted is enabled through control of the built-in CPU, and programs and data can be upgraded efficiently.

Features of Flash memory• 32 Kbytes × 8 bits: (16K + 8K + 8K sector) sector configuration

• Automatic algorithm (same as Embedded Algorithm:MBM29LV200)

• Erase pause/restart function

• Detects completion of writing/erasing using data polling or toggle bit functions

• Detects completion of writing/erasing by CPU interrupts

• Interchangeability to JEDEC normalized form command

• Sector erase function (any combination of sectors)

• Programming/erase count 10,000 (min.)

Embedded Algorithm TM is a registered trademark of Advanced Micro Devices, Inc.

How to program and erase flash memoryProgramming and erasing flash memory cannot be performed at one time. In other words, whendata is written to or deleted from the flash memory, writing is possible without accessing theprogram from the flash memory by copying the program on the flash memory once and runningthe RAM.

Register of Flash memory

Table 16.1-1 Flash Memory Control Status Register (FMCS)

Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

002E H INTE RDYINT WE RDY Reserved Reserved - Reserved

Read/Write (R/W) (R/W) (R/W) (R) (R/W) (R/W) (-) (R/W)

Initial value (0) (0) (0) (X) (0) (0) (-) (0)

342


16.2 Sector configuration for flash memory

The sector configuration of the flash memory is shown in Table 16.2-1 . The upper and lower addresses of each sector are given in the figure.

Sector configurationAddresses supporting sectors for access using the CPU and flash writers are shown as sectorconfigurations for the flash memory in Table 16.2-1 .

*: Writer address

Flash memory writer address indicates the address equivalent to the CPU address when data iswritten to the flash memory using a parallel writer. When writing or deletion is carried out using ageneral-purpose writer, execute writing or deletion based on this address.

Table 16.2-1 Sector configuration for flash memory

Flash memory CPU Address Writer Address *

16K Byte FFFFH to C000H 1FFFFH to 1C000H

8K Byte BFFFH to A000H 1BFFFH to 1A000H

8K Byte 9FFFH to 8000H 19FFFH to

343


16.3 Flash Memory Control Status Register (FMCS)

The control status register (FMCS) is the register placed on the flash memory interface circuit, and is used to write and delete flash memory.

Control status register (FMCS)

Figure 16.3-1 Control status register (FMCS)

RDY

INTE

Reserved Reserved Reserved


0 0 2 EH

Address

000X00X0B

Initial value

R/W R/W R/W R R/W R/WR/W

RDYINT RDY

ReadDY bit(for enabling data to be written into/erased from flash memory)

Data is being written or erased.

Data writing/erasing has been completed. (Subsequent data can be written/erased.)

Reserved Reserved bit

Reserved bit for testing. "0" must be set for regular use.

INTE WE

0

Unused bit

"0" must be set for regular use.0

Reserved Reserved bit

Reserved bit for testing. "0" must be set for regular use.0

0

1

WE Write enable bit

Flash memory write/erase disable

Flash memory write/erase enable

0

1

Bit causing an interrupt to the CPU to be generated

Disables an interrupt when data writing/erasing is completed.

Enables an interrupt when data writing/erasing is completed.

0

1

RDYINT Flash memory operation state indication bit

Data is being written/erased.

Data writing/erasing has been completed. (An interrupt request is generated.)

0

1

R/WR

: Readable and Writable: Read only: Unused: Initial value

344


Note

The RDYINT bit and RDY bit are not changed simultaneously. A program should be created so thatthe decision will be made by one of the bits.

Table 16.3-1 Function explanation for each bit on the control status register (FMCS)

Bit name Function

Bit7 INTE: INTERRPUT Enable

Bit causing an interrupt to the CPU to be generated when writing into or erasing fromflash memory is completed. When the INTE bit is "1" and the RDYINT bit is "1", interruption to the CPU will begenerated. When the INTE bit is "0", no interruption will be generated.

Bit6 RDYINT: READY INTERRUPT

This bit expresses the operating status of the flash memory.It will be "1" when writing or deletion of the flash memory ends. After writing ordeletion of the flash memory, while this bit is "0", further writing or deletion of theflash memory is impossible. When it is "1", after finishing writing or deletion, furtherwriting or deletion of the flash memory is possible.It will be cleared to "0" by writing "0", and writing "1" will be ignored. 1 will be setonce the flash memory auto algorithm (Refer to "16.4 Flash memory auto algorithmstart-up method".) ends. When the Read Modify Write (RMW) command is used, "1"can always be read.

Bit5 WE: WRITE ENABLE

This is the write enable bit for the flash memory area.When this bit is 1, any writing after issuing a command sequence to 1000H to FFFFH

(Refer to "16.4 Flash memory auto algorithm start-up method". ) will be written to theflash memory area. When this bit is "0", no writing or deletion signal will begenerated. This bit is used when activating a writing or deletion command on the flashmemory.Setting "0" regularly when writing or deletion is not performed to prevent data beingwritten to the flash memory by mistake.

Bit4 RDY: READY

This bit permits writing to or deletion from the flash memory.While this bit is "0", writing to or deletion from the flash memory is impossible. Readand reset commands, and suspend commands, such as suspending sector deletions,can be accepted under this status.

Bit3,Bit2

Reserved bit Reserved bit for testing. "0" must be set for regular use.

Bit1 Unused bit "0" must be set for regular use.

Bit0 Reserved bit Reserved bit for testing. "0" must be set for regular use.

Auto algorithmstop timing

RDYINT bit

RDY bit

1 machine cycle

345


16.4 Flash memory auto algorithm start-up method

There are four commands that start up automatic flash memory algorithms, namely read, reset, write, and delete chip. Suspend and re-start can be controlled for sector deletion.

Command Sequence TableTable 16.4-1 list the commands used in programming/erasing flash memory.

Table 16.4-1 Command Sequence Table

Com

mand

Sequence

Bus W

rite Cycle

First busWrite Cycle

2nd busWrite Cycle

3rd busWrite Cycle

4th busWrite Cycle

5th busWrite Cycle

6th busWrite Cycle

Address Data Address Data Address Data Address Data Address Data Address Data

Read/

Reset * 1 XXXX F0 - - - - - - - - - -

Read/

Reset * 3 AAAA AA 5554 55 AAAA F0 RA RD - - - -

Programmingprogram

3 AAAA AA 5554 55 AAAA A0 PA PD - - - -

Chiperase

6 AAAA AA 5554 55 AAAA 80 AAAA AA 5554 55 AAAA 10

Sectorerase

6 AAAA AA 5554 55 AAAA 80 AAAA AA 5554 55 SA 30

Sector Erasing being Suspended (Sector not being Erased)Sector deletion is suspended by inputting Address"XXXX "Data (B0H)

Resume (Sector being Erased)After sector deletion is suspended, deletion is re-started by inputting Address"XXXX "Data (30H)

Note: Addresses in the table are the values in the CPU memory map. All addresses and data are expressed as hexadecimals. However, "X"is any value.RA: Read addressPA: writing addressSA: See "16.2 Sector configuration for flash memory".RD: Read dataPD: Write data*: Two kinds of read/reset commands can reset flash memory to the read mode.

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16.5 Check the Execution State of Automatic Algorithm

Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm can check operation status of built-in flash memory using the following hardware sequence.

Hardware sequence flagHardware sequence flags are configured of 5 output bits, namely DQ7, DQ6, DQ5, DQ3, andDQ2. Each of them has data pouring flag (DQ7), toggle bit flag (DQ6), timing limit excess flag(DQ5), sector deletion timer flag (DQ3), and toggle bit flag 2 (DQ2) functions. Writing/terminatingchip sector deletion, and whether deletion code rights are valid can be checked using this.

In order to refer to the hardware sequence flag, read access the targeted sector address withinthe flash memory after setting up the command sequence (Table 16.4-1 Command sequencetable). Table 16.5-1 shows the bit allocation of hardware sequence flags.

For decisions on whether or not auto writing or chip sector deletion are being executed, whetheror not the writing has ended can be confirmed by checking the hardware sequence flag or theRDY bit on the flash memory control register (FMCS). After writing or deletion ends, it returns tothe read/reset status. When programs are actually created, the next process, such as readingdata, should be carried out after confirming that auto writing or deletion has ended by using oneof the flags. Whether or not the second or later sector deletion code rights are valid can bechecked using the hardware sequence flag. Explanation of hardware sequence flag. Table 16.5-2lists the functions of the hardware sequence flag.

Table 16.5-1 Bit Allocation of Hardware Sequence Flags

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 DQ2 - -

Table 16.5-2 List of Hardware sequence flag function (Continued)

State DQ7 DQ6 DQ5 DQ3 DQ2

Duringexecution

Automatic Programming operation Toggle 0 0 1

Writing or deletion during auto deletion 0 Toggle 0 1 Toggle

Erasetemporarystop

Read (Sector being erased) 1 1 0 0 Toggle

Reading (sectors that were not deleted) DATA DATA DATA DATA DATA

Writing (sectors that were not deleted) Toggle 0 0 1 *1

Time limitexceeded

Automatic Programming operation Toggle 1 0 1

Writing or deletion during auto deletion 0 Toggle 1 1 *2

*1: During writing suspension of deletion, DQ2 outputs logic "1" to reading of the address with the writing. However, DQ2operates toggles to continuous reading from the sector whose deletion is suspended.*2: When DQ5 is "1" (time limit excess), DQ2 operates toggles to continuous reading of the sector during writing ordeletion, and does not toggle to read other sectors.

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16.5.1 Data polling flag (DQ7)

The data pouring flag advises that the auto algorithm is being executing or end status using the data pouring function.

At automatic programming operationWhile the auto writing algorithm is executing, if read access is carried out, flash memory outputsreverse data of the data that was written last (bit 7) regardless of the indicated address. If readaccess is carried out when the auto writing algorithm ends, the flash memory outputs the readvalue of "bit 7" for the indicated address.

During auto deletionWhile executing the auto deletion algorithm, if read access is carried out, the flash memoryoutputs "0" regardless of the indicated address. In the same way, "1" is output when it ends.

Sector Erasing being SuspendedWhile sector deletion is suspended, when read access is carried out, the flash memory outputs"1" if the indicated address is the sector during deletion, or bit 7 (DATA:7) of the read value of theindicated address if it is not the sector being deleted. By referring to it together with the toggle bitflag, a decision can be made as to whether or not the sector is currently suspended, and whichsector is being deleted.

Note

When the auto algorithm operation approaches the end, bit7 (data pouring) will be changedasynchronously during reading. This indicates that the flash memory sends information about itsoperating status to bit7, and sends the defined data to the next one. When the flash memoryterminates the auto algorithm, or even when bit7 outputs defined data, other bits are still undefined.Defined data of other bits are read by executing continuous reading.

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16.5.2 Toggle bit flag (DQ6)

The toggle bit flag mainly notifies that the auto algorithm is executing or ending using the toggle bit function, in the same way as the data pouring flag.

During auto writing or deletionWhile the auto writing or deletion algorithm is executed, if read access is carried out continuously,the flash memory outputs a toggle status of "1" and "0" alternately per read regardless of theindicated address. When the auto writing and deletion algorithm ends, if read access is carriedout continuously, the flash memory stops the toggle operation of bit6, and outputs bit6 (DATA: 6)of the read value of the indicated address. Toggle bit is validated after the last writing cycle ofeach command sequence.

Sector Erasing being SuspendedWhile sector deletion is suspended, when read access is carried out, the flash memory outputs"1" if the indicated address belongs to the sector during deletion. If it does not belong to thesector during deletion, bit6 (DATA:6) of the read value of the indicated address is output.

Note

• When writing, if the sector in which writing is attempted is protected from re-writing, after toggleoperation is carried out for about 2µs, the toggle operation ends without re-writing the data.

• When deleting, if all selected sectors are protected from re-writing, the toggle bit carries out toggleoperation for about 100µs, and after that, returns to read/reset status without re-writing the data.

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16.5.3 Timing limit over flag (DQ5)

The timing limit excess flag notifies that execution of the auto algorithm has exceeded the prescribed time (the number of internal pulses) within the flash memory.

During auto writing or deletionBit5 indicates that execution of the auto algorithm has exceeded the prescribed time (the numberof internal pulses) within the flash memory. Bit5 outputs "1" under this status. In other words,when this flag outputs "1" while the auto algorithm is operating, it indicates that writing or deletionhas failed.

Bit5 will also indicate failure if attempting to write to non-blank areas without prior deletion. In thiscase, defined data cannot be read from bit7 (data pouring), and bit6 (toggle bit) will continuouslytoggle. "1" will be output to bit5 if the time limit is exceeded under this status. Please note that thisindicates that the flash memory was not used correctly rather than any defect with the flashmemory. If this status is generated, execute the reset command.

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16.5.4 Sector erasing timer flag (DQ3)

The sector deletion timer flag notifies whether or not the sector deletion waiting period is operative after starting up the sector deletion command.

In the sector erase operationAfter the first sector deletion command sequence is executed, the waiting period for sectordeletion is indicated. Bit3 outputs "0" during this period, or "1" if the waiting period for sectordeletion has been exceeded. The data pouring and toggle bits are validated after executing thefirst sector deletion command sequence.

When the deletion algorithm is shown during execution using the data pouring or toggle bitfunctions, if this flag is 1, internal controlled deletion has started, and continuous writingcommands will be ignored until the same data pouring or toggle bit indicates the end of suchdeletion. Input of deletion suspension code only is accepted.

When this flag is "0", the flash memory accepts writing of additional sector deletion code. In orderto confirm this, the use of software to check the status of this flag prior to writing continuoussector deletion code is recommended. If "1" is shown at the 2nd status check, the additionalsector deletion code may not have been accepted.

When reading is carried out while sector deletion is suspended, the flash memory outputs "1" ifthe address indicated by the address signal belongs to the sector during deletion. If it does notbelong to the sector during deletion, the read value "bit3" of the address indicated by the addresssignal is output.

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16.5.5 Toggle bit 2 flag (DQ2)

The toggle bit2 flag detects whether auto deletion or suspension of deletion is operative in addition to the toggle bit.

In the sector erase operationThis toggle bit is used to detect whether the flash memory is in auto deletion or suspension ofdeletion status in addition to the toggle bit of bit6. Bit2 operates the toggle when continuouslyreading from the sectors that have been deleted during auto deletion. If the flash memory is underdeletion suspension reading mode, bit2 operates the toggle by continuously reading from thesector in which deletion is suspended.

If the flash memory is under deletion suspension reading mode, "1" is read by bit2 bycontinuously reading from the sector in which deletion is not suspended. Bit6 operates the toggleduring normal writing or deletion, or while deletion is suspended in a different manner from bit2.

For example, bit2 and bit6 are used together to detect deletion suspension reading mode (bit2operates the toggle, whereas bit6 does not).

Bit2 is also used to detect the deleted sectors. When the flash memory is being deleted, bit2operates the toggle if reading from the deleted sector.

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16.6 Details of Programming/Erasing Flash Memory

The procedures for issuing commands to the flash memory that starts up the auto algorithm, and operations for reading/re-setting, writing, chip deletion, sector deletion, suspension of sector deletion, and re-starting sector deletion, are explained.

Details of Programming/Erasing Flash MemoryThe flash memory can execute auto algorithm when the operations for reading/resetting, writing,chip deletion, sector deletion, suspension of sector deletion, and re-starting deletion implementthe writing cycle to the command sequence buses (Table 1.4-1 Command sequence table). Thewriting cycle to each bus must be carried out continuously. The end timing of the auto algorithmcan also be confirmed using the data pouring function. After normal termination, it returns to theread/reset state.

Each operation is described in the following order from the next section.

16.6.1 Flash memory reading/reset status

16.6.2 Writing data to the flash memory:

16.6.3 All data deletion of flash memory (chip deletion)

16.6.4 Arbitrary data deletion of flash memory (sector deletion)

16.6.5 Suspending sector deletion of flash memory:

16.6.6 Resumption of Flash memory sector erase

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16.6.1 Flash memory reading/reset status

The procedure for issuing the Read/Reset command to set the flash memory to the read/reset state is explained.

Flash memory reading/reset statusIn order to set the flash memory to reading/reset status, continuously send read/reset commandsin the command sequence table ("Table 16.4-1 Command sequence table") to the targeted sectorwithin the flash memory.

In terms of the read/reset commands, there are two types of command sequence whichimplement the bus operation either once or thrice, but there is no essential difference betweenthem.

The read/reset status is the initial status of the flash memory, and when the power is turned on, orwhen commands end normally, the read/reset status is always shown. The read/reset statusindicates a waiting status for input from other commands.

Under the read/reset status, data can be read using standard read access. Program access fromthe CPU is possible in the same way as a mask ROM. This command is not required to readordinary data. This command is mainly used to initialize auto algorithms, for example, whencommands do not end normally for some reason.

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16.6.2 Programming of Flash memory

Procedures for issuing writing commands and writing data to the flash memory are explained. Figure 16.6-1 shows procedure example for writing to flash memory.

Programming of Flash memoryContinuously sending writing commands in the command sequence table ("Table 16.4-1Command sequence table") to the targeted sector within the flash memory activates the datawriting auto algorithm for flash memory. Auto algorithm is activated and auto writing is startedwhen writing data to the targeted address ends in the 4th cycle.

How to specify addressWriting is possible in any address order, or even beyond the order of the sector, but only 1 byte ofdata can be written using writing commands at a time.

Notes on data programmingWhen data 1 is written to data 0, the data pouring algorithm (DQ7) or toggle operation (DQ6)does not end, and the flash memory element is deemed to be defective, the specified writing timeis exceeded and a timing limit excess flag (DQ6) will determine an error, or it will appear asthough data 1 has been written. However, data is read under read/reset status, and the dataremains as "0". Data 0 can be changed to "1" only by deletion.

All commands are ignored while auto writing is executing. When hardware reset is activatedduring writing, care must be taken as the data of the address to which writing is carried out is notprotected.

Programming procedure of Flash memoryA procedure example for writing to the flash memory is shown in Figure 16.6-1 . The status of theauto algorithm within the flash memory can be determined using the hardware sequence flag(refer to "1.5 Confirming the auto algorithm execution status"). Data polling flag (DQ7) is used toconfirm an end of writing.

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Figure 16.6-1 Procedure example for writing to flash memory:

Data is read from the address to which writing was last carried out to check the flag.

Data pouring flag (DQ7) is changed simultaneously with the timing limit excess flag (DQ5), soeven if the timing limit excess flag (DQ5) is 1, the data pouring flag bit (DQ7) needs to be re-checked.

In the same way, for the toggle bit flag (DQ6), toggle operation is stopped at the same time thatthe timing limit excess flag bit (DQ5) is changed to "1", so the toggle bit flag (DQ6) needs to bere-checked.

FMCS:WE(bit5)

Flash memory write enable

Writing command sequenceAAAA AA5554 55AAAA A0Writing address Writing data

Data polling (DQ7)

Data polling (DQ7)

Internal address read

Internal address read

Timing limit (DQ5)

FMCS:WE(bit5)Flash memory writing disable

End address

Next address

Writing start

Writing completion

Writing error

Data

Data

Data

0

1

Data

Check byHardware sequence flag

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16.6.3 All data deletion of flash memory (chip deletion)

Procedures for issuing chip deletion commands, and deleting all data on the flash memory are explained.

All data deletion of flash memory (chip deletion)All flash memory data can be deleted by continuously sending the chip deletion commands in thecommand sequence table ("Table 16.4-1 Command sequence table") to the targeted sectorwithin the flash memory.

Chip deletion commands are carried out by 6 bus operations. Chip deletion is started whenwriting at the 6th cycle is completed. Before chip erasing, the user need not perform programmingto flash memory. While the auto deletion algorithm is executing, flash memory writes "0" andverifies before automatically deleting all cells.

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16.6.4 Arbitrary data deletion of flash memory (sector deletion)

Procedures for issuing the sector deletion command and arbitrary sector deletion of flash memory are explained. Deletion per sector is possible, and simultaneous specification of a number of sectors is also possible.

Arbitrary data deletion of flash memory (sector deletion)Arbitrary flash memory sectors can be deleted by continuously sending the sector deletioncommands in the command sequence table ("Table 1.4-1 Command sequence table") to thetargeted sector within the flash memory.

How to specify sectorThe sector erase command is executed in six bus operations. Waiting for sector deletion for 50µsis started by writing the sector deletion code (30h) to an arbitrary even-numbered address thatcan be accessed within the targeted sector at the 6th cycle. When a number of sectors aredeleted, write the deletion code (30h) to the address within the sector to be deleted followed bythe above process.

Instructions for specifying a number of sectorsDeletion is started by ending the 50µs sector deletion waiting period from the final writing of thesector deletion code. In other words, in order to delete a number of sectors simultaneously, thefollowing deletion sector address and deletion code (6th cycle of the command sequence) needsto be input within 50µs, and may not be accepted after that period. Whether or not continuedsector deletion code writing is valid can be checked using the sector deletion timer (hardwaresequence flag DQ3). In this case, the address that reads the sector deletion timer should indicatethe sector to be deleted.

Sector erase procedureThe status of the auto algorithm within the flash memory can be determined using the hardwaresequence flag (refer to "1.5 Confirming the auto algorithm execution status"). Procedure examplefor deleting the flash memory sector is shown in Figure 16.6-2 . In this example, the toggle bit flag(DQ6) is used to check that erase ends.

With regard to the data to be read to check the flag, the data is read from the sector to bedeleted, so care must be taken.

358

359


Figure 16.6-2 Example of sector deletion procedure

The toggle bit flag (DQ6) terminates toggle operation at the same time that the timing limit excessflag (DQ5) is changed to "1", so even if the timing limit excess flag (DQ5) is 1, the toggle bit flag(DQ6) needs to be re-checked.

The data pouring flag (DQ7) is also changed at the same time as the timing limit excess flag(DQ5), so the data pouring flag (DQ7) must be re-checked.

FMCS:WE(bit5)

Flash memory deletion enable

Deletion command sequenceAAAA AA5554 55AAAA 80AAAA AA5554 (30H)

Internal address read 1


Timing limit (DQ5)

FMCS:WE(bit5)Flash memory deletion disable

End sector

Next sector

Deleting start

Deletion completion

Deletion error

N

Y

Y

0

1

N


(DQ6)Toggle bitdata 1(DQ6)= data 2(DQ6)


toggle bit (DQ6)Data 1(DQ6)=Data 2(DQ6)

Input code to deletion sector (30H)

Another deletion sector

Sector Erase completed?

Y

N

Y

N

Check byHardware sequence flag

Y

N

55


16.6.5 Suspension of Flash memory sector erase

Procedures for issuing sector deletion suspension commands and carrying out suspension of flash memory sector deletion are explained. Data can be read from the sector not being erased.

Suspension of Flash memory sector eraseSector deletion of flash memory can be suspended by continuously sending the sector deletionsuspension commands in the command sequence table ("Table 1.4-1 Command sequence table)to the flash memory.

Sector deletion suspension commands suspend deletion during sector deletion, and enablereading of data from sectors that are not being deleted. Under this status, only reading ispossible; writing is impossible. This command is only valid during sector deletion including thewaiting time for deletion, and is ignored during chip deletion and during writing.

It is implemented by writing deletion suspension code (B0h). In this case, an arbitrary addresswithin the flash memory should be indicated as the address. Commands for re-suspension ofdeletion during suspension of deletion will be ignored.

During the waiting period for sector deletion, if a suspend command for sector deletion is input,waiting for sector deletion is immediately terminated, the deletion operation is suspended anddeletion suspension status starts. During sector deletion following the waiting period for sectordeletion, if a deletion suspension command is input, deletion suspension status starts after amaximum of 15 µs.

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16.6.6 Resumption of Flash memory sector erase

Procedures for issuing sector deletion re-start commands, and re-starting sector deletion of suspended flash memory are explained.

Resumption of Flash memory sector eraseSuspended sector deletion can be re-started by continuously sending the sector deletion re-startcommands in the command sequence table ("Table 1.4-1 Command sequence table") to the flashmemory.

The sector erase resume command resumes sector erasing suspended by the sector erasesuspend command. This command is executed by writing the deletion re-start code (30h), and inthis case, an arbitrary address within the flash memory area should be indicated.

Issuance of sector deletion re-start commands during sector deletion will be ignored.

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16.7 Notes on using Flash memory

Instructions for using MB89F051 regarding flash memory are described as follows.

Hardware reset (RST)If the hardware is reset when auto algorithm is not activated, such as during reading, a minimumof 500 ns should be adopted as the low level width.

If hardware is reset when the auto algorithm is activated, such as during writing or deletion, aminimum of 500 ns should also be adopted as the low level width. In this case, it takes 20 µs untiloperations under execution will end, the flash memory will be initialized, and data reading isenabled.

If hardware is reset during writing, data being written will be undefined. If hardware is reset duringdeletion, the sector being deleted may become unusable, so care must be taken.

Software reset and watchdog timer reset:While normal mode is set for writing or deletion of flash memory, when the memory access modeof the CPU is used under internal ROM mode, if reset factors for them are raised while the autoalgorithm of the flash memory is activated, the CPU may run out of control. Because the flashmemory main unit is not initialized with these reset factors and the auto algorithm continues, as aresult when the CPU begins sequencing after the reset is canceled, the flash memory may notshift to reading status. Care must be taken not to generate these reset factors during reading ordeletion operations on the flash memory.

Program access to flash memoryRead access to the flash memory is not possible while the auto algorithm is active. For example,when the memory access mode of the CPU is used under internal ROM mode, writing or deletionshould be activated after moving the program area to another area, such as the RAM.

In this case, if the sector in which an interruption vector is placed will be deleted, at the very least,such interruption when writing or deletion ends cannot be executed.

For exactly the same reason, other interruptions are prohibited while the auto algorithm is active.

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CHAPTER 17Connection Examples forMB89F051 Serial Writing

In this chapter, connection examples for serial writing using the flash micon programmer made by Yokogawa Digital Computer Corporation are explained.

17.1 Basic configuration for the MB89F051 serial writing connection

17.2 Connection example for serial writing (when user power is used)

17.3 Minimum connection example with the flash micon programmer (when user power is used):

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CHAPTER 17 Connection Examples for MB89F051 Serial Writing

17.1 Basic configuration for the MB89F051 serial writing connection

The MB89F051 supports the serial on-board programming of flash ROM (Fujitsu standard). The specification for serial on-board programming are explained below.

Basic configuration for the MB89F051 serial writing connectionThe flash microcontroller programmer made by Yokogawa Digital Computer Corporation is usedfor Fujitsu standard serial on-board programming.

The basic configuration for the MB89F051 serial writing connection is shown in Figure 17.1-1 .

Figure 17.1-1 Basic configuration for the MB89F051 serial writing connection

Note

Please inquire directly to Yokogawa Digital Computer Corporation about the functions and operatingmethods of their flash micon programmers (AF220, AF210, AF120, AF110), and general-purposecommon connection cable (AZ210) and connector.

RS232C

Host interface cable (AZ221)

CLKsynchronous serial

General-purpose common cable (AZ210)

MB89F051User system

Operable in stand-alone mode

Flash miconprogrammer

+Memory card

364


Pins Used for Fujitsu Standard Serial On-board Programming

The control circuit shown in Figure 17.1-2 is required when the SI1, SO1, and SCK1 terminals arealso used for the user system. (The user circuit can be cut off during serial writing using the TICSsignal of the flash micon programmer. Refer to the connection examples.)

Figure 17.1-2 Control circuit

Oscillation Clock Frequency and Serial Clock Input Frequency

The MB89F051 serial clock frequency that can be input can be calculated using the followingformula. Accordingly, change the serial clock input frequency by setting up a flash miconprogrammer in accordance with the oscillation clock frequency used.

Imputable serial clock frequency = 0.125 x oscillation clock frequency.

Table 17.1-1 Pins Used for Fujitsu Standard Serial On-board Programming

Pin Function Supplementary Information

MOD2,MOD1, MOD0,P23,P22

Mode Pin Serial writing mode is adopted by setting MOD2=0, MOD1=1, MOD0=1,P23=0, P22=1.

X0, X1 Oscillation pins Operation clock within the CPU under terminal serial writing mode foroscillations will be 4 cycles of the oscillation frequency. When serial writing is carried out, an oscillation frequency of 3 MHz ormore needs to be input, so care must be taken.

RST Reset pin -

SI1 Serial data input pin 8-bit serial I/O is used.

SO1 Serial data output pin

SCK1 Serial clock input pin

VCC Supply voltage pin The flash micon programmer does not need to be connected when powerfor writing is supplied from the user system.

VSS GND pin GND pin is common to the ground of the flash microcontrollerprogrammer.

AF220/AF210/AF120/AF110Writing control Pin MB89F051

Writing control Pin

AF220/AF210/AF120/AF110 /TICS pin

10K

User

365


Example;

System configuration for the flash micon programmer (made by Yokogawa Digital Computer

Corporation)

Note

The AF200 flash micon programmer is a retired product, but it can be supported using controlmodule FF201. This serial writing connection example can also be supported by the connectionexamples shown in the next section.

Oscillation clockfrequency (FC)

Internal main clockfrequency (FCH)

Maximum serialclock frequencyacceptable to themicrocontroller

Maximum serialclock frequency thatcan be set with theAF220, AF210,AF120, or AF110

Maximum serialclock frequency thatcan be set with theAF200

in 6MHz in 12MHz 1.5MHz 1.5MHz 500kHz

Table 17.1-2 System configuration for the flash micon programmer (made by Yokogawa Digital Computer Corporation)

Model Function

Unit AF220/AC4P Built-in Ethernet interface model/100 V to 220 V power adapter

AF210/AC4P Standard model/100 V to 220 V power adapter

AF120/AC4P Built-in single key Ethernet interface model/100 V to 220 V power adapter

AF110/AC4P Single key model/100 V to 220 V power adapter

AZ221 PC/AT RS232C cable for writer

AZ210 Standard target probe (a) length: 1 m

FF201 Control module for Fujitsu F2MC-16LX flash microcontroller

AZ290 Remote controller

/P2 2MB PC Card (Option) Flash memory corresponding Max. 128KB

/P4 4MB PC Card (Option) Flash memory corresponding Max. 512KB

Contact for inquiries: Yokogawa Digital Corporation Tel: 042-333-6224

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17.2 Connection example for serial writing (when user power is used)

Connection example for serial writing (when user power is used): MOD1, MOD0 = 11 is input to the mode terminals that are set to MOD2, MOD1, MOD0 = 000 on user systems from TAUX3 of AF220/AF210/AF120/AF110, and will be serial writing mode (serial writing mode; MOD2, MOD1, MOD0=011).

Connection example for serial writing (when user power is used)Connection example for serial writing (when user power is used) is shown in Figure 17.2-1 .

Figure 17.2-1 MB89F051 serial writing connection example (when user power is used)

AF220/AF210/AF120/AF110Flash miconprogrammer

TAUX3

TTXD

TRXD

TCK

/TICS

/TRES

TVCC VCC

VSSGND

3,4,9,11,12,16,17,18,20,23,24,25,26pins are OPEN

DX10-28S: right-angle type

DX10-28S

14 pin

28 pin

1 pin

15 pin

(7,8,14,15,21,22,1,28)

(2)

(5)

(10)

(6)

(27)

(13)

(19)

User systemconnectorDX10-28S

10 k

10 k

RST

SCK1

SO1

SI1

X0

X1

P22

MOD2

MOD1

MOD0

P23

MB89F051

User

User

User power

Connector (made by Hirose Electric) pin layout

10 k

10 k

10 k

10 kP10

367


Note

Power supply voltage when user power is used shall be 3.3V ± 10%, as the direct current standardfor the SI1, SO1, and SCK1 terminals of the 8-bit serial I/O supports 3V.

When SI1 and SO1 terminals are also used for the user system, a control circuit as per thefollowing figure is required in the same way as for the SCK1 terminal. (The user circuit can be cutoff during serial writing using the TICS signal of the flash micon programmer.)


Connect the AF220/AF210/AF120/AF110 while the user power is off.

AF220/AF210/AF120/AF110Writing control pin MB89F051

Writing control pin


10 k

User

368


17.3 Minimum connection example with the flash micon programmer (when user power is used):

If each terminal (MOD1, MOD0) is set up as shown in Figure 17.3-1 for serial writing, MOD1/MOD0 and the flash micon programmer do not need to be connected.

Minimum connection example with the flash micon programmer (when user power is used):

Minimum connection example with flash micon programmer (when user power is used) is shownin Figure 17.3-1 .

Figure 17.3-1 MB89F051 Minimum connection example with the flash micon programmer (when user power is used):

AF220/AF210/AF120/AF110Flash miconprogrammer

TTXD

TRXD

TCK

/TRES

TVCC VCC

VSSGND

3,4,9,10,11,12,16,17,18,19,20,23,24,25,26pins are OPEN

DX10-28S: right angle-type

DX10-28S

14 pin

28 pin

1 pin

15 pin

(7,8,14,15,21,22,1,28)

(2)

(5)

(6)

(27)

(13)

User system

ConnectorDX10-28S

10K

10K

10K

10K

10K

10K

RST

SCK1

SO1

SI1

X0

X1

P22

MOD2

MOD1

MOD0

P23

MB89F051

User power

connector (made by Hirose electric) pin layout

When 1, serial programming

When 1, serial programming

10K

P1010K

369


Note

Power supply voltage when user power is used shall be 3.3V ± 10, as the direct current standard forthe SI1, SO1, and SCK1 terminals of the 8-bit serial I/O supports 3V.

When the SI1, SO1, and SCK1 terminals are also used for the user system, a control circuit asper the following figure is required. (The user circuit can be cut off during serial writing using theTICS signal of the flash micon programmer.)


Connect the AF220/AF210/AF120/AF110 while the user power is off.

AF220/AF210/AF120/AF110Writing control pin MB89F051

Writing control pin


10K

User

370

APPENDIX

I/O map and command list, etc. are described in this section.

APPENDIX A I/O Map

APPENDIX B Overview of Instructions

APPENDIX C MB89051series pin status

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APPENDIX

APPENDIX A I/O Map

The address shown in the attached Table A-1 is allocated to each register of the peripheral functions built into the MB89051 series.

I/O Map

Table A-1 I/O Map

Address Registerabbreviation

Register Name Read/Write Initial value

0000H PDR0 Port 0 data register R/W XXXXXXXXB

0001H DDR0 Port 0 data direction register W 00000000B


0003H DDR1 Port 1 direction register W 00000000B

0004H PDR2 Port 2 data register R/W 00000000B

0005H Reserved

0006H DDR2 Port 2 direction register R/W 00000000B

0007H SYCC System clock control register R/W XXX11X00B

0008H STBC Standby control register R/W 0001XXXXB

0009H WDTC Watchdog control register R/W XXXXXXXX

000AH TBTC Time-base timer control register R/W 00XXX000B

000BH Vacancy

000CH PDR3/ USBP Port 3 data register/Pull-up control for USB R/W XXXXXXXXB

000DH DDR3/USBPC Port 3 direction register/Pull-up control for USB R/W 00000000B

000EH Reserved

000FH Vacancy


0011H DDR4 Port 4 direction register R/W 00000000B

0012H PDR5 Port5 data register R/W XXX11XXXB

0013H to0015H

Reserved

0016H to 0020H

Vacancy

0021H PURR0 Port 0 pull-up option setting registers R/W 11111111B



0024H PURR3 Port 3 pull-up option setting registers R/W 1111111XB


372

APPENDIX A I/O Map

0026H Reserved

0027H CNTR1 PWM Control Register 1 R/W 00000000B

0028H CNTR2 PWM Control Register 2 R/W 000X0000B

0029H CNTR3 PWM Control Register 3 R/W X000XXXXB

002AH COMR1 PWM compare register 1 W XXXXXXXXB

002BH COMR2 PWM compare register 2 W XXXXXXXXB

002CH CKR Clock output control register R/W XXXXXX00B

002DH SCS Serial Clock Switching Register R/W XXXXXXX0B

002EH FMCS Flash memory control status register (Only built-in flash memory product)

R, R/W 000X00X0B

002FH SMC1 Serial Mode Control Register 1 R/W 00000000B

0030H SMC2 Serial Mode Control Register 2 R/W 00000000B

0031H SSD Serial Status and Data Register R 00001XXXB

0032H SIDR/SODR Serial input / Serial output data register R/W XXXXXXXXB

0033H SRC Serial Rate Control Register R/W XXXXXXXXB

0034H IBSR I2C bus status register R 00000000B

0035H IBCR I2C bus control register R/W 00011000B

0036H ICCR I2C clock control register R/W 0X0XXXXXB

0037H IADR I2C address register R/W XXXXXXXXB

0038H IDAR I2C data register R/W XXXXXXXXB

0039H Vacancy

003AH SMR1 Serial mode register 1 R/W 00000000B

003BH SDR1 Serial data register 1 R/W XXXXXXXXB

003CH EIE External interrupt control register R/W 00000000B

003DH EIF External interrupt flag register R/W XXXXXXX0B

003EH , 003FH

Vacancy

0040H HMDR USB hub mode register R/W 10XXXXX0B

0041H HDSR1 Hub descriptor register 1 R/W XXXXXXXXB



0044H HSTR Hub status register R/W 00000000B

0045H OCCR Over current register R/W 0XXX0000B

0046H DADR Descriptor ROM Address Register R/W XXXXXXXXB

0047H Reserved

Table A-1 I/O Map



373

APPENDIX

0048H ,

0049H

Vacancy

004AH SMR2 Serial mode register 2 R/W 00000000B

004BH SDR2 Serial data register 2 R/W XXXXXXXXB

004CH ,

004FH

Vacancy

004EH HDSR4 Hub descriptor register 4 R/W 00000101B

004FH Vacancy

0050H UMDR USB Reset Mode Register R/W 1000XX00B

0051H DBAR DMA Base Address Register R/W XXXXXXXXB

0052H TDCR0 Transfer data count registers 0 R/W X0000000B


0054H Reserved


0056H Reserved


0058H UCTR USB control register R/W 00000000B

0059H USTR1 USB status register 1 R/W 00000000B

005AH USTR2 USB status register 2 R XXXXXX00B

005BH UMSKR USB Interruption Mask Register R/W 00000000B

005CH UFRMR1 USB Frame Status Register 1 R XXXXXXXXB

005DH UFRMR2 USB Frame Status Register 2 R XXXXXXXXB

005EH EPER USB end point enable register R/W XXXX0001B

005FH EPBR0 EndPoint 0 Setup Register 0 R/W X0000000B

0060H EPBR11 EndPoint 1 Setup Register 11 R/W XX0000XXB

0061H EPBR12 EndPoint 1 Setup Register 12 R/W X0000000B





0066H Reserved

0067H to 0078H

Vacancy

0079H Reserved

007AH Vacancy

Table A-1 I/O Map



374

APPENDIX A I/O Map

Explanation on read/writeR/W: Readable and Writable

R: Read only

W: Write only

Explanation of initial values0:The initial value of this bit is "0".

1:The initial value of this bit is "1".

X: The initial value of this bit is undefined.

Note

Do not use the reserved and vacancy space.

007BH ILR1 Interrupt level set register 1 W 11111111B

007CH ILR2 Interrupt level set register 2 W 11111111B

007DH ILR3 Interrupt level set register 3 W 11111111B

007EH ILR4 Interrupt level set register 4 W XXXXXX11B

007FH Reserved

Table A-1 I/O Map



375

APPENDIX


Appendix B describes the instructions used by the F2MC-8L.

Description of F2MC-8L instruction

The F2MC-8L has 140 single-byte machine instructions (256 byte map). An instruction codeconsists of the instruction followed by its operand.

Figure B-1 shows the correspondence between the instruction codes and the instruction map.

Figure B-1 Instruction code and instruction map

Instructions are divided into four categories: transfer instructions, arithmetic instructions, branchinstructions, and other instructions.

A range of methods can be used to specify an address. Ten different addressing modes areavailable depending on the instruction and its operand.

Bit manipulation instructions are provided to perform read-modify-write operations.

Instructions that specify special operations exist.

Higher 4 bits

Lower 4 bits

byte

0 to 2 bytes, which are assigned depending on the instruction.

[Instruction map]

Instruction code Machineinstruction Operand Operand

376


Description of instruction presentation items and symbolsThe symbols used as explanations of the command codes, which comprise Appendix B, areexplained.

Table B-1 Explanation on Symbols in the Instruction List

Representation Explanation

Dir Direct address (8 bits)

Off Offset (8 bits)

Ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir:b Bit direct address (8 bits:3 bits)

Rel Branch relative address (8 bits)

@ Register indirect addressing (examples: @A, @IX, @EP)

A Accumulator (8 or 16 bits, which are determined depending on the instruction being used)

AH Higher 8 bits of the accumulator (8 bits)

AL Lower 8 bits of the accumulator (8 bits)

T Temporary accumulator(8 or 16 bits, which are determined depending on the instruction being used)

TH Higher 8 bits of the temporary accumulator (8 bits)

TL Lower 8 bits of the temporary accumulator (8 bits)

IX Index register (16 bits)

EP Extra pointer (16 bits)

PC Program counter (16 bits)

SP Stack pointer (16 bits)

PS Program status (16 bits)

Dr Accumulator or index register (16-bit length)

CCR Condition code register (8 bits)

RP Register bank pointer (5 bits)

Ri General-purpose registers (8-bit, i=0 to 7)

× X is immediate data (8 or 16 bits, which are determined depending on the instruction being used).

(×) The content of X is to be accessed (8 or 16 bits, which are determined depending on the instructionbeing used).

((×)) The address indicated by the X is to be accessed (8 or 16 bits, which are determined depending onthe instruction being used).

377

APPENDIX

B.1 Addressing

The F2MC-8L has the following ten addressing modes.• Direct addressing• Extended addressing• Bit direct addressing• Index addressing• Pointer addressing• General-purpose register addressing• Immediate addressing• Vector addressing• Relative addressing• Inherent addressing

Explanation of addressing

Direct addressing

Direct addressing is indicated by "dir" in the instruction list. This addressing is used to access thearea between "0000H " and "00FFH ". In this addressing mode, the higher byte of the address is

"00H " and the lower byte is specified by the operand.

Figure B.1-1 shows example.

Figure B.1-1 Direct addressing example

Extended addressing

The "ext" addressing in the instruction list can be used to access the entire 64Kbyte area. In thisaddressing mode, the first operand specifies the higher byte of the address, and the secondoperand specifies the lower byte.

Figure B.1-2 shows extended addressing example.

Figure B.1-2 Extended addressing example

MOV 1 2H, A

4 5H 4 5HA0 0 1 2H

1 2 3 4H

MOVW A, 1 2 3 4H

5 6 7 8HA5 6H

7 8H1 2 3 5H

378


Bit direct addressing

Bit direct addressing is indicated by "dir:b" in the instruction list. This addressing is used toaccess a particular bit in the area between "0000H " and "00FFH ". In this addressing mode, the

higher byte of the address is "00H " and the lower byte is specified by the operand. The bit

position at the address is specified by the lower three bits of the operation code.

Figure B.1-3 shows bit direct addressing example.

Figure B.1-3 Bit direct addressing example

Index addressing

The "@IX + off" addressing in the instruction list can be used to access the entire 64Kbyte area.In this addressing mode, the address is the value resulting from sign-extending the contents ofthe first operand and adding them to IX (index register).

Figure B.1-4 shows index addressing example.

Figure B.1-4 Index addressing example

Pointer addressing

The "@EP" addressing in the instruction list can be used to access the entire 64Kbyte area. Inthis addressing mode, the address is contained in EP (extra pointer).


Figure B.1-5 Pointer addressing example

General-purpose register addressing

General-purpose register addressing is indicated by "Ri" in the instruction list. This addressing isused to access a register bank in the general-purpose register area. In this addressing mode, thehigher byte of the address is always "01" and the lower byte is specified based on the contents ofRP (register bank pointer) and the lower three bits of the operation code.

SETB 3 4H : 2

X X X X X 1 X XB0 0 3 4H

7 6 5 4 3 2 1 0

2 7 F FH

MOVW A, @IX+5AH

1 2 3 4HA1 2H

3 4H2 8 0 0H

2 7 A 5HIX

2 7 A 5H

MOVW A, @EP

1 2 3 4HA1 2H

3 4H2 7 A 6H

2 7 A 5HEP

379

APPENDIX

Figure B.1-6 shows general-purpose register addressing example.

Figure B.1-6 General-purpose register addressing example

Immediate addressing

Immediate addressing is indicated by "#d8" in the instruction list. This addressing is used whenimmediate data is required. In this addressing mode, the operand is used as immediate data.Whether the data is specified in bytes or words is determined by the operation code.

Figure B.1-7 shows immediate addressing example.

Figure B.1-7 Immediate addressing example

Vector addressing

Vector addressing is indicated by "vct" in the instruction list. This addressing is used to branch toa subroutine address stored in the vector table. In this addressing mode, "vct" information isincluded in the op-code and the table address is generated as described in Table B.1-1 .

0 1 5 6H

MOV A, R 6

A BHAA BH0 1 0 1 0BRP

MOV A, #5 6H

5 6HA

Table B.1-1 The vector table address for "vct".

#vct Vector table address (higher address: lower address of branch destination)

0 FFC0H :FFC1H

1 FFC2H :FFC3H

2 FFC4H :FFC5H

3 FFC6H :FFC7H

4 FFC8H :FFC9H

5 FFCAH :FFCBH

6 FFCCH :FFCDH

7 FFCE H :FFCFH

380



Figure B.1-8 Vector addressing example

Relative addressing

Relative addressing is indicated by "rel" in the instruction list. This addressing is used to branch towithin the area between the address 128 bytes higher and that 128 bytes lower relative to theaddress contained in the PC (program counter). In this addressing mode, the result of a signedaddition of the contents of the operand to the PC is stored in the PC.

Figure B.1-9 shows an example of relative addressing.

Figure B.1-9 Relative addressing example

In this example, a branch to the address of the BNE operation code occurs, thus resulting in aninfinite loop.

Inherent addressing

Inherent addressing is indicated as the addressing without operands in the instruction list. Thisaddressing is used to perform the operation determined by the operation code. In this addressingmode, different operations are performed via different instructions.


Figure B.1-10 Inherent addressing example

F F C AH

CALLV # 5

F E D CHPCF EH

D CHF F C BH

(convert)

9 A B AH

BNE F EH

New PC9 A B CHOld PC9ABCH + FFFEH

9 A B DH

NOP

New PC9 A B CHOld PC

381

APPENDIX

B.2 Special instruction

This section describes the special instructions used for other than addressing.

Special instruction

JMP @A

This instruction sets the contents of A (accumulator) to PC (program counter) as the address, andcauses a branch to that address. One of the N branch destination addresses is selected from atable, and then transferred to A. The instruction can be executed to perform N-branch processing.

Figure B.2-1 shows an overview.

Figure B.2-1 JMP @A

MOVW A, PC

This instruction performs the operation which is the reverse of that performed by "JMP @A". Thatis, the instruction stores the contents of PC in A. When the instruction is executed in the mainroutine, so that a specific subroutine is called, whether A contains a predetermined value can bechecked by the subroutine. This can be used to determine that the branch source is not anyunexpected section of the program and to check for program runaway.


Figure B.2-2 MOVW A, PC

After the MOVW A, PC instruction is executed, A contains the address of the operation code ofthe next instruction, rather than the address of the operation code of MOVW A, PC. Accordingly,in Figure B.2-2 , the value in A ("1234H") is the address containing the next op-code after the

"MOVW A, PC" instruction.

MULU A

This instruction performs an unsigned multiplication of AL (lower eight bits of the accumulator)and TL (lower eight bits of the temporary accumulator), and stores the 16-bit result in A. Thecontents of T (temporary accumulator) do not change. The contents of AH (higher eight bits of theaccumulator) and TH (higher eight bits of the temporary accumulator) before execution of the

1 2 3 4HA

X X X XHOld PC

1 2 3 4HA

New PC

(before execution) (after execution)

1 2 3 4H

X X X XH

1 2 3 3H

A

Old PC

1 2 3 4HA

New PC


1 2 3 4H

382


instruction are not used for the operation. The instruction does not change the flags, andtherefore care must be taken when a branch may occur depending on the result of amultiplication.


Figure B.2-3 MULU A

DIVU A

This instruction divides the 16-bit value in T by the unsigned 8-bit value in AL, and stores the 8-bitresult and the 8-bit remainder in AL and TL, respectively. A value of "0" is set to both AH and TH.The contents of AH before execution of the instruction are not used for the operation. For datawhose results total 8 bits or more, such results are not guaranteed. Even if the result exceeds 8bits, it is not indicated, so data that has such possibility should be determined before use.

The instruction does not change the flags, and therefore care must be taken when a branch mayoccur depending on the result of a division.


Figure B.2-4 DIVU A

XCHW A, PC

This instruction swaps the contents of A and PC, resulting in a branch to the address contained inA before execution of the instruction. "A" after execution will have the following address value outof the addresses in which "XCHW A, PC" operation codes are stored. This instruction is effectiveespecially when it is used in the main routine to specify a table for use in a subroutine.


Figure B.2-5 XCHW A, PC

After the MOVW A, PC instruction is executed, A contains the address of the operation code ofthe next instruction, rather than the address of the operation code of MOVW A, PC. Accordingly,in Figure x.x, the value in A ("1235H") is the address containing the next op-code after the

1 2 3 4H

A

T

1 8 6 0HA

T 1 2 3 4H

5 6 7 8H


1 8 6 2H

A

T

0 0 3 4HA

T 0 0 0 2H

5 6 7 8H


1 2 3 4H

A

PC

1 2 3 5HA

PC 5 6 7 8H

5 6 7 8H


383

APPENDIX

"XCHW A, PC" instruction. This is why "1235 H " is stored instead of "1234 H ".

Figure B.2-6 shows some example assembly code.

Figure B.2-6 Example of using "XCHW A, PC"

CALLV #vct

Use it to cause a branch to the subroutine address registered in the table. The instruction savesthe return address (contents of PC) in the location at the address contained in SP (stack pointer),and uses vector addressing to cause a branch to the address stored in the vector table. BecauseCALLV #vct is a 1-byte instruction, the use of this instruction for frequently used subroutines canreduce the entire program size.


Figure B.2-7 CALLV #3 operating example

The value of the PC saved on the stack when this instruction is executed is the address of thenext instruction, not the address of the op-code for this instruction. Accordingly, in Figure B.2-7 ,the value "5679H" saved on the stack (1232H and 1233H) is the address containing the next op-

code after the "CALLV #Vct" instruction (the return address).

MOVWXCHWDBMOVW

A, #PUTSUBA, PC'PUT OUT DATA', EOLA, 1234H

• •

••

• •

(Main routine)

XCHW A, EPPUSHW AMOV A, @EPINCW EPMOV IO, ACMP A, #EOLBNE PTS1POPW AXCHW A, EPJMP @A

PUTSUB

PTS1

(Sub routine)

Output table data here

1 2 3 4H

PC

SP

F E D CHPC

SP 1 2 3 2H

5 6 7 8H

1 2 3 2H

1 2 3 3H

X XH

X XH

F EH

D CH

F F C 6H

F F C 7H

1 2 3 2H

1 2 3 3H

5 6H

7 9H

F EH

D CH

F F C 6H

F F C 7H

(-2)


384


B.3 Bit manipulation instructions (SETB,CLRB)

Some bits of peripheral function registers include bits that are read by a bit manipulation instruction differently than usual.

Read-modify-write operationBy using these bit manipulation instructions, only the specified bit in a register or RAM locationcan be set to 1 (SETB) or cleared to "0" (CLRB). However, as the CPU operates on data in 8-bitunits, the actual operation (read-modify-write operation) involves a sequence of steps: 8-bit datais read, the specified bit is changed, and the data is written back to the location at the originaladdress.

Table B.3-1 shows the bus operation for bit manipulation instructions.

Read operation upon the execution of bit manipulation instructionsFor some I/O ports and for the interrupt request flag bits, the value to be read differs between anormal read operation and a read-modify-write operation.

I/O ports (during a bit manipulation)

From some I/O ports, an I/O pin value is read during a normal read operation, while an outputlatch value is read during a bit manipulation. This prevents the other output latch bits from beingchanged accidentally, regardless of the I/O directions and states of the pins.

Interrupt request flag bits (during a bit manipulation)

An interrupt request flag bit functions as a flag bit indicating whether an interrupt request existsduring a normal read operation. However, "1" is always read from this bit during a bitmanipulation. This prevents the flag from being cleared accidentally by a value of "0" which wouldotherwise be written to the interrupt request flag bit when another bit is manipulated.

Table B.3-1 Bus operation for a bit manipulation instruction.

CODE MNEMONIC to Cycle Address bus Data bus (GRAPHICS)

(GRAPHICS)

RMW

A0 to A7 CLRB dir:b 4 1 N+1 Dir 0 1 0

2 dir address Data 0 1 1

A8 to AF SETB dir:b 3 dir address Data 1 0 0

4 N+2 Next instruction 0 1 0

385

APPENDIX

B.4 F2MC-8L Instruction List

A list of commands used for F2MC-8L is shown in the attached Figure B.4-1 to Figure B.4-5 , and explanations of items on the list are shown in the attached Table B.4-1 Description of Items in the Instruction List".

Transfer instructions

Figure B.4-1 Instruction list of communication

MNEMONIC TL TH AH N Z V C OP CODE

1 MOV di r, A 3 2 (

( )

dir )((

(

( (

))

( )

)45

2 MOV @I X off, A 4 2 I X off 463 MOV ex t, A 4 3 ext 614 MOV @EP, A 3 1 EP 475 MOV Ri , A 3 1 R i 48 4F

6 MOV A, #d8 2 2 A( ) )A( ( ()A( ) )A(

(( ()

) )

) )A

( )) ) A

( ( EP )

( ( ) )

)

( ( EP ) )

(

)A

( )A

( )A( )A

d8 AL 047 MOV A, dir 3 2 dir

)(

)() ) )( ( )((

dir

AL 058 MOV A, @IX off 4 2 I X off

( ( ) ) ) ) )I X off

AL 069 MOV A, ext 4 3

( )A

( )A

( () )A

( )A

ext AL 6010 MOV A, @A 3 1 A AL 92

11 MOV A, @EP 3 1 AL 0712 MOV A, Ri 3 1 R i AL 08 0F13 MOV di r, #d8 4 3 d8 8514 MOV @I X off, #d8 5 3 IX off d8

d8

8615 MOV @EP, #d8 4 2 87

16 MOV Ri , #d8 4 2 Ri d8

)( EP

( )A )( EP( )EP

( )A )( IX

( )A )( SP

88 8F17 MOVW dir, A 4 2 dir

( ) ( ( (AH ,

, dir 1 AL

) ) )( ( )( (AH , 1AL

) ) )( ( )( (dirAH

)(

( )IX ( )A

( )SP

A )(

A )( T )(

A )( EP)(

A )( IX )(

A )( SP)(

PS )(( )IX

( )A

( )PS( )SP( )AH ( )AL

( )AL( )dir

( )dir

( )TL

( )A

AH

, dir 1AL

) ) )( ( )((ext AH , ext

ext ext

1 AL) ) ) ) )( ( ( )(( (EP

) )( ( EP

AH , EP 1 AL

( )(,

,

) )( ( EP 1

) )( ( A 1

AL)( AH ) )( ( A

) )( ( A )( T) )( ( A )( TH )( TL

)(, ) )( ( A 1AL

D518 MOVW @IX off , A 5 2 AH X off 1 AL

( ( ) ) ) ))I X off( ) ( ((,AH X off 1AL

D619 MOVW ext, A 5 3 D420 MOVW @EP, A 4 1 D7

21 MOVW E P, A 2 1 E322 MOVW A , #d16 3 3 d16 AL AH dH E423 MOVW A , dir 4 2 AL AH dH C524 MOVW A , @IX off 5 2 AL AH dH C625 MOVW A , ext 5 3 AL AH dH C4

26 MOVW A, @A 4 1 AL AH dH 9327 MOVW A, @EP 4 1 AL AH dH C728 MOVW A, EP 2 1 dH F329 MOVW EP, #d16 3 3 d16 E730 MOVW I X, A 2 1 E2

31 MOVW A , I X 2 1 dH F232 MOVW S P, A 2 1 E133 MOVW A , SP 2 1 dH F134 MOV @A, T 3 1 8235 MOVW @A, T 4 1 83

36 MOVW I X, #d16 3 3 d16 E637 MOVW A , PS 2 1 dH 7038 MOVW P S, A 2 1 7139 MOVW S P, #d16 3 3 d16 E540 SWAP 2 1 AL 10

41 SETB d ir : b 4 2 : b 1 A8 AF42 CLRB d ir : b 4 2 : b 0 A0 A743 XCH A, T 2 1 AL 4244 XCHW A, T 3 1 AL AH dH 4345 XCHW A, EP 3 1 dH F7

46 XCHW A, I X 3 1 dH F647 XCHW A, SP 3 1

A ) )( PC(dH F5

48 MOVW A , PC 2 1 dH F0

Processing

386


Note

In automatic transfer to T during byte transfer to A, AL is transferred to TL.

If an instruction has two or more operands, they are assumed to be saved in the order indicated byMNEMONIC.

387

APPENDIX

Arithmetic instructions

Figure B.4-2 Instruction list of arithmetic (Continued)

MNEMONIC TL TH AH N Z V C OP CODE1 ADDC A, Ri 3 1 ( A ) ( (A ) )

( A ) ( A )( A ) ( (A ) )( A ) ( A ) )( A ) (

((

((A )

(( ) )

( A ) (A ) )

( A ) ( (A ) )( A ) ( A )( A ) ( (A )

( A ) ( A ) ) )( A ) (

((

((A )

( A ) ( A )

) )( A ) ( )( T )

)

)) )

Ri C 28 2F2 ADDC A, #d8 2 2 d8 C 243 ADDC A, dir 3 2 dir C 254 ADDC A, @IX off 4 2 IX off C 265 ADDC A, @EP 3 1 EP C 27

6 ADDCW A 3 1 T C dH 237 ADDC A 2 1 AL( )AL

( )TL( )( ) ( )

( )( )

AL ( )AL

TL C 228 SUBC A, Ri 3 1 Ri C 38 3F9 SUBC A, #d8 2 2 d8 C 3410 SUBC A, dir 3 2 dir C 35

11 SUBC A, @IX off 4 2 IX off C 3612 SUBC A, @EP 3 1 EP C 3713 SUBCW A 3 1 A C dH 3314 SUBC A 2 1 C 3215 INC R i 4 1 Ri Ri

( ) ( )Ri Ri

1 C8 CF

16 INCW EP 3 1 EP( )EP

( )EP( )EP

1 C317 INCW IX 3 1 IX( )IX

( A ) ((A )

( A )( A ) ( () )( A ) ) ( )

( A )

( A ) ( A ))( A ) (

( ))(

)(

A)( )(

(

( )) )))

) )) )

(((

)()

))(

( )((

(((

((

)

( )

( )IX( )IX

1 C218 INCW A 3 1 1 dH C019 DEC R i 4 1 1 D8 DF20 DECW EP 3 1 1 D3

21 DECW IX 3 1 1 D222 DECW A 3 1 1 dH D023 MULU A 19 1 AL TL dH 0124 DIVU A 21 1 T ( )T/ AL , MOD dL 00 00 1125 ANDW A 3 1 T dH R 63

26 ORW A 3 1 T dH R 7327 XORW A 3 1 T dH R 5328 CMP A 2 1 TL AL 1229 CMPW A 3 1 T A 1330 RORC A 2 1 C A 03

31 ROLC A 2 1 C A 02

32 CMP A, #d8 2 2 A d8 1433 CMP A, dir 3 2 A dir 1534 CMP A, @EP 3 1 A EP 1735 CMP A, @IX off 4 2 A

) )( (A

IX off 16

36 CMP A, Ri 3 1 Ri 18 1F37 DAA 2 1 decimal adjust fo r addition 8438 DAS 2 1 decimal adjust fo r subtracti on 9439 XOR A 2 1 A AL TL R 5240 XOR A, #d8 2 2 A AL

) ) )( (A AL) )( (A AL) )

) )) )( (A AL

) )( (A AL) )

))( (

(

)(

((

((

((A AL

) )( (A AL) )( (A AL) )( (A AL) )

) )) )( (A AL

) ) )( (

((

((

(A AL

) )( ( )(A AL) )( (A AL) ) )( (A AL) )( (A AL) )

) )) )( (

(((

((A AL

d8 R 54

41 XOR A, dir 3 2 dir R 5542 XOR A, @EP 3 1 EP R 5743 XOR A, @IX off 4 2 IX off R 5644 XOR A, Ri 3 1 Ri R 58 5F45 AND A, 2 1 TL R 62

46 AND A, #d8 2 2 d8 R 6447 AND A, dir 3 2 dir R 6548 AND A, @EP 3 1 EP R 6749 AND A, @IX off 4 2 IX off R 6650 AND A, Ri 3 1 Ri R 68 6F

51 OR A 2 1 TL R 7252 OR A, #d8 2 2 d8 R 7453 OR A, dir 3 2 dir R 7554 OR A, @EP 3 1 EP R 7755 OR A, @IX off 4 2 IX off R 76

Processing

388


Figure B.4-3 Instruction list of arithmetic (Continued)

Branch instructions

Figure B.4-4 Instruction list of branching

Other instructions

Figure B.4-5 Other instruction list

MNEMONIC Processing THTL AH N Z V C OP CODE56 OR A, Ri 3 1 (A) (AL) (Ri)V R 78 7F57 CMP dir, #d8 5 3 ( dir) d8 9558 CMP @ EP, #d8 4 2 ( (EP) ) d8 9759 CMP @ IX off, #d8 5 3 ( (IX) off) d8 9660 CMP R i, #d8 4 2 ( Ri) d8 98 9F

61 INCW SP 3 1 (SP) (SP)(SP) (SP)

1 C162 DECW SP 3 1 1 D1

MNEMONIC TL TH AH OP CODE1 BZ/BEQ rel 3 2 if Z = 1 then P C PC rel FD2 BNZ/BNE rel 3 2 if Z = 0 then P C PC rel FC3 BC/BLO rel 3 2 if C = 1 then P C PC rel F94 BNC/BHS rel 3 2 if C = 0 then P C PC rel F85 BN re l 3 2 if N = 1 then P C PC rel FB

6 BP re l 3 2 if N = 0 then P C PC rel FA7 BLT r el 3 2 if V N = 1 t hen PC PC rel FF8 BGE rel 3 2 if V N = 0 t hen PC PC rel FE9 BBC d ir : b, rel 5 3 if ( dir : b) = 0 t hen PC PC rel B0 B710 BBS d ir : b, rel 5 3 if ( dir : b) = 1 t hen PC PC rel B8 BF

11 JMP @A 2 1 (PC) (A)

(PC) (A) 1(PC) (A) ,

(PC)E0

12 JMP ext 3 3 ext 2113 CALLV #vct 6 1 vector call E8 EF14 CALL ext 6 3 subroutine call 3115 XCHW A, PC 3 1 dH F4

16 RET 4 1 return from subro utine 2017 RETI 6 1 return from inter rupt r estore 30

N Z V CProcessing

MNEMONIC TL TH AH N Z V C OP CODE1 PUSHW A 4 1 402 POPW A 4 1 dH 503 PUSHW IX 4 1 414 POPW IX 4 1 515 NOP 1 1 00

6 CLRC 1 1 R 817 SETC 1 1 S 918 CLRI 1 1 809 SETI 1 1 90

Processing

389

APPENDIX

Description of Items in the Instruction List

Table B.4-1 Description of Items in the Instruction List

Item Description

Mnemonic Assembler notation of an instruction

~ Number of instructions. A single instruction cycle consists of two machine cycles.

# Number of bytes

Operation Operation of an instruction

TL, TH, AH A content change when each of the TL, TH and AH instruction is executed. Symbols in the column indicate the following:• "-" indicates no change.• dH is the 8 upper bits of operation description data.• AL and AH must become the contents of AL and AH immediately before the

instruction is executed.• 00 becomes 00.

N, Z, V, C An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag.

OP code Code of an instruction. If an instruction is more than one code, it is written according to the following rule:

Example: 48 to 4F <-- This indicates 48, 49, ... 4F.

390


B.5 Instruction Map

Figure B.5-1 contains the F2MC-8L instruction map.

Instruction Map

Figure B.5-1 F2MC-8L instruction map

0 1 2 3 4 5 6 7 8 9 A B C D E F

NOP

MUL

U

A

ROLC

A

RORC

A

MO

V

A, #

d8

MO

V

A,

dir

MO

V

A, @

IX+d

MO

V

A, @

EP

MO

V

A

, R0

MO

V

A

, R1

MO

V

A

, R2

MO

V

A

, R3

MO

V

A

, R4

MO

V

A

, R5

MO

V

A

, R6

MO

V

A

, R7

SWAP

DIVU

A

CMP

A

CMPW

A

CMP

A, #

d8

CMP

A

, dir

CMP

A, @

IX+d

CMP

A, @

EP

CMP

A

, R0

CMP

A

, R1

CMP

A

, R2

CMP

A

, R3

CMP

A

, R4

CMP

A

, R5

CMP

A

, R6

CMP

A

, R7

RET

JMP

add

r16

ADDC

A

ADDC

W

A

ADDC

A, #

d8

ADDC

A

, dir

ADDC

A, @

IX+d

ADDC

A, @

EP

ADDC

A

, R0

ADDC

A

, R1

ADDC

A

, R2

ADDC

A

, R3

ADDC

A

, R4

ADDC

A

, R5

ADDC

A

, R6

ADDC

A

, R7

RETI

CALL

add

r16

SUBC

A

SUBC

W

A

SUBC

A, #

d8

SUBC

A,

dir

SUBC

A, @

IX+d

SUBC

A, @

EP

SUBC

A

, R0

SUBC

A

, R1

SUBC

A

, R2

SUBC

A

, R3

SUBC

A

, R4

SUBC

A

, R5

SUBC

A

, R6

SUBC

A

, R7

PUSH

W

A

PUSH

W

IX

XCH

A

, T

XCHW

A

, T

MO

V

d

ir, A

MO

V

@IX

+d, A

MO

V

@EP

, A

MO

V

R

0, A

MO

V

R

1, A

MO

V

R

2, A

MO

V

R

3, A

MO

V

R

4, A

MO

V

R

5, A

MO

V

R

6, A

MO

V

R

7, A

POPW

A

POPW

IX

XOR

A

XORW

A

XOR

A, #

d8

XOR

A

, dir

XOR

A, @

IX+d

XOR

A, @

EP

XOR

A

, R0

XOR

A

, R1

XOR

A

, R2

XOR

A

, R3

XOR

A

, R4

XOR

A

, R5

XOR

A

, R6

XOR

A

, R7

MO

V

A,

ext

MO

V

ex

t, A

AND

A

ANDW

A

AND

A, #

d8

AND

A

, dir

AND

A, @

IX+d

AND

A, @

EP

AND

A

, R0

AND

A

, R1

AND

A

, R2

AND

A

, R3

AND

A

, R4

AND

A

, R5

AND

A

, R6

AND

A

, R7

MO

VW

A,

PS

MO

VW

PS

, A

OR

A

ORW

A

OR

A, #

d8

OR

A,

dir

OR

A, @

IX+d

OR

A, @

EP

OR

A

, R0

OR

A

, R1

OR

A

, R2

OR

A

, R3

OR

A

, R4

OR

A

, R5

OR

A

, R6

OR

A

, R7

CLRI

CLRC

MO

V

@A,

T

MO

VW

@A,

T

DAA

MO

V

dir,

#d8

MO

V

@IX

+d,#

d8

MO

V

@EP

#, d

8

MO

V

R0, #

d8

MO

V

R1, #

d8

MO

V

R2, #

d8

MO

V

R3, #

d8

MO

V

R4, #

d8

MO

V

R5, #

d8

MO

V

R6, #

d8

MO

V

R7, #

d8

SETI

SETC

MO

V

A, @

A

MO

VW

A, @

A

DAS

CMP

dir,

#d8

CMP

@IX

+d,#

d8

CMP

@EP

#, d

8

CMP

R0, #

d8

CMP

R1, #

d8

CMP

R2, #

d8

CMP

R3, #

d8

CMP

R4, #

d8

CMP

R5, #

d8

CMP

R6, #

d8

CMP

R7, #

d8

CLRB

d

ir : 0

CLRB

d

ir : 1

CLRB

d

ir : 2

CLRB

d

ir : 3

CLRB

d

ir : 4

CLRB

d

ir : 5

CLRB

d

ir : 6

CLRB

d

ir : 7

SETB

d

ir : 0

SETB

d

ir : 1

SETB

d

ir : 2

SETB

d

ir : 3

SETB

d

ir : 4

SETB

d

ir : 5

SETB

d

ir : 6

SETB

d

ir : 7

BBC

di

r : 0

, rel

BBC

di

r : 1

, rel

BBC

di

r : 2

, rel

BBC

di

r : 3

, rel

BBC

di

r : 4

, rel

BBC

di

r : 5

, rel

BBC

di

r : 6

, rel

BBC

di

r : 7

, rel

BBS

di

r : 0

, rel

BBS

di

r : 1

, rel

BBS

di

r : 2

, rel

BBS

di

r : 3

, rel

BBS

di

r : 4

, rel

BBS

di

r : 5

, rel

BBS

di

r : 6

, rel

BBS

di

r : 7

, rel

INCW

A

INCW

SP

INCW

IX

INCW

EP

MO

VW

A,

ext

MO

VW

A,

dir

MO

VW

A, @

IX+d

MO

VW

A, @

EP

INC

R0

INC

R1

INC

R2

INC

R3

INC

R4

INC

R5

INC

R6

INC

R7

DECW

A

DECW

SP

DECW

IX

DECW

EP

MO

VW

ex

t, A

MO

VW

d

ir, A

MO

VW

@IX

+d, A

MO

VW

@EP

, A

DEC

R0

DEC

R1

DEC

R2

DEC

R3

DEC

R4

DEC

R5

DEC

R6

DEC

R7

JMP

@A

MO

VW

SP

, A

MO

VW

IX

, A

MO

VW

EP

, A

MO

VW

A, #

d16

MO

VW

S

P, #

d16

MO

VW

I

X, #

d16

MO

VW

E

P, #

d16

CALL

V

#0

CALL

V

#1

CALL

V

#2

CALL

V

#3

CALL

V

#4

CALL

V

#5

CALL

V

#6

CALL

V

#7

MO

VW

A,

PC

MO

VW

A,

SP

MO

VW

A,

IX

MO

VW

A,

EP

XCHW

A,

PC

XCHW

A,

SP

XCHW

A,

IX

XCHW

A,

EP

BNC

rel

BC

rel

BP

rel

BN

rel

BNZ

rel

BZ

rel

BGE

rel

BLT

rel

01

23

45

67

89

AB

CD

EF

LH

391

APPENDIX


Terminal status during each operation for the MB89051 series is shown.

Pin States in Each Operation Mode

Table C-1 Pin States in Each Operation Mode

Pin Name Normally At sleep In stop modeSPL=0

In stop modeSPL=1

Duringresetting

P31/INT1 to P37/INT7/SI2

Port I/OExternal interrupt inputResource input/output

HoldExternal interrupt inputResource input/output

HoldExternal interruptinput

Hi-Z/ External interruptinput

Hi-Z

X0 Oscillation input Oscillation input Hi-Z Hi-Z Oscillationinput

X1 Oscillation output Oscillation output "H" output "H" output Oscillationoutput

MOD0, 1, 2 Mode input Mode input Mode input Mode input Mode input

(GRAPHICS) Reset input/output Reset input/output Reset input/output

Reset input/output

Reset input/output

P00 to P07 Port I/O Hold Hold Hi-Z Hi-Z

P10 to P17

P20 to P27 Port output

P40/POW5 Port I/OResource input/output

HoldResource input/output

P41/POW2

P42/POW3

P43/POW4

P44/UCK

P45/UO

P46/UI/PWM1

P47/PWM2

P53/SDA, P54/SCL

RPVP USB Port I/O USB Port I/O USB port input *1 USB port input *1 Hi-Z

RPVM

D2VP to D5VP Hi-Z *2

D2VM to D5VM

USBP USBP Output Hold Hold Hi-Z Hi-Z

CLK1, CLK2 Clock Output Clock Output "L" Output "L" Output "L" Output

392


Hi-Z: High impedance.*1: Will be port input when stopped due to USB factor, and status immediately prior will be unchanged when stopped for other reasons. *2: Will be undefined during power on reset.

Note:Pin state specification bit of the standby control register (STBC)Retain: Terminals set to output retain the status (level) of the terminal just before the change of mode

393

APPENDIX

394

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

395

INDEX

Index

ÉoÉXÉGÉâÅ ........................................................325

Numerics

2CH 8ÉrÉbÉgPWMÉ^ÉCÉ

2CH 8ビットPWMタイマ使用上の注意 1592CH 8 ビット PWM タイマに関連するレジ

スタ 1362CH 8 ビット PWM タイマに関連する割込

み 1332CH 8ビット PWMタイマの概要(PWMタイ

マ機 1292CH 8 ビット PWM タイマのブロックダイ

ヤグラム 1328ÉrÉbÉgÉVÉäÉAÉãI/O

8 ビットシリアル I/O 使用上の注意 3018 ビットシリアル I/O の接続例 3038 ビットシリアル I/O のブロックダイヤ

グラム 2838ビットシリアルI/Oのプログラム例305

8ÉrÉbÉgÉVÉäÉAÉãI/O1

8ビットシリアルI/O1に関連するレジスタ 288

8ÉrÉbÉgÉVÉäÉAÉãI/O2


8ÉrÉbÉgéÛêMìÆçÏ

8 ビット受信動作 2768ÉrÉbÉgëóêMìÆçÏ

8 ビット送信動作 2788ÉrÉbÉgPWMÉ^ÉCÉ

8ビットPWMタイマ1(CH1)および8ビット PWM タイマ 2(CH2)132

C

ÉAÉNÉmÉåÉbÉW

アクノレッジ (確認応答信号 )328ÉAÉhÉåÉX

アドレス指定方法 355ÉAÉhÉåÉbÉVÉìÉO

アドレッシング 328アドレッシングの説明 378

ÉCÉìÉXÉgÉâÉNÉVÉáÉìÉTÉCÉNÉã

インストラクションサイクル (tinst)53ÉEÉHÉbÉ`ÉhÉbÉOêßå‰ÉåÉWÉXÉ^

ドッグ制御レジスタ (WDTC)120ÉEÉHÉbÉ`ÉhÉbÉOÉ^ÉCÉ

ウォッチドッグタイマ使用上の注意 122ウォッチドッグタイマの動作 121ウォッチドッグタイマのブロックダイ

ヤグラム 119ウォッチドッグタイマのプログラム例

123ウォッチドッグタイマリセット 362

ââéZåãâþ

演算結果を示すビット 26ÉGÉìÉhÉ|ÉCÉìÉgÉCÉl-ÉuÉãÉåÉWÉXÉ^

エンドポイントイネ - ブルレジスタ(EPER)229

ÉGÉìÉhÉ|ÉCÉìÉgÉZÉbÉgÉAÉbÉvÉåÉWÉXÉ^

エンドポイントセットアップレジスタ(EPBR0, EPBRn1,n2)n=1,2,3230

èëçûÇ›

書込み /読込みについての説明 375自動書込み /消去時 349フラッシュメモリ書込み/消去の方法342

ämîFâûìöêMçÜ

アクノレッジ (確認応答信号 )328â?ìdó¨åüèoèàóù

過電流検出処理 194äOïîÉVÉtÉgÉNÉçÉbÉN

外部シフトクロックを使用した場合 299äOïîäÑçûÇ›âÒòH

外部割込み回路動作時の割込み 176外部割込み回路に関連するレジスタ 172外部割込み回路の機レベル検出 )168外部割込み回路の動作 177外部割込み回路のブロックダイヤグラ

ム 169外部割込み回路のプログラム例 178

äOïîäÑçûÇ›êßå‰ÉåÉWÉXÉ^

外部割込み制御レジスタ (EIE)173外部割込み制御レジスタ (EIE) の各ビッ

トの機柏燒ｾ 174äOïîäÑçûÇ›ÉtÉâÉOÉåÉWÉXÉ^

外部割込みフラグレジスタ (EIF)175ãüããÉÉbÉv

クロック供給マップ 47ÉNÉçÉbÉN

396

INDEX

クロック供給マップ 47クロック制御部のブロックダイヤグラ

ム 50クロック発生部 49

ÉNÉçÉbÉNãüãã

クロック供給機狽ﾌ動作 113ÉNÉçÉbÉNèoóÕêßå‰ÉåÉWÉXÉ^

クロック出力制御レジスタ (CKR)336çÇë¨PWMÉ^ÉCÉ

高速 PWM タイマ機狽ﾌ動作 152ÉRÉÉìÉhâûìö

コマンド応答時の各レジスタ動作 242ÉTÉXÉyÉìÉh

サスペンド処理 246サスペンドの解除について 246

ÉVÉXÉeÉÄÉNÉçÉbÉNêßå‰ÉåÉWÉXÉ^

システムクロック制御レジスタ (SYCC)の告ｬ 52

ÉVÉtÉgÉNÉçÉbÉNé¸îgêî

シフトクロック周波数を設定する場合の注意 322

é¸ï”ã@î:é¸ï”ã@îÇ©ÇÁÇÃäÑçûÇ›óvãÅ .................. 32é¸îgêî

シフトクロック周波数を設定する場合の注意 322

è¡ãé

自動書込み /消去時 349フラッシュメモリ書込み/消去の方法342

èâäŽíl

初期値についての説明 375ÉVÉäÉAÉãèëçûÇ›

MB89F051 シリアル書込み接続の基本告ｬ364

ÉVÉäÉAÉãÉNÉçÉbÉNêÿë÷Ç¶ÉåÉWÉXÉ^

シリアルクロック切替えレジスタ (SCS)260

ÉVÉäÉAÉãèoóÕ

シリアル出力完了時の動作 295シリアル出力動作 294シリアル出力のプログラム例 305

ÉVÉäÉAÉãì¸èoóÕ

シリアル入出力動作時の割込み 293双方向でシリアル入出力を行う場合 303

ÉVÉäÉAÉãì¸óÕ

シリアル入力完了時の動作 297シリアル入力動作 296シリアル入力のプログラム例 307

é©ìÆèëçûÇ›

自動書込み /消去時 349

自動書込み /消去動作中 350自動書込み動作時 348

é©ìÆè¡ãé

自動消去動作時 348éÛêMäÑçûÇ›

受信割込み 266èÛë‘ëJà⁄状態遷移図 63

ÉXÉ^ÉbÉNìÆçÏ

割込み処理開始時のスタック動作 39割込み復帰時のスタック動作 39

ÉXÉ^ÉbÉNóÃàÊ

割込み処理のスタック領域 40ÉXÉ^ÉìÉoÉCêßå‰ÉåÉWÉXÉ^

スタンバイ制御レジスタ (STBC)61ÉXÉgÉbÉvÉRÉìÉfÉBÉVÉáÉì

ストップコンディション 329ÉZÉNÉ^

セクタ消去一時停止時 348セクタ指定方法 358複数のセクタを指定するときの注意 358

ÉZÉNÉ^çê¨

セクタ告ｬ 343ÉZÉNÉ^è¡ãé

セクタ消去一時停止時 349セクタ消去動作中 351, 352セクタ消去手順 358

ë¾èdäÑçûÇ›

多重割込み 37ëó..........................................................................328ëóèIó¼éûÇÃäÑçûÇ› ............................................325ÉfÉBÉXÉNÉäÉvÉ^ROMÉAÉhÉåÉXÉåÉWÉXÉ^

ディスクリプタ ROM アドレスレジスタ(DADR)195

ÉfÉoÉCÉX

デバイス取扱い上の注意 18éÊàµÇ¢è„ÇÃíçà”

デバイス取扱い上の注意 18ì‡ïîÉVÉtÉgÉNÉçÉbÉN

内部シフトクロックを使用した場合 298ì¸èoóÕâÒòH

入出力回路形式 13ÉtÉâÉbÉVÉÖÉÅÉÇÉä

フラッシュメモリ書込み /消去の詳細説明 353

フラッシュメモリ書込み/消去の方法342フラッシュメモリ書込み手順 355フラッシュメモリへのプログラムアク

セス 362

397

INDEX

フラッシュメモリのセクタ消去再開 361フラッシュメモリのセクタ消去の一時

停止 360フラッシュメモリの特長 342フラッシュメモリの読出し /リセット状

態 354フラッシュメモリのレジスタ 342

ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

2CH 8 ビット PWM タイマのブロックダイヤグラム 132

8 ビットシリアル I/O のブロックダイヤグラム 283

ウォッチドッグタイマのブロックダイヤグラム 119

外部割込み回路のブロックダイヤグラム 169

クロック制御部のロックダイヤグラム50UART/SIO のブロックダイヤグラム 251USB ファンクション回路のブロックダイ

ヤグラム 207USBハブ回路のブロックダイヤグラム181

ÉvÉãÉAÉbÉvÉIÉvÉVÉáÉì

プルアップオプション 338ÉvÉãÉAÉbÉvÉIÉvÉVÉáÉìê›íËÉåÉWÉXÉ^

プルアップオプション設定レジスタ(PURR0,1,2)339

ÉvÉçÉOÉâÉÄÉAÉNÉZÉX

フラッシュメモリへのプログラムアクセス 362

ÉvÉçÉOÉâÉÄó·

8ビットシリアルI/Oのプログラム例305ウォッチドッグタイマのプログラム例

123外部割込み回路のプログラム例 178シリアル出力のプログラム例 305シリアル入力のプログラム例 307PWM タイマ機狽ﾌプログラム例 164

ÉmÉCÉYÉLÉÉÉìÉZÉâ

P53/SDA と P54/SCL のノイズキャンセラ314

ëóêMäÑçûÇ›

送信割込み 266ÉÉtÉgÉEÉFÉAÉäÉZÉbÉg

ャ tトウェアリセット 362ÉrÉbÉgëÄçÏ

ビット操作命令実行時の読出し先 385ïé¶ãLçÜ

命令の侮ｦ記号の説明 377ïWèÄÉfÉBÉXÉNÉäÉvÉ^

標準ディスクリプタ告ｬ 196ïiéÌ

品種選択時の注意事項 6ÉåÉWÉXÉ^

汎用レジスタの特長 31ÉäÉZÉbÉg

ャ tトウェアリセット ,ウォッチドッグタイマリセット 362

RAM 内容のリセットによる影響 45ÉäÉZÉbÉgèÛë‘

発振安定待ちリセット状態 45ÉäÉZÉbÉgìÆçÏ

リセット動作の概要 44ÉäÉZÉbÉgóvàˆ

リセット要因 41リセット要因とメインクロックの発振

安定待ち 42ì«çûÇ›

書込み /読込みについての説明 375ñ¾ó?

演算系命令 388特殊な命令について 382分岐系命令 389その他命令 389ビット操作命令 (SETB,CLRB)385ビット操作命令実行時の読出し先 385転送系命令 386命令一覧浮ﾌ項目の説明 390命令マップ 391命令の侮ｦ記号の説明 377F2MC-8L の命令の概要 376

ÉÅÉCÉìÉNÉçÉbÉN

リセット要因とメインクロックの発振安定待ち 42

メインクロックの発振安定待ち時間 55ÉÅÉÇÉäãÛä‘

メモリ空間の告ｬ 20ÉÅÉÇÉäÉÉbÉv

メモリマップ 21CH

8ビットPWMタイマ 1(CH1)および8ビット PWM タイマ 2(CH2)132

CH12PWMèoóÕêßå‰âÒòH

CH12PWM 出力制御回路 133ÉåÉWÉXÉ^

2CH 8 ビット PWM タイマに関連するレジスタ 136


398

INDEX


外部割込み回路に関連するレジスタ 172専用レジスタの告ｬ 24フラッシュメモリのレジスタ 342I2C クロック制御レジスタ (ICCR)321I2C バス制御レジスタ (IBCR)318UART/SIO に関連するレジスタ 255USB ハブに関連するレジスタ 185

ÉåÉWÉXÉ^ìÆçÏ

コマンド応答時の各レジスタ動作 242ÉåÉWÉXÉ^ÉoÉìÉNÉ|ÉCÉìÉ^

レジスタバンクポインタ (RP) の告ｬ 29ÉåÉxÉãåüèo

外部割込み回路の機レベル検出 )168äÑçûÇ›

2CH 8 ビット PWM タイマに関連する割込み 133

外部割込み回路動作時の割込み 176シリアル入出力動作時の割込み 293割込みの受付けを制御するビット 27USB ファンクション動作時の割込み 236

ëóèIó¼éûÇÃäÑçûÇ› ............................................ 325äÑçûÇ›èàóù

割込み処理開始時のスタック動作 39割込み処理時間 38割込み処理のスタック領域 40

äÑçûÇ›ìÆçÏ

割込み動作時の処理 35äÑçûÇ›óvãÅ

周辺機狽ｩらの割込み要求 32äÑçûÇ›ÉåÉxÉãê›íËÉåÉWÉXÉ^

割込みレベル設定レジスタ(ILR1,2,3,4) の告ｬ 33

òAë±éÛêMìÆçÏ

連続受信動作 277òAë±ëóêMìÆçÏ

連続送信動作 279CK12ÉZÉåÉNÉ^

CK12 セレクタ 133CKR

クロック出力制御レジスタ (CKR)336CLRB

ビット操作命令 (SETB,CLRB)385CNTR

PWM 制御レジスタ1,2,3(CNTR1,CNTR2,CNTR3)133

CNTR1

PWM 制御レジスタ 1(CNTR1)137

CNTR2

PWM 制御レジスタ 2(CNTR2)139CNTR3

PWM 制御レジスタ 3(CNTR3)141î¦êUà¿íËë“Çø

発振安定待ちリセット状態 45î¦êUà¿íËë“Çøéûä‘

メインクロックの発振安定待ち時間 55発振安定待ち時間 55, 66

ÉnÉuÉfÉBÉXÉNÉäÉvÉ^ÉåÉWÉXÉ^

ハブディスクリプタレジスタ(HDSR1,2,3,4)188

íçà”

8 ビットシリアル I/O 使用上の注意 301îƒópÉåÉWÉXÉ^

汎用レジスタの告ｬ 30îƒópÉåÉWÉXÉ^óÃàÊ

汎用レジスタ領域 22ÉoÉX

I2C バスによる通信機狽ﾌ概要 310COMR

PWM コンペアレジスタ1,2,(COMR1,COMR2)133

COMR1

PWM コンペアレジスタ 1(COMR1)143COMR2

PWM コンペアレジスタ 2(COMR2)145

D

DADR

ディスクリプタ ROM アドレスレジスタ(DADR)195

DBAR

DMA ベ - スアドレスレジスタ (DBAR)216

E

16ÉrÉbÉgÉfÅ .........................................................23ÉåÉMÉÖÉåÅ ..........................................................45I2CÉfÅ ..................................................................324ÉfÅ..........................................................................23ÉIÉyÉâÉìÉh

オペランドが 16 ビットの場合のデ 23ÉXÉ^ÉbÉN

スタックの 16 ビットデ 23ÉtÉâÉbÉVÉÖÉÅÉÇÉä

フラッシュメモリの全デ 357フラッシュメモリの任意デ 358

ÉVÉäÉAÉãÉAÉEÉgÉvÉbÉgÉfÅ ..........................264

399

INDEX

ÉVÉäÉAÉãÉCÉìÉvÉbÉgÉfÅ................................263ÉåÉWÉXÉ^

I2C デ 324IDAR

I2C デ 324SIDR

シリアルインプットデ 263SODR

シリアルアウトプットデ 264ÉVÉäÉAÉãÉfÅ .....................................................292ÉåÉWÉXÉ^

シリアルデ 292SDR1/SDR2

シリアルデ 292ÉfÅ .......................................................................355ÉtÉâÉbÉVÉÖÉÅÉÇÉä

フラッシュメモリのデ 355ì]ëóÉfÅ .................................................................218ëóÉfÅ ...................................................................218TDCR

転送デ 218ì]ëóÉfÅ .................................................................271ëóÉfÅ ...................................................................271I2CÉoÉXÉXÉeÅ ...................................................316ÉVÉäÉAÉãÉXÉeÅ ...............................................261SSD

シリアルステ 261ÉnÉuÉXÉeÅ .........................................................191USBÉtÉå-ÉÄÉXÉeÅ ............................................228USBÉXÉeÅ ..................................................221, 224HSTR

ハブステ 191ÉåÉWÉXÉ^

I2C バスステ 316IBSR

I2C バスステ 316UFRMR

USB フレ -ムステ 228USTR

USB ステ 221, 224äÑçûÇ›

デ 325ÉfÅ ...............................................................325, 328ëó

デ 325, 328ÉvÉäÉXÉPÅ.................................................132, 156ÉåÉWÉXÉ^

専用レジスタの機納れじすたせんようれじすたのきのう ]24

ÉRÉìÉgÉçÅ.......................................................... 344FMCS

コントロ 344ÉEÉHÉbÉ`ÉhÉbÉOÉ^ÉCÉ

ウォッチドッグタイマ機納うぉっちどっぐたいま

うぉっちどっぐたいまきのう ]118I/OÉ|Å ............................................................ 70, 104É|Å ................................................. 72, 74, 73, 72, 75DDR0

ポ 73ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

ポ 73É|Å ........................................... 77, 78, 79, 78, 77, 80ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ




ポ 94É|Å ................................... 99, 100, 101, 100, 99, 102ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

ポ 100ÉvÉçÉOÉâÉÄó·

I/O ポ 104ÉTÉ|Å................................................................... 238USBÉtÉ@ÉìÉNÉVÉáÉì

USB ファンクションのサポ 238ÉfÉoÉCÉX

デバイスからのリモ 247ÉfÉBÉXÉNÉäÉvÉ^

USB ハブサポ 199USBÉnÉu

USB ハブサポ 199ÉXÉ^Å.......................................................... 272, 327ÉVÉäÉAÉãÉåÅ.................................................... 265SRC

シリアルレ 2658ÉrÉbÉgÉ^ÉCÉÉÇÅ .......................................... 160CH12PWMÉÇÅ.................................... 166, 154, 147CK12ÉÇÅ............................................................. 162CLKîÒìØäŽÉÇÅ................................... 273, 271, 272ÉÉXÉ^ì]ëóÉÇÅ ................................................... 331ÉÅÉÇÉäÉAÉNÉZÉXÉÇÅ ...................................... 67

400

INDEX

ÉÅÉCÉìÉNÉçÉbÉNÉÇÅ ........................................ 54ÉNÉçÉbÉNÉÇÅ ..................................................... 54ÉVÉìÉOÉãÉ`ÉbÉvÉÇÅ.......................................... 67ÉXÉ^ÉìÉoÉCÉÇÅ .............................. 57, 157, 65, 58ÉXÉgÉbÉvÉÇÅ ...................................................... 60ìÆçÏÉÇÅ .............................................................. 268UART/SIO

UART/SIO の動作モ 268ìÆçÏÉÇÅ .............................................................. 274UART/SIO

UART/SIO の動作モ 2748ÉrÉbÉgÉVÉäÉAÉãI/O

8ビットシリアルI/Oの動作中の各モ 298ÉvÉçÉOÉâÉÄó·

8 ビットタイマモ 160マスタ転送モ 331CH12PWM モ 166CK12 モ 162

ëóÉÇÅ.................................................................. 331ÉRÉìÉfÉBÉVÉáÉìÉRÅ .......................................... 26USBÉäÉZÉbÉgÉÇÅ ............................................ 214USBÉnÉuÉÇÅ ..................................................... 186CCR

コンディションコ 26HMDR

USB ハブモ 186UMDR

USB リセットモ 214ÉVÉäÉAÉãÉÇÅ ................................................... 289ÉåÉWÉXÉ^

シリアルモ 289SMR

シリアルモ 289ÉäÅ ...................................................................... 385ÉtÉâÉO

ハ 347ÉnÅ ...................................................................... 347ÉÇÅ.................................................................. 67, 46ÉVÉäÉAÉãÉÇÅ ........................................... 256, 258SMC1

シリアルモ 256SMC2

シリアルモ 258ÉÇÅ........................................................................ 45EIE

外部割込み制御レジスタ (EIE)173EIF

外部割込みフラグレジスタ (EIF)175ÉEÉFÅ ......................................................... 247, 248

ÉzÉXÉgPC

ホスト PC からのウェ 248ÉNÉçÉbÉNãüãã

クロック供給機納くろっくきょうきゅう

くろっくきょうきゅうきのう ]107ÉNÉçÉbÉNèoóÕã@î:ÉNÉçÉbÉNèoóÕã@î[Ç¦ÇÎÇ¡Ç

¦ÇµÇ„Ç¬ÇËÇÂÇ¦Ç´ÇÃÇ§

くろっくしゅつりょくきのう ]334ÉCÉìÉ^Å.......................126, 106, 147, 113, 148, 112ï°å`îgèoóÕã@î:ÉCÉìÉ^Å......................................126ëOèë....................................................................... -iiiÉIÅ........................................................................193OCCR

オ 193EPBR

エンドポイントセットアップレジスタ(EPBR0, EPBRn1,n2)n=1,2,3230

ÉRÉÉìÉhÉVÅ ......................................................346EPER

エンドポイントイネ - ブルレジスタ(EPER)229

äOïîäÑçûÇ›í..........................................................171äOïîÉäÉZÉbÉgí ......................................................43í.............................................134, 285, 286, 392, 3142CH 8ÉrÉbÉgPWMÉ^ÉCÉ

2CH 8 ビット PWM タイマに関連する 1348ÉrÉbÉgÉVÉäÉAÉãI/O

8 ビットシリアル I/O に関連する 2858ÉrÉbÉgÉVÉäÉAÉãI/O1

8 ビットシリアル I/O1 に関連する 2858ÉrÉbÉgÉVÉäÉAÉãI/O2

8 ビットシリアル I/O2 に関連する 285äOïîäÑçûÇ›âÒòH

外部割込み回路に関連する 170ÉNÉçÉbÉNèoóÕ

クロック出力 (CLK1,CLK2) に関連する 335

CLK

クロック出力 (CLK1,CLK2) に関連する 335

UART/SIO

UART/SIO に関連する 253USBÉnÉu

USB ハブに関連する 183í...............................................................................10äOïîäÑçûÇ›âÒòH

外部割込み回路の割込み許可ビットと外部割込み 171

401

INDEX

äÑçûÇ›ãñâ¬ÉrÉbÉg

外部割込み回路の割込み許可ビットと外部割込み 171

ÉäÉZÉbÉg

リセット中の 462CH 8ÉrÉbÉgPWMÉ^ÉCÉ

2CH 8 ビット PWM タイマに関連する 1348ÉrÉbÉgÉVÉäÉAÉãI/O

8 ビットシリアル I/O に関連する 286ÉNÉçÉbÉNèoóÕ

クロック出力に関連する 335ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

2CH 8 ビット PWM タイマに関連する 1348 ビットシリアル I/O に関連する 286外部リセット 43外部割込み回路に関連する 171クロック出力に関連する 335 184UART/SIO に関連する 254

äOïîäÑçûÇ›âÒòH

外部割込み回路に関連する 171UART/SIO

UART/SIO に関連する 254í ................................................................................8ÉAÅ ......................................................................329íþêMãñâ¬éËèá

ア 329äÑçûÇ›

バスエラ 325ÉxÉNÉgÉãÉeÅ ....147, 293, 176, 112, 325, 198, 2372CH 8ÉrÉbÉgPWMÉ^ÉCÉ

2CH 8 ビット PWM タイマの割込みに関連するレジスタとベクトルテ 147

8ÉrÉbÉgÉVÉäÉAÉãI/O

8 ビットシリアル I/O の割込みに関連するレジスタとベクトルテ 293

äOïîäÑçûÇ›âÒòH

外部割込み回路の割込みに関連するレジスタとベクトルテ 176

ÉåÉWÉXÉ^


外部割込み回路の割込みに関連するレジスタとベクトルテ 176

USB ファンクションの割込みに関連するレジスタとベクトルテ 237

äÑçûÇ›


USBÉtÉ@ÉìÉNÉVÉáÉì

USB ファンクションの割込みに関連するレジスタとベクトルテ 237

USBÉnÉu

USB ハブの割込みに関連するレジスタとベクトルテ 198

ÉxÉNÉgÉãÉeÅ .................................................... 266ÉåÉWÉXÉ^

UART/SIO の割込みに関連するレジスタとベクトルテ 266

UART/SIO

UART/SIO の割込みに関連するレジスタとベクトルテ 266

ÉxÉNÉgÉãÉeÅ ...................................................... 22ÉVÉäÉAÉãèëçûÇ›

シリアル書込み時の接続例 (ユ 367ÉtÉâÉbÉVÉÖÉÉCÉRÉìÉvÉçÉOÉâÉ

フラッシュマイコンプログラマとの最小限の接続例 (ユ 369

ÉVÉäÉAÉãì¸èoóÕ

シリアル入出力機納しりあるにゅうしゅつりょく

しりあるにゅうしゅつりょくきのう]282

ÉXÉäÅ ................................................................... 59ÉZÉbÉgÉAÉbÉvÉXÉeÅ....................................... 244ÉXÉeÅ ................................................................. 243USBÉRÉÉìÉh

USB コマンドの各ステ 243USB 標準コマンドのセットアップステ

244ÉCÉìÉ^ÉtÉFÅ .............................. 310, 314, 312, 315I2CÉCÉìÉ^ÉtÉFÅ ........ 310, 314, 325, 312, 315, 330ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

I2C インタフェ 314ÉåÉWÉXÉ^

I2C インタフェ 325äÑçûÇ›

I2C インタフェ 325ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

I2C インタフェ 312É^ÉCÉÄÉxÅ ........ 112, 108, 116, 113, 115, 113, 112î¦êUà¿íËë“Çøéûä‘

発振安定待ち時間とタイムベ 112ÉåÉWÉXÉ^

タイムベ 112ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

タイムベ 108ÉvÉçÉOÉâÉÄó·

402

INDEX

タイムベ 116É^ÉCÉÄÉxÅ......................................................... 110TBTC

タイムベ 110DMAÉxÅ .............................................................. 216ÉåÉWÉXÉ^

I2C インタフェ 315MB89051ÉVÉäÅ ...................................... 9, 2, 7, 8, 5ÉuÉçÉbÉNÉ_ÉCÉÑÉOÉâÉÄ

MB89051 シリ 7ïiéÌ

MB89051 シリ 5

H

HDSR

ハブディスクリプタレジスタ(HDSR1,2,3,4)188

I

I/OÉÉbÉv

I/O マップ 372I2CÉAÉhÉåÉX

I2C アドレスレジスタ (IADR)323I2CÉNÉçÉbÉNêßå‰ÉåÉWÉXÉ^

I2C クロック制御レジスタ (ICCR)321I2CÉoÉX

I2C バスシステム 327I2C バスによる通信機狽ﾌ概要 310

I2CÉoÉXêßå‰

I2C バス制御レジスタ (IBCR)318IADR

I2C アドレスレジスタ (IADR)323IBCR

I2C バス制御レジスタ (IBCR)318ICCR

I2C クロック制御レジスタ (ICCR)321ILR

割込みレベル設定レジスタ(ILR1,2,3,4) の告ｬ 33

N

ñ¾ó?

F2MC-8L 命令一覧票めいれいF2MC-8Lめいれいいちらんひょう]386

P

P53/SDA

P53/SDA と P54/SCL のノイズキャンセラ

314P54/SCL

P53/SDA と P54/SCL のノイズキャンセラ314

PURR

プルアップオプション設定レジスタ(PURR0,1,2)339

PWMÉRÉìÉyÉAÉåÉWÉXÉ^

PWM コンペアレジスタ 1(COMR1)143PWM コンペアレジスタ 1,2,(COMR1,

COMR2)133PWM コンペアレジスタ 2(COMR2)145

PWMêßå‰ÉåÉWÉXÉ^

PWM 制御レジスタ 1(CNTR1)137PWM 制御レジスタ

1,2,3(CNTR1,CNTR2,CNTR3)133PWM 制御レジスタ 2(CNTR2)139PWM 制御レジスタ 3(CNTR3)141

PWMÉ^ÉCÉ

2CH 8ビット PWMタイマの概要(PWMタイマ機 129

PWM タイマ機狽ﾌ動作 150PWM タイマ機狽ﾌプログラム例 164PWM タイマ機納 PWM たいまPWM たいまきのう ]130

R

RP

レジスタバンクポインタ (RP) の告ｬ 29

S

SCS

シリアルクロック切替えレジスタ (SCS)260

SETB

ビット操作命令 (SETB,CLRB)385STBC

スタンバイ制御レジスタ (STBC)61SYCC

システムクロック制御レジスタ (SYCC)の告ｬ 52

T

tinst

インストラクションサイクル (tinst)53

U

UART/SIO

403

INDEX

UART/SIO に関連するレジスタ 255UART/SIO の機納 UART/SIOUART/SIO のきのう ]250

UART/SIO の動作 267UART/SIO のブロックダイヤグラム 251

UCTR

USB コントロ -ルレジスタ (UCTR)220UMSKR

USB 割込みマスクレジスタ (UMSKR)226USBÉRÉìÉgÉç-ÉãÉåÉWÉXÉ^

USB コントロ -ルレジスタ (UCTR)220USBÉtÉ@ÉìÉNÉVÉáÉì

USB ファンクション回路に関連するレジスタ 209

USB ファンクション回路のブロックダイヤグラム 207

USB ファンクション動作時の割込み 236USB ファンクションの動作 239

USBópÉvÉãÉAÉbÉvêßå‰ÉåÉWÉXÉ^

USB 用プルアップ制御レジスタ(USBPC,USBP)234

USBäÑçûÇ›ÉÉXÉNÉåÉWÉXÉ^

USB 割込みマスクレジスタ (UMSKR)226

USBÉnÉu

USBハブ回路のブロックダイヤグラム181USB ハブ動作時の割込み 198USB ハブに関連するレジスタ 185USB ハブの動作 202

USBÉnÉuâÒòH

USB ハブ回路の機納 USB はぶかいろUSB はぶかいろのきのう ]180

USBÉtÉ@ÉìÉNÉVÉáÉì

USB ファンクション回路の機納 USB ふぁんくしょん

USB ふぁんくしょんかいろのきのう ]206

USBP


USBPC


W

WDTC

ドッグ制御レジスタ (WDTC)120

404

CM25-10148-XE

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

F2MC-8L

8 BIT MICRO CONTROLLER

MB89051Series

HARDWARE MANUAL

January 2004 the first edition

Published FUJITSU LIMITED Electronic Devices

Edited Business Promotion Dept.

Documents

8 BIT MICRO CONTROLLER MB89051 Series HARDWARE ......Series products original ASIC (Application Specific IC) compatible, 8-bit one-chip microcontrollers. Their application is wide-ranging