8086 Interrupts · Interrupt Structure of 8086 •2 types of Interrupts –Hardware Interrupts •Interrupts caused by External Signal –External Signal applied to the nonmaskable

8086 Interrupts

D.Murali Krishna

ECE, SVECW.

D Murali Krishna, ECE Dept, SVECW

Introduction • Polling

– It effects the throughput

• The requests from the devices are called “INTERRUPT”.

• The programs which does the service is called “Interrupt Service Routine (ISR)”


Interrupt Structure of 8086

• 2 types of Interrupts

– Hardware Interrupts

• Interrupts caused by External Signal – External Signal applied to the nonmaskable interrupts (NMI)

(pin no.17) input pin, or the interrupt (INTR)(pin no.18) input pin

– Software Interrupts

• Special Instructions in the Program – INT to execute special program

• Condition produced by instruction – Interrupted by the execution of an instruction.

– Eg: divide by zero

• 8086 supports a total of 256 interrupts.


Interrupt Response


Interrupt Response • At the end of each instruction cycle 8086 checks to see if there is

any interrupt request.

• If any request is there, 8086 performs some actions and responds to interrupt – It decrements the stack pointer by 2 and pushes the Flag register on the

stack.

– It disables the INTR interrupt by clearing the interrupt flag in the flag register.

– It resets the trap flag in the flag register.

– It decrements stack pointer by 2 and pushes the current code segment register contents on the stack.

– It decrements stack pointer by 2 and pushes the current instruction pointer contents on the stack.

– It does an indirect far jump at the start of the procedure by loading the CS and IP values for the start of the ISR

• An IRET instruction at the end of the interrupt service procedure returns execution to the main program.


Interrupt Vector Table


• Interrupt Vector Table is 1st 1k byte memory area of 1MB of 8086.

• 4 Memory Locations are assigned for each ISR address. – 1st 2 Memory locations are for offset address to be loaded in Instruction

Pointer (IP).

– Next 2 memory locations are for base address to be loaded in code segment register.

• In this way the addresses for all 256 ISRs are accommodated in 1kB memory.

• These 4 memory locations having two 16-bit addresses are called a “VECTOR”.

• Vector is also referred as “POINTER”

• The 1kB memory area for vectors starts from 00000H and ends at 003FFH.


8086 Interrupt Types

• 256 Interrupts are divided into 3 Groups

1. Type0 – Type4 :

• Used for fixed operations and hence called dedicated Interrupts.

– Divide Error (or) Divide by zero

– Single Step

– Non Maskable Interrupt

– Break Point

– Overflow


Contd.,

2. Type5 – Type31:

• Not used by 8086

• Reserved for future Processors

3. Type32 – Type255:

• Available for user and hence called user defined interrupts.

• These can be hardware interrupts and activated through INTR line of 8086 (or) can

be software interrupts.


• Divide Error (or) Divide by Zero Interrupt (Type 0):

– If the quotient from either DIV (or) IDIV instruction is too large to fit in the register, the 8086 will automatically execute “INT0” instruction

– The Corresponding “ISR” can display the error message

– Divide by zero also comes under this interrupt type


• Single Step Interrupt (Type 1): – This interrupt is used to execute the program in a Single

Step Mode

– ie., one instruction at a time and checking the results after each instruction.

– For doing this Trap Flag has to set. So if Trap Flag is set, 8086 executes “INT1” instruction after executing one instruction of the program.

– The control will go to corresponding “ISR”

– Trap Flag will be reset by CPU before transferring the control to “ISR”

– Hence complete “ISR” is executed in one operation and control will go back to main program.

– If single stepping is required during “ISR” , trap flag should be set again.


– The Trap Flag cannot be set (or) reset by a single instruction.

– To do this

• Move the contents of Flag Register to Stack Memory

• Change memory contents to set (or) reset the bit corresponding to Trap Flag and move memory contents back to Flag register.

• The instructions required are give below.

PUSHF ;

MOV BP,SP ;

OR [BP], 0100H ;

POPF ;


• Non-Maskable Interrupt (NMI) (Type 2)

– This interrupt cannot be masked (or) disabled by software instruction.

– If an external device gives a positive edge signal to this pin (No.17) then it will be register by 8086 immediately.

– 8086 will complete the instruction during which NMI became active and then executes “INT2” instruction.

– Hence the control will transferred to “ISR” of “INT2”.


• Break Point Interrupt (Type3)

– This is used to provide the break points in the program.

– It is implemented by executing INT3 instruction.

– This instruction is introduced (or) inserted any where in the program. It is called a break point.

– In the ISR, we can display registers and memory contents and verify the result.

– After ISR control will go back to the main program.

– It is used as a debugging aid.

– This technique require less time and faster compare to single stepping.


• Overflow Interrupt (Type 4):

– This interrupt is used for handling overflow(OF) error which could occur after any Singed Arithmetic Operation.

– Here “INT0” instruction is used immediately after signed arithmetic operation instead of INT4.

– If overflow flag (OF) is set the execution of INT0 will transfer the control to ISR corresponding to INT4

– Here processing of overflow condition will be done.


Contd.,

– If OF flag is not set after singed arithmetic operation, INT0 instruction will be treated as NOP instruction.

– OF can also be tested by using instruction JO immediately after signed arithmetic instruction

– If OF is set, control is transferred to address specified in JO instruction and overflow processing is done there.

– The choice of JO (or) INT0 depends on user requirements.


Type 5 – Type 31:

– These interrupts are kept for future use.

– They will be used by 80286 microprocessor onwards.

Type0 – T ype255: (Software Interrupts)

– INT instruction is used to cause any one of 256 interrupts.

– The type of interrupt to be mentioned after INT. • Eg: INT40

– It executes ISR at the address available in vector 40 of interrupt vector table.

– If you want to execute ISR2 without NMI (actually coming to 8086 CPU) INT2 instruction can be executed.

– IIIly ISR0 can be executed without divide error, but executing INT0 instruction.


• Type0-Type255: (Hardware Interrupts) – 8086 can be interrupted by external devices through

INTR input.

– This interrupt is maskable. It can be disabled (masked) by making IF = 0

– ‘IF’ can set to 0 (or) 1 by executing STI (or) CLI instruction. Once IF = 1 interrupts are accepted.

– In response to INTR, 8086 will automatically reset IF flag and sends interrupt acknowledge signal (INTA) twice.

– INTA is used by interrupting device to clear INTR line and send the interrupt type number.

– Based on the type number control will be transferred to corresponding ISR.


Priority of Interrupts

• 8086 can be interrupted by more interrupts at the same time.

• At this time priority has to be assigned so that highest priority interrupt can be served first.


Interrupt Service Routine (ISR) • It is a program which is written for a specific task (or)

interrupt.

• All ISRs will be different from each other, because each one is assigned for different tasks.

• But some activities of ISR are common to all ISRs, they are

– Save those registers on stack which will be used by ISR.

– This is to make sure that the data present in registers at the time of interrupt is not destroyed

– Now specific instruction can be written to meet the requirements of the interrupt.


Contd., – Once these instructions are executed, you need to

restore the values in the register which were saved earlier.

– The last instruction of ISR should be IRET.

• No need to save the registers which are not used by main program.


Thank you


8259 PROGRAMMABLE INTERRUPT

CONTROLLER

D Murali Krishna

Dept. of ECE, SVECW.

Introduction

• In small systems, number of devices interrupting the CPU will be less. So 2 interrupt lines (NMI, INTR) are sufficient.

• NMI is generally used for emergency situations like power failure etc.,

• So we have only one interrupt pin, which can be used for a single interrupt device.

Contd.,

• If we want to connect multiple interrupting devices to 8086, we have to use 8259 programmable interrupt controller (PIC).

• 8 interrupt devices will be connected to input of 8259 and output of 8259 will be connected to INTR pin of 8086.

• This controller can be expanded further to accept 64 interrupts by providing one master 8259 and 8 slave 8259s for this purpose.

Introduction

Internal Architecture of 8259

Contd.,

Bidirectional data buffer:

– It is 8-bit bidirectional buffer and is connected to system bus of 8086.

– 8086 send (write) the CONTROL WORDS to the 8259 & reads STATUS WORD from the 8259

– 8259 sends interrupt type to CPU on the data lines (D0-D7).

Read/Write Logic (A0,RD*,WR* and CS*):

– This block controls the data transfer (read/write) through buffer when device is selected through CS* line.

– CS* is the output of address decoder.

– A0 is used to select different command word of 8259

Contd.,

Control Logic (INT, INTA):

– This block has an input and an output line.

– If the 8259 is properly enable, the interrupt request will cause 8259 to assert its INT output pin high.

– If this pin is connected to the INTR pin of 8086, the interrupt flag of 8086 is set.

Interrupt Request Register (IRR):

– It is a 8-bit register

– This blocks has 8 i/p’s IR0-IR7

– External devices will send the interrupt request on these line

– These request will be registered by IRR, indicates how many interrupt lines are active

Contd.,

Interrupt Service Register (ISR):

– It is an 8-bit register

– This register keeps the track of which interrupts are being serviced currently.

– For each interrupt being serviced, the corresponding bit will be set.

– This register can’t be written by CPU, but is read to know the status of interrupts.

Priority Resolver (PR): – It determines the priorities of the bit set in the IRR

– The bit corresponding to the highest priority interrupt input is set in the ISR during the INTA input.

Contd.,

• Interrupt Mask Register (IMR):

– It is 8-bit register

– It is used to mask (or) disable the interrupt request inputs.

– Each bit controls one input.

– ‘Bit 0’ is for ‘IR0’ & ‘Bit1’ is for ‘IR1’ and so on.

– Logic ‘0’ in the bit will enable (unmask) the corresponding interrupt

– Logic ‘1’ in the bit will disable (mask) the corresponding interrupt

– This register can be read & write by CPU.

Contd.,

• Cascade Buffer Comparator: – This section generates the control signals necessary

for cascade operations.

– 8259 is cascaded with other 8259s to expand interrupt handling capacity.

– In this case the former is called Master and other are called slaves.

– The 8259 can be set up as master (or) slave by the SP*/EN* pin.

• If SP*/EN* = 1, for master mode

• If SP*/EN* = 0, for slave mode

Pin diagram of 8259:

Interfacing of 8259 with 8086:

Cascading of 8259s

• One 8259 can serve eight interrupts.

• If more than 8 interrupt requests are required then we have to take nine 8259’s

• One 8259 will act as a master and remaining will be slaves.

• Master 8259 will be connected to microprocessors

Contd.,

Cascading of 8259s

Contd.,

Cascading of 8259s

Master 8259

• INT of 8259 is connected to INTR of 8086

• SP/EN of 8259 is connected to VCC (+5V)

• M0 input of 8259 is connected to INT output of slave 0

• M1 is connected to INT of slave 1 , and so on.,

• Data lines D0 – D7, INTA and other control singals are directly connected to system bus of 8086.

• A0 of 8259 is connected to A1 of address bus and CS is connected to output of address decoder

• Cascade lines CAS0 – CAS2 are outputs and connected to CAS0 – CAS2 input of all slaves

Contd.,

Cascading of 8259s

Slave 8259

• INT of each slave 8259 is connected as interrupt request input of master 8259

• SP/EN of 8259 is connected to GND

• Data lines D0 – D7, INTA and other control signals are directly connected to system bus of 8086.

• A0 of 8259 is connected to A1 of address bus and CS is connected to output of address decoder

• Cascade lines CAS0 – CAS2 are inputs and connected to CAS0 – CAS2 output of master 8259

• 8 interrupt request inputs are connected to interrupting devices

Priority Modes

• 8259 has priority modes & these are under software control and can be changed dynamically

1. Fully Nested Mode (Default Mode):

– ‘IR0’ has the Highest Priority & ‘IR7’ has Lowest Priority

– Priorities are arranged in order

2. Specific Rotation Mode:

– An IR (Eg:IR3) will be assigned lowest priority

– Thus fixing the priorities of other interrupts in a cyclic manner • IR3 – Low,

• IR2 – Next Higher …….IR4 will be the highest priority

Contd.,

Priority Modes

3. Automatic Rotation Mode:

– An ‘IR’ level after being serviced gets the lowest priority

– Other priorities will get fixed in cyclic order

4. Special Fully Nested Mode (SFNM):

– It allows the highest priority interrupt from a slave to be recognized while another lower priority interrupt from the same slave is under service

END of Interrupts

• In Service Register bit gets set when an interrupt is in service

• This bit has to reset after completion of its ‘ISR’

• This is called ‘EOI’ (End of Interrupts)

• There are 3 ways to do this

Contd.,

END of Interrupts

1. Automatic EOI • In Service Register bit will be reset by last INTA*

pulse

2. Non Specific EOI • It resets the highest priority In Service Register

bit

• It is used in fully nested mode

3. Specific EOI • It resets the In Service Register bit which is

specified as a part of command

• L0 – L2 specifies which bit has to reset

Programming of 8259:

• Programmed by two sets of command words

– Initialization Command Words (ICW) • These are programmed to begin with and decide the basic operations of

8259

– Operational Command Words (OCW) • Programmed during the normal course of operation

• ICWs:

– 4 ICWs

• ICW1 & ICW2 are essential

• ICW3 &ICW4 are optional

• ICW3 is required if 8259 is to be operated in cascade mode

• ICW4 may (or) may not be needed if 8259 is interfaced with 8085

• ICW4 is needed when interfaced with 8086

• All these must issued in a sequence Contd.,

Flow chart

Contd.,


ICW1

• It is written using PORT 0 address of 8259

• It programs the basic operations

Contd.,


ICW1

Contd.,


ICW2


• It is used to specify the interrupt type number which is sent by 8259 in response to interrupt acknowledge

Contd.,


ICW3


Contd.,


ICW4


Contd.,


OCW1


Contd.,


OCW2 • It is written using PORT 0 address of 8259

Contd.,


OCW3:


Cond.,


Program1:

Cond.,


• The figure shows 8259A interfacing connections with 8086 at the address 074x. Write an ALP to initialize the 8259A in single level triggered mode with call address interval of 4, non-buffered, no special fully nested mode. Then set the 8259A to operate with IR6 masked, IR4 as bottom priority level, with special EOI mode. Set special mask mode of 8259A. Read IRR and ISR into registers BH and BL respectively. IR0 of 8259 will have type 80H

Program:

Cond.,


Solution:

Cond.,


• To initialize the 8259A in single level triggered mode with call address interval of 4, non-buffered, no special fully nested mode.

ICW1

ICW1 = 1F H

• IR0 of 8259 will have type 80H

ICW2

ICW2 = 80 H

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 1 1 1 1 1

A0 T7 T6 T5 T4 T3 A10 A9 A8

1 1 0 0 0 0 0 0 0

Solution:

Cond.,


• ICW3 not required here. So ICW3 is ICW3

ICW3 = 00 H

• Non-buffered, no special fully nested mode

ICW4

ICW4 = 01 H

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 0 0 0

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 0 0 0 0 1

Solution:

Cond.,


• Set the 8259A to operate with IR6 masked, OCW1

OCW1 = 40 H

• IR4 as bottom priority level, with special EOI mode.

OCW2

OCW2 = E4 H

A0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 1 0 0 0 0 0 0

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 1 0 0 1 0 0

Solution:

Cond.,


• OCW3 sets special mask mode of 8259A and reads IRR & ISR

• For Reading IRR OCW3

OCW3 = 6A H

• For reading ISR

OCW3

OCW3 = 6B H

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 1 0 1 0 1 0

A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 1 0 1 0 1 1

Cond.,

Programming of 8259: ALP ASSUME CS:CODE

START: MOV AL, 1FH

MOV DX, 0740H

OUT DX, AL

MOV DX, 0742H

MOV AL,80H

OUT DX, AL

MOV AL, 00H

OUT DX, AL

MOV AL,01H

OUT DX,AL

MOV AL, 40H

OUT DX, AL

Cond.,

Programming of 8259: ALP MOV AL, 0E4H MOV DX, 0740H OUT DX, AL MOV AL, 6AH OUT DX, AL IN AL, DX MOV BH, AL MOV AL, 68H OUT DX, AL IN AL, DX MOV BL, AL MOV AH,4CH INT 21H CODE ENDS END START

Program2:

Cond.,


• Interface 3 IC’s of 8259 with 8086 system in such a way that one is master and rest two are slaves connected at IR3 and IR6 interrupt request level of the master. The 8259s are having vector address 60H, 70H and 80H. Write a program to initialize 8259 PIC so that IR2 and IR7 levels of master are masked. Initialize master in AEOI mode and automatic rotation mode in minimum mode of operation

solution:

Cond.,


Solution:

Cond.,


ICW1

ICW2

D7 D6 D5 D4 D3 D2 D1 D0

M 0 0 0 1 1 1 0 1

SL3 0 0 0 1 1 1 0 1

SL6 0 0 0 1 1 1 0 1

D7 D6 D5 D4 D3 D2 D1 D0

M 0 1 1 0 0 0 0 0

SL3 0 1 1 1 0 0 0 0

SL6 1 0 0 0 0 0 0 0

Solution:

Cond.,


ICW3

ICW4

D7 D6 D5 D4 D3 D2 D1 D0

M 0 1 0 0 1 0 0 0

SL3 0 0 0 0 0 0 1 1

SL6 0 0 0 0 0 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0

M 0 0 0 1 0 0 1 1

SL3 0 0 0 0 0 0 0 1

SL6 0 0 0 0 0 0 0 1

Solution:

Cond.,


OCW1

OCW2

D7 D6 D5 D4 D3 D2 D1 D0

M 1 0 0 0 0 1 0 0

SL3 0 0 0 0 0 0 0 0

SL6 0 0 0 0 0 0 0 0

D7 D6 D5 D4 D3 D2 D1 D0

M 1 0 0 0 0 0 0 0

SL3 0 0 0 0 0 0 0 0

SL6 0 0 0 0 0 0 0 0

Cond.,


THANK YOU

UNIT – V SERIAL DATA COMMUNICATION

WITH 8086 MICROPROCESSOR

- 1 -

D.Murali Krishna Dept of ECE, SVECW

Introduction

In order to transmit/receive any information to/from the peripherals connected to µP, it needs a communication

2 types of Communications Serial Communication

Parallel Communication

3/4/2020 D MuraliKrishna, ECE, SVECW

µP External Device

Contd.,

Serial Communication:


Transmitter

Data is transmitted, on a single line

one bit at a time

one after another

Receiver

1 0 1 0 0 1 1 0

Contd.,

Introduction

Parallel Communication:


R

ecei

ver

rece

ived

• Each bit has it’s own line of wire along which it travels

• All bits are sent simultaneously

Send

er transm

itted

1

0

0

1

1

0

0

1

Introduction

Methods of data Communication:

Serial Communications is classified on the basis of how transmission occurs

Simplex • Data is transmitted only in one direction

Eg: Radio

Half Duplex • Data is transmitted in both directions but at a time only one

direction

Eg: Walkie - Talkie

Full Duplex Data is transmitted in both directions at a time

Eg : Mobile Communication

3/4/2020 D MuraliKrishna, ECE, SVECW Contd.,

Methods of data Communication:

The Data in serial communication may be sent in 2 formats

Asynchronous

Synchronous


Asynchronous:


RX TX

Contd.,

• Bits of character (or) word are sent at a constant rate, But characters can come at any rate

• When no characters are sent, a line stays high at – Logic 1 is called “Mark”

– Logic 0 is called “space”

• The beginning of a character is indicated by a Start bit (Active low)

• This is used to synchronize the ‘Tx’ and ‘Rx’

• After start bit, the data bits are sent with LSB first, followed by one (or) two stop bits (Active high)

• The Stop bits indicated at the end of character

• The combination of start, stop and data bits is known as “Frame”


Synchronous: • In this ‘Tx’ and ‘Rx’ are synchronized by having a common clock signal

• So no need of Start and Stop bits

• But here we will use “sync bits”

• Character is sent and receive at a constant rate


• To implement Serial Communication in µP, we need

– Parallel to Serial Converter

– Serial to parallel Converter

• The devices designed for this purpose are called

– Universal Asynchronous Receiver-Transmitter (UART)

– Universal Synchronous Asynchronous Receiver-Transmitter (USART)

Eg: UART - - 8250

USART - - 8251


Serial Communication Diagram


µProcessor USART Tx/Rx

USART Rx/Tx

Ext Hardware

Contd.,

Architecture of 8251:


• It includes

– Data bus buffer

– Read/Write control logic

– Transmit buffer

– Transmit Control

– Receiver Buffer

– Receiver control &

– Modem control



Data Bus Buffer :

• Bi-directional, 8-bit buffer is used to interface Block Diagram of 8251 Microcontroller to the system data bus.

• Along with the data, control word, command words and status information are also transferred through the Data Bus Buffer.

Read/Write control logic :

• It accepts inputs from the system control bus and generates control signals for overall device operation.



Transmit Buffer:

• The transmit buffer accepts parallel data from the CPU, adds the appropriate framing information, serializes it, and transmits it on the TxD pin on the falling edge of TxC.

• It has two registers :

– A buffer register to hold eight bits and an output register to convert eight bits into a stream of serial bits.

– The CPU writes a byte in the buffer register, which is transferred to the output register when it is empty.

– The output register then transmits serial data on the TxD pin.



Transmit Control :

• It manages all activities associated with the transmission of serial data.

• TxRDY (Transmit Ready ) : This output signal indicates CPU that buffer register is empty and is ready to accept a data character. This signal is reset when a data byte is loaded into the buffer register.

• TxE (Transmitter Empty) : This is an output signal. A high on this line indicates that the output buffer is empty.

• TxC (Transmitter Clock) : This clock controls the rate at which characters are transmitted by USART. – In the synchronous mode TxC is equivalent to the ‘baud rate,

which is frequency.

– In asynchronous mode TxC is 1, 16, or 64 times the baud rate.



Receiver Buffer:

• The receiver accepts serial data on the RxD line, converts this serial data to parallel format, checks for bits (or) characters that are unique to the communication technique and sends an “assembled” character to the CPU.

• In the asynchronous mode if 8251 is ready to accept a character, it looks for a low level on the RxD line.

• When it receives the RxD low level, it assumes that it is a START bit and enables an internal counter, At a count equivalent to one-half of a hit time, the RxD line is sampled again.



Receiver Buffer:

• If the line is still low, a valid START bit is detected and the 8251A proceeds to assemble the character. After successful reception of a START bit the 8251A receives data, parity and STOP bits, and then transfers the data on the receiver input register. The data is then transferred into the receiver buffer register.

• In the synchronous mode the receiver simply receives the specified number of data bits and transfers them to the receiver input register and then to the receiver buffer register.



Receiver Control:

• It manages all receiver-related activities

RxRDY (Receiver Ready) :

• This is an output signal. It goes high (active), when the USART has a character in the buffer register and is ready to transfer it to the CPU.

• This signal is reset when a data byte from receiver buffer is

read by the CPU.



Receiver Control:

RxC (Receiver Clock) :

• This clock controls the rate at which the character is to be received by USART in the synchronous mode. RxC is equivalent to the baud rate, and is supplied by the modem.

• In asynchronous mode RxC is 1, 16, (or) 64 times the baud rate.

• The clock division is programmable. It can be programmed by writing proper mode word in the mode set register.



Modem Control:

• It is used to send/receive serial data over long distances

• It is also know as Data Terminating Equipment (DTE)

• The Terminal (or) Computer which is sending (or) receiving the data is known as DTE

• Four Hand shake signals are used b/w DTE and Data circuit terminating equipment (DCE)

• DSR , DTR, CTS, & RTS



Modem Control:

• DTR (Data Terminal Ready) :

– It is o/p from DTE. On power up DTE checks itself and informs DCE that it is ready to transmit/receive data

• DSR (Data Ser Ready) :

– It is i/p to DTE. On power up DCE checks itself and informs DTE that it is ready to transmit/receive data

Contd.,



Modem Control:

• RTS (Request to Send) :

– It is o/p from DTE. When DTE wants to send data it asserts this signal to DCE. It will unassert this signal after sending the required characters

• CTS (Clear to Send)

– It is i/p to DTE. It comes from DCE. Once DCE gets RTS signal asserted it will dial long distance computer and detect the carrier. Once it is fully ready to transmit data it asserts CTS signal. DCE will unassert it after RTS is unasserted by DTE



2


Pin Description of 8251:



• Data Bus : Bi-directional, tri-state, 8-bit Data Bus. This pin allow transfer of bytes between the CPU and the 8251A.

• RD (Read) : A low on this input allows the CPU to read data or status bytes from 8251A

• WR (Write) : A low on this input allows the CPU to write data or command word to the 8251A.

• CLK (Clock) : The CLK input is used to generate internal device timing. The frequency of CLK must be greater than 30 times the receiver or transmitter data bit rates.



• RESET : A high on this input forces the 8251A into an “Idle” mode. The device will remain at “Idle” until a new set of control words is written into the Pin Diagram of 8251 to program its functional definition.

• CS (Chip Select) : A low on this input allows communication between CPU and 8251A



• C / D (Control /Data) : This input in conjuction with the WR and RD inputs, informs the 8251A that the word on the Data Bus is either a data character control word (or) status information as shown in table.



Modem Control Signals:

• The Pin Diagram of 8251 Microcontroller has a set of control inputs and outputs that can be used to simplify the interface to almost any modem.

• DTR (Data Terminal Ready) : This output signal is used to tell modem that Data Terminal is ready.

• DSR (Data Set Ready) : This input signal is used to test modem conditions such as Data Set Ready.

• RTS (Request to Send ) : This output signal is asserted to begin transmission.

• CTS (Clear to Send) : A low on this input enables the 8251A to transmit serial data if the TxE bit in the command byte is set to a “one”.



Transmitter Signals:

• TxD : Transmit data : This output signal outputs a composite serial stream of data on the falling edge of TxC.

• TxRDY (Transmitter Ready) : This output signal indicates the CPU that the transmitter is ready to accept a data character.

• TxE (Transmitter Empty) : This output signal indicates that the transmitter has no character to transmit.

• TxC (Transmitter Clock) : This clock input controls the rate at which the character is to be transmitted.



Receiver Signals:

• RxD (Receiver data) : This input receives a composite serial stream of data on the rising edge of RxC.

• RxRDY (Receiver Ready) : This output indicates that the Pin Diagram of 8251 Microcontroller contains a character that is ready to be input to the CPU.

• RxC (Receiver Clock) :This clock input controls the rate at which the character is to be received.



SYNDET (Sync Detect)/ BRKDET (Break Detect):

• This pin is used in synchronous mode for detection of synchronous characters and may be used as either input (or) output.

• In asynchronous mode this pin (output) goes high if receiver line stays low for more than 2 character times. It then indicates a break in the data stream.

• When used as an input, (external sync detect mode) an active signal will cause the 8251A to start receiving data characters on the rising edge of the next RxC.



• The operation is controlled by 2 control registers

– Mode Instruction Control Word Control Registers

– Command Instruction Control Word

– Status word

• The address of 3 registers are same

• When writing, mode word is written first and command word has to be written immediately after that

• The status register has to be read from same address


Mode Word: (Asynchronous Mode)



Asynchronous Mode Transmit & Receive Formats



Mode Word: (Synchronous Mode)



Command Word:



Status Word:



Interfacing of 8251 with 8086

Design the hardware interface circuit for interfacing 8251 with 8086.

Set the 8251A in asynchronous mode as a transmitter and receiver

with even parity enabled, 2 stop bits, 8-bit character length,

frequency 160Khz and baud rate 10K

i) Write an ALP to transmit 100 bytes of data string at a location 2000:5000H

ii) Write an ALP to receive 100 byes of data string and store it at 3000:4000H



Solution

Asynchronous mode with even parity enabled, 2 stop bits, 8-bit

character length, frequency 160Khz and baud rate 10K (TRANSMITTER)



D7 D6 D5 D4 D3 D2 D1 D0

S2 S1 EP PEN L2 L1 B2 B1

1 1 1 1 1 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0

EN IR RTS ER SBRK RXE DTR TXEN

0 0 0 1 0 0 0 1

Solution ASSUME CS: CODE

CODE SEGMENT

START : MOV AX, 2000H

MOV DS, AX

MOV SI, 5000H

MOV CL, 64H

MOV AL, 0FEH

MOV DX, MIR ADDR

OUT DX, AL

MOV AL, 11H

OUT DX, CIR ADDR

OUT DX, AL



Solution REPEAT: MOV DX, SR ADDR WAIT: IN AL, DX SHR AL,01 JNC WAIT MOV AL, [SI] MOV DX, Tx BUFF ADDR OUT DX, AL INC SI DEC CL JNZ REPEAT MOV AH, 4CH INT 21H CODE ENDS END START



ii) Asynchronous mode with even parity enabled, 2 stop bits, 8-bit

character length, frequency 160Khz and baud rate 10K (RECEIVER)



D7 D6 D5 D4 D3 D2 D1 D0

S2 S1 EP PEN L2 L1 B2 B1

0 1 1 1 1 1 1 0

D7 D6 D5 D4 D3 D2 D1 D0

EN IR RTS ER SBRK RXE DTR TXEN

0 0 0 1 0 1 0 0

Solution ASSUME CS: CODE

CODE SEGMENT

START : MOV AX, 3000H

MOV DS, AX

MOV SI, 4000H

MOV CL, 64H

MOV AL, 7EH

MOV DX, MIR ADDR

OUT DX, AL

AGAIN: MOV AL, 14H

MOV DX, CIR ADDR

OUT DX, AL



Solution REPEAT: MOV DX, SR ADDR NXT BYTE: IN AL, DX AND 38H JZ CHECKRx JMP AGAIN CHECKRx: IN AL, DX AND 02H JZ CHECKRx MOV DX, Rx BUFFADDR IN AL, DX MOV [SI], AL INC SI DEC CL JNZ AGAIN MOV AH, 4CH INT 21H CODE ENDS END START





- 3 -


RS 232 for Serial Communication

RS (Recommended Standard) 232-C:

• Electronic Industries Association (EIA) developed EIA standard RS 232-C.

• It describes the standard for data and handshaking signals b/w – DTE (Data Terminal Equipment) &

– DCE (Data Communication Equipment)

• Total 25 signals are defined. For these 25 pin connector is used.

• DTE connector should be male & DCE connector should be female

• The most commonly used connector is DB-25.

For those systems where all 25 signals are not used, 9- pin connectors are used.


RS 232-C Interface:

9-pin connectors 25-pin connectors

• Three wires are sufficient:

• Transmit data,

• Receive data and

• Signal ground

• The remaining lines can be hardwired on (or) off permanently.


RS 232-C Interface:

Pin Description of RS 232C


• RS-232C standards also defines the voltage level of the signals.

Logic High (-3v to -15v) under load

(-3v to -25v) under no load

Logic Low (+3v to +15v) under load

(+3v to +25v) under no load

• The length of cable b/w DTE and DCE can be maximum of 50 feet.

• Maximum speed of data transfer is 20k baud.


RS 232-C Interface:

RS 232-C Interface:

TTL to RS232C & RS232C to TTL Conversion

• 8251 USART Input & Output signals are TTL compatible

• So these signals to be converted to RS232C levels and send via RS232 cable to DCE (Modem). At DCE, again these signals should be converted from RS232 to TTL and Vice Versa

• IC’s MC 1488 will convert TTL to RS232C &

MC1489 RS232 to TTL


RS 232-C Interface:

TTL to RS232C & RS232C to TTL Conversion


RS 232-C Interface:

Configuration b/w DTE and DCE


RS 232-C Interface:

RS 232 cable


DTE and DCE Connection


RS 232-C Interface:

Connecting of 2 computers


RS 232-C Interface:

PARAMETER RS232 RS422 RS485

Number of devices

One transmit and one

receive

Five transmitters and ten

receivers

32 transmitters and 32

receivers

Communication

mode Full duplex Full duplex / half duplex Half duplex

Maximum distance 50 feet at 19.2 kbps 4000 feet at 100 kbps 4000 feet at 100 kbps

Maximum data rate 19.2 kbps at 50 feet 10 Mbps at 50 feet 10 Mbps at 50 feet

Signalling mode Unbalanced Balanced Balanced

Mark (1) -5 to -15 V 2 V to 6 V max. (B>A) 1.5 V to 5 V max. (B>A)

Space (0) +5 to +15 V 2 V to 6 V max. (A>B) 1.5 V to 5 V max. (A>B

Output current

capability 500 mA 150 mA 250 mA


High-speed serial communication standards:


THANK YOU



- 4 -

USB


Universal Serial Bus (USB):

• Universal Serial Bus is the definition of Connectivity.

Features of USB

• USB acts as "plug and play" device.

• USB device has a maximum speed up to 480 Mbps (for USB 2.0)

• Length of individual USB cable can reach up to 5 meters without a hub and 40 meters with hub.

• A maximum of 127 peripherals can be connected to a single USB host controller.

• USB can draw power by its own supply (or) from a computer.

• USB devices use power up to 5 voltages and deliver up to up to 500 mA.


Features of USB

• If a computer turns into power-saving mode, some USB devices will automatically convert themselves into "sleep" mode.

USB Speed: USB supports 3 types of speed

• Low speed (1.5 Mbps)

• Full speed (12 Mbps)

• High speed (480 Mbps)


USB Connector:

• It is a 4-pin connector

USB Hub:

• Computers have 1 (or) 2 USB connectors

• HUB is required if more no. of USB’s have to be connected to Computer.

• A HUB will have 4 (or) more new USB ports

• HUBs can be powered (or) Unpowered


Pin Number Signal

1 +5V

2 -Data

3 +Data

4 Ground

Contd.,

USB Data:

• USB is serial bus means there is only one line transmitting signals.

• Hence 1 bit can be sent at a time. The bytes are written & read from LSB to MSB

• USB employs NRZI (Non return Zero Invert) data encoding when transmitting packets of data. – In this encoding a ‘1’ is represented by no change in level

– ‘0’ is represented by a change in level


USB Protocols:

• USB is a serial Interface

• The information sent is organized in the form of packets and frames

• This is done to provide error checking, flow control and to synchronize the devices

• Each USB transaction consists of

– Token Packet : It indicates the type of transaction to follow

– Handshake Packet : It is used for acknowledging data (or)

reporting error

– Start of Frame Packet : It is used to indicate start if new frame

– Data Packet : It contains payload


USB Packet fields:

• Packet consists of several fields – SYNC

– PID ( Packet Identifier)

– Address

– Frame Number

– Data

– CRC

– ENDP

– EOP

‘SYNC’ & ‘PID’ fields are standard for all packets where as other are specific for a particular type packet.


SYNC Filed:

• All packets must start with SYNC

• It is 8-bit long at low and full speed &

32-bit long for high speed

• It is used to synchronize the clock of a ‘RX’ with ‘TX’

• The last two bits are a marker to identify the end of sync filed and start of PID filed

PID filed:

• Used to identify the type of packet that is being sent

• It is an 8-bit filed and consists of – 4-bit packet type followed by

– 4-bit check filed

• Check filed is used to make sure that packet type filed is received correctly

• Check filed is generated by performing ones complement on packet type filed


PID3’ PID2’ PID1’ PID0’ PID3 PID2 PID1 PID0

Contd.,

Address Field:

• It is a 7-bit filed & specifies for which device the packet is designed

• Total 127 devices are supported.

• ‘0’ address is invalid

Frame Number Filed:

• It is an 11-bit filed that is incremented by the host on per framed basis

• Upon reaching the max. value (7FFH), the frame number filed rolls over

Data Filed:

• It varies from ‘0’ to ‘1024’ bytes

• It should always be multiple of bytes

• Data bits with in a byte are always shifted out with LSB first

• Data packet size varies with transfer type


Addr6 Addr5 Addr4 Addr3 Addr2 Addr1 Addr0

Contd.,

CRC Filed:

• Cyclic Redundancy Checks are performed on the data within the packet payload

• The packet is not included in the CRC check of a packet

• All CRC’s are generated for their respective fields in the Tx before bit stuffing is performed. |||ly CRCs are decoded in the receiver after stuff bit have been removed.

All token packets have 5 bit CRC while data packet have a 16 bit CRC

ENDP filed:

• The end point filed consists of four bits.

• It allows us to have 16 different end points.

EOP filed:

• End of packet filed.

• It is signaled by a single ended zero (SE0) for approximately two bit time followed by a 1 for 1 bit time


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