8120 M Tellabs Node Operating Manual

Tellabs® 8100 Managed Access SystemTellabs® 8120 Mini Node M Operating Manual

22030_1207.01.2013

Document Information

Revision History

DocumentNo.

Date Description of Changes

22030_12 07.01.2013 The Tellabs 8120 mini node has been discontinued. A discontinuationnote has been added in ch. 1.

22030_11 09.03.2009 Erroneous V35-M discontinuation note removed throughout thedocument.

22030_10 29.08.2008 Layout and cross reference changes due to format conversion throughoutthe document.

22030_09 02.11.2007 Safety notes related to grounding updated in chapters 4.5 and 6.11.Outdated data removed from the foreword.Figures 2, 24, 25 and 40 updated.The list of numbered items referring to the mechanical constructionupdated in chapter 4.8.Disassembling instructions updated in chapter 4.8.1.EMC standard updated in chapter 6.12.

© 2013 Tellabs. All rights reserved.

This Tellabs manual is owned by Tellabs or its licensors and protected by U.S. and international copyright laws, conventions andtreaties. Your right to use this manual is subject to limitations and restrictions imposed by applicable licenses and copyright laws.Unauthorized reproduction, modification, distribution, display or other use of this manual may result in criminal and civil penalties.The following trademarks and service marks are owned by Tellabs Operations, Inc. or its affiliates in the United States and/or

other countries: TELLABS®, TELLABS® logo, TELLABS and T symbol®, and T symbol®.

Any other company or product names may be trademarks of their respective companies.

The specifications and information regarding the products in this manual are subject to change without notice. All statements,information, and recommendations in this manual are believed to be accurate but are presented without warranty of any kind,

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Adobe® Reader® are registered trademarks of Adobe Systems Incorporated in the United States and/or other countries.

Tellabs® 8100 Managed Access System 22030_12Tellabs® 8120 Mini Node M Operating Manual © 2013 Tellabs.

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Document Information

Terms and Abbreviations

Term Explanation

ADPCM Adaptive Differential Pulse Code Modulation

AIS Alarm Indication Signal

CAS Channel Associated Signalling

CRC Cyclic Redundancy Check

DMA Deferred Maintenance Alarm

FAS Frame Alignment Signal

FrFEA Frame Far-end Alarm

HDLC High Level Data Link Control

IF Interface

MEI Maintenance Event Information

MFrFEA Multiframe Far-end Alarm

PMA Prompt Maintenance Alarm

RAI Remote Alarm Indication

TS Time Slot

VF Voice Frequency

Compliance Statement

Hereby, Tellabs Oy declares that this product is in compliance with the essential requirements andother relevant provisions of Directive 1999/5/EC.

22030_12 Tellabs® 8100 Managed Access System© 2013 Tellabs. Tellabs® 8120 Mini Node M Operating Manual

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Table of Contents

Table of Contents

About This Manual .............................................................................................................. 9

Objectives......................................................................................................................................................................... 9Audience........................................................................................................................................................................... 9Discontinued Products...................................................................................................................................................... 9Document Conventions .................................................................................................................................................... 9Documentation Feedback............................................................................................................................................... 10

1 Introduction ................................................................................................................. 11

1.1 Construction..........................................................................................................................................................11

2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element.................................. 13

2.1 General................................................................................................................................................................. 132.2 Framed Interfaces IF1 and IF2 ............................................................................................................................ 142.3 User Access Ports ................................................................................................................................................ 16

2.3.1 Unframed Interfaces ............................................................................................................................ 162.3.2 Framed Interface as User Access Port ................................................................................................. 172.3.3 Rules for Mixing Different Interface Types ........................................................................................ 17

2.4 Applications......................................................................................................................................................... 172.4.1 Framed Interfaces ................................................................................................................................ 172.4.2 Unframed Interfaces ............................................................................................................................ 20

2.5 Network Synchronization .................................................................................................................................... 23

3 Operation .....................................................................................................................25

3.1 General................................................................................................................................................................. 253.2 G.704 Framed Interfaces IF1 and IF2 ................................................................................................................. 26

3.2.1 Frame and Multiframe Structure ......................................................................................................... 273.2.2 Buffers ................................................................................................................................................ 283.2.3 Split Trunk Lines ................................................................................................................................. 303.2.4 1+1 Protection ..................................................................................................................................... 30

3.3 Operation of Framed Interfaces ........................................................................................................................... 313.4 Unit Controller..................................................................................................................................................... 343.5 Cross-Connect Block........................................................................................................................................... 35

3.5.1 Cross-Connection ................................................................................................................................ 353.5.2 Master Clock Synchronization ............................................................................................................ 37

3.6 Operation of Unframed Channel Interfaces IF3-IF6 ........................................................................................... 38


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Table of Contents

3.6.1 Data Formatting Functions .................................................................................................................. 393.6.2 Data Interfaces..................................................................................................................................... 433.6.3 Timing Modes...................................................................................................................................... 433.6.4 Rate Adaptation and Mapping............................................................................................................. 463.6.5 Cross-Connection of Unframed Interfaces .......................................................................................... 48

3.7 Test Resources ..................................................................................................................................................... 493.7.1 Equipment Test .................................................................................................................................... 493.7.2 Test of Framed Interfaces .................................................................................................................... 503.7.3 Tests of Unframed Interfaces............................................................................................................... 53

4 Installation ................................................................................................................... 56

4.1 Front Panel Indicators and Controls .................................................................................................................... 564.2 Back Panel Connections ...................................................................................................................................... 564.3 Mains Connection................................................................................................................................................ 584.4 Operating Environment ....................................................................................................................................... 58

4.4.1 DC Power Supply Cabling .................................................................................................................. 594.4.2 SC, Local Service Computer Connector.............................................................................................. 604.4.3 SYNC Connector ................................................................................................................................. 60

4.5 Configuration of Tellabs 8120 Mini Node M ...................................................................................................... 604.5.1 NMS Control ....................................................................................................................................... 624.5.2 Local Control ....................................................................................................................................... 62

4.6 Menus of Tellabs 8120 Mini Node M ................................................................................................................. 634.6.1 Security Menu...................................................................................................................................... 684.6.2 Faults Menu ......................................................................................................................................... 714.6.3 Parameters Menu ................................................................................................................................. 724.6.4 Interface Parameters Menu.................................................................................................................. 754.6.5 Cross-Connection Menu ...................................................................................................................... 804.6.6 Copy Settings Menu ............................................................................................................................ 864.6.7 Entering Security Menu of Tellabs 8120 Mini Node M...................................................................... 87

4.7 Recommended Settings of Framed Interfaces ..................................................................................................... 874.7.1 Framed Interface Used as 2048 kbit/s Trunk....................................................................................... 874.7.2 Framed Interface Used as 2048 kbit/s User Access Point ................................................................... 884.7.3 Framed Interface Used as 8448 kbit/s Trunk....................................................................................... 894.7.4 BTE-384-M Settings............................................................................................................................ 904.7.5 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Settings ......................................... 914.7.6 Cross-Connection Example ................................................................................................................. 934.7.7 Binary-to-Hexadecimal Conversion Table .......................................................................................... 93

4.8 Service Operations and Modifications................................................................................................................. 944.8.1 Instructions on Disassembling Tellabs 8120 Mini Node M ................................................................ 96

4.9 Unit List of Tellabs 8120 Mini Node M.............................................................................................................. 974.9.1 Common Units..................................................................................................................................... 974.9.2 Main Interface Modules....................................................................................................................... 984.9.3 V Series Interface Modules ................................................................................................................. 99

4.10 Connectors and Strappings of Framed Interfaces.............................................................................................. 1004.10.1 G703-75-M and G703-120-M, G.703 2 Mbit/s ................................................................................. 1004.10.2 LTE-M Line Terminal 1 or 2 Mbit/s.................................................................................................. 1024.10.3 G703-8M-M, 8 Mbit/s ....................................................................................................................... 1034.10.4 OTE-LED-M, Optical LED, 2 or 8 Mbit/s ........................................................................................ 1034.10.5 BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M, 384 kbit/s…4224

kbit/s .................................................................................................................................................. 1044.10.6 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M, 320…2304 kbit/s ....................... 106


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Table of Contents

4.10.7 V35-G704-SM, V.35 n x 64 kbit/s…2 Mbit/s ................................................................................... 1074.10.8 X21-G704-SM, n x 64 kbit/s…2Mbit/s............................................................................................. 108

4.11 Connectors and Strappings of Unframed Interfaces.......................................................................................... 1094.11.1 V35-M, V.35 48, 56, n x 64 kbit/s Interfaces, 2 pcs .......................................................................... 1094.11.2 V36-M, V.36 48, 56, n x 64 kbit/s Interfaces, 2 pcs ...........................................................................1104.11.3 V24-DCE-M, V.24/V.28 if/DCE, 0.6…64 kbit/s, 2 pcs .....................................................................1124.11.4 V24-DTE-M, V.24/V.28 if/DTE, 0.6…64 kbit/s, 2 pcs ......................................................................1134.11.5 X21-M, X.21 1.2…n x 64 kbit/s Interface, 2 pcs ...............................................................................1144.11.6 G703-64-M, G.703 64 kbit/s Co/Contradirectional Interface, 2 pcs ..................................................1154.11.7 V35/V24-M, V.24/V.28 if/DCE, 0.6…64 kbit/s; V.35-IEC if, n x 64 kbit/s.......................................1164.11.8 HSSI-M, TIA/EIA 612, 0.6…8448 kbit/s ..........................................................................................1174.11.9 Mini LAN Module, 10Base-T, 64…2048 kbit/s.................................................................................119

4.12 Software Update ................................................................................................................................................ 1204.12.1 Downloading Tellabs 8120 Mini Node M Software ......................................................................... 1204.12.2 Replacing EPROMs........................................................................................................................... 121

5 Faults and Actions .................................................................................................... 123

5.1 Terminology....................................................................................................................................................... 1235.2 Common Faults and Actions ............................................................................................................................. 124

5.2.1 Common Logic Faults (Block 0) ....................................................................................................... 1245.2.2 Master Clock Faults (Block 0)........................................................................................................... 1255.2.3 Cross-Connect Block Faults (Block 0).............................................................................................. 1255.2.4 Faults of Framed IF Tx Signal (Block 1, 2) ..................................................................................... 1265.2.5 Faults of Framed IF Rx Signal (Block 1, 2) ...................................................................................... 1275.2.6 1+1 Protection Switch Fault Messages (Block 0) ............................................................................. 1305.2.7 Miscellaneous Faults of Framed Interfaces (Block 1, 2)................................................................... 1305.2.8 Fault and Service Status (PMA, DMA, MEI, S) in 1+1 Mode of Framed Interfaces ....................... 1305.2.9 Fault Conditions of Framed Interfaces .............................................................................................. 131

5.3 Faults and Actions of Unframed Interfaces...................................................................................................... 1325.3.1 General IF Faults of Unframed Interfaces ......................................................................................... 1325.3.2 IF Signal Faults of Unframed Interfaces ........................................................................................... 1335.3.3 Net Side Signal Faults of Unframed Interfaces ................................................................................. 1335.3.4 Test Loop Activation of Unframed Interfaces ................................................................................... 1345.3.5 Performance Conditions of Unframed Interfaces.............................................................................. 1345.3.6 Common Faults of Unframed Interfaces ........................................................................................... 1355.3.7 Reference Points of Unframed Interfaces.......................................................................................... 135

6 Technical Specifications of Tellabs 8120 Mini Node M.......................................... 136

6.1 Relevant Recommendations .............................................................................................................................. 1366.2 Cross-Connect ................................................................................................................................................... 1376.3 Timing................................................................................................................................................................ 1386.4 G.704 Framed Interface..................................................................................................................................... 138

6.4.1 Frame and Multiframe Buffer............................................................................................................ 1386.4.2 8448 kbit/s Interface (CCITT G.704) ................................................................................................ 1396.4.3 2048 kbit/s Interface (CCITT G.704/706)......................................................................................... 1406.4.4 N x 64 kbit/s Interface with G.704 Type Frame ................................................................................ 141

6.5 Unframed Data Interfaces.................................................................................................................................. 1426.5.1 V.24/V.28,V.35,V.36/V.11; 1.2…19.2 kbit/s, 48, 56, n x 64 kbit/s .................................................... 142


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Table of Contents

6.5.2 X.21 1.2…19.2 kbit/s, 48, 56, n x 64 kbit/s....................................................................................... 1436.5.3 Transparent 2 Mbit/s, n x 64 kbit/s .................................................................................................... 143

6.6 Data Interface Modules ..................................................................................................................................... 1436.6.1 8448 kbit/s, G.703 Interface (G703-8M-M Module) ........................................................................ 1436.6.2 2048 kbit/s, G.703 Interface (G703-75-M) ....................................................................................... 1446.6.3 2048 kbit/s, G.703 Interface (G703-120-M) ..................................................................................... 1446.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module)............................................ 1446.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module) ......................................... 1456.6.6 Baseband Line Interface 64…384 kbit/s (BTE-384-M Module) ...................................................... 1456.6.7 Baseband Line Interfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M, BTE-2048-2W-M,

BTE-4096-M, BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules) ............. 1466.7 Service Computer (SC) Interface ...................................................................................................................... 1466.8 Power Supply..................................................................................................................................................... 147

6.8.1 Power Consumptions of Tellabs 8120 Mini Node M Units and Modules......................................... 1476.9 Mechanics.......................................................................................................................................................... 1486.10 Environmental Conditions................................................................................................................................. 148

6.10.1 Climatic/Mechanical Compatibility .................................................................................................. 1486.11 Safety Compatibility.......................................................................................................................................... 1496.12 Electromagnetic Compatibility.......................................................................................................................... 149

Appendix 1: Frame Structures ...................................................................................... 150

Frame Structures at Bit Rates 48…2048 Kbit/s ........................................................................................................... 150Frame Structures at Bit Rates below 48 Kbit/s ............................................................................................................ 157

Appendix 2: G.704 Frame Structures............................................................................ 162

8448 kbit/s Frame Structure ......................................................................................................................................... 1622048 kbit/s Frame Structure ......................................................................................................................................... 163N x 64 kbit/s Frame Structure ...................................................................................................................................... 164Multiframe Structure in Signalling Time Slot.............................................................................................................. 166CRC Multiframe Structure in TS0 for 2 Mbit/s and n x 64 kbit/s Frames................................................................... 167


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About This Manual

About This Manual

This section discusses the objectives and intended audience of this manual, Tellabs® 8100 ManagedAccess System Tellabs® 8120 Mini Node M Operating Manual and consists of the followingsections:

• Objectives

• Audience

• Discontinued Products

• Document Conventions

• Documentation Feedback

Objectives

The goal is to describe the network element features of Tellabs 8120 mini node M and its installation.

Audience

This manual is intended for system specialists and personnel involved in network planning.

Discontinued Products

Tellabs® 8100 Managed Access System Discontinued Products list can be found in Tellabs Portal,www.portal.tellabs.com by navigating to Product Documentation > Managed Access > Tellabs8100 Managed Access System (Includes all 81XX products) > Technical Documentation >Network Element Manuals > 8100 List of Discontinued Products.

Document Conventions

This is a note symbol. It emphasizes or supplements information in the document.

This is a caution symbol. It indicates that damage to equipment is possible if the instructionsare not followed.

This is a warning symbol. It indicates that bodily injury is possible if the instructions are notfollowed.


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https://www.portal.tellabs.com

About This Manual

Documentation Feedback

Please contact us to suggest improvements or to report errors in our documentation:

Email: [email protected]

Fax: +358.9.4131.2430


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1 Introduction

1 Introduction

The Tellabs 8120 mini node M has been discontinued.

This operating manual describes the version 6.1 or later of Tellabs® 8120 mini node M (SBM2048M).

Tellabs® 8120 mini node M (SBM 2048M) is a small cross-connect device, which can operateeither as part of the Tellabs® 8100 managed access system network connected to Tellabs® 8000network manager, or as a separate cross-connect device controlled and supervised locally. Thispiece of equipment can be furnished with up to two framed interfaces and up to two unframedinterface modules (usually two interfaces per module). Tellabs 8120 mini node M can makeconnections between interfaces of any type.

The transmission rates and physical features of the interfaces depend on the used interface modules.Different interface modules are available for different applications.

The transmission rates of framed interfaces are 2048 kbit/s, 8448 kbit/s and n x 64 kbit/s, wheren = 2…33. The frame structure of a framed interface is according to CCITT G.704. The modifiedG.704 frame is used at n x 64 kbit/s. The transmission rates of unframed interfaces can be0.6…2048 kbit/s. The interfaces can, for example, be V.35, V.36, V.24 or X.21 depending onthe used interface module.

The configuration and control of Tellabs 8120 mini node M can be applied in different ways. As partof the Tellabs 8100 network, the control can be realised through Tellabs 8000 manager, where thecontrol channel is connected to the device through a framed interface. On the front panel there is aconnector for the service computer, which can manage the configuration and control with a userinterface with windows. The front panel of Tellabs 8120 mini node M is provided with an LCDdisplay and keyboard (four buttons) which can handle the menu controlled user interface controlfunctions needed when using Tellabs 8120 mini node M.

1.1 Construction

Tellabs 8120 mini node M is built into a compact metallic case. It is suitable for tabletop use. Underthe metallic cover there are the following parts:

• main unit

• switching power supply unit (AC or DC)

• channel board

• two user access interface modules

• two framed interface modules

On the front panel there are an LCD display with 2 x 24 characters, four pushbuttons, alarm LEDsfor each channel and a connector for the service computer.


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1 Introduction

Fig. 1 Tellabs 8120 Mini Node M Front Panel

On the back panel of Tellabs 8120 mini node M there are the interface connectors, a power cord,the synchronization connectors and a measurement point connector. The connector type dependson the module in use.

The connectors for framed interfaces IF1 and IF2 are on the lower part of the back panel and theconnectors for user access ports on the upper part.

Fig. 2 Example of Tellabs 8120 Mini Node M Back Panel Connectors

A framed interface module has one interface. The type for interfaces IF1 and IF2 can be selectedirrespective of each other. An unframed interface module has typically two interfaces which are ofthe same type. The desired combination of modules can be selected for one piece of equipmentaccording to the unit list. For further details and possible exceptions refer to 4.9 Unit List of Tellabs8120 Mini Node M.

For example in Fig. 2, the connectors for the framed interfaces IF1 and IF2 are on the bottom row ofthe back panel and the connectors for the user access ports at the upper part of it. In this examplethe interface IF1 is G703-75-M, and the interface IF2 is OTE-LED-M. The interfaces IF3 and IF4are of type V.36, and the interfaces IF5 and IF6 are of type V.35.


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2 Tellabs 8120 Mini Node M as Tellabs 8100 Network Element

2 Tellabs 8120 Mini Node M as Tellabs 8100Network Element

2.1 General

Tellabs 8120 mini node M is connected through the framed interfaces to another Tellabs 8120 mininode or a corresponding piece of equipment, a Tellabs 8100 node, the public transmission networkor another transmission device with a G.703/G.704 interface. The interfaces with which Tellabs8120 mini node M is connected to the Tellabs 8100 network or to another similar piece of equipmentare called trunk interfaces in this manual. Tellabs 8120 mini node M can also be described as adigital multiplexer equipped with two trunk interfaces. Like an ordinary multiplexer, it can supportchannel interfaces. The cross-connect function of the equipment is independent of the channelinterfaces. This facilitates the flexible implementation of different channel interfaces.

Fig. 3 Architecture of Tellabs 8120 Mini Node M

The trunk interfaces are provided with the CCITT G.704/706 compliant frame structure. The systemuses a synchronous time slot interleaved framing. A part of the frame is reserved for the internalinformation transfer of the system (frame alignment, CRC check, network management channel).For example, in the 2 Mbit/s G.704 frame this information is typically in time slot TS0. These timeslots of the trunk lines are never used for transporting cross-connect channels (XB/XD channels).

The user access interfaces can be divided into two main categories:

• unframed user data

• G.704 framed user data

A framed interface can also be a user access interface.

Cross-connections can be made in accordance with the following:


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• framed/framed

• framed/unframed

• unframed/unframed

When an interface is used for cross-connection, it is called a port. The mapping of the user accessports to the trunks by the cross-connect are based on the following signals:

• time slots: n x 64 kbit/s

• time slot bits: n x 8 kbit/s

The n x 8 kbit/s and n x 64 kbit/s groups mapped by the channel interfaces are called XB channels.The XB channel can also be a combination of 64 kbit/s and 8 kbit/s signals.

Fig. 4 XB and XD Channels

If the interfaces are equipped with signalling or control signals, they are either mapped to the XBchannel or to the corresponding signalling bits (n x 500 bit/s) of the XB channel. In the lattercase the signals are mapped into the G.704-compliant multiframe of the 2 or 8 Mbit/s trunk. Then x 500 bit/s signalling bits are called the XD channel of the interface. Unframed interfaces donot normally use the XD channel.

2.2 Framed Interfaces IF1 and IF2

In most cases the framed interfaces of Tellabs 8120 mini node M are used as trunk interfaces. Theframed interfaces (IF1, IF2) provided by Tellabs 8120 mini node M are shown in the table below.(The modules are electrically, but not mechanically, identical with the modules in the GMH unitof the Tellabs 8100 system.)


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Framed Interface Modules

Module Type ElectricalInterface

Bit Rate XB/XD Capacity1

BTE-384-M2 2W/4WBiphasecode

n= 2…6 n-2 TS for XB channels1 TS for XD channels4

BTE-320-M2 2W2B1Q code

n=5 n-1 TS for XB channels


n=5, 9 n-1 TS for XB channels

BTE-1088-2W-M2

2W/4W2B1Q code

n=5, 9, 16, 17 n-1 TS for XB channels


n=16, 17, 32, 33 n-2 TS for XB channels1 TS for XD channels4

BTE-2048-2W-M2

2W2B1Q code

n=16, 17, 32, 33 n-1 TS for XB channels


n=5, 9, 17 n-2 TS for XB channels1 TS for XD channels4

BTE-2304-M2 2W/4W2B1Q code

n= 16, 17, 32, 33, 34,36

n-1 TS for XB channels


n= 16, 17, 82, 33, 64,66

n-2 TS for XB channels1 TS for XD channels4

1088 kbit/s n-2 TS for XB channels1 TS for XD channels4

LTE-M2, 3 LTE

2048 kbit/s 30 TS for XB channels1 TS for XD channels4

V35-G704-SM2 V.36/V.11 n x 64 kbit/sn = 2…33


X21-G704-SM2 V.11 n x 64 kbit/sn = 2…33



OTE-LED-M OpticalLED


5 spare TS5

G703-75-M G.703 2048 kbit/s 30 TS for XB channels1 TS for XD channels4

G703-120-M G.703 2048 kbit/s 30 TS for XB channels1 TS for XD channels4

G703-8M-M2 G.703 8448 kbit/s 120 TS for XB channels4 TS for XD channels4

5 spare TS5

1TS = 64 kbit/s time slot.2The interface module has been discontinued.3LTE = integrated line terminal.4XD time slots can be turned off and used as XB time slots.5One is used for HDLC. These five XB time slots do not have XD channels associated with them.


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2.3 User Access Ports

2.3.1 Unframed Interfaces

Tellabs 8120 mini node M supports two channel interface modules.

Unframed Channel Interface Modules

Module Type Electrical Interface Bit Rate

V35-M, V36-M6 V.35 or V.36/V.11 0.6…4224 kbit/s7

V24-DCE-M6

V24-DTE-M6V.24/V.28 0.6…64 kbit/s

V35/V24-M6 V.24/V.28V.35-IEC

0.6…64 kbit/s /0.6…8192 kbit/s8

X21-M X.21/X.27 0.6…4224 kbit/s7

G703-64-M6 G.703 co/contradir 64 kbit/s

HSSI-M6 TIA/EIA 612 0.6…8448 kbit/s

Mini LAN Module9 10Base-T Ethernet 64…2048 kbit/s

The modules are electrically, but not mechanically, identical with the modules in the channel unitof the Tellabs 8100 system.

The functions of these data interfaces are

• V.110 rate adaptation for bit rates ≤ 56 kbit/s

• CRC end-to-end monitoring possible with all bit rates

• control signal transmission through the network (V.13 simulated carrier or in the V.110 frame)

• interface, local and V.54 remote loops

One end of the circuit can be any other data interface or a G.704 user access point in another Tellabs8120 mini node or in a Tellabs 8100 node. The circuit types can be

• point-to-point (pp)

• broadcast (bc)

Tellabs 8120 mini node M does not support the point-to-multipoint server functions as the channelunit in the Tellabs 8100 node. The user interfaces, however, can be connected as end points to apoint-to-multipoint circuit when the Point-to-Multipoint (pmp) Servers (branch points) are in theTellabs 8100 nodes.

6The interface module has been discontinued.7The maximum bit rate per module is 8448 kbit/s. This capacity can be divided between two channels in the modules V35-M, V36-M and X21-M.Tellabs recommends the HSSI-M module for usage above 2 Mbit/s bit rates as it offers the possibility to have more cable length.8Tellabs recommends the HSSI-M module for usage above 2 Mbit/s bit rates as it offers the possibility to have more cable length.9The technical name SMU-BRIDGE can be seen in Tellabs 8000 manager.


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2.3.2 Framed Interface as User Access Port

Framed n x 64 kbit/s, 2 Mbit/s or 8 Mbit/s interfaces can be used as user access interfaces in whichcase the interfaces are called G.704 user access ports which means that there is no HDLC channel.In principle, the framed interfaces provide the same features as the corresponding trunk interfaces.A framed channel interface can offer several user access ports. A 2 Mbit/s G.704 user access portcan comprise the following time slots and time slot fractions.

Cross-ConnectableTime Slot Fractions

XB XD

n x 64 kbit/s n x 64 kbit/s n x (a, b, c, d)

32 kbit/s 32 kbit/s a, b/c, d

16 kbit/s 16 kbit/s a/b/c/d

8 kbit/s 8 kbit/s -

A typical G.704 user access port is a 2 Mbit/s interface for a digital PABX.

2.3.3 Rules for Mixing Different Interface Types

Usually, both ends of the connection use the same interface type. In some cases it is possible to mixdifferent interface types. Different electrical interfaces are not usually of major concern.

At least the following points must be checked between both ends:

• same use of control bits in V.110 frame

• same XB/XD capacity

• same XB framing of data circuits (V.110, modified V.110, no framing)

The structure of the XB/XD channel is not normally transported outside the network. It is, however,very easy to do by using the G.704 framed user access port. In this case the standard proceduresshould be used:

• V.110 framing (≤56 kbit/s)

• V.13 simulated carrier (V type interfaces ≥64 kbit/s)

• X.30-specified X.21 C/I mapping (X.21 ≤48 kbit/s)

2.4 Applications

2.4.1 Framed Interfaces

There are different applications for the transmission rate and the features of the framed interfaces inTellabs 8120 mini node M.

Fig. 5 presents the different ways to interconnect two Tellabs 8120 mini node M devices. The samealternatives are available when connecting Tellabs 8120 mini node M to a Tellabs 8100 node.


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Fig. 5 Tellabs 8120 Mini Node M Trunk Lines


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BTE Modules

The BTE modules10 serve baseband transmission at rates 128-4224 kbit/s. The frame structure is amodified G.704 frame, where the overhead of 64 kbit/s is used for the frame structure. The availabletransmission rate for the terminal equipment is the line rate subtracted by 64 kbit/s. The rate canfreely be allocated between all user access points by the cross-connection of the equipment.

BTE-384-M uses biphase transmission for 2- or 4-wire lines at rates 128-384 kbit/s. The cablelength can be up to 3.5-6 km depending on the cable type and the transmission rate.

BTE-1088-M, BTE-2048-M, BTE-4096-M offer HDSL-like performance at rates 320-4224 kbit/susing 4-wire transmission, 2B1Q line code. BTE-2048-2W-M offers 2-wire full duplex operationover a single wire pair using echo cancellation. The cable length can be 3-10 km depending on therate, module and cable characteristics.

BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M offer HDSL-like performance atrates 320-2304 kbit/s using 2-wire full duplex transmission over a single wire pair. The line code is2B1Q. BTE-1088-2W-M and BTE-2304-M offer also additional 4-wire modes at rates 320-2304kbit/s. The cable length can be 4-10 km depending on the rate, module and cable characteristics.

Using a BTE module, Tellabs 8120 mini node M can be connected to a Tellabs 8100 node witha corresponding interface, another Tellabs 8120 mini node or to table top baseband modemsSBM 384A (with BTE-384-M), STU-2048 (with BTE-2048-M), STU-1088 (with BTE-1088-M),STU-320 (with BTE-320-M), STU-576 (with BTE-576-M), STU-1088-2W (with BTE-1088-2W-M)or STU-2304 (with BTE-2304-M).

LTE-M11

The LTE-M module provides a line interface for a symmetrical pair cable. The transmission rates ofthe LTE module are 2048 kbit/s and 1088 kbit/s. The impedance of the transmission line is 120Ω and the maximum attenuation of the transmission line can be -36 dB. The 2048 kbit/s interfacecomplies with G.703/G.704 Recommendations. At the 1088 kbit/s rate a modified G.704 frameis used. Depending on the cable type and transmission rate, cable lengths of over two kilometerscan be reached.

G703-75-M and G703-120-M

The G703-75-M and G703-120-M modules offer an interface with a transmission rate of 2048 kbit/s.The impedance of the transmission line is fixed (75 or 120 Ω, respectively). The maximumattenuation of the transmission line is 6 dB. The interface complies with the correspondingRecommendations G.703/G.704. The interface is designed for the interconnection of equipment inthe same physical location.

10The production of the interface modules BTE-64-M, BTE-320-M, BTE-384-M, BTE-576-M, BTE-1088-M, BTE-1088-2W-M, BTE-2048-M,BTE-2048-2W-M, BTE-2304-M, BTE-4096-M and baseband modems SBM 384, STU-320, STU-576, STU-1088, STU-1088-2W, STU-2048 andSTU-2304 has been discontinued.11The production of the interface module LTE-M has been discontinued.


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G703-8M-M12

The G703-8M-M module is similar to G703-75-M but with a transmission rate of 8448 kbit/s.The impedance of the transmission line is fixed 75 Ω and the maximum allowable attenuation ofthe transmission line is 6 dB.

OTE-LED-M

The OTE-LED-M module is an optical fiber interface. Almost all fiber types which are suitable fordata transmission (not plastic-coated fibers) can be used with this module. The connector is of typeFC. Transmission distances of several dozens of kilometers can be achieved with an OTE module.The transmission rates are 2048 kbit/s and 8448 kbit/s, and the frame structure is according to G.704.

V35-G704-SM and X21-G704-SM13

Tellabs 8120 mini node M can be equipped with a V35-G704-SM module, where the connectionsignal levels are according to the V.35 or V.11 Recommendations, the interface timing iscodirectional and the connectors are of type D with 9 pins. The rate of the interface is n x 64 kbit/s(n = 2…33) and the frame structure is modified G.704. The interface is designed for the connectionof Tellabs 8120 mini node M to the V series interface provided by the public data transmissionnetwork, using the bit rate of n x 64 kbit/s. The modules V35-G704-SM and X21-G704-SM have223-1 type scramblers in both transmission directions. The scramblers can be used when thetransmission rate is 31 x 64 kbit/s or lower except by the unframed mode, where the scramblerscannot be used. It is advisable to use the scramblers whenever it is possible.

Special Modes

The interfaces IF1 and IF2 of Tellabs 8120 mini node M can be connected to 1+1 protecting modewhen both interfaces transmit the same data in the transmission direction. In the receive direction,however, the better one of the two received signals is selected for the terminal equipment interfaces.This duplication is used in order to protect the transmission. The protection can be realised with anytwo modules with the same transmission rate.

The interfaces IF1 and IF2 can use the split trunk transmission method as well, where the signalfrom the terminal equipment interface is distributed to the two framed connections and returned atthe receiving end in its original form. This facilitates a transmission where the transmission rateof the signal from the terminal equipment interface is higher than the rate of a separate framedinterface. Restrictions for the maximum propagation time difference between the transmission linesof the framed interfaces are set. It is recommended that both interfaces use the symmetrical pairslocated in the same cable.

2.4.2 Unframed Interfaces

The unframed interfaces of Tellabs 8120 mini node M support user bit rates 600 bit/s…8448 kbit/s.Normally, Tellabs 8120 mini node M should be installed near the equipment in order to be accessed.

12The production of the interface module G703-8M-M has been discontinued.13The production of the interface modules V35-G704-SM and X21-G704-SM has been discontinued.


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Unframed Channel Interface Types

Interface BitRate kbit/s

Interface Type XB Bit Rate kbit/s Structure Notes

0.6…4.87.2…9.614.4…19.238.44856

V24, X21V24, X21V24, X21V24, X21V24, 35, 36, X21V24, 35, 36, X21

81632646464

V.110V.110V.110V.110V.110V.110

1415

1415

1415

1415

1615

1615

7280144160

V35, 36, X21V35, 36, X21V35, 36, X21V35, 36, X21

72 (+8 or 16)80 (+8 or 16)152 (+8)160 (+8 or 16)

frameframeframeframe

17

17

17

17

n x 64n x 64

V35, 36, X21V35, 36, X21

n x 64 (+8,16 or 24)n x 64 (+8 or 24)

frameV.13

17

18

64 G.703 (co orcontradir)

64 +(8) - 17

V.24/V.28 can be synchronous or asynchronous. The ITU-T-specified V.14 synchronous/asyn-chronous conversion is used.

The C/I control signal mapping of the X.21 interface is done for bit rates ≤48 kbit/s according to theRecommendation X.30 (compatible with V.110). At bit rates 56 kbit/s and n x 64 kbit/s the C/I canbe mapped through the network but it is proprietary.

The XB structure in the table above refers to the framing or coding of user data when it is mappedinto the trunk. V.110 is a typical frame used for data connections and it is used in an ISDN networkfor the rate adaptation of V and X series interfaces. The framing is used between the user accessports of the connection and it is not visible outside the trunks of the network.

The end-to-end connection is monitored and supervised by the V.110 frame in the data interfacetypes <64 kbit/s. With bit rates n x 64 kbit/s it is only possible to map the user data into the XB/XDchannel. It is, however, possible to map the data with an additional n x 8 kbit/s frame which includesend-to-end monitoring (CRC) and network-independent clocking for channels. The bit rate of theadditional frame is presented below.

Bit Rate of Additional Frame

105/109 Transfer CRC Network In-dependentClocking

User Rate ≤512kbit/s Frame Ratekbit/s

User Rate >512kbit/s Frame Ratekbit/s

ON 8 8

ON 8 8

ON 8 24

ON ON 16 16

14A special, modified V.110 framing can be used (CRC error monitoring is included).15Also synchronous bit rates of up to 64 kbit/s are supported.16A modified V.110 framing can be used (CRC error monitoring and network independent clocking).17A separate 8, 16 or 24 kbit/s frame can be used (CRC, 105/109 and network independent clocking).18Simulated carrier function according to Recommendation V.13 (can be turned off). A separate 8 or 24 kbit/s frame can be used (CRC and networkindependent clocking).


21


105/109 Transfer CRC Network In-dependentClocking

User Rate ≤512kbit/s Frame Ratekbit/s

User Rate >512kbit/s Frame Ratekbit/s

ON ON 16 24

ON ON ON 16 24

ON ON 8 24

The end-to-end monitoring supervises the XB/XD signal path through the network. A V.110 framedport does this by counting errored frames. The CRC monitored ports count errored CRC blockswhich include every bit of the user signal.

Network independent clocking means that the user’s DTE equipment can provide timing fortransmission data which is not frequency-synchronized to the network clock. The standard V.110framing for low speed interfaces also supports the network independent clocking.

The typical applications for the low-speed interfaces V.24/V.28 (≤0.6…19.2, 38.4 kbit/s andn x 3.6 kbit/s) are

• termination of point-to-point circuits in a data processing centre

• end point of point-to-multipoint circuits in the Tellabs 8100 network

• termination of V.110 formatted circuits

The typical applications for the medium speed interfaces V.35, V.36 (≤9.6…38.4, 48, 56, andn x 64 kbit/s) are

• termination of point-to-point circuits in a data processing centre

• end point of point-to-multipoint circuits in the Tellabs 8100 network

• links for data multiplexers, PADs, LAN bridges and routers

• data links between two computers

• trunks of low or medium capacity data networks

The typical applications for the high speed interfaces V35, V.36, HSSI (64…8448 kbit/s) are

• links for data multiplexers, PADs

• links for LAN bridges, routers

• data links between two computers

• trunks of low or medium capacity data networks

The typical applications for the LAN module (64…2048 kbit/s) are

• LAN interconnection

Low speed interfaces V.24/V.28 at rates n x 3.0 and n x 3.2 kbit/s may be used for access links todata networks using 6+2 (n x 3.2 kbit/s) or 8+2 (n x 3.0 kbit/s) signalling formats.

Interfaces X.21 at rates 0.6, n x 1.2, 48, 64 and (n x 64) kbit/s may be used for X.21 access links toX.21 or X.25 data networks. In X.21 bis mode the X.21 interface may be applicable for a variety ofapplications with data multiplexers etc.


22


The G.703 interface is mainly used for transfer between the Tellabs 8100 network and anothertransport network or switching system based on the G.700 Series ITU-T Recommendations. Somecomputers and data multiplexers may also be equipped with a 64 kbit/s G.703 interface.

2.5 Network Synchronization

Trunks use the synchronous octet interleaving; the buffer memories of the framed interfaces requirethat the average bit rate in the incoming signals is the same in all trunks (mesochronous clocks). Thesame requirement usually applies to the synchronous n x 64 kbit/s data interfaces (user access ports).Some data interface types allow the use of a plesiochronous clock in the user access ports.

Tellabs 8120 mini node M is provided with an internal master clock, which gives timing to thecross-connect switch. The master clock can be locked to

• an external n x 64 kHz clock input

• an incoming n x 64 kHz clock of a trunk or channel interface

If the master clock is not locked to any external reference timing, the clock operates in an internalmode with an accuracy of ±30 ppm.

The clock reference source is defined by a clock fallback list which can have up to five clockentries. The following clock faults are recognized:

• loss of clock or signal

• loss of frame alignment at a clock interface

• far-end alarm concerning the loss of the reference clock of the node

Two examples on the synchronization of Tellabs 8120 mini node M are given below.

Fig. 6 Independent Timing of Network Nodes

Nodes can be timed independently of one another. This practise can be used if an accurate stationclock is available. In this practise the equipment uses exclusively the external clock input (EXTCLK).


23


Fig. 7 Synchronization through Trunk

The usual practise with two pieces of equipment is to synchronize one to the external clock or to useits internal clock. The other piece is synchronized to the trunk coming from the master equipment.Both pieces should not be synchronized at the same time to the trunk coming from the other endbecause it causes a closed timing loop and corruption of data transfer.

The same practise can also be used if there are many pieces of equipment in the same network. Onepiece is the master and the clock is distributed via the network to the other pieces. The network isnormally locked to an external clock source via the network master equipment or to the internalclock of the master. The clock distribution network can make use of reserve routes. A change-overis based on the clock faults criteria. The selection of the reserve clock route must be done so that thechange-over to a reserve route does not cause a closed timing loop.


24

3 Operation

3 Operation

3.1 General

The functional block diagram is presented in Fig. 8.

Fig. 8 Tellabs 8120 Mini Node M Functional Block Diagram

The common functional blocks of Tellabs 8120 mini node M are

• G.704 framed interfaces IF1 and IF2

• cross-connect block

• microprocessor block for control functions

• keyboard and display

• AC/DC power supply or DC/DC power supply


25

3 Operation

The microprocessor block, the cross-connect block and the G.704 framing block are located on themain board. Two changeable interface modules for framed interfaces are located on the main boardand connected through connectors to the framing block. The power supply is a separate boardconnected through cables to the main board and covered with a metallic shield to prevent the maincurrent causing a hazard when the case is opened.

The keyboard and the display are on the front panel.

The channel board and two changeable user access interface modules are located over the mainboard and the framed interface modules. The cross-connect and microprocessor busses connectthe channel board and the main board together.

3.2 G.704 Framed Interfaces IF1 and IF2

The G.704 framing block processes framed signals at 8448 kbit/s, 2048 kbit/s and n x 64 kbit/s.The block includes two independent transmission channels to carry data and also to provide aninternal communication link of the Tellabs 8100 system. The transmission channel interfacesare independent of each other and they may, for example, be G.703 interfaces, optical interfaces,and, at certain speeds, also baseband interfaces.

The framed signal which is carried on the transmission line is assembled and disassembled in theG.704 framing block. In the transmitting direction the Tx frame block creates a signal by mappingdata from the X-bus into the correct time slots, adding frame alignment signal bits and the CRCcheck sum, and by generating the HDLC channel at a required position within the frame with theaid of the processor.

In the receiving direction the Rx frame block searches the received signal for the framesynchronization word. When the synchronization is found, the Rx frame block can extract the datatransmission time slots, check the CRC check sum, and recover and supply the HDLC channelto the processor.

The frame structure and the use of the certain bits in the frame depend on the transmission speed.At 2048 kbit/s and 8448 kbit/s the frame structure is in accordance with G.704. A modified G.704frame structure is used for other speeds. If required, it is also possible to remove the framing andhave the channel to operate in transparent mode.

In the G.704 framing block there are data buffers for the data transmission. The transmit buffers ofthe channels are used to store data so that there is always a time slot available to be transmitted bythe Tx frame block. The transmit buffers also synchronise the phase of the transmitted frame withthe phase of the X-bus and stuff idle data in the unused time slots of the frame.

The receiving buffers of the channels store incoming data so that required time slots are alwaysavailable for the cross-connect block. These buffers also form a flexible buffer in order tocompensate for minor momentary speed differences between the X-bus and the received signal. Thelength of the receiving buffers can be changed in accordance with the application requirements.For instance, in some cases a minimum connection delay is required whereas in plesiochronousoperation slips should occur as seldom as possible.


26

3 Operation

3.2.1 Frame and Multiframe Structure

The unit has two independent G.704 framed interfaces. The frame has the following three modes.

• 8448 kbit/s = 132 TS

• 2048 kbit/s = 32 TS

• n x 64 kbit/s = n TS

The 2 Mbit/s and 8 Mbit/s frame structures conform with ITU-T G.704 Specification. The 8 Mbit/sframe structure is shown in Fig. 80 of Appendix 2 and the 2 Mbit/s frame structure in Fig. 81 ofAppendix 2. For further details see Appendix 2.

The 8 Mbit/s signal has four 2 Mbit/s groups (thirty time slots). The 2 Mbit/s frame has onesignalling time slot (TS16), and in the 8 Mbit/s frame each group has its own signalling time slot(TS67…70).

The main features of the n x 64 kbit/s frame are the same as those of the 2 Mbit/s frame. The framelength is n time slots. Possible signalling bits are in the last time slot of the frame, or in TS16, if n≥18. The framed interface lines primarily use the following time slots for XB channels.

8 Mbit/s TS 5…32, 34…65, 71…98,100…131

Total 120 TSs

2 Mbit/s TS 1…15, 17…31 Total 30 TSs

n x 64 kbit/s TS 1…n-2TS 1…15, 17…n-1

Total n-2 TSs if n ≤17Total n-2 TSs if n ≥18

The table of Multiframe Structure in Signalling Time Slot in Appendix 2 shows the G.704multiframe structure of the signalling time slot.

For the transmission of the XD channels the following time slots are used:

8 Mbit/s TS 67, 68, 69, 70

2 Mbit/s TS 16

n x 64 kbit/s TS n-1 if n ≤17TS16 if n ≥18

The trunk lines always use the G.704 compliant CRC check in order to detect errors in the receivedsignal and to prevent alignment to an imitative frame alignment word. On the user access lines theCRC check can be turned off if the user equipment does not support the CRC frame structure. TheCRC check is inserted into the different frame structures in the following way.

Frame Time Slot CRC Check

8 Mbit/s TS99 CRC-6

2 Mbit/s TS0/B1 CRC-4

n x 64 kbit/s TS0/B1 CRC-4


27

3 Operation

3.2.2 Buffers

In the transmit direction the buffer supplies time slot data from the X-bus to the frame to betransmitted. When the cross-connect block supplies data to the X-bus, it also adds information aboutthe location in the transmitted frame where the data is to be placed. The unit stores the data in itstransmit buffer in a position corresponding to the position of the time slot in the frame. The framemultiplexing circuits will fetch the data when they are transmitting the corresponding time slot. Asit is possible to write the data from the bus to any time slot position in the buffer, the buffer mustcontrol that the write and read operations do not simultaneously address the same time slot. Thetransmit buffer length is two frames. The frame multiplexing block reads the first frame area andthe bus writes into the second frame area. This transmit buffer arrangement causes a delay ofone frame (125 µs).

In the receiving direction the buffer supplies received time slot data from the demultiplexed frame tothe X-bus. When the cross-connect block via the X-bus requests data from the interface block, italso specifies the time slot concerned. Usually, the phase of the received frame does not coincidewith the frame phase of the X-bus; on the other hand, the receiver writes the time slot data into theRx buffer clocked by the received frame. Therefore, the Rx buffer has to control that the readand write operations do not collide, in spite of speed fluctuations and jitter. If the read and writeaddresses come too close, one of them has to be moved, in other words, centred. The centring ismade by changing the read address, and the change is always one frame or a multiple of a frame.The centring causes a certain number of frames to be lost or retransmitted.

Centring is required when equipment is powered up, when a received signal contains disturbances,or when the transmission is plesiochronous. If a plesiochronous system constantly exhibits afrequency difference in the same direction, the buffer has to be centred at regular intervals. Thelength of the interval depends on the frequency difference and on the buffer mode.

Frame Buffers

The buffers have four operating modes.

Buffer Mode Rx Delay(Frames)

Tx Delay(Frames)

Usage

4 Fr19 1…3 1 Framed user access interfaces,n x 64 kbit/s trunks

8 Fr 1…7 1 Special use

8 Fr/Split 2…6 1 Split trunk line components

64 Fr 1…63 1 Special use, e.g. small slip rate inplesiochronous use

In a plesiochronous system the interval between the centring situations is:

19Fr = frame = 125 µs


28

3 Operation

Buffer Mode n x 64 kbit/s 2048 kbit/s 8448 kbit/s

4 Fr20 n x 8/df21 256/df 1056/df

8 Fr 4 x n x 8/df 1024/df 4224/df

8 Fr/Split 2 x n x 8/df 512/df

64 Fr 32 x n x 8/df 8192/df

The 4 Fr buffer is the normal mode of the buffer.

A buffer with a length of eight frames is used for split trunk operation. It may also be used for otherapplications; it should be used if, for example, unusually large fluctuations have to be handledcorrectly or if the frame alternation has to be intact after the centring as well.

The long buffer leads to a delay of up to 63 frames; thus, this buffer mode is recommended for specialpurposes only. The slip distance is very large in a plesiochronous system and the buffer is well suitedfor large frequency fluctuations. This buffer mode can be used at 2048 kbit/s and n x 64 kbit/s.

Multiframe Buffers

In the transmitting direction the signalling data is directed through the same buffer as the time slotdata. The signalling multiframe of the frame to be transmitted is synchronized to the multiframeclock of the X-bus. The cross-connect block supplies the frame signalling data, along with theother time slot data of the frame. The framing block generates a synchronization time slot in thefirst frame of the signalling multiframe. Thus, the signalling data and the time slot data have equaldelays in the transmitting direction.

In the receiving direction the phase of the received signal multiframe usually differs from thephase of the X-bus multiframe. Thus, the received signalling data has to be buffered until thecross-connect block performs the cross-connect function for the data concerned. There are twoalternatives for the multiframe buffer length: two and four multiframes. The multiframe bufferlength depends on the selected length of the frame buffer.

Frame BufferMode22

MultiframeBuffer Mode23

MFr-Rx Delay MFr-Tx Delay

4…8 frames 2 MFr 0…2 MFr 1 Fr

64 frames 4 MFr 1…3 MFr 1 Fr

The time slot data and signalling data have separate buffers. Therefore, there are different delays inthe processing of signalling data and time slot data. This means that the signalling data and the timeslot data which are placed in a transmitted frame do not necessarily originate from the same frame.

20Fr = frame = 125 µs21df = frequency difference between the signal received from the line and the receiving frequency generated by the master clock oscillator.22The length of a frame is 125 µs.23The multiframe length is 2 ms.


29

3 Operation

3.2.3 Split Trunk Lines

A split trunk line can be used to combine two parallel n x 64 kbit/s or 2048 kbit/s interfaces inorder to increase the maximum number of time slots of a n x 64 kbit/s trunk interface. The timeintegrity of the time slots in the split trunk line is preserved even if the n x 64 kbit/s is connectedthrough physically separated cables. The split trunk mode can be used for line speeds n x 64 kbit/sand 2048 kbit/s when a frame with CRC4 is used. The split trunk mode always requires longbuffers (8 frames). One of the interfaces will function as a master and the others as slaves. Splitcomponents must have the same bit rate.

The interfaces are synchronized to each other by their CRC4 multiframe structure. In thetransmitting direction the interface transmit buffers and the Tx frame multiplexers are synchronizedwith the X-bus MSYN signal to transmit in the same multiframe phase. In the receiving directionthe master interface sends information about its receiving buffer read phase to the slaves, whichwill centre their own receiving buffers to the same phase. This operation causes data time slotssent from a transmitting node in the same frame to be read together within one frame into thecross-connect block of the receiving equipment.

Theoretically, the maximum delay allowed between lines in a split trunk line is 0.5 frames. Due totechnical reasons, however, the maximum delay is 50 µs.

Each line of a split trunk line will handle its own signalling data. Those lines which carry one ormore data channels with signalling data will use the last time slot, or TS16, if it is possible, as asignalling channel with a multiframe structure. It is not necessary to use a CAS time slot for linesthat do not include data channels with signalling.

When making cross-connection for a split trunk, a unidirectional channel from the control port ofthe master channel to the control port of the slave channel must be created. The port numbers fordata ports of interfaces correspond to the interface numbers. In Tellabs 8120 mini node M thecontrol port numbers are 20 for IF1 and 21 for IF2.

3.2.4 1+1 Protection

The interface can be 1+1 protected by another framed interface. In the protected mode bothchannels must have the same rate and framing mode settings. Framed interfaces working in theprotected mode will look like one cross-connect port towards the X-bus. In the protected mode bothchannels transmit the same data signal coming from a buffer. Both channels use their own framemux to create the frame structure. The receiving direction includes a change-over switch that selectsthe active receiver. Rx signal faults are classified into several categories. The switch uses faultcategories to select the interface to be used. The fault categories are indicated in the fault table. Forexample, 1.x means first category, the worst or most serious fault.


30

3 Operation

Fig. 9 Protection Mode of Framed Interfaces

The operating modes of the change-over switch are

• normal operation

• prefer operation

• forced operation

In normal operating mode the switch will automatically switch to the other interface if the Rx signalfault category (1, 2, 3, 4, 5, OK) of the active interface is continuously worse than the fault categoryof the other interface for a longer period than the given time delay. No switch-over operation isactivated when the categories are the same for both interfaces.

In prefer operating mode a switch-over is triggered if there is a difference between the interfacefault categories. The better interface is switched into being active. In a situation with equal faultcategories for both interfaces the switch selects the preferred interface.

In forced operating mode the switch is forced to switch over without delay. Received data fromthe active interface is immediately connected to the X-bus. In this situation the Protection SwitchForced fault message with status MEI (maintenance event information) appears, and the red LED isturned on.

A switch operating time delay is defined for the prefer and normal operating modes. The delay isdefined as n x 10 ms, where n = 0…6000; in other words, the delay is 0…1 minutes. The delaydefines the allowed fault duration before the switch is triggered to switch-over.

3.3 Operation of Framed Interfaces

Tellabs 8120 mini node M is connected to a transmission line through interface modules. Theinterface modules contain the analog components required for the interface and also the analogcomponents needed for generating the input and the output clocks. The signals between the framingblock and the interface module are digital signals which are converted to the transmission line levelin the module. Line codes are coded/decoded in the framing block when modules of G.703 type oroptical modules are used; in baseband modules the line coding is performed in the module. Eachmodule type supports defined transmission rates which can be selected with the user interface. Thecodes and the available transmission rates are described in Technical Specifications.


31

3 Operation

The processor bus is connected to both interface module connectors. Through this bus it is possibleto detect the module type and to read data regarding the module status, e.g. a missing incomingsignal. Parameters which define the module functions, e.g. the transmission rate and possiblelooping commands, can be selected through the bus.

In the receive direction the interface module regenerates the coded signal received from thetransmission line and transforms the signal to the digital level. The module monitors the level of thereceived signal; if it is too low or missing completely, the module sets an AIS signal to the framingblock and at the same time activates a missing signal alarm via the processor bus.

Fig. 10 Data and Clock Processing in the Receive Direction

The receive direction clock is recovered from the data in the interface module. The clock is suppliedto the framing block, which uses it to decode the line code and to demultiplex the frame. If there isno received signal, the interface module replaces the received clock with the transmitted clock. Thereceive clock in the V series modules is taken from the circuit 113 from line. The missing signalalarm with V series modules is based on detecting the incoming clock signal.

The received clock from both framed interfaces is connected to the synchronization bus where theprocessor can select a desired clock to be used as a synchronization signal for the master clock of theequipment. The clock to the synchronization bus is disconnected if there is a received signal failure.

The framing block generates the frame structure for the data in the transmit direction. The linecode of the data is generated in the framing block for G.703 interfaces and for optical interfaces.The coded digital data is connected to the interface module where it is converted to a line levelsignal. NRZ data for baseband interfaces is connected to the interface module where it is coded andtransformed into a line level signal.


32

3 Operation

Fig. 11 Transmit Direction Clock and Data Generation at 8448 kbit/s

The transmit direction clock generation depends on the interface module and the transmissionrate. In all cases the transmit direction clock is phase-locked to the C16M frame clock receivedfrom the X-bus.

The transmit direction clock for 8448 kbit/s is usually generated by dividing the bus clock C16Mby two. This divided clock is used to create the frame and to generate the output pulses in thecoder. If the C16M clock is missing, the output clock is generated by using the oscillator of theinterface module, which then is used to create the frame and to generate the output pulses in thecoder. If the C16M clock is missing, a frame is transmitted, but the time slot data and possiblemultiframe signalling are set to AIS.

Fig. 12 Transmit Direction Clock and Data Generation at 2048 kbit/s

The transmit direction clock for 2048 kbit/s and 1088 kbit/s is generated by the phase-locked crystaloscillator of the interface module. The oscillator is locked to the C16M clock of the bus which isused to create the frame and to generate the output pulses in the coder.

Even if the C16M clock is missing, the output signal is generated with the aid of the clock signalfrom the interface module crystal oscillator. The phase-locked oscillator will then be adjusted to itsnominal frequency and the time slot data in the frame is set to AIS.


33

3 Operation

Fig. 13 Transmitting Direction Clock and Data Generation in Baseband Modules

The clock which is used to create the frames for baseband modules is generated in the framing blockby dividing the C16M bus clock by a programmable divider to the nominal transmission rate. Thisclock signal and the data to be transmitted are supplied to the module, where the phase-lockedoscillator is locked to the clock. The clock, again, is generated by the framing block. The line codeddata is then generated with the aid of the phase-locked oscillator clock signal.

If the C16M clock is missing, the clock generated by the module is connected to the framing circuit.The output signal rate is adjusted to its nominal value, and the frame and a possible control channelare transmitted, but all other data is set to AIS.

The transmit direction clock for V35-G704-SM and X21-G704-SM modules is generated bydividing the C16M clock by a suitable divider. This clock is used as the transmit clock of themodule in circuit 115. The dividing process may cause some jitter to the clock in this case. If theC16M clock is missing, no signal or clock is sent from the module.

3.4 Unit Controller

The unit is controlled with an 80C186 microprocessor. The system program is stored on the boardin two interchangeable EPROM memories. The application programs are stored in non-volatileFLASH memories; it is thus possible to update these programs without opening the case of thedevice. The non-volatile memory is also used to store the operating parameters and the serialnumber of the unit. In case of power interruption the unit is automatically reset to the conditionsprevailing before the interruption, without specific parametrisation. The RAM memory of theprocessor operates as a working storage containing e.g. error counters and data buffers for theHDLC links and the frame control bus.

The unit includes a multichannel analog-to-digital converter (A/D) which monitors the operatingvoltages and also the control voltage from the interface module connectors. The control voltage is,for instance, a voltage received from a baseband module controlling the baseband line power-offsituation.


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3 Operation

3.5 Cross-Connect Block

The cross-connect block has the following main functions:

• cross-connection of XB and XD channels

• control of the cross-connect bus

• master clock oscillator of the unit

• interface for external clock input and output

• selection of a reference signal for the master clock oscillator

• selection of a clock signal for the external clock output

The cross-connection is done in the switching matrix of the cross-connect block. Thecross-connection bus contains approximately 1050 cross-connectable time slots (8-bit bytes). Thebits from the interface blocks are collected by using this bus. The cross-connect switch combinesthe needed new bytes for the interfaces by using 8 kbit/s granularity. Usually, whole time slots orbytes are cross-connected. The delay caused by the cross-connection is one 8-kHz frame (125 µs).

The cross-connect block exchanges data with the interface units by placing a channel address on theX-bus which activates the data buffers of the corresponding channel. Received and transmitted datais carried on separate 8-bit-wide busses. The G.704 framing block receives from the cross-connectblock the time slot address which directs the bus data transmission to one selected time slot at a time.

The cross-connect block supplies the C16M bus clock through the X-bus. The C16M clock is alsothe central clock of the equipment; it is used to create clock frequencies for the transmitted signals.The bus supplies frame alignment and multiframe alignment signals to the frame buffers.

Bus functions are also monitored by the interface blocks. When the interface is synchronized andthe corresponding cross-connection is made, the unit will activate the IA Activity Missing alarmif it cannot receive its channel address from the bus. The interface blocks monitor the combinedinformation formed by the bus clock and multiframe synchronization signal; if this information ismissing, the unit will activate the Bus Sync Missing alarm.

3.5.1 Cross-Connection

The cross-connect block executes the cross-connection commands from the NMS or from the frontpanel user interface. The cross-connect commands are stored in a non-volatile memory.

By means of cross-connection the data of the user access interface is placed in the selected time slotsof the framed interface or in an another user access interface. Time slots from a framed interfacecan also be connected to freely selectable time slots of another framed interface. Thus, the datafrom the framed interface can consist of data from several interfaces, and some time slots can beunused. In this case the free TS data, which can be defined in the user interface, is placed in theunused time slots.

The port is a description of interface properties for the cross-connection block. Every interface hasone or more cross-connect ports. The port numbers for framed interfaces are 1 and 2, correspondingto the interface numbers IF1 and IF2. These port numbers are used to specify the port used by thepayload data of the interface. The port numbers for user access interfaces are dependent on the usedchannel board and user access interface modules. Other port numbers are reserved for controlchannels.


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3 Operation

The cross-connection ports are defined by using interface definition, TS definition and a possiblebit mask (n x 8 kbit/s connections). If need be, the cross-connection commands can include thesignalling bits. The bit mask means a combination of eight bits, where state 1 indicates an 8 kbit/schannel of a time slot which is connected; state 0 means capacity left free. The mask can alsobe presented in hexadecimal format.

The cross-connect types supported by the unit are

1. Bidirectional connection: interface/(TS/bits) ⇔ interface/(TS/bits)

2. Unidirectional connection: interface/(TS/bits)→ interface/(TS/bits)

The n x 8 kbit/s and n x 64 kbit/s groups mapped by the interfaces are called the XB channel. TheXB channel can be a combination of 64 kbit/s and 8 kbit/s signals. If the interfaces are equippedwith signalling or control signals, they are either mapped to the XB channel or to the correspondingsignalling bits (n x 500 bit/s) of the XD channel. In the latter case the signals are mapped to theG.704 compliant multiframe of the 2 or 8 Mbit/s trunk. The n x 500 bit/s signalling bits are calledthe XD channel of the interface. The number of the signalling bits depends on the capacity of theXB channel. Signalling bits are reserved for the XB channel in the following way.

XB Capacity XD Capacity

TSn/B1…B8 64 kbit/s 4 bits (a, b, c, d bits in G.704 structure)

TSn/B1…B4 32 kbit/s 2 bits (a, b)

TSn/B5…B8 32 kbit/s 2 bits (c, d)

The a, b, c, and d bits of the XD channel in the G.704 multiframe correspond to the XB channeltime slots in the G.704 frame. The capacity reserved by XB and XD channels is determined bythe interface type and the user requirements. Four signalling bits are reserved for each time slot.Even if only some of the bits are needed, all four bits are cross-connected and transferred to thefar-end channel interface.

Port Locking

After the operator has changed the parameters of the interface to the desired state, the parametersof the interface must be locked. This means that the properties of the port are transferred to thecross-connect block which needs the information for capacity allocation. The cross-connect cannotbe made before the port is locked, and the port cannot be unlocked if there are any cross-connectionsmade to the port. The parameters of the interface can be changed if the port is in unlocked state.

Split Trunk Connection

In split trunk mode there is always a master and a slave. The data buffer of the slave follows theaction of the master interface through a control channel created by the cross-connection. The controlchannel is made by unidirectional connection command, and its direction is from master to slave. InTellabs 8120 mini node M the control port number is 20 for IF1and 21 for IF2.

Protection Connection

The framed interfaces in protected mode will look like one cross-connect port towards the X-bus. Across-connect command made to one port causes a cross-connection to both interfaces. The portnumber for the protected ports is 1.


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3 Operation

3.5.2 Master Clock Synchronization

The 16 MHz master clock of the equipment is used for generating the timing of the cross-connectbus. The timing consists of

• 16 MHz

• 8 kHz frame synchronization

• 500 Hz multiframe synchronization

The 16 MHz clock is also used to generate the Tx clock of each data interface. The master clockis usually synchronized to an incoming data signal (generally a 2 Mbit/s trunk, see 2.5 NetworkSynchronization on network synchronization). The clock of the desired interface is derived by usinga separate sync clock bus. The cross-connect block controls the status of the synchronization clockand tells the required interface to connect the received clock of the interface to this bus.

Quality Level (QL) of Clock Signal

When a HDLC channel is used at interface (IF1…IF3) and theMessage Sending option is activated,Tellabs 8120 mini node M may receive messages from its neighbour node. Some of these messagesinclude information about the clock signal to which this neighbour node is synchronized. Thisinformation is called Quality Level (QL) and it has been defined as numerical values from 1 to 7where 1 is the highest and 6 the lowest one (7 means do not use this clock; the figure is used toprevent timing loops).

If for some reason the neighbour node changes its clock signal used for synchronization, the QL ofthis new reference clock is transmitted via the HDLC channel. Tellabs 8120 mini node M polls theseQL values from all the interfaces and thus can select the best available clock signal.

The clock signal which has the highest QL and whose status is OK is the one to which the masterclock is synchronized. If clock signals have the same QL, the clock to which it is synchronized isthe one with the highest priority according to the fallback list.

Whenever all the clock signals are available for synchronization (the status of the clocks is OK),there is no activated alarm related to the master clock even if the last entry of the fallback listwould be used.

The QL of the clock signal from an interface which does not use the HDLC channel is fixed to value1. The QL of the internal clock is normally fixed to 6.

Clock Fallback List

The clock fallback list defines the interfaces which can be used for synchronization. It also describesthe priority order for situations where two or more clock signals have the same QL.

The list can have up to five entries. The form of the list is

• 1. IF_

• 2. IF_

• 3. IF_ (Internal)

The last entry is automatically followed by the internal state.


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3 Operation

3.6 Operation of Unframed Channel Interfaces IF3-IF6

The channel interface board accesses unframed user signals at rates 0.6 kbit/s…8448 kbit/s. Itsupports four independent data transmission interfaces. The board can take two interface modules,both supporting two channel interfaces. The available interface types support V.24, V.35, V.36,X.21, G.703 (64 kbit/s), HSSI or 10Base-T interfaces. Note that the HSSI-M interface module andMini LAN Module support only one channel per module.

User signals at bit rates below 64 kbit/s are rate-adapted in accordance with the frame structureV.110/X.30. The V.110 signals are transported as 8, 16, 32 or 64 kbit/s across the network. Then x 64 kbit/s signals are transported at the user rate across the network. Whenever required, theequipment supports end-to-end CRC supervision of the user signals and plesiochronous data timing.At rates below 64 kbit/s the CRC and plesiochronous timing features are supported in the V.110frame. At higher rates an extra transmission capacity of 8, 16 or 24 kbit/s is required across thenetwork. Asynchronous start-stop signals are supported at bit rates below 256 kbit/s.

The basic functional blocks of the channel board are

• data formatting circuitry

• bus interfaces

• interface modules

Data Formatting Circuitry

The data formatting circuitry determines the majority of the characteristics of the data interfacesprovided by the channel board. The data formatting circuitry is described in more detail in3.6.1 Data Formatting Functions.

Bus Interfaces

The bus interfaces perform the adaptation between the data formatting circuitry and the data busand the address bus of the main board of the equipment. There are also data and address busses forthe microprocessor controls. The master clock of the equipment can be synchronized to the clockreceived from the unframed interfaces through the sync bus.

Interface Modules

Tellabs 8120 mini node M accesses the physical interfaces through the interface modules. Theinterface modules convert the CMOS level data, timing and control signals to balanced orunbalanced V.11, V.28, V.10, or G.703, according to the requirements for each interface type. Thereceiver circuits convert the incoming signal levels to CMOS level data, clock and control signals.

The interface module monitors the existence of the received signal level; if the signal is missing, apower off signal indication is given to the unit controller.

The interface signal coding (e.g. G.703 co- and contradirectional operation, or sync/async converter)is performed in the channel board.

There is an additional 16-bit input buffer on the V24-DTE-M module. This buffer can be used if thebuffer length in the base unit is not sufficient.


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3 Operation

3.6.1 Data Formatting Functions

The data formatting circuitry provides the main data processing functions:

• rate adaptation and framing

• CRC monitoring

• V.13 simulated carrier

• bit rate generation

• user interface signal coding (e.g. G.703)

• sync/async conversion

• V.54 and X.21 test loops

• test pattern generation and error counting

Fig. 14 Functional Block Diagram of Channel Board

Rate Adaptation and Framing

Bit Rates <64 kbit/s

Data bit rates ≤64 kbit/s are, using the ITU-T Method V.110, rate-adapted to 8, 16, 32 or 64kbit/s which can be handled by the cross-connect block and the routing tools. The V.110 frame istransparently transported through the network and can be used for the end-to-end monitoring of thechannel quality.


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3 Operation

The V.110 frame offers three channels for the transfer of the control signals. They are called SA,SB, and X. The channel SA carries the signals 108/107 and the channel SB the signals 105/109.The channel X carries both the signal 106 and the far-end alarm.

The signal 106 is either derived locally from the signal 105 or from the channel X received from thefar-end. When 105 is turned on, the locally generated 106 signal is delayed until 105 is sampledby the framer. This generates the minimum 106 delay which guarantees that 109 is turned onbefore the first data bit is received at the far end.

When the 107/108 transfer is not required, both SA and SB (SA+SB = S) may carry the 105/109or C/I signal, enabling the minimum control signal delay. The S signal is sampled once for eachbyte of user data. In the management menus this mode is called V.110S or X.30, and the basicV.110 mode simply V.110.

The V.110 or V.110S configurations use bit oriented data buffering with a 2 bit jitter/wander margin.The byte oriented data buffering is used in X.21 applications or when octet timing is desired. Thebyte oriented buffering and minimum control signal delay is called X.30 as the mode conforms tothe CCITT Recommendation X.30.

User data rates < 600 bit/s are transferred by sampling at rate 4800 bit/s.

Rates 0.6 kbit/s, n x 1.2 kbit/s (up to 38.4 kbit/s), and 48 kbit/s are supported in V.110, V.110S andX.30 modes. User rates n x 3.0 kbit/s (data network formats 8+2 bits), n x 3.2 kbit/s (data networkformats 6+2 bits) and n x 3.6 kbit/s (including rates 3.6, 7.2, 14.4 and 28.8 kbit/s) are supported inmodes V.110 and V.110S.

At 56 kbit/s both ITU-T V.110b and V.110c (b, c refer to V.110 table 7b and 7c) framing is supported.

Bit Rates n x 8 kbit/s

At rates 8, 16, 32 kbit/s the user data is transferred in one, two or four bits of a time slot. At rates 72and 80 kbit/s the data is transferred using one full time slot and one or two bits of another one. Rates144 and 160 kbit/s need two full time slots and three or four bits of a third one (144 kbit/s uses oneextra bit due to an ASIC restriction). No data framing is needed for the data transfer. The rates 48kbit/s and 56 kbit/s are selected as 6 x 8 and 7 x 8 kbit/s in the management menu.

Bit Rates n x 64 kbit/s

At n x 64 kbit/s (rates 64…2048 kbit/s) the unframed user data is transferred in 1…32 time slots.The data buffer length may vary from three to sixty-four bytes. The nominal buffer length selectionallows for 18 µs, or at minimum one byte of jitter and wander.

Bit Rates n x 64+8 kbit/s

The n x 64+8 kbit/s rate is basically intended for the T1 rate 1544 kbit/s. Certain other n x 64+8 kbit/srates are also supported. This mode uses n full time slots and one extra bit.


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3 Operation

CRC Monitoring

The channel board can support end-to-end CRC monitoring of the user data. The CRC-4 procedureused is similar to the one for the G.704 2-Mbit/s frames. At rates < 1.2, n x 1.2, n x 3.0, n x 3.2, andn x 3.6 kbit/s, the CRC check sum is transferred on the last five bits of frame alignment signal of theV.110 or X.30 frame. A modified V.110 frame is used at rates 48 and 56 kbit/s. When transferringthe CRC check sum, the frames are called V.110M or X.30M, because the corresponding ITU-Tframes do not support CRC monitoring.

At n x 64 kbit/s and n x 64+8 kbit/s the CRC check sum is transferred end-to-end in a proprietaryMartis frame, using 8 kbit/s extra XB capacity.

The end-to-end performance monitoring is based on the end-to-end CRC monitoring, when activated.Channel associated end-to-end CRC monitoring is the only way to get accurate performancecharacteristics for a channel. Performance data is expressed in terms of G.821 parameters.

Control Signals

The unframed interfaces support control signals for the following user channels:

• 105/109 transfer at all bit rates (X.21bis)

• 108/107 transfer at V.110 based frames (X.21bis)

• 106 locally generated

• 106 transfer from the far-end (V.110 only, X.21bis)

• C/I at X.21 interfaces and bit rates 0.6, n x 1.2, 48 and n x 64 kbit/s

The control channels can be transferred in several ways, depending on the user bit rate. The SA, SBand X bits are normally used (selection V.110, X.30) with V.110, V.110M, X.30, X30M frames. TheV.13 simulated carrier or an 8 kbit/s channel are used at n x 8 and n x 64 kbit/s rates.

The 8 kbit/s channel requires additional transmission capacity but it offers a continuous channelwhich is, for example, required for X.21 applications.

V.13 Simulated Carrier

The V.13 simulated carrier is an inband transfer method which does not require extra capacity.When 105 is turned off, the user data is substituted by a pseudo random pattern. When 48 bits ofthat pattern have been received, 109 is turned off and the user data (104) is blocked to off state.When 105 turns on, the pattern generator input is changed from 1 to 0 for 8 bits. After that 106turns on, and the channel is ready for the transfer of the user data.

If, due to transmission errors, the receiving end misses the turn on sequence, it will automaticallyreturn to on state when more than 31 errors have been detected in the pseudo random pattern duringa certain time period.

106 Delay

Normally, the minimum 106 delay required to guarantee proper operation is used. Wheneverrequired, an additional delay may be selected in the range of 8…8000 bits. The delay is expressed intime units at the management interface.


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105 Supervision

In some applications 105 should continuously stay in on condition. If desired, the channel boardcan monitor the 105 state and generate an alarm if 105 goes off.

Bit Rate Generation

A variety of bit rates is required for the unframed interfaces. The data timing signals are derivedfrom the 16896 kHz system clock by built-in programmable frequency synthesisers. There isa synthesiser for each channel and each transmission direction.

Timing Sources

Depending on the configuration, the timing signal for the incoming data (Tx direction) can comefrom the user equipment or from the clock source of the channel board. The clock for the outgoingdata (Rx direction) can come from the channel board or it can be taken from the Tx clock receivedfrom the user.

Plesiochronous Clocking

When the user data clock cannot be synchronized to the master clock of Tellabs 8120 mini node M,the plesiochronous operation (the same nominal bit rate) is required. The equipment supports thetransfer of plesiochronous clocking at all bit rates except for at 8, 16 and 32 kbit/s.

Plesiochronous transfer is supported in the standard ITU-T V.110 frame at rates n x 1.2, n x 3.2,and n x 3.6. A Martis modification of V.110 (V.110M) also supports plesiochronous clocking at nx 3.0, 48 and 56 kbit/s. An extra 8 kbit/s channel with the Martis frame is required at rates n x 8kbit/s and n x 64 kbit/s. The 8 kbit/s channel supports both CRC monitoring and plesiochronoustiming at bit rates of up to 512 kbit/s. With rates above 512 kbit/s plesiochronous clocking requiresa 24 kbit/s channel.

The V.110 method of transferring the data phase and stuffing is used at all bit rates. The synthesisersoperate in a digital PLL mode with slight jitter filtering of the input clock before phase comparisonwith the system reference clock. At the receiving end the synthesiser adjusts its phase according tothe value received from the far-end. The phase adjustments take place in small steps in order tominimize the phase jitter amplitude and frequency spectrum width.

With plesiochronous clocking the V.110 data buffer operates in bit mode. At n x 64 kbit/s rates thedata buffer operates in a so-called frame synchronous mode where the data transferred duringone X-bus frame form a block. The stuffing bits are deleted and inserted at the border betweentwo blocks.

Async/Sync Conversion

The asynchronous/synchronous converter samples the incoming signal at 16 times the user rate. Theconverter recognizes the start-stop pattern which may have start-stop bits and 6, 7, 8 or 9 data bits.Each detected erroneous pattern start-stop is considered as an input signal code error.


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3 Operation

In case of overspeed, the stop bits are deleted at certain intervals. The receiving side adds the deletedstop bits and compensates for the overspeed by shortening the stop bits of the eight consecutivecharacters. The method allows for 1.25% overspeed. At underspeed additional stop characters areinserted. In extended operation mode, the stop bits can be deleted from every fourth characterenabling 2.5% overspeed.

The async converter can be used at bit rates 600 bit/s…64 kbit/s, 128 kbit/s and 256 kbit/s. At bitrates below 600 bit/s the async converter is by-passed and the user data is sampled at the rate of4800 bit/s.

3.6.2 Data Interfaces

The interface signals of V.24/V.28, V.35, V.36 and X.21 interfaces are NRZ coded. Data and controlsignals can change their states at the edge of a clock period. The clock signal has a falling edgeat the beginning of a period and a rising one in the middle of the period. The interface modulesconvert the CMOS level signals to appropriate interface signals.

Interface Module Signal Levels

Interface TypeSignal Name

V.24/V.28 V.35 V.36 X.21 HSSI

103 V.28 V.35 V.11 V.11 TIA/EIA-612

104 V.28 V.35 V.11 V.11 TIA/EIA-612

105 V.28 V.28 V.11 V.11 TIA/EIA-612

106 V.28 V.28 V.11 V.11 TIA/EIA-612

107 V.28 V.28 V.11 V.11 TIA/EIA-612

108 V.28 V.28 V.11 V.11 TIA/EIA-612

109 V.28 V.28 V.11 V.11 TIA/EIA-612

113 V.28 V.35 V.11 V.11 TIA/EIA-612

114 V.28 V.35 V.11 V.11 TIA/EIA-612

115 V.28 V.35 V.11 V.11 TIA/EIA-612

140 V.28 V.28 V.28 - TIA/EIA-612

141 V.28 V.28 V.28 - TIA/EIA-612

142 V.28 V.28 V.28 - TIA/EIA-612

The data and clock signals for G.703 outputs come as positive and negative CMOS level pulsesfrom the base unit. By the aid of drivers and transformers the control signals are converted to G.703signals. The G.703 input signals are converted to CMOS signals using comparators.

3.6.3 Timing Modes

The clocking mode of data interfaces depends on the type of interface, on the type of the interfacedequipment and on the operation mode. The user clock may be considered to be locked to thenetwork timing source if


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3 Operation

1. the user equipment uses the clock supplied by the network interface

2. the user system and the network use the same timing source, e.g. a national timing distributionnetwork

3. both the user system and the network are locked to the timing source according to the CCITTRecommendations G.811 and G.823

V Series Interfaces

In most cases the unframed V series interface (V.24/V.28, V.35, V.36) is connected to a DTE as if itwere a data modem (DCE). The data interface is clocked from the network. The clocking methodcan be used when the transfer delay between the DCE and DTE is below 0.15 bit (L < 30/(bit rate)m); bit rate in Mbit/s. The timing mode is called synchronous 114/115.

• Data in the direction DCE to DTE (104) is clocked by the timing signal 115.

• Data in the direction DTE to DCE (103) is clocked by the timing signal 114 from the DCE (IFmodule).

At longer DTE-DCE distances and in applications where the DTE terminates a data circuit withclock looping at the far-end, or it is clocked by a timing source locked to the same source as Tellabs8120 mini node M, the clock 113 is used in the direction DTE-DCE instead of 114. The signals inthe direction DTE-DCE may contain jitter and wander when compared to the DCE-DTE timing.The timing mode is called 113/115 mesochronous.

• Data in the direction DCE to DTE (104) is clocked by the timing signal 115.

• Data in the direction DTE to DCE (103) is clocked by the timing signal 113.

Fig. 15 Contradirectional Synchronous and Codirectional Mesochronous Timing of anUnframed Data Interface in DCE Mode

Fig. 16 Contradirectional Synchronous and Codirectional Mesochronous Timing of anUnframed Data Interface in DTE Mode


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3 Operation

When interfacing a DCE, the interface module may operate either as a DCE (signals cross-connectedin the interface cable) or as a DTE (without signal cross-connection in the interface cable). Thetiming signals may, in contradirectional mode, come from the DCE to the interface module (cases115/114 EXT or 115 EXT), or, in codirectional mode, from both the DTE and DCE (115/113).Currently, only the V.24 DTE interface is available.

Fig. 17 Codirectional Plesiochronous Timing of an Unframed Data Interface

A data source (DTE or DCE) which cannot be synchronized to the Tellabs 8100 network is accessedusing plesiochronous timing. In plesiochronous mode only codirectional timing is supported.

Asynchronous V Series Interface

The asynchronous operation is supported at bit rates of up to 256 kbit/s. The timing signals areswitched off in the asynchronous mode.

X.21 Interface

Fig. 18 Timing of an X.21 Unframed Data Interface


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3 Operation

Only one clock signal is used in X.21 mode. The clock comes from the interface module or towardsit. The clock is always locked to the same source as the clock of Tellabs 8120 mini node M. Whenrequired, octet timing may also be used.

G.703 Interface

Fig. 19 Timing of a 64 kbit/s G.703 Unframed Data Interface

The G.703 interface at 64 kbit/s supports co- and contradirectional operation. Octet timing isalso supported.

3.6.4 Rate Adaptation and Mapping

The frame structures used are described in Appendix 1. The signals and control signals in thechannel board are rate-adapted and mapped as follows.

Rate Adaptation and Mapping at Bit Rates ≤48 kbit/s

User Ratekbit/s

RateAdaptationMethod

XB Mappingkbit/s

ControlSignals

Ple-siochronousClocking

< 0.6 V.110 1 x 8 SA, SB, X No

0.6, 1.2, 2.4 V.110 1 x 8 SA, SB, X No

0.6, 1.2, 2.4 X.30 1 x 8 S No

4.8 V.110 1 x 8 SA, SB, X Yes

4.8 X.30 1 x 8 S No

9.6 V.110 2 x 8 SA, SB, X Yes

9.6 X.30 2 x 8 S No

19.2 V.110 4 x 8 SA, SB, X Yes

19.2 X.30 4 x 8 S No

38.4 V.110 8 x 8 SA, SB, X Yes

38.4 X.30 8 x 8 S No

3 V.110 1 x 8 SA, SB, X Yes

6 V.110 2 x 8 SA, SB, X Yes

12 V.110 4 x 8 SA, SB, X Yes

24 V.110 8 x 8 SA, SB, X Yes

3.2 V.110 1 x 8 SA, SB, X Yes


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3 Operation

User Ratekbit/s

RateAdaptationMethod

XB Mappingkbit/s

ControlSignals


6.4 V.110 2 x 8 SA, SB, X Yes

12.8 V.110 4 x 8 SA, SB, X Yes

25.6 V.110 8 x 8 SA, SB, X Yes

3.6 V.110 1 x 8 SA, SB, X Yes

7.2 V.110 2 x 8 SA, SB, X Yes

14.4 V.110 4 x 8 SA, SB, X Yes

28.8 V.110 8 x 8 SA, SB, X Yes

End-to-end CRC monitoring can be supported at all bit rates mentioned above. The CCITT/ITU-TRec. V.110 and X.30 do not support CRC monitoring. The frame type is renamed V.110M, orX.30M when CRC is activated.

Rate Adaptation and Mapping at Bit Rates ≥48 kbit/

UserRatekbit/s

AdaptationMethod24

XB Mappingkbit/s

ControlSignals

CRCSupport


48 V.110 1 x 64 SA, SB, X No No

48 V.110M 1 x 64 SA, SB, X Yes Yes

56 V.110/7b 1 x 64 - No No

56 V.110/7c 1 x 64 SA, SB, X No No

56 V.110M 1 x 64 SA, SB, X Yes Yes

64 - 1 x 64 - No No

64 MartisDXX 1 x 64+ 8 + 8 SB Yes Yes

72 - 1 x 64+1 x 8 - No No

72 MartisDXX 1 x 64+1 x 8+ 8 + 8 SB Yes Yes

80 - 1 x 64+2 x 8 - No No


144 - 2 x 64+3 x 8 - No No

144 MartisDXX 2 x 64+3 x 8+ 8 SB Yes Yes

160 - 2 x 64+4 x 8 - No No


N x 64 - N x 64 - No No

N x 64 MartisDXX N x 64+ 8 + 8 SB Yes Yes N ≤ 8

N x 64 MartisDXX N x 64+ 8 + 8 SB Yes No N > 8

N x 64 MartisDXX N x 64+ 24 SB Yes Yes N > 8

24V.110/7b refers to CCITT Rec. V.110 Frame Table 7b, and V.110M/7c is a slightly modified V.110 frame. MartisDXX is a V.110 (56 kbit/s) likeMartis specific frame. 8, 16 denotes extra capacity carrying CRC with plesiochronous timing control. SA, SB and X refer to SA, SB, X bits in theframe.


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3 Operation

UserRatekbit/s

AdaptationMethod24

XB Mappingkbit/s

ControlSignals

CRCSupport


1544 - N x 64+8 - No No

1544 MartisDXX N x 64+8+ 8 + 8 SB Yes No

1544 MartisDXX N x 64+8+ 24 SB Yes Yes

At all data rates the channels can support simulated carrier in accordance with V.13 for transfer ofthe 105/109 signal. V.13 is mostly used at rates n x 64 kbit/s.

3.6.5 Cross-Connection of Unframed Interfaces

The cross-connection ports are defined by using interface definition, TS definition, and a possible bitmask (n x 8 kbit/s connections). In some cases an unframed interface can be defined only by usingthe interface definition (in Tellabs 8000 manager only). The first time slot of a port definition ofan unframed interface is always TS0. The bit mask means a combination of 8 bits where state 1indicates an 8 kbit/s channel of a time slot which is connected; state 0 means capacity left free. Themask can also be presented in hexadecimal format.

The entire capacity of the unframed interface must be connected in order to ensure the properfunction of the interface. The unframed interface can be provided with a control channel in somecases. Then the control channel must be connected as well.

Many interface types can produce n x 8 kbit/s capacity even when the data speed in the user interfaceis n x 64 kbit/s. For example, an unframed n x 64 kbit/s connection with end-to-end CRC checkingneeds 8 kbit/s additional capacity in the XB channel.

When the XB capacity of the unframed interface is exactly n x 64 kbit/s, the n x 8 kbit/scross-connection is not needed. 48…56 kbit/s data interfaces after V.110 rate adaptation, forexample, need 64 kbit/s XB capacity.

All low rate data interfaces (≤19.2 kbit/s) need n x 8 kbit/s cross-connection.

When making connection to the unframed interface which has such control bits as CRC checking,the control bits are the last bits of the port. If the data uses the whole n x 64 kbit/s capacity (wholetime slots), the control bits are the lowest bits of the next time slot. When the unframed interface isconnected to the framed interface and a part of the full capacity consists of n x 8 kbit/s portions, a bitmask must be used for the connection of the n x 8 kbit/s portion. The control bits can be connectedto any usable time slot and bit in the framed interface.


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Fig. 20 Example of Cross-Connection

The figure above shows an unframed interface IF3 with a bit rate of 144 kbit/s and control channelwith 2 x 8 kbit/s (in all 160 kbit/s) connected to a framed interface IF1 which has the G.704 framestructure. The unframed port is specified as capacity 2 x 64 kbit/s and 4 x 8 kbit/s, which means twotime slots and four bits. The first time slot of the unframed interface is TS0. TS0 and TS1 of interfaceIF3 are connected to TS2 and TS3 of IF1. This can be made with the TS pair or TS area commands.

In the TS pair command one time slot from both interfaces is defined, and the cross-connection iscreated between these time slots. In the TS area command the first and the last time slot of anarea with equal amount of time slots in both interfaces are defined, and the cross-connection ismade between these areas. The last four bits of the unframed interface (two payload bits and twocontrol bits) in TS2 are connected to the TS4 of the framed interface with the TS bits command.In the TS bits command the time slot and the bit mask for both the interfaces are defined, and thecross-connection is made between the unmasked bits.

The control bits are automatically connected when the Connect whole port command in Tellabs8000 manager is used.

3.7 Test Resources

Tellabs 8120 mini node M has many functions to indicate a defect in the operation of the equipmentor in the data transmission. Some tests are performed when the power is switched on, some of themare running as background processes, and some of them are activated by the user.

In the following chapters the tests are grouped to equipment tests, like the control of the voltages ofthe power supply, and to interface tests, by which the quality of data transmission can be controlledand the failure localisation in fault conditions can be performed.

The type of the user-activated tests depends on the user interface. Usually, tests can only beactivated through the service computer or the Tellabs 8000 manager network management system.In Tellabs 8120 mini node M, however, some tests can be activated through the front panel userinterface. If the equipment is connected to Tellabs 8000 manager, it is possible to activate the testresources for the specified circuits in the desired place in the network.

3.7.1 Equipment Test

When the equipment is restarted after a reset, some start-up tests are executed. For instance, thecorrect starting of the main oscillator and the condition of the cross-connect RAM memory ischecked. The equipment is not allowed to start other processes if these things are not in order.


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When the equipment is running, many tests are executed as background processes. The uP memorytest and the data buffer test are checking the condition of certain components of the equipment. TheuP memory test checks the EPROM, RAM and flash memories, and the data buffer test checks theTx-ram and the Rx-ram memories of the framed interfaces. The tests run continuously. The resultscan be read with the service computer. A detected fault situation causes an alarm. The reason for thealarm can be traced using the user interface, or a service computer, if available.

The equipment has capability to measure the voltages generated by the main power unit. Themeasurement process runs continuously and the results can be read using the service computer.Values that are too low will cause an alarm.

The cross-connect bus test is also running as a background process for locked interfaces. This testchecks the cross-connect data busses and some parts of the ASIC circuits. A failure of the testcauses the IA Missing alarm for the failed interface.

3.7.2 Test of Framed Interfaces

G.821 Statistics

To control the quality of the data transmission of the framed interfaces, the signal statistic valuesaccording to the ITU-T G.821 Specification are supported in both framed interfaces separately.

Near-end and far-end statistics:

• total time (seconds)

• unavailable time (seconds)

• errored seconds

• severely errored seconds (10-3)

• degraded minutes (10-6)

Error Counters

The number of the following events can be read and cleared by the user interface in both framedinterfaces separately in order to check the reason for poor quality, or to search the fault of thetransmission line:

• code errors

• number of G.704 frame losses

• number of frame synchronization word errors

• number of CRC block errors

• buffer slips

The count time of the counters is from the last reset of the counters or from the last reset of theequipment. In some cases all the values are not available; for example, the V.35 interface does notuse coding in the transmission, and for this reason the code errors are not counted.


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Test Loop Functions

The loops and measurement points are used to find a faulty section of the line and to detect thefaulty transmit or receive direction. When the framed interface is looped, all data circuits goingthrough the interface are looped. The equipment includes a loop time-out control which will turn offa loop when the time defined by the user has come to an end.

Fig. 21 Loops of a Framed Interface

Interface Loop

The following signals are activated during the interface loop.

• Tx data of the interface module is looped back to the receiver of the interface.

• Tx clock is looped to the Rx clock.

• AIS is transmitted to the line.

• Looped data is connected back to the demultiplexer.

The type of the module determines the point where the loop is created in the module. In most cases,due to technical reasons, the loop is not made by using a signal with line level. The loop will,however, always test the control bus of the interface module, the connectors, and a part of themodule logic. The line coder and decoder, as well as the frame multiplexer and demultiplexer, arealso tested in the loop. There should be no other faults in the unit fault list when the loop is created.

Equipment Loop

The following signals are activated during the equipment loop.


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• Tx data from the G.704 multiplexer (before the interface module) is looped back to the demulti-plexer.

• AIS is transmitted to the line.

• Looped data is connected back to the frame demultiplexer.

The equipment loop is made in the unit. This loop tests the frame multiplexer and demultiplexer.Neither the line coder, the decoder nor the interface module are included in the loop. It is alsopossible to detect faults in the transmitting and receiving buffers. If no problems are detectedwith the equipment loop, it is suggested that the user perform a test with the interface loop toensure that the module is in order.

Line Loop

The following signals are activated during the line loop.

• Rx data, received by the interface module, is looped back to the interface output.

• The received clock signal is used as the transmitter clock.

• AIS signal is connected to the X-bus instead of the received signal.

The interface module, the line coder, and the decoder, as well as the frame demultiplexer and themultiplexer, can be tested from the line connector of the module with the line loop test. When it isused, the HDLC controller works with the line loop. All other bits are looped back to the interface.

Remote Line Loop

The remote line loop operates in the looped unit in the same way as the local line loop. The remoteline loop is activated from the unit at the other end of the line. The loop is made via the HDLCchannel, and the control channel will continue to operate even when the remote line loop is active.The status of the looped unit can be checked with the user interface. When the loop is made, theyellow LED of the unit controlling the loop is switched on, and the yellow LED of the loopedinterface is also lit. The whole line can be tested with the remote line loop.

Measuring Point

A 75 Ω G.703 type coaxial cable measuring point is provided on the back panel of the unit. Themeasuring point is isolated with a transformer, but the connector body is connected to the unitground. Through the measuring point it is possible to measure the input and output signals of bothframed interfaces IF1 and IF2, as well as the corresponding clocks. The choices are

• Rx data after the interface module but before the frame demultiplexer

• Rx clock

• Tx data after the frame multiplexer but before the interface module

• Tx clock

The signal to be measured is selected with the service computer in the General Unit Parameterswindow. The selection can also be made with the front panel user interface in Tellabs 8120 mininode M. This selection is stored in the non-volatile memory of the unit so that the selection is alsoretained after a possible power interruption.


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The data signal of the measurement point is HDB3 coded and independent of the type of theinterface module and the coding of the data interface signal. The signal levels and formats are inaccordance with G.703. The loops and the measurement point can be used to detect a faulty Txand Rx direction and to pinpoint a faulty line.

3.7.3 Tests of Unframed Interfaces

G.821 Statistics

Every unframed interface has its own group of counters when the V.110, X.30 or the Martis framingis activated with the CRC transfer. The available circuit performance values are

• total time (seconds)

• unavailable time (seconds)

• errored seconds

• severely errored seconds

• degraded minutes

With these values the quality of the data transmission can be controlled in accordance with theCCITT G.821. The values can be read and cleared with the user interface separately.

Error Counters

The channel board can count the following event numbers by using the software and the hardwarecounters. These event numbers can be read and cleared by user interface, each interface separately:

• number of V.110 frame losses (the frame from the net) (the frame of XB channel)

• number of multiframe losses (the frame from the net)

• number of frame word errors (the frame from the net)

• number of CRC block errors

• code errors in the user interface (G.703, start-stop format)

• buffer slips and adjustments

Test Loop Functions

To find the places where problems might occur in the unframed interfaces, there are test loopfunctions which can be activated separately for each interface with the service computer or with thefront panel user interface. All loops have a separate time-out counter which is adjustable by theuser. The counter deactivates the loop when the set time has expired. The V.54 loops supported bythe equipment can be limited or even disabled with the user interface. The V.54 loops also havespecial configurable values, adjustable to seconds, which will turn off a loop when the definedtime has come to an end. A loop activated to an unframed interface only affects the data circuitwhich goes through the involved circuit.


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Fig. 22 Loops of Unframed Interface

Interface Loop

The following signals are activated during the interface loop:

• The Tx data of the interface module is looped back to the receiver of the interface.

• The Tx clock is looped to the Rx clock.

• The looped signal is connected back to the cross-connection.

The operator can activate an interface loop which is close to the physical user interface backtowards the network. When this loop is activated, it is possible to test the correct function andcross-connection of the unframed interface by connecting measuring equipment to the framedinterface to where the looped interface is cross-connected, or by connecting the data measuringequipment to the remote end of the circuit.

Line Loop

The following signals are activated during the line loop:

• Rx data, received by the interface module, is looped back to the interface output.

• AIS signal is connected to the X-bus, instead of the received signal.

A line loop can be activated close to the X-bus interface towards the user interface. If some of theframing formats are used, the frame multiplexer and demultiplexer, as well as the CRC circuit, areincluded in the loop. By activating the line loop it is possible to test the whole interface from theline connector of the module.


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Local Loop and Remote Loop

The unframed interfaces are equipped with the V.54 test loop functions supporting the local loop(loop 3, LL) and the remote loop (loop 2, RL). The X.21 loop functions (LL, RL, RLB) aresupported by the X.21 interface module. The loops can be controlled with the user interface, orthe loops can also be controlled with the user device through the signals 140 and 141. For theseloops the user interface has configurable parameters to disable, enable, enable with timer, or onlyallow the operator to control the loops. All the loops have an adjustable enable timer. In general, theloops should be enabled in the equipment which are as close as possible to the user interfaces, anddisabled in all intermediate equipment.

The local loop can be activated with the user interface or by activating the input signal 141.Activating the local loop makes it possible to check the operation of the interface and the userline from the user device.

The remote loop is activated when the V.54 loop circuit receiver recognizes the activation patterncoming from the far-end through the X-bus. The sending of the pattern from the far-end is activatedby the user interface or by the input signal 141. The remote loop makes it possible to check the wholedata circuit through the network. One way to perform this is to use the built-in test pattern generatorand pattern error detector of the unframed interface. There is one test pattern generator per interface.

When some of the V.54 loops are on, the test loop indication signal 142 goes on. Thereafter, theloop tests can be started. A loop 2 (RLB) activated from the far-end turns the signal 142 on andsets the received data to off. In case of X.21, loop 2 activated at the far-end sets the received datato off or to pattern 1010….

Test Pattern Generator

The channel module has built-in per channel test pattern generators and pattern error detectors. Thetest pattern is according to the ITU-T Recommendation O.151. Typically, a test is performed withthe remote loop activated at the far-end. The user interface facilitates the activation of the testresources and presentation of the test results.


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4 Installation

4.1 Front Panel Indicators and Controls

The front panel of Tellabs 8120 mini node M is presented in Fig. 23.

Fig. 23 Front Panel of Tellabs 8120 Mini Node M

The four buttons and the LCD display are for local control operations.

The front panel of Tellabs 8120 mini node M is equipped with LEDs to display the alarms of thesystem and the interface circuits. There are two alarm LEDs (red and yellow) for each block;IF1…IF6 and SYS. Each block reports its own alarms with these LEDs.

For the service computer (SC) there is a 9.6 kbit/s asynchronous V.24 interface with a 9-pin Dconnector.

4.2 Back Panel Connections

Fig. 24 shows a typical back panel arrangement of Tellabs 8120 mini node M. The fixed items of theback panel are a power connector, a measurement connector, and the synchronization connectors.The back panel is furnished with four different changeable interface modules. The type of theconnector depends on the type of the module. The numbering of the interfaces is also shown inthe figure below.


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Fig. 24 Tellabs 8120 Mini Node M with BTE-384M, G703-75-M, V35-M and V36-M Modules

There are two places for unframed interface modules on the upper part of the panel. In one unframedmodule there are two channels with the same type of an interface. Each module can be of a differenttype, and there are no restrictions to usage of different types of unframed modules in the samepiece of equipment.

On the lower part of the back panel there are two places for framed interface modules. On theframed interface modules there is one interface in each module. Also the framed interfaces can be ofa different type in the same piece of equipment.

The synchronization connectors provide a 75 Ω input and output for the clock signal of the masterclock oscillator of the equipment. Through these connectors the equipment can be synchronized toan external clock source, or the equipment can give a clock to another data transmission equipmentconnected to the same transmission network. The control of the clock signal is handled with theMaster Clock menu of the user interface.

The interface signals and the Rx and Tx clocks of the framed interfaces can be measured withmeasurement equipment through the measurement connector. The impedance of the interface is75 Ω.

The back panel arrangement for Tellabs 8120 mini node M with a different module configurationis shown in Fig. 25.

Fig. 25 Example of Back Panel with G703-75-M, OTE-LED-M, V36-M and V35-M Modules


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If an unframed interface module (user access interface module) is removed permanently bythe user, it must be replaced with a blank upper interface, part code 880070157A, to closethe back panel opening.

If a framed interface module is removed permanently by the user, it must be replaced with ablank lower interface, part code 880070158A, to close the back panel opening.

4.3 Mains Connection

Tellabs 8120 mini node M is connected to a 100…240 V AC mains supply with a three-pingrounded plug. The maximum power consumption is approximately 40 V A. The consumptionvaries depending on the installed module configuration and the bit rates in use. Other power supplyalternatives are a 48 V DC or a 24 V DC power supply.

Tellabs 8120 mini node M is equipped with one primary fuse. If the green power indicator isswitched off, it indicates a failure of the fuse. Other power supply problems can be checked with theuser interface which has a voltage measurement facility. The fuse of the AC model is located insidethe metallic case. Only qualified personnel is allowed to change the fuse.

Tellabs 8120 mini node M must be disconnected from the mains supply before removing thecover as high voltages are present inside the case.

The AC model mains supply primary fuse can be changed after the metallic top cover and powersupply shield have been removed. The primary fuse of the DC models is accessible on the backpanel of the device.

The fuse is of a standard 5 x 20 mm size and it must be replaced with the ratings indicated below.

Power Unit Fuse Input Voltage

8990NFS40 T1A 100…240 V AC ±10% 47…63 Hz

PDU422 24 V DC25 T4A 19…36 V DC, negative pole earthed

PDU423 48 V DC T4A 40…60 V DC, positive pole earthed

Power consumption: 40 V A max.

4.4 Operating Environment

When installing Tellabs 8120 mini node M, do not put it in a warm place.

25The power supply module PDU422 has been discontinued.


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Never put Tellabs 8120 mini node M on top of another piece of equipment of the same kindbecause it can cause overheating and malfunctioning of the equipment. A very dusty orhumid installing place can also cause incorrect working of Tellabs 8120 mini node M and, insome cases, even danger for the user.

Operating temperature: +5…+35 °C

Operating humidity: < 85% RH, non-condensing

The figure below shows how the ventilation air goes through the device. Enough free space shouldbe left around Tellabs 8120 mini node M to guarantee proper functioning and ventilation.

Fig. 26 Route of Ventilation Air

Do not cover the ventilation holes on the case of Tellabs 8120 mini node.

4.4.1 DC Power Supply Cabling

Tellabs 8120 mini node M with DC power supply is connected to the main battery system with atwo-wire cable which has the following color codes:

24 V DC Power Supply Wire Color

+24 V Red

0 V Black

48 V DC Power Supply Wire Color

-48 V Blue

0 V Black


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4.4.2 SC, Local Service Computer Connector

The SC, local service computer connector is provided with a 9-pin female D-connector according toISO 2110 Standard. The connector is furnished with two UNC 4-40 locking screws.

Pin # ITU-T Circuit # Signal Level Function

1 109 V.28 Received line signal indicator

2 104 V.28 Received data

3 103 V.28 Transmitted data

4 108 V.28 Data terminal ready

5 102 - Signal ground

6 107 V.28 Data set ready

7 105 V.28 Request to send

8 106 V.28 Clear to send

9 - - Not connected

4.4.3 SYNC Connector

The SYNC connectors are SMB type connectors, electrically of G.703/75 Ω impedance.

4.5 Configuration of Tellabs 8120 Mini Node M

Step 1 Check that Tellabs 8120 mini node M is ready for operation:

• Interface modules are properly installed and fastened.

• The cover is installed.

• The metallic case is in its place and fastened with all screws.

• No loose parts are inside the case.

Step 2 Put Tellabs 8120 mini node M to correct operation environment as described in 4.4 OperatingEnvironment.

• Check that nothing covers the ventilation holes of Tellabs 8120 mini node M.

• Note that there are ventilation holes also on the sides of the metallic case.

Step 3 Connect interface connectors to the back panel of Tellabs 8120 mini node M.

Step 4 Connect the power cord to the main power supply and the protective earth wire to the groundingterminal. See the exact location of the wire in Fig. 40.

• Screw the grounding earth wire with washers tightly to the M5 nut at the back of the node.


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When DC power supply is used, Tellabs 8120 mini node M must be permanently connected toearth using the supplied grounding earth wire.

Fig. 27 Grounding Earth Wire Assembly

Step 5 Tellabs 8120 mini node M is now ready for use.

• Check that no unusual alarms are on.

Step 6 Configure Tellabs 8120 mini node M with planned parameters.

• Check that the parameters for the framed interfaces and master clock are correct. (See4.7 Recommended Settings of Framed Interfaces for recommended settings.)

• Set the node ID.

When the power cord is connected, the green and yellow LEDs are lit. After a start-up time, whichis from 30 to 60 seconds and depends on the configuration of the equipment, the yellow LED will beswitched off and Tellabs 8120 mini node M is ready for operation.

The meaning of the color of LEDs is explained below.

Green Lit when Tellabs 8120 mini node M is connected to the mains supply and the power isswitched on.

Yellow Lit when Tellabs 8120 mini node M is receiving alarm indication from the network(far-end alarm, AIS). Test state (loops etc.).

Red All other fault situations.

The configuration of Tellabs 8120 mini node M can be monitored and altered through Tellabs8000 manager or by a local service computer connected to the front panel connector, a 9.6 kbit/sasynchronous V.24 interface. There are two HDLC control channels (one in both framed interfacesIF1 and IF2). These are normally used when Tellabs 8120 mini node M is connected to Tellabs8000 manager. The control functions operate as in a Tellabs 8100 cross-connect node. The Tellabs8120 mini node M blocks have the same Tellabs 8000 manager functions as in the correspondingunits in the Tellabs 8100 node. The common test resource, which is in the SCU unit of the othernodes, does not, however, exist in Tellabs 8120 mini node M.

The configuration can also be done locally through the front panel keys and the LCD display. It canbe monitored on the LCD display during operation without interfering with data transmission.


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4.5.1 NMS Control

Tellabs 8120 mini node M is designed to be controlled by Tellabs 8000 manager. The controlfunctions operate as in a Tellabs 8100 cross-connect node. There are two HDLC control channels(one in both framed interfaces IF1 and IF2). These control channels are used when Tellabs 8120mini node M is connected to Tellabs 8000 manager.

There is a 9.6 kbit/s asynchronous V.24 interface on the front panel. Through this interface Tellabs8120 mini node M can be controlled also with the service computer of the Tellabs 8100 system. TheTellabs 8120 mini node M blocks have the same NMS functions as the corresponding units in theTellabs 8100 node. The common test resource, which is in the SCU unit of the other nodes, doesnot, however, exist in Tellabs 8120 mini node M.

4.5.2 Local Control

Tellabs 8120 mini node M has a local keyboard (four buttons) and an LCD display for local controloperations. With these tools the local user can make the same operations that are possible with theservice computer connected to the SC interface on the front panel.

With the local keyboard and the LCD display the user can perform the following operations:

• read the node parameters

• node ID

• unit ID (hardware and software versions, serial number)

• read/set master clock parameters

• creating and deleting cross-connections (not possible with SC)

• alarm information from each interface and block

• read the active faults or the fault history

• clear the fault history

• set interface tests and loops

• read the error counters and G.821 error statistics from each interface

• read the status of V interface control signals

• read/set interface parameters

In the following description the abbreviation NTUM refers to Tellabs 8120 mini node M.

The NTUM parameter settings can be monitored during operation through the display withoutinterfering the normal data transmission. The parameter settings are stored in a non-volatilememory. The Configuration menu recognizes the interface units and transmission modules anddisplays the correct menu items accordingly.


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The LCD display has two lines with 24 characters each. In most cases three item fields are shown ata time. The upper line is used to show the heading of an item; on the lower line there is the value ofthe item or the text DIR, which means that there is a sub-menu for the item. Although there are threeitems on the display, there may be many other items at the same level of the menu. The other itemscan be scrolled to the display with the keys. The blinking cursor indicates the current item field.When the cursor is on the upper line, the SCROLL keys (< or >) are used to move from one item toanother at the same menu level. When the cursor is on the lower line, the SCROLL keys are used tochange the value of the parameter of the item.

By using the EXIT and ENTER keys the user can move up or down in the menu structure. TheENTER key is also used to confirm a selection from a menu. When the cursor is on the upper line,the EXIT key causes a move upwards to the next menu level. On the lower line the EXIT keymoves the cursor from the value field to the heading of the item. The ENTER key moves the cursorfrom the heading to the value field of the item or to the sub-menu if the value is DIR. When thecursor is on the value field, the use of the ENTER key confirms that the present value of the field isused as a new value of the item and the cursor moves to the heading of the item. If the value ofan item is changed, the new value of the menu branch must be confirmed by the Update field,which is the first field of the branch.

The value of an item is changed in the following way.

Step 1 Move the cursor with the SCROLL and ENTER keys to the heading of the item you want to change.

Step 2 Press the ENTER key to move the cursor to the value field.

Step 3 Use the SCROLL keys to select the new value for the item.

Step 4 Press the ENTER key to confirm the new value.

Step 5 Use the SCROLL keys to move the cursor to the Update field of the present menu branch.

Step 6 Press the ENTER key to move the cursor to the value field of the Update field.

Step 7 Press the ENTER key to confirm the update.

Step 8 The text Updating appears on the display. Do not push the keys before the text disappears and themenu text is visible.

All the needed changes of a menu branch can be made before using the Update field.

If the phase of the present menu level (menu, sub-menu or item) is unknown to the user, the mainlevel is reached by pressing the EXIT key several times.

4.6 Menus of Tellabs 8120 Mini Node M

The following figures present the menu structure of Tellabs 8120 mini node M.


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Fig. 28 Main Menu of Tellabs 8120 Mini Node M

Fig. 29 Menu of Main Parameters


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Fig. 30 Main Interface Parameters Menu of IF1 and IF2


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Fig. 31 Menu for IF1 and IF2 Parameters


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Fig. 32 Menu for Neighbour Node Message Parameters


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Fig. 33 Cross-Connect Menu

4.6.1 Security Menu

The security menu contains two items (device mode and panel locking) which can be set. This menuis entered in a specific way explained in 4.6.7 Entering Security Menu of Tellabs 8120 Mini Node M.

Device Mode Menu

The Device Mode menu specifies the device mode of the NTUM. The NTUM can be either aMartisDXX device or a stand-alone device. The MartisDXX device is usually a part of the Tellabs8100 network and it is managed by Tellabs 8000 manager. Therefore, you are not allowed toconfigure the cross-connections of the MartisDXX device by using the front panel keys and theLCD display. Neither are remote configuration and monitoring allowed when the NTUM is inthe MartisDXX device mode. The text DXXNTUM indicates that the NTUM is in MartisDXXdevice mode.


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The text NTUM indicates that the NTUM is in the stand-alone mode. In this mode all theconfiguration and monitoring operations are allowed by the use of the front panel keys and theLCD display if the panel is unlocked.

To change the device mode, use the SCROLL keys to select the new mode and press ENTER. WhenENTER is pressed, the new mode is saved into the non-volatile memory to make sure that theNTUM will go to the correct mode after reset.

Panel Menu

The item for key panel locking has three settings (panel unlocked, panel locked, panel configurationlocked) to prevent the user from accidentally selecting the wrong settings to the configuration itemsand thus making the NTUM non-functional. To make any changes to the NTUM configuration, theitem for the key panel locking has to be unlocked. The items for panel locking and their features are

• Panel locked, Locked

• NTUM configuration cannot be seen nor altered

• Some statistics are available to the user

• Panel configuration locked, Cfg. Lock

• NTUM configuration can be seen but not altered

• Panel unlocked, Unlocked

• NTUM configuration can be seen and altered

• Menus are available to the user according to the device mode

To change the panel mode, use the SCROLL keys to select the new mode and press ENTER. Whenthe ENTER is pressed, the new mode is saved into the non-volatile memory to make sure that theNTUM will go to the correct mode after reset.


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Fig. 34 Device Modes of Tellabs 8120 Mini Node M


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NTUM Menu

The NTUM user interface can be used to configure a local or a remote NTUM. The local NTUM isthe target by default. The remote NTUM that is connected to the local NTUM via a trunk interface(IF1 or IF2) can be configured by using the local user interface if the HDLC communication channelis established over the trunk. To set the target NTUM, use the SCROLL keys to select it and pressENTER. Choices for the target NTUM are Local, Remote1 and Remote2. The number after the textRemote specifies the trunk interface that is used. The yellow LED of the corresponding interfaceblinks on the front panel of the local NTUM when it is in remote mode.

The remote configuration is not allowed if the NTUM is part of the Tellabs 8100 network.

4.6.2 Faults Menu

Three menu branches are available from the field of Faults by pressing the ENTER key: ActFlts,FltHist and ClrHist. From these fields the user can see the fault(s) which are active at the momentor receive the information of the latest fault state transitions (the fault history report) and clearthe history report.

ActFlts

The ActFlts menu is used to ask active faults from the target NTUM by pressing the ENTER key.The active faults can be seen in the following list format (fault/interface or common level fault).

1 Rx signal mis. IF 1

2 Master clock flt Com

3 Fr fe alarm IF 2

4 AIS from X-bus IF 5

If there are several faults, two of them will be displayed and the rest of the faults can be viewed byusing the SCROLL keys. Pressing the ENTER key activates a new fault query from the NTUM.

FltHist

From the FltHist menu the user can see the fault history report by pressing the ENTER key. Thefault history is useful when a fault has been on (the red LED flashes) but when asking for activefaults the response is No faults. The display format is:

1 Reset Com DLT

2 Master clock Com ON

3 Rx signal mi IF 1 ON

4 Fr f-e alarm IF 2 ON

5 Fr f-e alarm IF 2 OFF

6 Rx signal mi IF 1 OFF


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If there are several faults on the history report, two of them will be displayed and the rest of thefaults can be viewed by using the SCROLL keys. The latest fault transition has the biggest number(in the case above 6 Rx signal mi IF1 OFF is the latest fault transition). Pressing the ENTER keyactivates a new fault query from the NTUM.

ClrHist

The fault history can be cleared in the ClrHist menu by pressing the ENTER key. After clearing thefaults the unit starts the fault history collection automatically.

4.6.3 Parameters Menu

The general node and unit level parameters can be read and changed in the branch Param. (allparameters, e.g. the serial number, are not changeable). The readable and changeable parametersare the node and unit level identification data, the cross-connection clock selection (MastClk), themodule defining, the 1+1 protection and the measurement point selection.

Node Identification Menu

The NTUM has its own node identification number 0…65535 which can be changed by the user.Each node in the network must have a different Node ID.

Unit Identification Menu

Only the unit level information of the NTUM can be read in this branch.

Hw-ver The hardware version of the unit.

Sw-ver The software version of the unit is used to identify the downloaded software version etc.

Year The year when the unit was manufactured.

Week The week when the unit was manufactured.

Serial The serial number which is an absolute identification of the unit. The serial number is set atthe production phase of the unit.

Master Clock Menu

The NTUM has a 16-MHz master clock which is used for generating the timing of the cross-connectbus. The timing consists of

• 16 MHz

• 8 kHz frame sync

• 500 Hz multiframe sync

The interfaces use these signals in the bus interface. The 16-MHz clock is also used to generate theTx clock of each data interface. The master clock is usually synchronized to one of the incomingdata signals (generally a 2 Mbit/s trunk). The clock of the desired interface is collected by usinga separate synchronization clock bus (SYB). The master clock object tells the required interfaceto connect its Rx clock to this bus.


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The clock fallback list is used to define the synchronization priority order. The list can have up tofive entries. The form of the clock fallback list is

1. IF_

2. IF_

3. IF_

4. IF_

5. Ext. clock (Internal)

The list can also be made shorter. The last entry is followed automatically by the internal state.

On the back panel of the NTUM there is a connector for the external clock input. It can be selectedto the clock fallback list. The frequency of the external clock can be defined as n x 64 kHz, wheren = 1…132 (64 kHz…8448 kHz).

The NTUM also has a clock output. It is electrically similar to the clock input. The clock outputfrequency is derived from the master clock and its frequency can be selected (n x 64 kHz). Usually2048 kHz is used.

The master clock of an NTUM can be configured and monitored by using the master clockmenu. The master clock menu is entered by pressing the ENTER key when the cursor blinks onthe MastClk text.

TheMaster Clock menu contains the following fields (upper line).

Update This field updates the new master clock parameters to the target NTUM (local or remote).

Choices All the available interfaces that can be used as the master clock are displayed here. Ifthere are no available interfaces, the text None is shown. The text Ext refers to theexternal clock. The list of the available interfaces can be scanned by using the SCROLLkeys. To add an interface in the fallback list, press ENTER when the cursor blinks onthat interface. The text Add IFn in 1st FBL slot is shown. Use the SCROLL keys tochange the slot number. When the slot number of the fallback list is selected, pressENTER to add the interface in the fallback list.

FB List The fallback list of the master clock is displayed in this field. The elements of the list arein the priority:source format. The text None indicates that the list is empty. The fallbacklist can be scanned by using the SCROLL keys. To remove an interface from the fallbacklist, press ENTER when the cursor blinks on that interface. The text Remove IFn fromFB List is shown. Press ENTER again to remove the interface, otherwise press EXIT.

State This is the sub-menu for the state monitoring of the master clock. Press ENTER to startthe state monitoring. The State Monitoring sub-menu contains the following fields whichare automatically updated every fifth second.

Source This field indicates the current source of the master clock: Intern, SYB1, SYB2 orExtern.

State This field indicates the current state of the master clock: OK, Alarm.

SYB1/2 This field displays the source interfaces of the sync clock busses.

Ext Clk This field specifies the frequency of the external clock. To change the frequency, use theSCROLL keys to select a new frequency and press ENTER.

Clk Out This field specifies the frequency of the clock output. To change the frequency, use theSCROLL keys to select a new frequency and press ENTER.


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OutCtrl This field specifies the control mode of the clock output. The output clock controlling iseither ON or OFF. If the output clock controlling is ON and the output clock is enabled(an output clock frequency is specified), the output clock will be disabled if the source ofthe master clock is either an internal or an external clock. If the output clock controllingis OFF, the state of the output clock does not depend on the source of the master clock. Tochange the control mode, use the SCROLL keys to select a new mode and press ENTER.

AcpTime This field specifies the acceptance time for the clock sources. A clock source is a validsource for the master clock if the status of the clock source has been OK for at least aslong as the acceptance time specifies. The acceptance time value is 0-120 s. To changethe acceptance time, use the SCROLL keys to select a new time and press ENTER.

Module Configuration Menu

The NTUM device has six interfaces and four independent interface modules. The modules arenumbered so that the modules 1 and 2 have corresponding interfaces (1 and 2), but modules 3 and 4have both two interfaces (3, 4 and 5, 6). When the user has decided to install a new interfacemodule, also the module configuration must be changed from the Config branch.

IF1

Install This field shows the currently installed module (read-only information).

Type This field appears only if the installed module contains strappings. The field shows theinformation on module strapping (75 Ω/120 Ω/ contradirectional/codirectional).

Config The module configuration field defines what kind of a module the unit program currentlyservices. Thus, there should be the same module in the Install field as in the Configfield. There is also a Not def selection which means that the interface has not beendefined (module not in use) and no faults which belong to this module will be reported.If, for example, a module is not installed, the module should be configured as Not def.

1+1 Protection Menu

The interfaces 1 and 2 can be configured into the 1+1 protected mode. In the protected mode bothinterface modules must support the selected bit rate. The Rx signal faults are classified into severalcategories. The switch uses fault categories to select the interface to be used. When the IF1 or IF2parameters are updated in the protected mode, both interface parameters will be updated (exceptfor the baseband parameters Line, Level, ScrmTyp, ScrmMo, 10E-3 Consequences, FltMsk andConfigured Module).

Update This field is used to update the 1+1 protection parameters in the NTUM. The 1+1parameters (Mode, HomeSta, ChaDel and Force) can be changed on other fields butafter the changes the parameters must be updated by pressing the ENTER key in theUpdate field.

Mode In this field the 1+1 mode can be defined on/off. The No prot selection means normalunprotected mode, ProtIf1 means protected mode by settings of interface 1, and ProtIf2protected mode by settings of interface 2.

CurSele The field is displayed only in the 1+1 protected mode; it shows which Rx signal isconnected to the cross-connection. The field is auto-refreshed.


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HomeSta This field is displayed only in the 1+1 protected mode. The home state can be changedin the field to the switch which selects the Rx signal. The selection No H-S meansthat the switch chooses the better Rx signal and the selection changes will be madeonly when the unused Rx signal quality is better than the used Rx signal. The selectionIF1/IF2 means that the IF1 or IF2 interface is defined as the home state, and whenboth interfaces are classified to the same category, the switch selection returns alwaysback to the home state interface.

ChaDely This field is displayed only in the 1+1 protected mode. The field handles the protectionswitch change delay (0 ms…10 min). The change delay is a filter parameter of theprotection switch so that the fault transition which can affect the switch turning must beactive for the duration of the change delay before the switch turns.

Force This field is displayed only in the 1+1 protected mode. The field handles the forcecontrol of the protection switch. The state None is normal; in the state IF1 or IF2 theprotection switch is forced to select IF1 or IF2. The time-out for this control is the sameas the time-out for IF1 controls.

Measurement Point Menu

The NTUM device has one measurement point. The signal can be selected to this point frominterfaces 1 or 2 and the signal can be either Rx clock or data or Tx clock or data.

MeasPnt The measurement point selections can be scanned by using the SCROLL keys. Pressthe ENTER key to confirm the selection.

4.6.4 Interface Parameters Menu

The interface parameters (interface 1…6) can be read and changed in this branch. Thereading/change possibility depends on the panel state (see 4.6.1 Security Menu). Interfaces canbe divided into two groups according to their sub-menus: interfaces 1…2 have the same type ofsub-menus, whereas the sub-menus of interfaces 3…6 are similar.

Parameters of Interface 1 and 2

The following menus are available when the selected interface is IF1 or IF2.

Param The general interface parameters can be read, changed and updated in this branch.

Update This field is used to update the interface parameters. The interface parameters (Framing,Rate, Basband, BitUse, CAS, CntrlTyp, Buffer, FtsData, FltMsk, FltAct) can be changedin other fields and sub-menus but after changes the parameters must be updated bypressing the ENTER key in the Update field.

Framing The possible selections are On, Off RxM, Off. All selections are available when theinterface is in unlocked state. If the state is locked, the changes can be made onlybetween Off RxMon/ Off.

Rate The selectable bit rate depends on the configured module (the module must support theselected bit rate). If the device is in 1+1 protected mode, both interfaces must support theselected bit rate. When the framing is on, the minimum bit rate is 128 kbit/s (2 x 64k). Ifthe interface is locked, no bit rate changes can be made.


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Basband This field is displayed when the configured interface module is a baseband module. Thereare three sub-menus under the Basband menu.

*Line The type of the line can be 2-wire or 4-wire when the biphase coding is used (BTE384).

*Level The possible output levels depend on the type of the BTE.

*ScrmTyp With BTE384 the possible scrambler types are None, V32, V29, NDPN and NPDNV29;with other BTEs None and V29.

*ScrmMo The field is displayed only when the configured module is BTE384 and the possiblescrambler modes are call and answer.

*WetCur The field is displayed only when the configured module is BTE384 and the wettingcurrent has the states ON/OFF. In the state ON, the BTE module detects when the NTU isin the POWER OFF state.

VdhScrm This field is displayed when the configured interface module is V35-G704 or X21-G704.The scrambler has two states, ON/OFF.

BitUse This field is displayed when the framing is ON and the sub-menus depend on the selectedbit rate (in the 8M mode the sub-menus are different).

The following fields (TS0B1, CRCE, FSW/RAI, TS0B4…TS0B8) are displayed when the bitrate is not 8M.

TS0B1 The field for selecting the use of TS0B1; one of the following:CRC use: CRC4 will be generated into this bitHDLC use: HDLC channel in this bitX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by a separate command, e.g. in master clock remote alarm use0: the bit will be transmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state.Note! When the control type is master or slave, this bit must be in CRC use.

CRCE The field is displayed if TS0B1 is in the CRC state and the CRCE bit can be configuredas:ReEnd: CRCE bit is used to indicate remote end CRC errors0: the bit will betransmitted at the permanent 0 state1: the bit will be transmitted at the permanent 1 state

FSW/RAI The frame synchronization word and the far-end alarm (TS0B3) usage:Regen:Transmitted sync. word and remote-end alarm are regeneratedX-Con: Transmittedsync. word and remote-end alarm comes from the cross-connectionX-Sync: Sent frameis synchronized to the frame coming from the cross-connectionRAIXcon: Remote-endalarm comes from the cross-connection

TS0B4…8 Fields for selecting the use of TS0B4…TS0B8 are similar (but independent).HDLC use:the bit is selected for HDLC useX-Con: the bit comes from the cross-connectionCBSC:the bit is controlled by a separate command e.g. in master clock remote alarm use0: thebit will be transmitted at permanent 0 state1: the bit will be transmitted at permanent 1state

The following fields (TS99B1-7, CRCE, TS99B8 and TS66B8) are displayed when the bit rate is 8M.


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*TS99B1-7 The field for selecting the use of TS99B1-7.CRC use: CRC will be generated inthese bitsHDLC use: bits are selected for HDLC useX-Con: bits come from thecross-connectionCBSC: bits are controlled by a separate command e.g. in master clockremote alarm use0: bits will be transmitted at the permanent 0 state1: bits will betransmitted at the permanent 1 state

*CRCE The field is displayed if TS99B1-7 are configured for CRC use.ReEnd: CRCE bit is usedto indicate remote-end CRC errors0: the bit will be transmitted at the permanent 0 state1:the bit will be transmitted at the permanent 1 state

*TS99B8 The field for selecting the use of TS99B8.HDLC use: the bit is selected for HDLCuseX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by aseparate command e.g. in master clock remote alarm use0: the bit will be transmitted atthe permanent 0 state1: the bit will be transmitted at permanent 1 state

*TS66B8 The field for selecting the use of TS66B8.HDLC use: the bit is selected for HDLCuseX-Con: the bit comes from the cross-connectionCBSC: the bit is controlled by aseparate command e.g. in master clock remote alarm use0: the bit will be transmitted atthe permanent 0 state1: the bit will be transmitted at the permanent 1 state

The HDLC and MCLRAI fields are both present whatever the bit rate is.

*HDLC The HDLC control channel usage is selected in this branch. When the HDLC channel isused in the time slots TS0, TS66 and TS99 or it is desired to be used there, the HDLCusage must be defined in the special time slot/bit field(s).

*HDLC The following can be selected in this field:In use: the HDLC channel will be in use.-----:the HDLC channel is not in use.

*TS When the HDLC channel is in use, the time slot for HDLC use can be selected in thisfield.

*Bit1…8 When the HDLC channel is in use, the bit(s) for HDLC use can be selected in these fields.

*MCLRAI The master clock remote alarm usage can be controlled in this branch. The clockremote-end alarm can be configured into frame special bits or in data bits. Specialbits must be configured as CBSC for the clock remote-end alarm usage. If the clockremote-end alarm is in the data bit, this time slot must not be cross-connected (MCLRAIusage reserves the whole time slot).MCLRAIIn use: MCLRAI will be in use.-----:MCLRAI is not in use.TS: When MCLRAI is in use, the time slot for MCLRAI use canbe selected in this field.Bit1…8: When MCLRAI is in use, the user can define in thisfield which bit of the time slot is in MCLRAI usage.Pol.: When MCLRAI is in use, theuser can define the polarity of alarm in this field.

CAS This field is displayed when the framing is ON and sub-menus depend on the selectedbit rate (in the 8M mode there are four CAS groups A, B, C and D; and in the other bitrate modes for signalling only one time slot is reserved).

The following fields (CAS, Bit5,7,8) are displayed when the bit rate is not 8M.


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*CAS Use of channel associated signalling. When the bit rate is 1088 kbit/s (17 x 64 kbit/s) orhigher, TS16 is used for signalling. In other cases the last time slot is used for signalling,e.g. if the rate is 384 kbit/s (6 x 64 kbit/s), the signalling will be in TS5:On: one timeslot is reserved for signallingOff: signalling is not used and the signalling time slotcan be in data use

*Bit 5,7,8 The fields are displayed if CAS is turned ON. There are three similar fields for selectingthe usage of the special bits B5, B7, B8 of the signalling time slot.X-Con: the bit comesfrom the cross-connectionCBSC: the bit is controlled by a separate command e.g. inmaster clock remote alarm use0: the bit will be transmitted at the permanent 0 state1: thebit will be transmitted at the permanent 1 state

The following fields (CAS A, Bit5,7,8…CAS D, Bit5,7,8) are displayed when the bit rate is 8M.The fields for the signalling groups are similar. For this reason only the group CAS A is mentionedhere. The time slots for the signalling groups are CAS A in TS67, CAS B in TS68, CAS C inTS69 and CAS D inTS 70.

*CAS A Use of channel associated signalling of group A (TS67).On: TS67 time slot is reserved forsignallingOff: signalling is not used and the signalling time slot can be used for data use

*Bit 5,7,8 Use of the bits 5, 7, 8 is as above.

Buffer The field is for handling the Rx buffer. The possible selections: 4, 8, 64 frame buffer.The selected bit rate and the split trunk usage affect the possible buffer length.

FtsData The idle data of unconnected time slots can be defined in this branch. This meansthat the time slots which are not cross-connected are transmitted with idle data. It isrecommended that all bits are set at the state 1.

*Bit1…8 There are eight similar fields (one field for each bit).1: the bit will be transmitted at thepermanent 1 state.0: the bit will be transmitted at the permanent 0 state.

FltMsk In this field the fault mask state (ON/OFF) can be handled. When the fault mask is ON,no interface faults will be generated (only the fault of the mask itself).

FltAct Some fault actions and consequences can be defined in this branch. There are foursub-menus (AisInh, RaiInh, RaiCsq and E3Csq), each with two states ON/OFF.

*AisInh The AIS inhibit ON affects the AIS alarm generating.OFF: the AIS alarm will begeneratedON: when the received signal is AIS or in the received signalling TS is AIS, noalarms will be generated due to this fault.

*RaiInh RAI inhibit ON affects the far-end remote alarm generating (from frame and multiframelevel).OFF: the remote-end alarm(s) will be generatedON: when the received frame ormultiframe far end alarm, no alarms will be generated due to this fault.

*RaiCsq The remote alarm consequences affect to the AIS inserting into the received signallingtime slot when the frame or the multiframe far-end alarm has been received.ON: AIS willbe inserted when the far-end alarm has been received. The far-end alarm fault is providedwith service alarm status (S).OFF: The far end alarm does not cause AIS inserting into thesignalling time slot(s). The far-end alarm fault is generated without service alarm status.

*E3Csq This field affects the AIS inserting into the received signal when the received signal errorrate is worse than 10E-3.ON: AIS will be inserted into the received signal when theerror rate is worse than 10E-3. The BER10E3 alarm will have the service alarm status(S).OFF: The error rate 10E3 does not cause the AIS insertion into the received signal.The BER10E3 alarm is generated without service alarm status.

AisDet AIS detection in unframed mode ON/OFF:


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NnmPara This branch handles the neighbor node parameters of the interface. When the interfaceframing is ON and the HDLC channel is in use, these parameters affect the sending andthe monitoring of neighbor node parameters.

Update This field is used to update the neighbor node parameters into the NTUM. The neighbornode parameters (Expected neighbour and Options) can be changed in other fields butafter the changes the parameters must be updated by pressing the ENTER key in theUpdate field.

Alarms This branch has two sub-menu fields Own and the Neighbour alarms (Loop, Unexpectedneighbour, No connection, OK). The Alarm fields are auto-refreshed.

*Own This is a read-only field where the neighbor node alarms of the target NTUM can be read.

*Far-end This is a read-only field where the neighbor node alarms of the neighbor of the targetNTUM can be read. The field is displayed only if there is a connection between theneighbors.

Exist This branch has six sub-menu fields each of which has data of the existing neighbor(neighbor: node ID, subrack address, unit number, link number, interface number andport number). The fields are auto-refreshed.

Expec The expected neighbor data has the same kind of data fields as in the Exist branch.

CpyExi Copies the existing data structure to the expected field (you have to remember to update).This is useful when updating the correct neighbor info.

Options This branch has three sub-menus to activate or deactivate the sending, the supervisionand the monitoring.

*MesSend ON: the neighbor node data sending activatedOFF: the neighbor node data sendingdeactivated

*StaMon ON: the neighbor node state monitoring activatedOFF: the neighbor node statemonitoring deactivated

*NeigSup ON: the neighbor node supervision activatedOFF: the neighbor node supervisiondeactivated

Locking This field is used to lock or unlock the interface. Locking means that the interfaceallocates the needed capacity from the cross-connection and unlocking that the interfacedeallocates the reserved cross-connection capacity. Please note that the text on the LCDdisplay describes the next movement in the locking state if ENTER is pressed (e.g. ifthere is the text Lock, the interface is in the unlocked state and the next change is madeto lock the interface).

Loops The loop can be activated/deactivated and the state of the loops can be seen in this branch.

State This is a read-only field where the loop state can be seen (e.g. Line Loop, EquipmentLoop, Interface Loop, Remote Loop). The field is auto-refreshed.

Set The loops can be activated/deactivated in this field. The Remote loop availabilitydepends on the interface parameters (Framing, HDLC, NnmPara/MesSend and Module).

When the remote loop is a V54 loop (BTE384, and HDLC is not used), the following menus aredisplayed.

TraBits The count of transmitted bits during a test (test generator connected when RL).

ErrBits The count of errored bits during the test.

InjErr Inject one error into the transmitted data.

Time-out The interface controls time-out parameter can be handled in this branch.

Time-out The interface controls time-out in minutes. (When the loop has been activated, it will bedeactivated automatically after the time defined in Time-out).


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ErCntrs The error counters can be read and cleared in this branch. The fields are auto-refreshed.

ResCtrs Clear all error counters.

FraLos Count of frame alignment losses (read-only).

FSW Count of faulty frame alignment words (read-only).

CRC Count of CRC errors (read-only).

CRCE Count of faulty CRC E-bits (read-only).

BufSlip Count of buffer slips (read-only).

Code Count of code errors (read-only).

RxDelay The value describes the time which the incoming data is in the buffer before it is clockedinto the cross-connection. The time value should remain the same. If the time increasesor decreases, the incoming clock of the interface differs from the clock used by thecross-connection system. This field is auto-refreshed.

G.821 Branch to the standard G.821 statistics.

*Display By pressing the ENTER key in this field the total time of the statistics can be seen on thedisplay:Total Time9 dd 13 h 24 min 5 sWhen pressing the SCROLL keys, the displaywill show the available time, the unavailable time, severely errors seconds, erroredseconds and degraded minutes. This field is auto-refreshed.

*ResG821 Clears the G.821 counters.

BbInfo This branch is displayed if the interface module is BTE-384 or BTE-768.

*RxLevel Read-only information from the received signal level.

*RxOual Read-only information from the received signal quality with A (best quality) through F(poorest quality).The fields are auto-refreshed.

4.6.5 Cross-Connection Menu

The cross-connection is done in the switching matrix of the NTUM. The cross-connection buscontains about 1050 cross-connectable time slots (8-bit bytes). The bits from the interfaces arecollected by using this bus. The cross-connect switch combines (in other words, makes thecross-connection) the needed new bytes for the interfaces in accordance with the cross-connectioncommands by using 8 kbit/s granularity. The commands are stored in a non-volatile memory.

The cross-connections of the target NTUM (local or remote) can be configured and seen by usingthe Cross-Connection menu. To simplify the use of this menu it is divided into four sub-menus.

Cross-Connection Configuration Menu

Cross-connections can be created and deleted by using the Configuration menu. This sub-menucan be accessed only when the NTUM is in the stand-alone mode and the panel is unlocked. Thissub-menu is divided into sub-menus to support the configuration of the various cross-connectionformats (TS pair, TS area and TS bits) and the powerful delete operation (Del All). The followingfields are common to all of these sub-menus:


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Oper This is the leftmost field of the TS pair, TS area and TS bits sub-menus and it isused to execute the desired cross-connection operation that is either CreCons(create) or DelCons (delete). When it has been selected by using the SCROLL keys,the operation can be executed by pressing the ENTER key. Before executing thecross-connection operation all parameters should be set.

Dir This field is used to specify the directionality of the cross-connection: eitherunidirectional (A→B) or bidirectional (A⇔ B).

XB+XD This field is used to specify the channel of the cross-connection. The n x 8 kbit/s andn x 64 kbit/s groups mapped by the channel interfaces are called the XB channel.The XB channel can be a combination of 64 kbit/s and 8 kbit/s signals. If theinterfaces are equipped with signalling or control signals, they are mapped eitherto the XB channel or to the corresponding signalling bits (n x 500 bit/s) of the XDchannel. In the later case the signals are mapped to the G.704 compliant multiframeof the 2 or 8 Mbit/s trunk. The n x 500 bit/s signalling bits are called the XD channelof the interface. The number of the signalling bits depends on the capacity of theXB channel. Data interfaces do not normally use the XD channel. Signalling bitsare reserved for the XB channel in the following way.

XB Capacity XD Capacity

TSn/B1…B8 64 kbit/s 4 bits (a,b,c,d bits in G.704 structure)

TSn/B1…B4 32 kbit/s 2 bits (a,b)

TSn/B5…B8 32 kbit/s 2 bits (c,d)

TSn/B1…B2 16 kbit/s 1 bit (a )

TSn/B3…B4 16 kbit/s 1 bit (b )

TSn/B5…B6 16 kbit/s 1 bit (c )

TSn/B7…B8 16 kbit/s 1 bit (d )

The a, b, c and d bits of the XD channel in the G.704 multiframe correspond to the XB channeltime slots in the G.704 frame. The capacity reserved by XB and XD channels is determined bythe interface type and the user requirements. Four signalling bits are reserved for each time slot.Even if only some of the bits are needed, all four bits are cross-connected and transferred to thefar-end channel interface.


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Fig. 35 XB and XD Channels in Network

X-Group If the cross-connection is a part of the cross-connection group (X-Group), the IDof the group can be set by using this field. A zero X-Group ID indicates that thecross-connection is not a member of any of the X-Groups and it is always in theactive state. The X-Group IDs 1…16382 are valid.

Time Slot Pair The TS pair cross-connection format describes the connection between the time slotof an interface and another time slot of the same or another interface. Both interfacesof the connection should reside in the same NTUM (local or remote).

The TS Pair sub-menu contains the following fields: Oper X-Group, Dir, XB+XD, IF A, IF B, TSA, TS B where

• IF A: Interface number (only locked interfaces are valid). This is the source interface of theunidirectional connection.

• IF B: Interface number (only locked interfaces are valid). This is the destination interface of theunidirectional connection.

• TS A: Number of the time slot in the IF A. This is the source time slot of the unidirectionalconnection.

• TS B: Number of the time slot in the IF B. This is the destination time slot of the unidirectionalconnection.

Example: DIR = A<->B, XB, IF A = 1, IF B = 2, TS A = 2, TS B = 5


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Fig. 36 Cross-Connection of One Time Slot between Two Framed Interfaces

Time Slot Area The TS area cross-connection format describes the connection between thecontinuous area of time slots of an interface and another continuous area of timeslots of the same or another interface. Both interfaces of a connection should residein the same NTUM (local or remote).

The TS Area sub-menu contains the following fields: Oper X-Group, Dir , XB+XD, IF A, IF B,fstTS A, lstTS A, fstTs B, lstTs B where

• IF A: Interface number (only the locked interfaces are valid). This is the source interface of theunidirectional connection.

• IF B: Interface number (only the locked interfaces are valid). This is the destination interface ofthe unidirectional connection.

• fstTS A: Number of the first time slot of the area in the IF A. This specifies the source of theunidirectional connection.

• lstTS A: Number of the last time slot of the area in the IF A. This specifies the source of theunidirectional connection.

• fstTS B: Number of the first time slot of the area in the IF B. This specifies the destination of theunidirectional connection.

• lstTS B: Number of the last time slot of the area in the IF B. This specifies the destination of theunidirectional connection.

Example: DIR = A->B, XB, IF A = 1, IF B = 2, fstTS A = 0, lstTS A = 2, fstTS B = 3, lstTS B = 5

Fig. 37 Cross-Connection of Three Time Slots between Two Framed Interfaces


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Time Slot Bits The TS Bits cross-connection format describes the connection between the bitsin a time slot of an interface and other bits in a time slot of the same or anotherinterface. The interfaces that are to be connected should reside in the same NTUM(local or remote).

The TS area sub-menu contains the following fields: Oper X-Group, Dir, XB+XD, IF A, IF B, TSA, TS B, bMask A, bMask B where

• IF A: Interface number (only the locked interfaces are valid). This is the source interface of theunidirectional connection.

• IF B: Interface number (only the locked interfaces are valid). This is the destination interface ofthe unidirectional connection.

• TS A: Number of the time slot in the IF A. This is the source time slot of the unidirectionalconnection.

• TS B: Number of the time slot in the IF B. This is the destination time slot of the unidirectionalconnection.

• bMask A: Bit mask of the TS A. The bit mask consists of eight bits (one byte) where a 1 state ofa bit indicates the connection. In the user interface of the NTUM the bit mask is presented in thehexadecimal format. 4.7.7 Binary-to-Hexadecimal Conversion Table contains the table for thebinary to hexadecimal conversion.

• bMask B: Bit mask of the TS B.

Example: DIR = A<->B, XB, IF A = 1, IF B = 2, TS A = 2, TS B = 5, bMask A = 85H, bMask = 62H

Fig. 38 Cross-Connection of Time Slot Bits

Delete All This menu is used to delete all cross-connections of the target NTUM (local orremote). The X-Group identifier of the cross-connections to be deleted can bespecified. The default value of the X-Group identifier is Any, which will delete allcross-connections of the target NTUM.


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Cross-Connection Display Menu

By using this menu the current state of the cross-connections can be seen. Also the existingcross-connections can be deleted more efficiently than by using the Configuration menu. TheX-Group identifier and one interface of the cross-connections to be displayed can be specified.

To see the existing cross-connections, press the ENTER key twice when the cursor blinks over theGetCons field on the upper line of the LCD display. The text Getting is shown on the displayduring the message send/receive operation. If the target NTUM does not contain the specified(interface, x-group) connections, the text No connections is shown. Otherwise, the first connectionis shown. The cross-connection is shown so that it occupies both lines of the LCD display and thesource end of the unidirectional connection is on the upper line. The rest of the connections can beviewed by using the SCROLL keys.

The existing cross-connection can be deleted by using this menu only when the NTUM is instand-alone mode and the panel is unlocked. To delete it, press the ENTER key when the existingcross-connection is on the display. After that, a question Delete connection? is shown. PressENTER again if you want to delete the connection, otherwise press EXIT.

X-Group Menu

An x-group is a group of the cross-connections that have a common x-group identifier. The x-groupis either active or passive. If the x-group is active, all cross-connections of that x-group are active.Several x-groups can be in active state at the same time if the cross-connections of these x-groups donot overlap each other. The x-group IDs 1…16382 are valid and the state of the x-groups are storedin a non-volatile memory.

The x-group concept is very useful when the user wishes to use one NTUM in the differentcross-connection configurations. It is much more simple to passivate the current configuration andactivate the new one by passivating and activating the x-groups than deleting the current commandsand creating new ones by using the Cross-Connection Configuration menu.

The state of the x-groups of the NTUM can be configured and seen by using the X-Group menu. Tosimplify the use of this menu it is divided into two sub-menus (Config, Display).

• Configuration: This menu is used to activate and passivate the x-groups. It can be accessed onlywhen the NTUM is in stand-alone mode and the panel is unlocked.The x-group configuration menu consists of the following fields.

• Oper: This field specifies an operation which is used either to activate (ActGrp) or to pas-sivate (PassGrp). When the operation has been selected by using the SCROLL keys, theoperation can be executed by pressing the ENTER key. Before executing the operation thex-group should be specified.

• X-Group: This field is used to specify the x-group to be activated or passivated.

• Display: By using this menu the current state of the x-groups can be seen and their states can bechanged.

To see the state of the x-groups of the existing cross-connections, press ENTER when the cursorblinks over the Display field. The text Getting is shown on the display during the messagesend/receive operation. After that the states of the first two x-groups are shown on the LCD display,each on its own line. The rest of the x-groups can be viewed by using the SCROLL keys. Theletter E in the status line of an x-group indicates that the x-group is empty, in other words it doesnot contain any cross-connections.


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The state of the x-groups can be changed by using this menu only when the NTUM is in stand-alonemode and the panel is unlocked. To change the state of the x-group, press ENTER when the cursor ison the upper line of the display. After that the question Activate/Passivate X-Group n? is shown.Press ENTER again if you want to change the state, otherwise press EXIT. Note that x-group 0 isalways active and it is not possible to change its state.

Interface Capacity Menu

This menu displays the cross-connection capacity of the locked interfaces of the target NTUM (localor remote). The capacity of an interface is displayed in the time slots + bits format. Each time slotcontains eight bits. If the interface has signalling capacity, the XD symbol is added at the end of theline. To see the capacity of the interfaces, press ENTER when the cursor blinks on the IF Cap?text. The capacities of the two first interfaces are displayed and the rest of the interfaces can beviewed by using the SCROLL keys.

4.6.6 Copy Settings Menu

The interface parameters can be copied from one interface to another (the locking state and theconfigured module type are not copied). Also the cross-connection of one interface can be copied toanother, or the whole cross-connection of the device can be copied. The copying possibility dependson the mode of the device and the panel state.

Copy Interface Parameters Menu

The copying of the interface parameters is started by pressing the ENTER key in the IfParam field.After that the text CpyFrom is shown on the display.

Now the ENTER key must be pressed and the cursor moves on the LocIf1 text. Then the interfacewhere parameters will be copied from is selected by using the SCROLL keys.

When the interface has been selected, the reading of the parameters is activated by pressing theENTER key and the text CpyTo is displayed. Now the ENTER key must be pressed and the cursormoves to the interface selection. The interface where parameters will be copied to is selected withthe SCROLL keys and the parameters are copied by pressing the ENTER key.

Copy Cross-Connections Menu

The copying of the cross-connections is started by pressing the ENTER key in the X-Con field.After that the CpyFrom text is shown on the display.

Now the ENTER key must be pressed and the cursor moves on the LocIf1 text. Thecross-connection(s) that are to be copied are selected using the SCROLL keys.

When the interface/device has been selected, the reading of the cross-connections is activated bypressing the ENTER key and the text CpyTo is displayed. Now the ENTER key must be pressedand the cursor moves to the interface/device selection.

The target to which the cross-connections are to be copied is selected with the SCROLL keys. Thecopy of the cross-connections is confirmed by pressing the ENTER key. If the selected interfacewhere the copy has been performed from has connections only to one interface, the text Peerinterface is IF1 appears on the LCD display where the user can select the other interface of thecross-connection(s).


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The copying of the cross-connections is confirmed by pressing the ENTER key.

4.6.7 Entering Security Menu of Tellabs 8120 Mini Node M

To enter the Security menu, press all the four keys simultaneously for about five seconds until thedisplay shows the items of the Security menu. This must be performed as the first operation after areset and within 30 seconds from the activation of the display.

4.7 Recommended Settings of Framed Interfaces

In the next chapter there are some examples of setting parameters for framed interfaces.

4.7.1 Framed Interface Used as 2048 kbit/s Trunk

Main Parameters

Bit rate 2048 kbit/s

Framing ON

Control type Normal

Buffer length 4 Frames

Bit Usage

FSW usage FSW Regenerate

TS0 B1 usage CRC

CRC E-bits usage Rem end error ind

TS0 B4B5B6B7B8

Permanent 1HDLCHDLCHDLCHDLC

HDLC link ON TS0

Master clock RAI OFF

Free TS Data

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1

CAS ON

Free bits B5B7B8

Permanent 1Permanent 1Permanent 1


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NNM Parameters

NNM options

Neighbour supervision Off

State monitoring Off

Message sending On

Expected neighbour

Node Any

Subrack Any

Unit Any

Link Any

Interface Any

Port Any

4.7.2 Framed Interface Used as 2048 kbit/s User Access Point

Main Parameters


Framing ON

Control type Normal

Buffer length 4 Frames

Bit Usage


TS0 B1 usage CRC


TS0 B4B5B6B7B8

Permanent 1Permanent 1Permanent 1Permanent 1Permanent 1

HDLC link OFF --


Free TS Data

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1

CAS ON

Free bits B5B7B8



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NNM Parameters

NNM options



Message sending Off

Expected neighbour

Node Any

Subrack Any

Unit Any

Link Any

Interface Any

Port Any

The HDLC channel is not used in a user access point. Because the HDLC channel is not used, allNNM options are set to the off state. CAS will be used if the user access device needs the channelassociated signalling. CRC shall be used if the user access device can use G.704 framing withCRC-4. If the CRC is not used, the recommended usage for TS0 B1 is Permanent 1.

4.7.3 Framed Interface Used as 8448 kbit/s Trunk

Main Parameters


Framing ON

Control type Normal

Buffer lenght 4 Frames

Bit Usage

TS99 B1…B7 usage CRC

TS99 B8 usage Permanent 1

TS66 B8 usage Permanent 1


HDLC link ON TS33

Bit mask

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1



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Free TS Data

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1

CAS, All Groups ON

Free bits B5B7B8


NNM Parameters

NNM options



Message sending On

Expected neighbour

Node Any

Subrack Any

Unit Any

Link Any

Interface Any

Port Any

4.7.4 BTE-384-M Settings

Main Parameters

Bit rate 6 x 64 kbit/s(384 kbit/s)

Framing ON

Control type Normal

Buffer lenght 4 Frames

Bit Usage


TS0 B1 usage CRC


TS0 B4B5B6B7B8


HDLC link ON TS0


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Free TS Data

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1

Baseband

Line connection 2-wire full duplex

Scrambler type V.32

Scrambler mode Call

Output level +0 dBm

Wetting current Off

CAS OFF

NNM Parameters

NNM options



Message sending On

Expected neighbour

Node Any

Subrack Any

Unit Any

Link Any

Interface Any

Port Any

The Baseband settings depend on which equipment Tellabs 8120 mini node M is connected to.These settings are for connection to a Tellabs 8100 node. If the piece of equipment connected toTellabs 8120 mini node M is SBM 384A, the Scrambler mode setting will be Answer and theWetting current setting will be in the On state.

4.7.5 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Settings

Main Parameters

Bit rate(depends on the module)

5 x 64 kbit/s (BTE-320-M)9 x 64 kbit/s (BTE-576-M)17 x 64 kbit/s (BTE-1088-2W-M)36 x 64 kbit/s (BTE-2304-M)

Framing ON


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Main Parameters

Control type Normal

Buffer length 4 frames

Bit Usage


TS0 B1 usage CRC


TS0 B4B5B6B7B8


HDLC link ON TS0


Free TS Data

1 2 3 4 5 6 7 8

1 1 1 1 1 1 1 1

Baseband

Line connection 2-wire full duplex

Scrambler type V.32

Scrambler mode Call/Answer26

Output level +13.5 dBm

Timing Master/Slave26

CAS OFF

NNM Parameters

NNM options



Message sending On

Expected neighbour

Node Any

Subrack Any

26It depends on the other end settings.


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NNM Parameters

Unit Any

Link Any

Interface Any

Port Any

4.7.6 Cross-Connection Example

IF 1; trunk <-> IF3; V.35 64kbit/s + CRC + Control Channel (8 kbit/s)

IF Cap = 1TS+2bits (Use the menu to get this information)

DIR = A<->B, XB, IF A = 1, IF B = 3, TS A = 4, TS B = 0

DIR = A<->B, XB, IF A = 1, IF B = 3, TS A = 6, TS B = 1, bMask A = c0H, bMask B = 03H

Fig. 39 Cross-Connecting Example

4.7.7 Binary-to-Hexadecimal Conversion Table

CCITT BITS BIT MASK IN

B1 B2 B3 B4 HEXADECIMAL

B5 B6 B7 B8 FORMAT

0 0 0 0 0

0 0 0 1 1

0 0 1 0 2

0 0 1 1 3


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B1 B2 B3 B4 HEXADECIMAL

B5 B6 B7 B8 FORMAT

0 1 0 0 4

0 1 0 1 5

0 1 1 0 6

0 1 1 1 7

1 0 0 0 8

1 0 0 1 9

1 0 1 0 A

1 0 1 1 B

1 1 0 0 C

1 1 0 1 D

1 1 1 0 E

1 1 1 1 F

Examples on Binary-to-Hexadecimal Conversion


B1 B2 B3 B4 B5 B6 B7 B8 HEXADECIMAL FORMAT

0 0 0 0 0 0 0 1 01

0 0 0 0 0 0 1 1 03

0 0 0 0 0 1 1 1 07

0 0 0 0 1 1 1 1 0F

0 0 0 1 1 1 1 1 1F

0 0 1 1 1 1 1 1 3F

0 1 1 1 1 1 1 1 7F

1 1 1 1 1 1 1 1 FF

0 1 0 1 1 0 1 0 5A

1 0 1 0 0 1 0 1 A5

4.8 Service Operations and Modifications

Tellabs 8120 mini node M is housed in a metallic case suitable for tabletop use. Because theconfiguration of Tellabs 8120 mini node M is performed with various user interfaces, most of thesettings needed in installation can be done without opening the case. The Fig. 40 presents themechanical construction of Tellabs 8120 mini node M. The numbers in brackets in the followingdescription refer to the numbers in that figure.


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Inside the metallic case there are the main unit (#6), the interface unit (#3), the power supply (#9)under the protection cover (#7) and up to four changeable interface modules (#1 and #4). In order tomake any physical changes in Tellabs 8120 mini node M hardware, such as changing the interfacemodules, the casing must be opened. The operation must be performed by qualified personnelonly, as it involves electrical safety.

Tellabs 8120 mini node M must be disconnected from the mains supply before removing thecover as high voltages are present inside Tellabs 8120 mini node M case.

The following service operations or modifications require the opening of the casing.

• Changing the interface modules.

• Changing the setting of the straps on the interface modules.

• Updating the controller software by changing the EPROMs.

The straps of the interface modules depend on the module type. Strapping instructions can be foundin 4.10 Connectors and Strappings of Framed Interfaces and 4.11 Connectors and Strappings ofUnframed Interfaces.

The numbered items in Fig. 40 are the following:

1. Upper modules (unframed interfaces)

2. Metal top cover

3. Interface unit VCM 402

4. Lower modules (framed interfaces)

5. Main unit SMU 701

6. Mains supply unit protection cover

7. Distance bolts

8. Power supply

9. Screws

10. Metallic lower casing

11. Front panel

12. Grounding earth wire

13. Spacers


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Fig. 40 Mechanical Construction of Tellabs 8120 Mini Node M

4.8.1 Instructions on Disassembling Tellabs 8120 Mini Node M

The following steps are required when disassembling Tellabs 8120 mini node M.

Step 1 Check that Tellabs 8120 mini node M is disconnected from the mains supply.

Step 2 Loosen and remove all the screws at the back panel of Tellabs 8120 mini node M, slide the coverbackwards and lift it off.

Step 3 To remove the upper modules (#1), loosen and remove the screws on the modules.

• The upper modules can now be lifted off.

Step 4 To remove the VCM402 PCB you have to remove both upper modules first and loosen and removethe distance bolts.

• VCM402 can now be lifted off.


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Step 5 To remove the lower interface modules loosen and remove the distance bolts.

• The lower modules can now be lifted off.

When adding a new interface module, remove the metal plate covering the interface slot inthe back panel. The cover is removed by bending the plate until the points of support brake.If the lower interface modules are not assembled, it is compulsory to use spacers underthe distance bolts.

Step 6 The Tellabs 8120 mini node M device is assembled in the opposite order.

Step 7 When connecting the transmission modules or the interface board to the pin connectors, take carenot to bend the pins of the connectors.

• Check very carefully that the pins are set into the connectors in the correct position and thatthe pins are not bent.

Step 8 Do not use unnecessary force when tightening the screws and nuts.

Step 9 Before connecting the power, make sure that no loose parts are left inside the box.

Step 10 When the power is connected, check that Tellabs 8120 mini node M starts running in the normalway and that no unusual alarms are visible.

• Check with the service computer or with the user interface of the NTU that the voltages arein normal range.

• If Tellabs 8120mini nodeMmalfunctions, disconnect the power and check that the assemblywas made correctly and that the pin connectors are positioned in the correct way.

4.9 Unit List of Tellabs 8120 Mini Node M

4.9.1 Common Units

Name Description Equipping

SMU-M Multiplexer for two G.704 interfaces and four Vtype interfaces

SMU 701 Main unit 1

VCM 402 V interface base unit 1

SMZ 414 Tellabs 8120 mini node M program 1

a 8990NFS40 AC/DC power supply 0…1/SMU

b PDU 42227 Unit power supply module,19…36 V DC, negative pole earthed

0…1/SMU

c PDU 423 Unit power supply module,40…60 V DC, positive pole earthed

0…1/SMU

27The product has been discontinued.


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4.9.2 Main Interface Modules

(G.704 framed interfaces IF1 and IF2, 1 interface/module)


a LTE-M28

LTE 404Line terminal 2 or 1 Mbit/sLTE-M base module

0…2/SMU1/LTE-M

b OTE-LED-MOTE 405

Optical LED 2 or 8 Mbit/sOTE-LED-M base module

0…2/SMU1/OTE-LED-M

c BTE-384-M28

BTE 406DPZ 380

Baseband module 384 kbit/sBaseband base module 128…384 kbit/sParameter PROM

0…2/SMU1/BTE-384-M1/BTE 406

d G703-75-MGDH 477

G703 2 Mbit/s, 75 Ω coaxialG703-75-M base module

0…2/SMU1/G703-75-M

e G703-120-MGDH 487

G703 2 Mbit/s, 120 Ω symmetricalG703-120-M base module

0…2/SMU1/G703-120-M

f G703-8M-M28

GDH 508G703 8 Mbit/s, 75 Ω coaxialG703-8M-M base module

0…2/SMU1/G703-8M-M

g BTE-2048-M28

BTE 424BAI 482DPZ 498

Baseband module 2048 kbit/sBaseband base moduleBaseband analog submoduleSignal processor PROM

0…2/SMU1/BTE1/BTE1/BTE

h BTE-2048-2W-M28


T-SDSL module 2048 kbit/s 2wT-SDSL base moduleT-SDSL analog submoduleSignal processor PROM


i BTE-1088-M28




j BTE-4096-M28






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k V35-G704-SM28

VDH 474V.35 n x 64 kbit/s…2 Mbit/s scramblerV35-G704-SM base module

0…2/SMU1/V35-G704-SM

l X21-G704-SM28

XDH 473X.21 n x 64 kbit/s…2 Mbit/s scramblerX21-G704-SM base module

0…2/SMU1/X21-G704-SM

m BTE-320-M28

BTE 592DPZ 650

T-SDSL module 320 kbit/s, 2-wireT-SDSL base moduleSignal processor PROM

0…2/SMU1/BTE1/BTE

n BTE-576-M28

BTE 596DPZ 650

T-SDSL module 576 kbit/s, 2-wireT-SDSL base moduleSignal processor PROM

0…2/SMU1/BTE1/BTE

o BTE-1088-2W-M28

BTE 559DPZ 650

T-SDSL module 1088 kbit/s, 2/4-wireT-SDSL base moduleSignal processor PROM

0…2/SMU1/BTE1/BTE

p BTE-2304-M28

BTE 562DPZ 650

T-SDSL module 2304 kbit/s, 2/4-wireT-SDSL base moduleSignal processor PROM

0…2/SMU1/BTE1/BTE

4.9.3 V Series Interface Modules

(Interfaces IF3-IF6)


a V35-MVDM 409

V.35 48, 56, n x 64 kbit/s interface module, 2 chV35-M base module

0…2/SMU1/V35-M

b V36-M28

VDM 410V.36 48, 56, n x 64 kbit/s interface module, 2 chV36-M base module

0…2/SMU1/V36-M

c V24-DCE-M28

VDS 411V.24/V.28 IF/DCE, 0.6…64 kbit/s IF module, 2 chV24-DCE-M base module

0…2/SMU1/V24-DCE-M

d V24-DTE-M28

VDS 416V.24/V.28 IF/DTE, 0.6…64 kbit/s IF module, 2 chV24-DTE-M base module

0…2/SMU1/V24-DTE-M

e X21-MXDM 412

X.21 0.6…n x 64 kbit/s interface module, 2 chX21-M base module

0…2/SMU1/X21-M


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f G703-64-M29

GCL 413G.703 64 kbit/s co/contradir. interface module, 2 chG703-64-M base module

0…2/SMU1/G703-64-M

g V35/V24-M29

VDM 434V.35-IEC+V.24/DCE, 0.6…n x 64 kbit/s, 2 chV35-IEC/V24-DCE-M base module

0…2/SMU1/V35-IEC/V24

h HSSI-M28

HDH 708HSSI, 0.6…n x 64 kbit/s interface module, 1 chHSSI-M base module

0…2/SMU1/HSSI-M

i Mini LANModuleEBH719

Mini LAN Module, interface module, 1 chMini LAN Module base module

0…2/SMU1/Mini LANModule

4.10 Connectors and Strappings of Framed Interfaces

4.10.1 G703-75-M and G703-120-M, G.703 2 Mbit/s

Front Panel of G703-75-M

Fig. 41 Front Panel of G703-75-M

The G703-75-M module is used when 75 Ω coaxial cable interface is needed. The Tx and Rxcoaxial cable shields are fixed to ground.

The connector is coaxial SMB.



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Front Panel of G703-120-M

Fig. 42 Front Panel of G703-120-M

The G703-120-M module is used when 120 Ω symmetrical cable interface is needed.

Fig. 43 D-Type 9-Pin Female Connector

J1 Connector Pins (v1.0)

Pin Signal

1 Transmit signal B

2 Transmit signal A

4 Receive signal B

5 Receive signal A

6 Tx cable shield

9 Rx cable shield

J1 Connector Pins (v2.0 or higher)

Pin Signal

1 TxB

2 TxA

4 RxB

5 RxA

6 Ground

9 Ground

Settings for Use with 120 Ω Symmetrical Cable

Strapping instructions for v1.0 are as follows.


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Strap Main Position Alternative Position Function of Main Position

CN5 ON OFF Tx cable shield grounded

CN8 ON OFF Rx cable shield grounded

Note that there are no strappings with v2.0 or higher.

4.10.2 LTE-M Line Terminal 1 or 2 Mbit/s

Front Panel

Fig. 44 Front Panel of LTE-M


P2 Connector Pins

Pin Signal

1 Transmit signal B

2 Transmit signal A

4 Receive signal B

5 Receive signal A

6 Tx cable shield

9 Rx cable shield

Settings for Use with 120 Ω Symmetrical Cable

Strap Main Position Alternative Position Function of Main Position

S1 2 1 Tx cable shield grounded

S2 1 2 Rx cable shield not grounded


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4.10.3 G703-8M-M, 8 Mbit/s

Front Panel

Fig. 46 Front Panel of G703-8M-M

The connector is coaxial SMB.

Strappings

There are no strappings on the G703-8M-M module. The Rx and Tx coaxial cable shields arefixed to ground.

4.10.4 OTE-LED-M, Optical LED, 2 or 8 Mbit/s

Front Panel

Fig. 47 Front Panel of OTE-M

The connector is a standard optical connector of FC type.

Strappings

There are no strappings on the OTE-M module.


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4.10.5 BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M,384 kbit/s…4224 kbit/s

Front Panel

Fig. 48 Front Panel of BTE-384-M, BTE-1088-M, BTE-2048-M, BTE-2048-2W-M and BTE-4096-M


Pin Assignment at CN1

4-WIRE USE 2-WIRE USE

Pin BTE-384-M BTE-2048-2W-M

1 Transmit signal B Not connected Tx/Rx signal B

2 Transmit signal A Not connected Tx/Rx signal A

3 Not connected Not connected Not connected

4 Receive signal B Tx/Rx signal B Not connected

5 Receive signal A Tx/Rx signal A Not connected

6 TX cable shield Not connected Not connected



9 RX cable shield Cable shield Cable shield

Strappings in BTE-384-M

There are two strappings available on the BTE-384-M baseband module.


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• S1: TX direction cable shield grounded/not grounded

• S2: RX direction cable shield grounded/not grounded (RX/TX direction in BTE-384 in 2-wiremode)

• S3/S4: wetting current enabled/disabled

• If wetting current is enabled, it can be turned ON or OFF in Tellabs 8000 manager. If wettingcurrent is disabled, this function is disabled in Tellabs 8000 manager.

• If the customer wants to enable switching of wetting current, both S3 and S4 must be inposition ON. This mode is not recommended due to EMC requirements.

Fig. 50 BTE-384-M Strappings

The strappings are located near the line connector. The default position of the strappings is off,shields not grounded.

Fig. 51 S3 and S4 Located between Line Transformers M1 and M2

Strappings in Other BTE Modules

There are two strappings available on the module.

• J1: TX direction cable shield grounded/not grounded

• J4: RX direction cable shield grounded/not grounded


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Fig. 52 BTE Strappings

The strappings are located near the line connector. The default position of the strappings is off,shields not grounded.

This strapping information does not concern the following BTE modules, BTE-320-M, BTE-576-M,BTE-1088-2W-M and BTE-2304-M. These modules do not have any strappings.

4.10.6 BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M, 320…2304 kbit/s

Front Panel

Fig. 53 Front Panel of BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules


Pin Assignment at CN1

Pin 4-WIRE USE(BTE-1088-2W-M, BTE-2304-M)

2-WIRE USE(BTE-320-M, BTE-576-M,BTE-1088-2W-M, BTE-2304-M)

1 Transmit signal B Tx/Rx signal B

2 Transmit signal A Tx/Rx signal A

3 Not connected Not connected

4 Receive signal B Not connected

5 Receive signal A Not connected


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4 Installation

Pin 4-WIRE USE(BTE-1088-2W-M, BTE-2304-M)

2-WIRE USE(BTE-320-M, BTE-576-M,BTE-1088-2W-M, BTE-2304-M)





Strappings in BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M Modules

The BTE-320-M, BTE-576-M, BTE-1088-2W-M and BTE-2304-M modules do not have anystrappings.

4.10.7 V35-G704-SM, V.35 n x 64 kbit/s…2 Mbit/s

Front Panel

Fig. 55 Front Panel of V35-G704-SM Module


D-Type 9-Pin Female Connector

Pin Signal Name (DTE) Direction

1 Transmit Signal B 104B Out

2 Transmit Signal A 104A Out

3 Ground

4 Receive Signal B 103B In

5 Receive Signal A 103A In

6 Transmit Clock B 115B Out

7 Transmit Clock A 115A Out

8 Receive Clock B 113B In

9 Receive Clock A 113A In


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4 Installation

Strappings

All strappings of the module must be in position 1.

4.10.8 X21-G704-SM, n x 64 kbit/s…2Mbit/s

Front Panel

Fig. 57 Front Panel of X21-G704-SM


D-Type 9-Pin Female Connector

Pin Signal Name (DTE) Direction Notice

1 Transmit Signal B T/b Out

2 Transmit Signal A T/a Out

3 Ground G

4 Receive Signal B R/b In

5 Receive Signal A R/a In

6 Transmit Clock B X/b Out

7 Transmit Clock A X/a Out

8 Receive Clock B S/b In DCE, out

9 Receive Clock A S/a In DCE, out

Strappings

All strappings of the module must be in position 1 when used in DTE mode.

All strappings of the module must be in position 2 when used in DCE mode.

The factory settings are in position 1.


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4 Installation

4.11 Connectors and Strappings of Unframed Interfaces

4.11.1 V35-M, V.35 48, 56, n x 64 kbit/s Interfaces, 2 pcs

Fig. 59 Front Panel of V35-M Module

Fig. 60 34-Pin Female Connector

The V.35 interface is equipped with a rectangular 34-pin female connector according to ISO 2593Standard. The nominal connector pin diameter is 1.6 mm. The connector is provided with two UNC6-32 locking screws. Data and timing signals are symmetrical with a level of 0.55 V (+ 20%) to 100Ω load. The electrical characteristics of the control circuits are in accordance with V.28.

V35 Connector Pin Assignment

PinNum-ber

CCITT V.35Circuit Number

Input/Out-put

Signal Level Signal

A --- Cable shield

B 102 Signal ground

P 103A input Transmitted data V.35

S 103B

R 104A output Received data V.35

T 104B

C 105 input Request to send V.28

D 106 output Ready for sending V.28

E 107 output Data set ready V.28


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4 Installation

PinNum-ber


Input/Out-put

Signal Level Signal

F 109 output Signal detector V.28

H 108 input Data terminal ready V.28

U 113A input Transmitted data timing fromDTE

V.35

W 113B

Y 114A output Transmitted data timing fromVCM

V.35

AA 114B

V 115A output Received data timing from VCM V.35

X 115B

N 140 input Remote loop-back V.28

L 141 input Local loop-back V.28

NN 142 output Test indicator V.28

4.11.2 V36-M, V.36 48, 56, n x 64 kbit/s Interfaces, 2 pcs

Fig. 61 Front Panel of V36-M Module


The V.36 interface is provided with a 37-pin female D-connector according to ISO 4902 Standard.The connector is furnished with two either UNC 4-40 or M3 locking screws.


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4 Installation

V36 Connector Pin Assignment

PinNum-ber


Input/Output

Signal Level Signal

1 --- Cable shield

19, 20 102 Signal ground

4 103A input Transmitted data V.11

22 103B

6 104A output Received data V.11

24 104B

7 105A input Request to send V.11

25 105B

9 106A output Ready for sending V.11

27 106B

11 107A output Data set ready V.11

29 107B

13 109A output Signal detector V.11

31 109B

12 108A input Data terminal ready V.11

30 108B

17 113A input Transmitted data timing fromDTE

V.11

35 113B

5 114A output Transmitted data timing fromVCM

V.11

23 114B

8 115A output Received data timing from VCM V.11

26 115B

14 140 input Remote loop-back V.28

10 141 input Local loop-back V.28

18 142 output Test indicator V.28


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4 Installation

4.11.3 V24-DCE-M, V.24/V.28 if/DCE, 0.6…64 kbit/s, 2 pcs

Fig. 63 Front Panel of V24-DCE-M Module


The V.24/V.28 interface is provided with a 25-pin female D-connector according to ISO 2110Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. Theelectrical characteristics of all circuits are according to V.28.

V24/V.28 Connector Pin Assignment

PinNum-ber


Input/Out-put

Signal

1 --- Cable shield

7 102 Signal ground

2 103 input Transmitted data

3 104 output Received data

4 105 input Request to send

5 106 output Ready for sending

6 107 output Data set ready

8 109 output Signal detector

20 108 input Data terminal ready

24 113 input Transmitted data timing from DTE

15 114 output Transmitted data timing from VCM

17 115 output Received data timing from VCM

21 140 input Remote loop-back


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4 Installation

PinNum-ber


Input/Out-put

Signal

18 141 input Local loop-back

25 142 output Test indicator

9 --- output +10 V output via 321R

10 --- output -10 V output via 321R

11-14 --- Not connected

16, 19 --- Not connected


4.11.4 V24-DTE-M, V.24/V.28 if/DTE, 0.6…64 kbit/s, 2 pcs

Fig. 65 Front Panel of V24-DTE-M Module


V24/V.28 Connector Pin Assignment

PinNum-ber


Input/Output

Signal

1 --- Cable shield

7 102 Signal ground

2 103 output Transmitted data

3 104 input Received data

4 105 output Request to send

5 106 input Ready for sending

6 107 input Data set ready

8 109 input Signal detector


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4 Installation

PinNum-ber


Input/Output

Signal

20 108 output Data terminal ready

24 113 output Transmitted data timing from VCM

15 114 input Transmitted data timing from DCE

17 115 input Received data timing from DCE

21 140 output Remote loop-back

18 141 output Local loop-back

25 142 input Test indicator

9 --- output +10 V output via 321R

10 --- output -10 V output via 321R

11-14 --- Not connected



4.11.5 X21-M, X.21 1.2…n x 64 kbit/s Interface, 2 pcs

Fig. 67 Front Panel of X21-M Module


The X.21 interface is provided with a 15-pin female D-connector according to ISO 4903Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. Theelectrical characteristics of all circuits are according to V.11. The X.21 interface is electricallyand mechanically compatible with CCITT Recommendation X.21 for point-to-point applications.Functionally, circuits C and I correspond to V.24 circuits 105 and 109. The signal levels forall circuits are X.27 (V.11).


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4 Installation

X.21 Connector Pin Assignment

PinNum-ber

CCITT X.21Circuit Number

ModeDCE/DTE

Signal

1 --- Cable shield

2 T(A) input/input Transmit

9 T(B)

3 C(A) input/input Control

10 C(B)

4 R(A) output/output Receive

11 R(B)

5 I(A) output/output Indication

12 I(B)

6 S(A) output/input Signal element timing

13 S(B)

7 X/B(A) output/input DTE transmit signal element timing/

14 X/B(B) Byte timing

8 G Signal ground or common return

15 ---- Not connected

4.11.6 G703-64-M, G.703 64 kbit/s Co/Contradirectional Interface, 2 pcs

Fig. 69 Front Panel of G703-64-M Module



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4 Installation

G.703 Connector Pin Assignment

PinNum-ber

Input/ Output Signal

1 output Receive data (A)

2 output Receive data (B)

3 input Transmit data (A)

4 input Transmit data (B)

5 output Receive data timing (A)

6 output Receive data timing (B)

7 output Transmit data timing (A)

8 output Transmit data timing (B)

9-15 Ground

4.11.7 V35/V24-M, V.24/V.28 if/DCE, 0.6…64 kbit/s; V.35-IEC if, n x 64 kbit/s

Fig. 71 Front Panel of V35/V24-M Module


The V.24/V.28 interface is provided with a 25-pin female D-connector according to ISO 2110Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. Theelectrical characteristics of all circuits are according to V.28. The pin assignment is the same as withthe V24-DCE-M module (See 4.11.3 V24-DCE-M, V.24/V.28 if/DCE, 0.6…64 kbit/s, 2 pcs).

The V.35-IEC interface is equipped with a 25-pin female D-connector according to ISO 2110Standard. The connector is furnished with two either UNC 4-40 or M3 locking screws. The dataand timing signals are symmetrical with a level of 0.55 V (+20%) to 100 Ω load. The electricalcharacteristics of the control circuits are according to V.28.


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4 Installation

V.35 IEC Connector Pin Assignment

PinNum-ber


Input/Output

Signal Signal Level

1 --- Cable shield

7 102 Signal ground

2 103A input Transmitted data V.35

14 103B

3 104A output Received data V.35

16 104B

4 105 input Request to send V.28

5 106 output Ready for sending V.28

6 107 output Data set ready V.28

8 109 output Signal detector V.28

20 108 input Data terminal ready V.28

24 113A input Transmitted data timing fromDTE

V.35

11 113B

15 114A output Transmitted data timing fromVCM

V.35

12 114B

17 115A output Received data timing from VCM V.35

9 115B

21 140 input Remote loop-back V.28

18 141 input Local loop-back V.28

25 142 output Test indicator V.28

4.11.8 HSSI-M, TIA/EIA 612, 0.6…8448 kbit/s

Fig. 73 Front Panel of HSSI-M Module


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4 Installation

Fig. 74 II-Type 50-Position SCSI Connector

HSSI-M Pin Assignment

PinNum-ber

TIA/EIA-613Circuit Number

Input/Output

Signal Signal Level

1 102 - Common -

26 102 - Common -

2 115A Output Receiver signal element timing TIA/EIA-612

27 115B Output Receiver signal element timing TIA/EIA-612

3 107A Output DCE ready TIA/EIA-612

28 107B Output DCE ready TIA/EIA-612

4 104A Output Received data TIA/EIA-612

29 104B Output Received data TIA/EIA-612

5 LCA30 Output Loopback request from DCE TIA/EIA-612

30 LCB 30 Output Loopback request from DCE TIA/EIA-612

6 114A Output Transmitter signal elementtiming

TIA/EIA-612

31 114B Output Transmitter signal elementtiming

TIA/EIA-612

7 102 - Common -

32 102 - Common -

8 108/2A Input DTE ready TIA/EIA-612

33 108/2B Input DTE ready TIA/EIA-612

30LC is not specified in TIA/EIA-613, the pair is reserved for future use interchange circuits from DCE.


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4 Installation

PinNum-ber

TIA/EIA-613Circuit Number

Input/Output

Signal Signal Level

9 113A Input Transmitter signal elementtiming

TIA/EIA-612

34 113B Input Transmitter signal elementtiming

TIA/EIA-612

10 143A Input Loopback A TIA/EIA-612

35 143B Input Loopback A TIA/EIA-612

11 103A Input Transmitted data TIA/EIA-612

36 103B Input Transmitted data TIA/EIA-612

12 144A Input Loopback B TIA/EIA-612

37 144B Input Loopback B TIA/EIA-612

13 102 - Common -

38 102 - Common -

19 102 - Common -

44 102 - Common -

24 142A Output Test mode TIA/EIA-612

49 142B Output Test mode TIA/EIA-612

25 102 - Common -

50 102 - Common -

4.11.9 Mini LAN Module, 10Base-T, 64…2048 kbit/s

Fig. 75 Front Panel of Mini LAN Module

Fig. 76 RJ-45 Connector


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4 Installation

The 10Base-T interface is implemented with an RJ-45 connector (twisted pair). The connectorcontact identification for RJ-45 is presented in Fig. 76 and the pin assignment in the table below.

Pin Signal

1 Tx+ (TD+)

2 Tx- (TD-)

3 Rx+ (RD+)

6 Rx- (RD-)

4,5,7,8 Not connected

The cabling of the LAN interface must remain inside the building.

4.12 Software Update

If the controller software needs to be updated, a service computer or Tellabs 8000 manager isneeded. The EPROMs inside Tellabs 8120 mini node M only include the operating system of thecontroller. The application software which is always needed for Tellabs 8120 mini node M tofunction is downloaded to the flash memories soldered on the main board of the equipment. Flashmemories are of an electrically programmable and erasable memory type. If only the EPROMs arechanged without performing a download, the equipment will not operate.

Updating software means in most cases only the downloading of the application software. Thesoftware can be downloaded on a running device. After the download process the piece ofequipment makes a reset which causes a short (30…60 seconds) interruption to the data transmissiongoing through the equipment. The downloading process does not change any settings or thecross-connection of the equipment.

The following instructions describe how to update the software of Tellabs 8120 mini node M bydownloading a compatible binary file through the management interface and how to replace theEPROMs on Tellabs 8120 mini node M.

4.12.1 Downloading Tellabs 8120 Mini Node M Software

The downloadable software for Tellabs 8120 mini node M is normally delivered as a binarySMZ4NN_X.Y file on a micro floppy disk, where X.Y is the version of the software (SMZ4NNcan be either SMZ 414 or SMZ 430, depending on the type of Tellabs 8120 mini node). Thedownloadable software must be compatible with the EPROM set of the target unit. The compatibilitybetween the target unit software and the downloadable file is defined by the following two rules:

• The product codes must be the same (SMZ4NN).

• Two versions, U.V and X.Y are compatible if U = X.

The following instructions should be followed when downloading the Tellabs 8120 mini node Msoftware.

Step 1 Check that you have the correct downloadable software available.


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4 Installation

Step 2 Select the correct target if you are using Tellabs 8000 manager.

Step 3 Check the compatibility of the software versions.

Step 4 Open the Downloading window.

Step 5 Select the correct binary file SMZ4NN_X.Y from your directory.

• For example: SMZ414_4.6

Step 6 Activate downloading.

Step 7 Wait for the operation to end.

The downloading takes some minutes, including erasing time, data transfer and programming time,and checking and restarting time. After downloading, check the software version.

4.12.2 Replacing EPROMs

There are two EPROMs for the software. The EPROMs are labeled with the identificationstickers which contain the following information: product code (SMZ4NN), version number andEVEN/ODD to indicate the positions of EPROMs.

The download must be disabled before installing the EPROMs with new versions.Tellabs 8120 mini node M must be disconnected from the mains supply before removing thecover as high voltages are present inside the Tellabs 8120 mini node M case.

The following instructions should be followed when installing or replacing the EPROMs.

Step 1 Check that the unit is executing the PROM application.

Step 2 Remove the metallic cover of Tellabs 8120 mini node M.

Step 3 Remove the old EPROMs from their sockets.

Step 4 Put the new EPROMs (SMZ4NN rx.y ODD and EVEN) into the sockets.

Step 5 Check the correct places of the EPROMs (see the figure below).

Step 6 Check the direction of the EPROMs. The Pin #1 end is identified by a slot at the end of thecomponent package.

Step 7 Replace the metallic cover of Tellabs 8120 mini node M.

Step 8 Download the new software version.


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4 Installation

Fig. 77 Location for EPROMs


122

5 Faults and Actions


5.1 Terminology

The following acronyms will be used in the tables below:

Maintenance Status

PMA Prompt maintenance alarm

DMA Deferred maintenance alarm

MEI Maintenance event information

Service Status

S Service alarm

LED Indications

R Red alarm LED

Y Yellow alarm LED

RB Red alarm LED blink

Consequent Actions

TxAIS AIS insertion to Tx signal

RxAIS AIS insertion to Rx signal

TxTS-AIS AIS insertion in time slots of Tx signal

AIS AIS insertion to whole signal

FrFEA Frame level far-end alarm (TS0/B3 in 2 Mbit/s frame, TS66/B7 in 8Mbit/s frame)

MFrFEA Multiframe level far end alarm (FR0/TS sig/B6)

Also MFrFEA is transmitted if FrFEA is transmitted.


123


5.2 Common Faults and Actions

5.2.1 Common Logic Faults (Block 0)

Fault Condition Sta-tus

LED Note

ResetThere has been a unit reset (detected always after thepower-up of the unit)

PMA,S

R Fault message (withdelta event) appearswhen the unit starts tooperate.

Power supply (5 V,+12 V,-12 V)The voltage generated by the main supply unit is belowthe threshold limit.

PMA R Rx signal action dependson the frame level alarmof the correspondinginterface.

CPU memory faultsRAM faultA background process has found a RAM location wherethe read value does not match with the written testpattern.EPROM faultThe calculated check sum does not match with the storedone.FLASH faultsA problem has been found when saving parameters orprograms to the non-volatile memory.

PMA,S

R -

Incompatible EPROM/FLASH SWThe downloaded software (on the flash) is not compatiblewith the system software on the EPROMs.

PMA R -

Checksum err in downloaded SWThe downloaded software has been corrupted.

PMA R -

SW unpredictedThis fault condition should never occur (or not yetsupported).

PMA R -

Missing settingsOne of the setting structures has been corrupted on thenon-volatile memory.

PMA,S

R -

Missing application programThere is no application program on the flashmemory.Download the latest version of the SMZprogram.

PMA,S

R -

Tx RAM errorThere is a difference between the written and read datain the Tx data buffer RAM of the framed interface.

PMA,S

R -

Rx RAM errorThere is a difference between the written and read datain the Rx data buffer RAM of the framed interface.

PMA,S

R -


124


5.2.2 Master Clock Faults (Block 0)


LED Note

Loss of master clock lockingThe internal clock is used with non-empty fallback list.

MEI

Fallback list warningThe lowest choice is used (there is more than one choicein the fallback list).

MEI

Loss of external clockThe external clock input is enabled but the clock,connected to input, is not acceptable.

PMA R

External clock warningThe external clock is included in the fallback list but theexternal clock input is not enabled.

MEI

Phase locked loop alarmThe phase locked loop of the master clock cannot belocked to any clock.

PMA R

Clock far end alarm choice NThe state of the fallback list choice N indicates the clockfar end alarm.

MEI Y

5.2.3 Cross-Connect Block Faults (Block 0)


LED Note

Block IA faultData transfer between the cross-connection and aspecified block (interface/port) does not work.

PMA,S

Y

X-connect RAM faultProblem found when configuring the cross-connectmatrix.

PMA,S

R

ASIC latch errorAn ASIC setting cannot be corrected by a checkingbackground process.

PMA,S

R

ASIC latch warningAn ASIC setting is corrected by a checking backgroundprocess.

MEI

Flash list check sum errorOne of the flash lists (e.g. a port descriptor list) has beencorrupted.

PMA,S R

X-connect flash lst conflictA corrupted cross-connect record has been found in thenon-volatile memory after the unit reset. The record hasbeen deleted.

MEI

PortDescr flash lst conflictA corrupted port descriptor record has been found inthe non-volatile memory after the unit reset. The recordhas been deleted.

MEI


125



LED Note

Swp trk flash lst conflictA corrupted swap trunk record has been found in thenon-volatile memory after the unit reset. The record hasbeen deleted.

MEI

Pass trk flash lst conflictA corrupted passivate trunk record has been found inthe non-volatile memory after the unit reset. The recordhas been deleted.

MEI

Time contr. X-conn warningA delta fault indicating a problem when switching thetime controlled cross-connection on/off. Additionalinformation can be read in the error log of the timecontrol process.

PMA

5.2.4 Faults of Framed IF Tx Signal (Block 1, 2)


LED Tx signal

Tx Clock fault (PLL)The fault will be activated if the interface moduletransmitting clock phase locking to X-bus clock fails.

PMA,S

R TxAIS

Bus faults

IA activity missingThe fault will be activated if the unit cannot find itslocked interface address on the cross-connection bus.The cross-connect block should activate the IA on thebus if the interface is locked.

PMA,S

R TxTS-AIS

Bus sync. fault (block 0)No cross-connection bus sync detected.

PMA,S

R TxTS-AIS

AIS from X-busThe fault will be activated if the frame sync. word andRAI from the X-bus and TS0B2 changes between 0 and1 are missing.

MEI,S

Y TxAIS31

BTE Tx line testThe fault will be activated if a BTE module Tx testpattern generator is activated (used in V.54 remote loop).

MEI,S

Y Test pattern

31Only when FAS is transferred through the network.


126


5.2.5 Faults of Framed IF Rx Signal (Block 1, 2)

Signal and Frame Faults Sta-tus

LED Rxsignal

Tx signal

1.1 Interface module missingNo interface module is present but one is defined in thesettings.

PMA,S

R RxAIS -

1.2 Wrong interface moduleThere is a conflict between the installed module and thesettings.

PMA,S

R RxAIS Cut off

1.3 Rx signal missingThe signal level is below a specific level (the leveldepends on the used interface module and the selectedbit rate).

PMA,S

R RxAIS FrFEA

1.4 Rx signal is AISThe Rx signal is detected to be AIS.

MEI,S

Y RxAIS FrFEA

1.5 Loss of frame alignment

1.5.1 Frame alignment lostSee CCITT G.706 Loss of frame alignment.

PMA,S

R RxAIS FrFEA

1.5.3 Frame alignment lost by CRCSee CCITT G.706 Frame alignment recovery (2048mode ≥915 CRC block errors detected).

PMA,S

R RxAIS FrFEA

1.5.2 CRC missingThis fault indicates that the remote end does not use theCRC.

DMA R RxAIS FrFEA

1.6 BER 10-3

The bit error rate is calculated from faulty framealignment words or from code errors. The 10E-3 alarmstatus depends on fault consequences (AIS insertion).

PMA,S

R RxAIS FrFEA

1.7 Wrong input signal

1.7.1 Own NNM messages receivedThe control channel of the interface is used and theneighbour supervision option of the interface is ONand the received NNM message contains the sameidentification data as the NNM message sent to theinterface.

PMA,S

R RxAIS -

1.7.2 Wrong IDs in NNM messagesThe control channel of the interface is used and theneighbour supervision option of the interface is ONand the received NNM message contains unexpectedneighbour identification data.

PMA,S

R RxAIS -

1.7.3 No response to NNM messageThe control channel of the interface is used and theneighbour node supervision option of the interface is ONand no NNM (Neighbour Node Monitoring) messagehas been received from the interface in eight seconds.

PMA,S

R RxAIS -

1.8 NTU problems


127


Signal and Frame Faults Sta-tus

LED Rxsignal

Tx signal

1.8.1 NTU power off / local loopThe fault will be activated if the used module is BTE384and the wetting current is ON and the received currentvalue differs in frequency of 1.5…4.5 Hz and the currentvalue difference is more than 1.5 mA.

MEI Y RxAIS -

1.8.2 NTU line breakThe fault will be activated if the used module is BTE384and the wetting current is ON and the received currentvalue is lower than 1.2 mA.

MEI Y - -

1.8.3 NTU short circuitThe fault will be activated if the used module is BTE384and the wetting current is ON and the received currentvalue is higher than 6.5 mA.

MEI Y - -

1.9 ASIC register errorThe fault will be activated if difference of the write/readdata of ASIC has been found.

PMA,S

R - -

2 Loops

2.1 Local loops

2.1.1 Interface back to equipmentAn interface loop is created in the interface module. Itloops the transmitted data and the clock signal back tothe interface receiver.

MEI,S

Y - TxAIS

2.1.2 MUX/DEMUX back to eq.As in the Interface back to equipment loop above, butthe loop is made before the interface module on theframing block in the base card.

MEI,S

Y - TxAIS

2.1.3 MUX/DEMUX back to lineRx data is looped back to the interface transmitter. Whenit is used, the HDLC channel works with this line loop.All other bits are looped back to the interface.

MEI,S

Y RxAIS

2.1.4 Line loop made by neighbourThis alarm will be activated if the HDLC channel is inuse and MUX/DEMUX back to line loop has been madefrom the remote end, or the BTE module is used andthe remote end has made loop by using the V.54 loopsequence.

MEI,S

Y RxAIS -

2.2 Remote loops

2.2.1 Remote controlled line loop (2.1.4)This alarm will be activated if the HDLC channel is inuse and MUX/DEMUX back to line loop has been madeto the neighbour unit, or the BTE module is used and theV.54 loop has been made to the remote end.

MEI,S

Y - -

3 Multiframe level faults

3.1 Multiframe alignment lost (group N)The multiframe alignment in signalling time slot is lost.

PMA,S

R Rx-AIS/SigTS

MFrFEA


128


3.2 AIS in signalling (group N)The signal in the signalling time slot is detected to beAIS.

MEI,S

Y Rx-AIS/SigTS

MFrFEA

Multiframe faults of the 8 Mbit/s signal are detectedseparately in each of the four signalling time slots(groups).

4 Far-End Alarms

4.1 Frame far-end alarm (FrFEA)The alarm state of the frame far end bit is received.The alarm status depends on fault consequences (AISinsertion into the signalling time slot).

MEI,S

Y Rx-AIS/SigTS

RxAISopera-tion canbe turnedoff

4.2 Multiframe far-end alarm (MFrFEA)The alarm state of the multiframe far end bit is received.The alarm status depends on fault consequences (AISinsertion into the signalling time slot).

MEI,S

Y Rx-AIS/SigTS

RxAISopera-tion canbe turnedoff

5 Degraded Signal

5.1 Error rate 10-3

See CCITT G.736. The bit error rate is calculated fromfaulty frame alignment words or from code errors. The10E-3 alarm status depends on fault consequences (AISinsertion).

DMA R - -

5.2 Error rate 10-6

The BER10E-6 error rate is calculated from CRC blockerrors when the bit rate is ≥1024 kbit/s. The countingtime is 10 s and the limit for the fault condition dependson the used bit rate (2048 limit is 10).

DMA R - -

5.3 Frequency differenceThe measurement period is 15 s and the phase driftinglimit is 5 µs. The fault will be activated if the phasedrifting limit has been exceeded in three measurementsout of four.

DMA R - -

5.4 Buffer slips/1 hourThe fault will be activated if one or more buffer slip(s)has been observed during the last hour.

MEI RB - -


129


5.2.6 1+1 Protection Switch Fault Messages (Block 0)


LED Rxsignal

Tx signal

Protection switch forcedWhen the unit is in 1+1 protected mode and theprotection switch has been forced to select a signal fromIF1 or IF2.

MEI R - -

Loss of protected signalIn 1+1 protection mode both interfaces IF1 and IF2 havefaults which in unprotected mode have S status.

PMA,S

R -32 -32

5.2.7 Miscellaneous Faults of Framed Interfaces (Block 1, 2)


LED Rxsignal

Tx signal

Port locking conflictThe fault will be activated if the cross-connection systemhas the port descriptor but the interface is unlocked, orif the cross-connection system has no port descriptoralthough the interface is locked. Use lock/unlock.

DMA R - -

HDLC overlap with X-busThe fault will be activated if the HDLC control channelbit(s) are also used by the cross-connection bus.

DMA R - -

Master clock RAI overlap with X-busThe fault will be activated if the MCLK/RAI bit is alsoused by the cross-connection bus.

DMA R - -

G821 unavailable stateThe fault will be activated if the G.821 supervision isused and the state of the signal becomes unavailable (10consecutive SES seconds). The fault will be deactivatedwhen 10 consecutive non-SES seconds have been found.

PMA,S

- - -

G821 limit eventThis fault will be activated as a delta fault if G.821supervision is used and at least one performance limithas been exceeded in a 15-minute period.

DMA - - -

Faults masked/TestThe fault will be activated when the interface fault masksetting is ON (all interface faults will be cleared).

MEI Y - -

5.2.8 Fault and Service Status (PMA, DMA, MEI, S) in 1+1 Mode of FramedInterfaces

In principle, both interfaces generate their own alarms (alarm messages with fault status). PMA andS statuses are processed in this mode.

32Signal actions depend on actions of the protected interfaces.


130


PMA Status Processing In protection mode the normal PMA status is changed to the DMA status,and with the PMA status there is an additional fault condition, Lossof protected signal. In normal or prefer operating modes this specialcondition is created when both interfaces have a fault of category 3 orworse. In forced operating mode this condition occurs if the forcedinterface has a fault of categories 3 through 1. The inactive interface isnot able to generate a fault with the PMA status.

S Status Processing In protection mode an S status is generated only in the Loss of protectedsignal fault condition.

Far-End Alarms in 1+1Mode

A far-end alarm indicates that the Rx signal is out of service (S status).FrFEA: Rx frame out of serviceMFrFEA: Rx multiframe out of serviceTx far-end alarms (FrFEA, MFrFEA) of both interfaces are generatedassuming a fault status of the active interface. During a short period,when the change-over switch is in a transition phase, the far-end maygenerate an alarm even if there is no fault in the better interface.In forced operating mode only the active forced interface can causefar-end alarms to be sent.

RxAIS Processing RxAIS and RxAIS to SigTS are always generated when FrFEA orMFrFEA are sent. AIS generating depends on the fault status of theselected interface.

5.2.9 Fault Conditions of Framed Interfaces

Multiframe Alignment Lost The fault will be activated if two consecutive faulty multiframe alignmentwords have been received or if all signalling time slots in one multiframecontain only zeros (0). The fault will be deactivated when the framealignment is found and the first four bits of the signalling time slot arefound to be zeros (0) and when the prior signalling time slot has hadat least one bit in state 1.

Frame Far-End Alarm(FrFEA)

The state of TS0B3 frame far-end alarm bit will be switched if theopposite state is received in three consecutive frames. State 1 for alarm.

Multiframe Far-End Alarm(MFrFEA)

The state of signalling time slot frame 0 B6 alarm bit will be switchedif the opposite state is received in three consecutive frames. State 1 foralarm.

AIS in Frame 2048 kbit/sand n x 64 kbit/s

A signal containing two or less zeros in a 2-frame period is recognized asan AIS signal.After AIS is detected, a signal containing three or more zeros in a2-frame period is recognized not to be an AIS signal.

AIS in Frame 8448 kbit/s A signal containing less than eight zeros in a 2-frame period is recognizedas an AIS signal.After AIS is detected, a signal containing 12 or more zeros in a 2-frameperiod is recognized not to be an AIS signal.

AIS in Multiframe A signal in the signalling time slots containing one or no zeros in amultiframe period is recognized as an AIS signal.

Error Rate 10E-3 Limitsfrom Frame AlignmentWord

2048 kbit/s and n x 64 kbit/s count time is 4 seconds:Count to activate alarm: 94Count to inactivate alarm: 178448 kbit/s count time is 2 seconds:Count to activate alarm: 199Count to inactivate alarm: 48

Error Rate 10E-3 Limitsfrom Code Errors

Count time is one second:


131


Speed kbit/s Activate Inactivate

844820481088

829619731033

893229126

CRC Spurious FrameAlignment Limits

Rate kbit/s Values from 1000 counted to starta new frame search

256320384448512576640704768108820488448

613637660681700719736753768832915826

CRC Missing The fault will be activated if in 2M mode a framing has been found andthe CRC multiframe alignment has been lost 100…200 ms; or if in 8Mmode more than six CRC alignment losses due to excessive block errorshave been found in a period of 3 seconds.In 2M mode the fault will be deactivated if a CRC multiframe alignmenthas been found; in 8M mode if no more than one frame alignment lost dueto excessive CRC block errors in a three-second period has been found.

5.3 Faults and Actions of Unframed Interfaces

5.3.1 General IF Faults of Unframed Interfaces


LED UI2 C1

IF module missingNo interface module is present but there is one defined inthe settings.

PMA,S

R - OFF/-

Wrong interface moduleThere is a conflict between the installed module and thesettings.

PMA,S

R - OFF/-

Power off in inputIncoming data signal (103) out of the CCITT specs.

MEI,- Y - AIS

ASIC register errHW error found in the ASIC.

PMA,S

R OFF OFF


132


5.3.2 IF Signal Faults of Unframed Interfaces


LED UI2 C1 Note

Input signal faults (UI1)

Interface signal missingNo carrier state of the baseband module.Faulty input signal in the case of a G.703module.

PMA,S

R - AIS

105 off in input105 signal off in input and 105 supervisionselected in parameters.

MEI,-

Y - AIS Used when105 should becontinuously on.

Code errors from inputCode erros (HDB3, AMI or G.703codir/contra). No input clock (NRZ).

PMA,S R - AIS

Timing errors

Rx buffer slipsBuffer slip in Tellabs 8100 bus interface,input signal (UI1) buffer slip (n x 64kbit/s).

DMA R - AIS

Tx buffer slipsBuffer slip in Tellabs 8100 bus interface,output signal (UI2) buffer slip (n x64kbit/s).

DMA R AIS -

Rx buffer alignmentV.110 or X.30 buffer slip.

DMA R - AIS V.110, X.30 orMartisDXX framingin use.

Tx buffer alignmentV.110 or X.30 buffer slip.

DMA R AIS -

5.3.3 Net Side Signal Faults of Unframed Interfaces


LED UI2 C1 Note

Input signal from net side (C2)

AIS detected from networkAIS from the cross-connection bus.

MEI,S

Y AIS - V.110, X30or MartisDXXframing in use

Loss of frame syncLoss of frame sync state in the case of aV.110 or X.30.

PMA,S

R AIS RAI V.110, X30or MartisDXXframing in use

Loss of multiframe syncLoss of multiframe sync state in the caseof a V.110 or X.30.

PMA,S

R AIS RAI Used at bit rates≤2.4 kbit/s.

Alarm from far endAlarm bit set in V.110 or X.30 frame.

MEI,S

Y - - V.110, X30or MartisDXXframing in use


133


5.3.4 Test Loop Activation of Unframed Interfaces


LED UI2 C1

Interface loop activeInterface loop activated (by the manager).

MEI,S

Y AIS -

Local loop or test activeLocal loop or test activated (by the manager).

MEI,S

Y - AIS

V.54 loop activeV.54 loop activated (by the interface signal or from thefar-end).

MEI,S

Y - -

5.3.5 Performance Conditions of Unframed Interfaces


LED UI2 C1 Note

Performance conditions

G821 unavailable stateThe fault will be activated if the G.821supervision is used and the state ofthe signal becomes unavailable (10consecutive SES seconds). The faultwill be deactivated when 10 consecutivenon-SES seconds have been found.

PMA,S - - - Available whenend-to-end CRCmonitoring isactivated.

G821 limit eventThis fault will be activated as a delta faultif the G.821 supervision is used and at leastone performance limit has been exceededin a 15-minute period.

DMA - - - Available whenend-to-end CRCmonitoring isactivated.

CRC errors from far endCRC errors detected at the far-end.

DMA R - - Available whenend-to-end CRCmonitoring isactivated.

CRC errors from near endCRC errors detected at the near-end.

DMA R - - Available whenend-to-end CRCmonitoring isactivated.

FAS-errorsFrame sync word errors detected in case ofV.110 or X.30.

PMA Y - - V.110, X.30or MartisDXXframing in use.


134


5.3.6 Common Faults of Unframed Interfaces


LED UI2 C1 Note

RL state program errorRemote loop state program not stored (HWerror).

PMA,S

R - -

Bus sync. fault (block 0)No cross-connection bus sync detected.

PMA,S

R AIS AIS

IA activity missingThe fault will be activated if the unit cannotfind its locked interface address on thecross-connection bus. The cross-connectblock should activate the IA on the bus ifthe interface is locked.

PMA,S

R AIS AIS

Faults masked/TestThe fault will be activated when interfacefault mask setting is ON (all interfacefaults will be cleared).

MEI,-

Y - -

5.3.7 Reference Points of Unframed Interfaces

The channel board in Tellabs 8120 mini M holds four identical interface blocks numbered 3 and 6.The common parts are named block 0. The signals and directions are identified as follows.

Signals and Directions of Fault Conditions

Reference point Signal description

UI1 Input signal at the receive part of the user interface

UI2 Output signal at the transmit part of the user interface

C1 XB output signal towards the X-bus interface

C2 XB input signal from the X-bus interface, net side signal

Fig. 78 Naming of Signal Reference Points


135

6 Technical Specifications of Tellabs 8120 Mini Node M

6 Technical Specifications of Tellabs 8120 MiniNode M

All CCITT references concern the Blue Book, 1988. When applicable, the references to formerCCITT Recommendations have been amended to ITU-T references. These references includethe date of the valid ITU-T Recommendation in case these are revised in the future. If a CCITTRecommendation has not been updated as ITU-T by the International Telecommunication Union,CCITT is used in this document.

6.1 Relevant Recommendations

The ITU-T/CCITT Recommendations concerning Tellabs 8100 trunk interfaces and user accessports are shown below.

Rec. ITU-TDate(CCITT1988)

Main Characteristics of Equipment and Trunk Interfaces

G.703 April 1991 Physical/electrical characteristics of hierachical digital interfaces

G.704 CCITT Synchronous frame structure used at primary and secondary hierachicallevels

G.706 CCITT Frame alignment and CRC procedures for G.704 frames

G.732 CCITT Characteristics of primary PCM multiplexing equipment operating at2048 kbit/s

G.736 March 1993 Characteristics of a synchronous digital multiplex equipment operatingat 2048 kbit/s

G.744 CCITT Second order PCM multiplex equipment operating at 8448 kbit/s

G.821 CCITT Error performance of an international digital connection

G.823 March 1993 The control of jitter and wander on the 2048 kbit/s hierarchy

Standard Transmission Network Interfaces (2 Mbit/s and 8 Mbit/s)

2048 kbit/s framed interface G.704, G.706, G.732, G.736, G.821, G.823

8448 kbit/s framed interface G.704, G.744, G.821, G.823

User Access Points For Unframed Data Interfaces33

V.11 (ITU-T 03/93) Electrical characteristics for balanced double-current interface circuits

V.13 (ITU-T 03/93) Simulated carrier control

V.14 Transmission of start-stop characters over synchronous bearer channels

33 All references to CCITT Recommendations, except those listed as ITU-T.


136


User Access Points For Unframed Data Interfaces33

V.24 Interface circuits between DCE and DTE

V.28 Electrical characteristics for unbalanced double-current interchangecircuits

V.29 9600 bits per second modem standardised for use on point-to-point4-wire leased telephone-type circuits

V.35 (CCITT Red Book) Data transmission at 48 kbit/s using group band modem

V.36 Modems for synchronous data transmission using group band modems

V.54 Loop test devices for modems

V.110 (ITU-T 09/92) ISDN rate adaption for V-series interfaces

X.21 (ITU-T 09/92) Synchronous data network interface between DCE and DTE

X.27 Same as V.11

X.30 ISDN rate adaption for X.21 interfaces

X.54 Allocation of channels on international multiplex links at 64 kbit/s.

User Access Points for Voice Frequency Interfaces

G.711 (CCITT) 64 kbit/s PCM encoding

G.712 (CCITT) 4-wire voice frequency interface

G.713 (CCITT) 2-wire voice frequency interface

G.714 Separate performance characteristics for the encoding and decodingsides of PCM channels applicable to 4-wire interfaces

G.715 Separate performance characteristics for the encoding and decodingsides of PCM channels applicable to 4-wire interfaces

G.721 (CCITT 1986/88) 32 kbit/s ADPCM

G.961 (ITU-T 03/93) Access digital section for ISDN primary rate at 2048 kbit/s

6.2 Cross-Connect

Cross-connection method Synchronous time slot interleaving

Frame frequency 8 kHz

Capacity: The sum of cross-connectedsignals

64 Mbit/s

Smallest cross-connect unit 8 kbit/s

Signalling cross-connection n x 500 bit/s (channel associated signalling = CAS)

Delay of cross-connect core n x 64 kbit/s1 frame = 125 µs

CAS bits (500 bit/s)2 ms

Time integrity between time slots in cross-connected signals is maintained.


137


6.3 Timing

Master clock frequency 16 896 kHz ±30 ppm

Master clock functional modes Locking to the interface rx clock (n x 64 kbit/s)Locking to external clock input (n x 64 kHz)Internal modeClock fallback list (5 levels + internal mode)

Locking frequency n x 64 kHz ±50 ppm

External clock input Frequency n x 64 kHz, n=1…32Electrically G.703/75 Ω

External clock output Frequency 2048 kHzLocked to node master clockElectrically G.703 /75 Ω

Connector type 75 Ω, SMB connector

Jitter transfer function and jitter in theoutput clock

G.736

6.4 G.704 Framed Interface

6.4.1 Frame and Multiframe Buffer

FrameBufferMode

Bit Rates RxDelayFrames

TxDelayFrames

Main Usage

4 Fr34 n x 64k, 2 Mbit/s, 8 Mbit/s 1…3 1 Non-trunk lines and n x 64 kbit/strunks

8 Fr n x 64k, 2 Mbit/s 2…6 1 Split trunk lines

8 Fr n x 64k, 2 Mbit/s, 8 Mbit/s 1…7 1

64 Fr n x 64k, 2 Mbit/s 1…63 1 Plesiochronous buffer

Slip rate when the incoming signal is plesiochronous

Buffer Length Slip Rate n x 64kbit/s

Slip Rate 2 Mbit/s Slip Rate 8 Mbit/s

4 Fr n x 8/df35 256/df 1056/df

8 Fr (split trunk line) 2 x n x 8/df 512/df -

8 Fr 4 x n x 8/df 1024/df 4224/df

64 Fr 32 x n x 8/df 8192/df -

Split trunk line operation (two physical lines combined to one logical trunk):

341 Fr = 125 µs35df=frequency difference (input x Mbit/s signal frequency - nodes x Mbit/s frequency)


138


• Line bit rates n x 64 kbit/s (3 ≤ n ≤ 32), 2 Mbit/s

• All split components must have the same bit rate

• Tolerated delay difference between lines < 50 µs

Multiframe buffer modes

When Frame Buffer Is MFr Buffer36 Rx Delay Tx Delay

4…8 frames long 2 MFr 0…2 MFr 1 Fr

64 frames long 4MFr 1…3 MFr 1 Fr

Jitter and wander tolerance G.823

6.4.2 8448 kbit/s Interface (CCITT G.704)

G.703See 6.6.1 8448 kbit/s, G.703 Interface (G703-8M-M Module).

Electrical interface

Optical lineSee 6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s(OTE-LED-M Module).

Multiplexing method Synchronous time slot interleaving (G.704)

Bits in time slot 8

Time slots in frame 132 numbered 0…131

Frame alignment time slot TS0/B1…8 + TS66/B1…6

Frame alignment procedure G.744

Far end alarm TS66/B7

CRC error check CRC-6 in bits TS99/B1…6 (can be disconnected)

CRC error indication to the remote end TS99/B7

Error performance monitoring G.821

Signalling multiframe time slots TS67,68,69,70 (G.704)

Multiframe time slot content F0/TS sig (0000 xyxx)

Multiframe far end alarm F0/TS sig/B6

Multiframe alignment procedure G.732 (same as in 2 Mbit/s interface)Separate multiframe alignment for each signalling time slot

Frames in multiframe 16

4 pcs a,b,c,d / 64 kbit/s time slot

2 pcs a,b / c,d / 32 kbit/s

Signalling bits

1 pc a / b / c /d / 16 kbit/s

n x 8 kbit/s (n=1…8)

Any time slot except TS0 and TS66

Control channel datalink

Tellabs 8100 trunk lines preferable TS01/B1…B8 (64 kbit/s)or TS33/B1…B8

361 MFr = 2 ms


139


Time Slot Usage in Trunks

Cross-connectable time slots 120 time slots

with signalling bits (CAS) TS5…TS32, TS34…TS65, TS71…TS98, TS100…TS131

Cross-connectable time slots withoutsignalling bits

5 time slotsTS1…TS4,TS33

Free bits TS66/B8, TS99/B8

6.4.3 2048 kbit/s Interface (CCITT G.704/706)

G.703See 6.6.2 2048 kbit/s, G.703 Interface (G703-75-M) and6.6.3 2048 kbit/s, G.703 Interface (G703-120-M).

Line terminalSee 6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface(LTE-M Module).

Optical lineSee 6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s(OTE-LED-M Module).

V.35See 6.5.1 V.24/V.28,V.35,V.36/V.11; 1.2…19.2 kbit/s, 48, 56,n x 64 kbit/s.


V.36/V.11See 6.5.1 V.24/V.28,V.35,V.36/V.11; 1.2…19.2 kbit/s, 48, 56,n x 64 kbit/s.

Multiplexing method Synchronous time slot interleaving

Bits in time slot 8

Time slots in frame 32 numbered 0…31

Frame alignment time slot TS0

Frame alignment method G.706


CRC error check CRC-4 in CRC multiframe of TS0/B1 (G.704/706,CRC canbe disconnected)

CRC block error indication to theremote end

CRC multiframe E-bit


Signalling multiframe time slot TS16 (G.704)

Multiframe alignment time slot content F0/TS16 (0000 xyxx)

Multiframe far end alarm F0/TS16/B6

Multiframe alignment method G.732


4 pcs a,b,c,d / 64 kbit/s time slots

2 pcs a,b / c,d / 32 kbit/s

Signalling bits

1 pc a / b / c /d / 16 kbit/s


140


Time slot usage in trunks:cross-connectable time slots withsignalling bits (CAS)free bits

30 time slots , TS1…TS15, TS17…TS31TS0/B4…8 (see Control Channel Data Link below)

Control channel datalink n x 8 kbit/s (n=1…8)Any time slot except TS0 frame alignment bitsTellabs 8100 trunk lines preferable TS0/B5…8 (16 kbit/s)

6.4.4 N x 64 kbit/s Interface with G.704 Type Frame

N x 64 kbit/s baseband interfaceSee 6.6.6 Baseband Line Interface 64…384 kbit/s(BTE-384-M Module) and 6.6.7 Baseband LineInterfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M,BTE-2048-2W-M, BTE-4096-M, BTE-320-M, BTE-576-M,BTE-1088-2W-M and BTE-2304-M Modules).

1088 kbit/s line terminalSee 6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface(LTE-M Module).

V.35 n x 64 kbit/s (signals 103,104,113,115; V.35 electricalspecs.)


V.36 n x 64 kbit/s (signals 103,104,113,115; V.11 electricalspecs.) for V.35 and V.36n=2…32, with n=32 the frame parameters are the same asin Fig. 81 in Appendix 2Fig. 81 in Appendix 2 in Tellabs®

8120 Mini Node M Operating Manual (document number22030_XX).

Multiplexing method Synchronous time slot interleaving

Bits in time slot 8

Time slots in frame N numbered 0…n-1

Frame alignment time slot TS0

Frame alignment method G.706


CRC error check CRC-4 in CRC multiframe of TS0/B1 (G.704/706,CRC canbe disconnected)

CRC block error indication to theremote end

CRC multiframe E-bit


Signalling multiframe time slot (TSsig.)

Last time slot in frame (TSn-1) except with n≥17 TSsignalling=16

Multiframe alignment time slot content F0/TS signalling (0000 xyxx)

Multiframe far end alarm F0/TS signalling/B6

Multiframe alignment method G.732


Signalling bits 4 pcs a, b, c, d / 64 kbit/s2 pcs a, b / c, d / 32 kbit/s1 pc a / b / c / d / 16 kbit/s


141


Time slot usage in trunk lines:cross-connectable time slots withsignalling bits (CAS)free bits

n-2 pcsTS0/B4…8 (see Control Channel Data Link below)

Control channel data link n x 8 kbit/s (n=1…8)Any time slot except TS0 frame alignment bitsTellabs 8100 trunk lines preferable TS0/B5…8 (16 kbit/s)

6.5 Unframed Data Interfaces

6.5.1 V.24/V.28,V.35,V.36/V.11; 1.2…19.2 kbit/s, 48, 56, n x 64 kbit/s

Interface type V.24/V.28 V.35,V.36/V.11,V.24/V.28

V.35,V.36,V.24(n=1)

Data bit rate 1.2, 2.4, 4.8, 7.2, 9.6,14.4, 19.2, 38.4 kbit/s

48, 56 kbit/s n x 64 kbit/sn=1,2,…,32

Framing inside Tellabs 8100network

V.110 V.110 -

Interface functions V.24 V.24 V.24

Handshake signal transmission37

- 105/109 SB SB V.13

- 106 X X -

- 108/107 SA SA -

- 140/142 V.54 V.54 V.54

Electrical Interface

- V.24 V.28 for all signals

- V.35 V.35 for signals 103, 104, 113, 114, 115, V.28 for other signals

- V.36 V.28 for signals 140, 141 and 142, V.11 for other signals

Interface signals 102, 103, 104, 105, 106, 107, 108, 109, 113, 114, 115, 140, 141,142

Connector type

- V.24 ISO 2110, D-type 25-pin female connector


- V.35-IEC ISO 2110, D-type 25-pin female connector


Test loops via data interface

- RL, V.54 remote loop, (loop 2)

- LL, V.54 local loop, (loop 3)

37SA, SB, X are bits in V.110 frame


142


6.5.2 X.21 1.2…19.2 kbit/s, 48, 56, n x 64 kbit/s

Data bit rate 1.2, 2.4, 4.8, 9.6,19.2, 38.4, 48kbit/s

56 kbit/s n x 64 kbit/sn=1, 2,…, 32

Framing inside Tellabs 8100network

X.30 (V.110) V.110 -

Interface functions V.24 V.24 -

Control signal transmission

- C/I S1+S3+S4S1, S3,S4 are bits in V.110frame

S3+S4 -

Interface signals

- bit rates 1.2…48 kbit/s G, T, R, S, C, I

- bit rates 56…n x 64 kbit/s G, T, R, S

Electrical interface X.27(V.11)

Connector type ISO 4903, D-type 15-pin female connector

6.5.3 Transparent 2 Mbit/s, n x 64 kbit/s

Interface type G.7032 Mbit/s

G.70364 kbit/s

OpticalLine

LineTerminal

BasebandLine

Data bit rate, n x 64 kbit/s n=32 n=1 n=32 n=17, 32 n x 64 kbit/sn=1…66

The G703-64-M interface is designed for indoor use only. It is not meant for externalconnections.

6.6 Data Interface Modules

6.6.1 8448 kbit/s, G.703 Interface (G703-8M-M Module)

Bit rate 8448 kbit/s ±30 ppm

Coding HDB3

Nominal impedance 75 Ω

Nominal peak voltage 2.37 V/75 Ω unbalanced

Pulse width 59 ns ±10 ns

Attenuation margin 0…6 dB/4 MHz

Jitter tolerance G.823

Connector type 50 Ω, SMB-type connector


143


6.6.2 2048 kbit/s, G.703 Interface (G703-75-M)


Coding HDB3


Nominal peak voltage 2.37 V/75 Ω unbalanced




Connector type 50 Ω, SMB-type connector

6.6.3 2048 kbit/s, G.703 Interface (G703-120-M)


Coding HDB3


Nominal peak voltage 3.0 V/120 Ω balanced




Connector type D-type 9-pin female connector

6.6.4 2048 kbit/s and 1088 kbit/s Line Terminal Interface (LTE-M Module)

Bit rate 2048 kbit/s ±50 ppm 1088 kbit/s ±50 ppm

Coding HDB3 HDB3

Nominal peak voltage 3.0 V / 120 Ω symmetrical

Pulse width 244 ns ±25 ns 460 ns ±40 ns

Attenuation margin 0…36 dB at 1024 kHz 0…36 dB at 544 kHz

Jitter tolerance G.823 Mask like G.823 for 2048 kbit/swith the following exceptions:A0: 19.6 (18 µs)A1: 0.75A2: 0.10f4: 50 kHz

Input impedance 120 Ω symmetrical

Return loss G.703


Overvoltage protection Gas discharge tubes, diodes


144


6.6.5 Optical Line Interface 2048 kbit/s / 8448 kbit/s (OTE-LED-M Module)

Bit rate 2048 kbit/s ±50 ppm8448 kbit/s ±30 ppm

Transmission path Standard multimode fiber (G.651)Standard single mode fiber (G.652)

Optical transmitter Semiconductor LED

Nominal wave length 1300 nm

Optical line code CMI

Symbol rate 4096 kBd (2 Mbit/s)16896 kBd (8 Mbit/s)

Optical receiver PIN diode

Min. sensitivity (BER 10-9) -50 dBm (2M)-42 dBm (8M)

Optical connector FC type with a receptacle

LED safety EN 60825-1/A2: 2001 (IEC 60825-1 Ed. 1.2, 2001-08)

Functional mode Minimum output power Attenuation margin

multimode LED 2 M -20 dBm 30 dB

single mode LED 2 M -30 dBm 20 dB

multimode LED 8 M -20 dBm 22 dB

single mode LED 8 M -30 dBm 12 dB

Fig. 79 Class 1 LED Product

6.6.6 Baseband Line Interface 64…384 kbit/s (BTE-384-M Module)

Bit rate N x 64 kbit/s (n=1…6)

Line interface 2/4W full-duplex

Line code Biphase space

Interface impedance 150 Ω symmetrical


145


Output level/150 Ω 0/-6 dBm

Return loss >12 dB

Maximum input level/150 Ω 0 dBm

Minimum input level/150 Ω -33 - -38 dBm (varies according to bit rate)

Equalizer Adaptive


6.6.7 Baseband Line Interfaces 320...4224 kbit/s (BTE-1088-M, BTE-2048-M,BTE-2048-2W-M, BTE-4096-M, BTE-320-M, BTE-576-M, BTE-1088-2W-Mand BTE-2304-M Modules)

Bit rate n x 64 kbit/s,n=5 (BTE-320-M)n=5, 9 (BTE-576-M)n=5, 9, 16, 17 (BTE-1088-2W-M)n=5, 9, 17 (BTE-1088)n=16, 17, 32, 33 (BTE-2048, BTE-2048-2W-M)n=16, 17, 32, 33, 34, 36 (BTE-2304-M)n=16, 17, 32, 33, 64, 66 (BTE-4096)

Line interface 4 W full-duplex (BTE-1088-M, BTE-2048-M, BTE-4096-M)2 W full-duplex (BTE-320-M, BTE-576-M)2 W/4W full-duplex (BTE-2048-2W-M, BTE-1088-2W-M,BTE-2304-M)

Line code 2B1Q

Interface impedance 135 Ω symmetrical

Output level/135 Ω +13.5 /+6 dBm/0 dBm

Return loss > 12 dB

Maximum input level/135 Ω + 15 dBm

Minimum input level/135 Ω -15…-30 dBm, varies according to bit rate and transmit level

Equalizer Adaptive

Connector type D type 9-pin female connector

6.7 Service Computer (SC) Interface

Interface type V.24

Electrical interface V.28

Data bit rate 9.6 kbit/s asynchronous

Character format 8 bit, no parity, 1 stop bit

Connector type ISO 2110, D-type 9-pin female connector

Interface signals 102, 103, 104, 105, 106, 107, 108, 109

Protocol Layers 2…7 proprietary


146


6.8 Power Supply

AC Power Supply

Input voltage 100...240 V AC ±10% 47…63 Hz

Type number 8990NFS40

DC Power Supply 24 V

Input voltage 19…36 V DC, negative pole earthed

Type number PDU 42238

DC Power Supply 48 V

Input voltage 40…60 V DC, positive pole earthed

Type number PDU 423

Power Consumption

Dependent on furnishing, max < 40 W

6.8.1 Power Consumptions of Tellabs 8120 Mini Node M Units and Modules

Unit or Module Description Power Consumption(max)

BTE-64-M39 Baseband interface module 2.3 W

BTE-320-M39 T-SDSL interface module 2.2 W




BTE-1088-2W-M39 T-SDSL interface module 2.2 W


BTE-2048-2W-M39 T-SDSL interface module 4.5 W



G703-64-M39 G.703 64 kbit/s interface module 1.5 W

G703-75-M G.703 2 Mbit/s 75-ohm interface module 1.0 W

G703-120-M G.703 2 Mbit/s 120-ohm interface module 1.0 W

G703-8M-M39 G.703 8 Mbit/s 75-ohm interface module 1.0 W

38The power supply module has been discontinued.39The interface module has been discontinued.


147


Unit or Module Description Power Consumption(max)

HSSI-M39 High-Speed Serial interface module 3.9 W

LTE-M39 Line terminal 1/2 Mbit/s 1. 1W

Mini LAN Module 10Base-T Ethernet interface module 2.0 W

OTE-LED-M Optical line interface module 2/8 Mbit/s 3.7 W

SMU-M Tellabs 8120 mini M base unit 5.0 W

VCM-M-M V-series interface base unit 1.5 W

VCM-V-M VF-series interface base unit 1.0 W

VCM-VM-M V/VF-series interface base unit 1.5 W

V24-DCE-M39 V.24 interface module 1.5 W

V24-DTE-M39 V.24/V.28 DTE interface module 1.5 W

V35-M V.35 interface module 1.5 W

V35/V24-M39 V.35/V.24 DCE interface module 1.5 W

V36-M39 V.36 interface module 1.5 W

X21-M X.21 interface module 1.5 W

6.9 Mechanics

Width 352 mm

Depth 278 mm

Height 75 mm

Weight, max. 4.5 kg, depends on furnishing

6.10 Environmental Conditions

6.10.1 Climatic/Mechanical Compatibility

Tellabs 8120 mini Node (SBM 2048) HW version 6.1 or later

Storage ETS 300 019-1-1:1992-02Class1.1Weather protected, partly temperature controlled storage locations-5°C...+45°C

Transport ETS 300 019-1-2:1992-02Class2.3Public transportation-25°C...+70°CRain is not allowed ; -25°C maximum

In use ETS 300 019-1-3:1992-02Class 3.1Temperature-controlled locations+5°C...+40°C (-5°C…+45°C)


148


6.11 Safety Compatibility

Tellabs 8120 mini node (SBM 2048) HW version 6.1 or later

Safety EN 60950-1:2001

When AC power supply is used, Tellabs 8120 mini M must be connected to a wall socket-outletwith protective earth contact.

When DC power supply is used, Tellabs 8120 mini node M must be permanently connected toearth using the supplied grounding earth wire.

6.12 Electromagnetic Compatibility

Tellabs 8120 mini Node (SBM 2048) HW version 6.1 or later

EMC EN 300 386:2005


149

Appendix 1: Frame Structures


Frame Structures at Bit Rates 48…2048 Kbit/s

Frames Not Supporting CRC Checking and Plesiochronous Clocking

The rate adaptation and multiplexing schemes used in the basic operation mode (no CRC check orindependent clocking) are as follows.

48 kbit/s CCITT V.110/X.30

V.110 Rate Adaptation 48 kbit/s → 64 kbit/s

Octetno.

Bit no.

1 2 3 4 5 6 7 8

1 1 D1 D2 D3 D4 D5 D6 S1

2 0 D7 D8 D9 D10 D11 D12 X

3 1 D13 D14 D15 D16 D17 D18 S3

4 1 D19 D20 D21 D22 D23 D24 S4

• FSW: 1011

• Dn: data bits

• S1, S3: SA =108/107 signal

• S4: SB = 105/109 signal

• X: X = 106 signal

• X.30: SA+SB = C/I (105/109) signal

• Frame length: 500 µs

56 kbit/s CCITT V.110 Tables b and c

V.110 Rate Adaptation 56 kbit/s → 64 kbit/s

Octet no Bit no.

1 2 3 4 5 6 7 8C 8B

1 D1 D2 D3 D4 D5 D6 D7 0 1

2 D8 D9 D10 D11 D12 D13 D14 X 1

3 D15 D16 D17 D18 D19 D20 D21 S3 1

4 D22 D23 D24 D25 D26 D27 D28 S4 1


150


Octet no Bit no.

5 D29 D30 D31 D32 D33 D34 D35 1 1

6 D36 D37 D38 D39 D40 D41 D42 1 1

7 D43 D44 D45 D46 D47 D48 D49 1 1

8 D50 D51 D52 D53 D54 D55 D56 1 1

V.110 defines two types of frames at 56 kbit/s. Bit 8 is used as 8B in frame mode 1 (CCITT V.110table 7b) and as 8C in mode 2 (CCITT V.110 table 7c).

• FSW0 - - - 1111

• Dn: data bits

• S3: SA =108/107 signal

• S4: SB = 105/109 signal


• Frame length: 1 ms

72, 80, 144 and 160 kbit/s

Mapping of 72, 80, 144, 160 kbit/s

Datarate

64 kbit/s bit no. 8 kbit/s chan no40

1 2 3 4 5 6 7 8 A B C D

72 D1 D2 D3 D4 D5 D6 D7 D8 D9 - - -

80 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 - -

144 D1 D2 D3 D4 D5 D6 D7 D8 D9 - - -

D10 D11 D12 D13 D14 D15 D16 D17 - D18 - -

160 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 - -

D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20

• Di: User data bits. The index shows sequence order.

• The frame length is 125 µs.

Frames Supporting CRC Checking and Plesiochronous Clocking

The rate adaptation and multiplexing schemes supporting CRC checking or/and plesiochronous dataclocking are shown below. The CRC checking procedure is based on the CRC-4 method used inG.704. The transfer of clock phase and stuffing bits is based on the method in V.110.

40A, B, C, D: 8 kbit/s channels used to transport the n x 8 kbit/s capacity


151


48 kbit/s Modified CCITT V.110/X.30

Rate Adaptation of 48 kbit/s → 64 kbit/s when Supporting CRC Check and IndependentClocking

Octetno

Bit no.

1A 1B 1C 2 3 4 5 6 7 8

1 0 0 0 D1 D2 D3 D4 D5 D6 S1

2 X X X D7 D8 D9 D10 D11 D12 X

3 CFE CFE 1 D13 D14 D15 D16 D17 D18 S3

4 1 1 1 D19 D20 D21 D22 D23 D24 S4

5 0 0 0 D25 D26 D27 D28 D29 D30 S1

6 1 1 1 D31 D32 D33 D34 D35 D36 X

7 1 1 1 D37 D38 D39 D40 D41 D42 S3

8 1 1 1 D43 D44 D45 D46 D47 D48 S4

9 1 1 1 D49 D50 D51 D52 D53 D54 S1

10 E4 1 E4 D55 D56 D57 D58 D59 D60 X

11 E5 1 E5 D61 D62 D63 D64 D65 D66 S3

12 E6 1 E6 D67 D68 D69 D70 D71 D72 S4

13 C1 C1 1 D73 D74 D75 D76 D77 D78 S1

14 C2 C2 1 D79 D80 D91 D82 D83 D84 X

15 C3 C3 1 D85 D86 D87 D88 D89 D90 S3

16 C4 C4 1 D91 D92 D93 D94 D95 D96 S4

56 kbit/s Modified CCITT V.110

Rate Adaptation of 56 kbit/s → 64 kbit/s when Supporting CRC Check and IndependentClocking

Octetno

Bit no.

1 2 3 4 5 6 7 8A 8B 8C 8D

1 D1 D2 D3 D4 D5 D6 D7 0 0 0 0

2 D8 D9 D10 D11 D12 D13 D14 X X X X

3 D15 D16 D17 D18 D19 D20 D21 CFE CFE S3 S3

4 D22 D23 D24 D25 D26 D27 D28 S4 S4 S4 S4

5 D29 D30 D31 D32 D33 D34 D35 0 0 0 0

6 D36 D37 D38 D39 D40 D41 D42 1 1 1 1

7 D43 D44 D45 D46 D47 D48 D49 1 1 1 1

8 D50 D51 D52 D53 D54 D55 D56 1 1 1 1

9 D57 D58 D59 D60 D61 D62 D63 1 1 1 1

10 D64 D65 D66 D67 D68 D69 D70 E4 X E4 X


152


Octetno

Bit no.

11 D71 D72 D73 D74 D75 D76 D77 E5 S3 E5 S3

12 D78 D79 D80 D91 D82 D83 D84 E6 S4 E6 S4

13 D85 D86 D87 D88 D89 D90 D91 C1 C1 1 1

14 D92 D93 D94 D95 D96 D97 D98 C2 C2 1 1

15 D99 D100 D101 D102 D103 D104 D105 C3 C3 1 1

16 D106 D107 D108 D109 D110 D111 D112 C3 C4 1 1

• 8A: both CRC checking and plesiochronous clocking are used

• 8B: only CRC checking in use

• 8C: only plesiochronous clocking in use

• 8D: neither CRC check nor plesiochronous clocking in use

• FSW: 0 - - -01111

• Dn: data bits

• S3: SA = 108/107 signal

• S4: SB = 105/109 signal


• CFE: CRC bit from remote end

• Ci: bits for transfer of the CRC word

• Ei: bits for transfer of clock phase and stuffing bits

• E6: transfers an extra D bit at positive justification inserted between D72 - D73 or D84 - D85

• D73: is set to 1 when performing negative justification


72, 80 kbit/s

Adaptation of 72 and 80 kbit/s when Supporting CRC Check and Plesiochronous Clocking

Setno

64 kbit/s bit no 8 kbit/s chan41

1 2 3 4 5 6 7 8 A B C

1 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0

2 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 X

3 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 CFE

4 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 S4

5 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 0

6 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1

418 kbit/s channel no B is not used at 72 kbit/s. Channel C uses a 16-bit long frame carrying the CRC check sum and phasing and stuffing data forplesiochronous clocking.


153


Setno

64 kbit/s bit no 8 kbit/s chan41

7 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1

8 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1

9 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1

10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E4

11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E5

12 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E6

13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C1

14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C2

15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C3

16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 C4

• Set: group of data bits transmitted each 125 µs

• FSW: 0 - - -01111

• Dn: data bits

• S3: SA = 108/107 signal

• S4: SB = 105/109 signal


• CFE: CRC bit from far-end



• E6: transfers an extra D bit at positive justification inserted before bit D1 of set 14

• D8 of set 13: is set to 1 when performing negative justification


144, 160 kbit/s

Adaptation of 144 and 160 kbit/s when Supporting CRC Check and Plesiochronous Clocking

Setno42

64 kbit/s bit no 8 kbit/s no43

1 2 3 4 5 6 7 8 A B C D E

1a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

1b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 0

2a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

2b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 X

42The sets a and b are transmitted during the same G.704 frame (125 µs).438 kbit/s channels B and D are not used at 160 kbit/s. Channel E uses a 16-bit long frame carrying the CRC check sum and phasing and stuffing datafor plesiochronous clocking.


154


Setno42

64 kbit/s bit no 8 kbit/s no43

3a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

3b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 CFE

4a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

4b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 S4

5a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

5b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 1

6a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

6b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 1

7a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

7b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 1

8a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

8b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 1

9a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

9b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 1

10a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

10b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 E4

11a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

11b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 E5

12a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

12b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 E6

13a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

13b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 C1

14a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

14b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 C2

15a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

15b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 C3

16a D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

16b D11 D12 D13 D14 D15 D16 D17 D18 - - D19 D20 C4

• FSW: 0 - - -01111

• Dn: data bits

• S3: SA = 108/107 signal

• S4: SB = 105/109 signal






155


• E6: transfers an extra D bit before D1 of set 13a at positive justification

• D8 of set 13a: is set to 1 when performing negative justification


Adaptation of n x 64 kbit/s when Supporting CRC Check and Plesiochronous Clocking

Frame No 8 kbit/s no

A B C

1 1 0 SB

2 E4 X SB

3 E5 CFE SB

4 E6 S4 SB

5 1 0 SB

6 E4 1 SB

7 E5 1 SB

8 E6 1 SB

9 1 1 SB

10 E4 E4 SB

11 E5 E5 SB

12 E6 E6 SB

13 1 C1 SB

14 E4 C2 SB

15 E5 C3 SB

16 E6 C4 SB

The 8 kbit/s channel A carries the clock phasing and justification data at bit rates exceeding 512kbit/s. When no independent clocking is needed or when bit rates are below 512 kbit/s, channelB is sufficient. If required, the 8 kbit/s channel C is used to carry signal SB transferring signal105/109 or C/I

• FSW: 0 - - -01111

• S4: SB = 105/109 signal





• E6: transfers an extra D bit at positive justification

The n x 64 kbit/s data is chopped into bytes. At positive justification the bit E6 is inserted after thelast bit of the first byte received in frame 13. A negative justification takes place by deleting thelast bit of the first byte received in frame 13.


156


Frame Structures at Bit Rates below 48 Kbit/s

Bit rates below 48 kbit/s are rate adapted to n x 8 kbit/s (XB rate) according to CCITTRecommendation V.110/X.30.

Relation between Data Rates and Adapted XB Rates

Data rate XB rate

1.2 kbit/s 8 kbit/s

2.4 kbit/s 8 kbit/s

9.6 kbit/s 16 kbit/s



The octet structured V.110 frame is 80 bits long.

User Rates n x 4.8 kbit/s

V.110 Frame for Adaptation of n x 4800 b/s to n x 8 kbit/s

Octetno

Bit no

1 2 3 4 5 6 7 8

1 0 0 0 0 0 0 0 0

2 1 D1 D2 D3 D4 D5 D6 S1

3 1 D7 D8 D9 D10 D11 D12 X

3 1 D13 D14 D15 D16 D17 D18 S3

5 1 D19 D20 D21 D22 D23 D24 S4

6 1 E1 E2 E3 E4 E5 E6 E7

7 1 D25 D26 D27 D28 D29 D30 S1

8 1 D31 D32 D33 D34 D35 D36 X

9 1 D37 D38 D39 D40 D41 D42 S3

10 1 D43 D44 D45 D46 D47 D48 S4

• FSW: 000000001…1…1…1…1…1…1…1…1

• Dn: data bits

• S1, S3, S6, S8: SA = 108/107 signal

• S4, S9: SB = 105/109 signal


• E1-E3: user data rate information code

• E4-E6: bits for transfer of clock phase information and stuffing bits at plesiochronous operation.They are set to 1 when not used


157


• E7: alignment bit for the four frame multiframe (MFSW=1110). E7 is set to 1 when not used

• E6: transfers an extra D bit at positive justification. The bit is inserted between D24 and D25

• D25 : is set to 1 when performing negative justification

• Frame length: 2.5, 5 or10 ms, depending on bit rate

The rates 600, 1200 and 2400 are mapped to the frame of the previously presented table Adaptationof n x 64 kbit/s when Supporting CRC Check and Plesiochronous Clocking as follows:

• Each 600 b/s bit occupies eight consecutive Dn bit positions starting from D1 (e.g. bit 1 =D1+D2+D3+D4+D5+D6+D7+D8)

• Each 1200 b/s bit occupies four consecutive Dn bit positions starting from D1 (e.g bit 1 =D1+D2+D3+D4, bit2 = D5+D6+D7+D8)

• Each 2400 b/s bit occupies two consecutive Dn bit positions (e.g. bit 1 = D1+D2, bit2 = D3+D4,bit3 = D5+D6).

One V.110 frame transfers 6 bits at 600 bit/s, 12 bits at 1200 bit/s and 24 bits at 2400 bit/s.


V.110 Frame for Adaptation of n x 3600 bit/s to n x 8 kbit/s

Octetno.

Bit no

1 2 3 4 5 6 7 8

1 0 0 0 0 0 0 0 0

2 1 D1 D2 D3 D4 D5 D6 S1

3 1 D7 D8 D9 D10 F44 F X

3 1 D11 D12 F F D13 D14 S3

5 1 F F D15 D16 D17 D18 S4

6 1 E1 E2 E3 E4 E5 E6 E7

7 1 D19 D20 D21 D22 D23 D24 S1

8 1 D25 D26 D27 D28 F F X

9 1 D29 D30 F F D31 D32 S3

10 1 F F D33 D34 D35 D36 S4

Otherwise see the table User Rates n x 4.8 kbit/s. D19 corresponds to D25.

44F = filling bit


158




Octet no Bit no

1 2 3 4 5 6 7 8

1 0 0 0 0 0 0 0 0

2 1 D1 D2 D3 D4 D5 D6 S1

3 1 D7 D8 D9 D10 F F X

3 1 D11 D12 F F D13 D14 S3

5 1 F F D15 D16 F F S4

6 1 E1 E2 E3 E4 E5 E6 E7

7 1 D17 D18 D19 D20 D21 D22 S1

8 1 D23 D24 D25 D26 F F X

9 1 D27 D28 F F D29 D30 S3

10 1 F F D31 D32 F F S4



Octet no Bit no

1 2 3 4 5 6 7 8

1 0 0 0 0 0 0 0 0

2 1 D1 D2 D3 D4 D5 D6 S1

3 1 D7 D8 D9 D10 F F X

3 1 D11 D12 F F D13 D14 S3

5 1 F F D15 F F F S4

6 1 E1 E2 E3 E4 E5 E6 E7

7 1 D16 D17 D18 D19 D20 D21 S1

8 1 D22 D23 D24 D25 F F X

9 1 D26 D27 F F D28 D29 S3

10 1 F F D30 F F F S4

Bit Rate Information Code E1-E3

The bit rate information is coded as follows.

Bit Information Code E1-E3

Bit rate bit/s E1 E2 E3

600 1 0 0

1200 0 1 0


159


Bit rate bit/s E1 E2 E3

2400 1 1 0

4800 0 1 1

9600 0 1 1

19200 0 1 1

38400 0 1 1

3600 1 0 1

7200 1 0 1

14400 1 0 1

28800 1 0 1

3000 0 1 1

6000 0 1 1

12000 0 1 1

24000 0 1 1

3200 0 0 1

6400 0 0 1

12800 0 0 1

25600 0 0 1

Use of Clock Phase and Stuffing Information Bits E4-E6

Network independent timing (plesiochronous) is supported at user data rates 3000 b/s and above.The E4-E6 bits are used as follows.

Clock Phase and Stuffing Information

Clock displacement, % E4 E5 E6

0 1 1 1

+20 0 0 0

+40 0 0 1

-40 0 1 0

-20 0 1 1

Stuffing control

Positive justification of a 1 1 0 1

Positive justification of a 0 1 0 0

Negative justification 1 1 0


160


Modified V.110 Frame for Transfer of CRC Check Sum

Octetno

Bit no

1 2 3 4 5 6 7 8

1 0 0 0 0 0 0 0 0

2 1 D1 D2 D3 D4 D5 D6 S1

3 1 D7 D8 D9 D10 D11 D12 X

3 1 D13 D14 D15 D16 D17 D18 S3

5 1 D19 D20 D21 D22 D23 D24 S4

6 CFE E1 E2 E3 E4 E5 E6 E7

7 C1 D25 D26 D27 D28 D29 D30 S1

8 C2 D31 D32 D33 D34 D35 D36 X

9 C3 D37 D38 D39 D40 D41 D42 S3

10 C4 D43 D44 D45 D46 D47 D48 S4

• FSW: 000000001…1…1…1

• Dn: data bits

• S1, S3: SA = 108/107 signal

• S4: SB = 105/109 signal


• E1-E3: user data rate information code

• E4-E6: bits for transfer of clock phase information and stuffing bits at plesiochronous

• CFE: CRC check sum indication to the far-end

• Ci: CRC check sum

• F: filling bits (not shown) are used for adaptation of n x 3600, n x 3000 and n x 3200 b/s ton x 8 kbit/s as in the tables of the Frame Structures at Bit Rates below 48 Kbit/s presented earlierin Appendix 1.


161

Appendix 2: G.704 Frame Structures


8448 kbit/s Frame Structure

Fig. 80 Frame Structure of G.704 8448 kbit/s


162


2048 kbit/s Frame Structure

Fig. 81 Frame Structure of G.704 2048 kbit/s


163


N x 64 kbit/s Frame Structure

Fig. 82 Frame Structure of G.704 n x 64 kbit/s; n ≤ 17


164


Fig. 83 Frame Structure of G.704 n x 64 kbit/s; n > 17


165


Multiframe Structure in Signalling Time Slot

(8 Mbit/s frame TS67, 68, 69, 70. 2 Mbit/s frame and n x 64 kbit/s frame with n >17 TS16.N x 64 kbit/s frame with n≤17 TSn-1.)

45Frame # SigTS-bits1234abcd

SigTS-bits5678abcd

Use

0 0000 SASS 0000=M-FSW, A=FEA (1-active), S=spare

1 TS1 TS17 abcd bits for TS1 and TS17 of the group

2 TS2 TS18 .

3 TS3 TS19 .

4 TS4 TS20 .

5 TS5 TS21 .

6 TS6 TS22 .

7 TS7 TS23 .

8 TS8 TS24 .

9 TS9 TS25 .

10 TS10 TS26 .

11 TS11 TS27 .

12 TS12 TS28 .

13 TS13 TS29 .

14 TS14 TS30 .

15 TS15 TS31 abcd bits for TS15 and TS31 of the group

45Multiframe length is 16 frames/125 µs = 2 ms (500 Hz)


166


CRC Multiframe Structure in TS0 for 2 Mbit/s and n x 64 kbit/s Frames

Frame # TS0 bits1 2345678 Use

Block #1

0 C1 0011011 46C1…C4 = CRC-4 bits

1 0 1ASHHHH A = FEA (1-active), S = spare

2 C2 0011011 0011011 = FSW, H = reserved for the HDLC link

3 0 1ASHHHH 001011 = CRC M-FSW

4 C3 0011011

5 1 1ASHHHH

6 C4 0011011

7 0 1ASHHHH

Block #2

8 C1 0011011

9 1 1ASHHHH

10 C2 0011011

11 1 1ASHHHH

12 C3 0011011

13 E1 1ASHHHH E1 = BlockI FEA (0-active)

14 C4 0011011

15 E2 1ASHHHH E2 = BlockII FEA (0-active)

46The CRC multiframe length is 16 frames/125 µs = 2 ms (500Hz)


167

Documents

8120 M Tellabs Node Operating Manual