(8th Semester) Project Report

Nirma Institute of Technology ( Approved by All India Council for Technical Education – New Delhi and Affiliated to Gujarat University, Ahmedabad )

Gandhinagar-Sarkhej Highway Tragad Patia, Post-Chandlodia, Via-Gota, Chharodi, Ahmedabad-382481. Ph.: (079) 3741911-15 Fax : (079) 3741917 E-mail : [email protected]

CERTIFICATE This is to certify that the under mentioned students of B.E. IV, Semester VIII,

(Instrumentation and Control), Nirma Institute of Technology, have been

working on the project titled ‘Autonomous and Semi-autonomous Robots for

Coordinated Task Solving (Robocon 2004)’ at Nirma Institute of Technology

under my guidance for the fulfillment of their curriculum requirement, since

December, 2003.

They have been regular, sincere and hard working to try and successfully

completed their project assignment.

Abhijit Karnik

Harsh Satyapanthi

Prof. B. B. Kadam DATE: Project Guide and Coordinator Robocon 2004 Nirma Institute of Technology

CERTIFICATE

NIRMA INSTITUTE OF TECHNOLOGY

AHMEDABAD

I hereby certify that the following students of B.E. IV, Semester VIII,

Instrumentation and Control have satisfactorily completed their project on

‘AUTONOMOUS AND SEMI-AUTONOMOUS ROBOTS

FOR COORDINATED TASK SOLVING

(ROBOCON 2004)’

at

NIRMA INSTITUTE OF TECHNOLOGY

SR. NO. NAME ROLL NO.

1 ABHIJIT KARNIK 00IC28

2 HARSH SATYAPANTHI 00IC44 (Mr. Vaibhav Gandhi) (Dr. M.D. Desai) INTERNAL GUIDE HEAD OF THE ELECTRICAL ENGINEERING DEPARTMENT DATE:

Project Report 8th Sem. I.C.

Nirma Institute of Technology

ACKNOWLEDGEMENT:

As students of the final year of engineering (Instrumentation & Control), we are

required to undertake a project as a part of our curriculum. Our project for 8th Semester is

titled “AUTONOMOUS AND SEMI-AUTONOMOUS ROBOTS FOR

COORDINATED TASK SOLVING”. Herewith is encapsulated a report of the same.

In our attempt, we have come to realize that robotics is a field which is not just an

isolated field on its own. It is the synthesis of a number of concepts from all the major

engineering fields. Hence our journey has had a number of guides, each one from a

different field. In submitting this report, we, the undersigned, would like to take the

opportunity to thank all these people, without whose help our modest endeavor would

never have seen the light of the day.

Thereby we take immense pleasure in thanking Prof. B. B. Kadam (Prof.

Electrical Dept.) who is our guide, Dr. M.D. Desai (HOD, Electrical Dept.), Mr. Vaibhav

Gandhi (Lecturer, IC Dept., & Internal Guide), Prof. D. M. Adhyaru (Asst. Prof., IC

Dept.), Ms. Gauri Mudaliar (Lecturer, Mechanical Dept.), Mr. Chintan Bhatt (Lecturer,

IC Dept.), Mr. Sachin Gajjar (Lecturer, EC Dept.), Mr. Dishang Trivedi (Lecturer,

Electrical Dept.), Mr. H.K. Patel (Lecturer, IC Dept.), Mr. Navinbhai Shah (Applications

Engineers).

We would also like to acknowledge the enthusiastic support that was given to us

by the management of college and faculty of I.C. Dept., who not only gave us moral

support but were actively interested in our project through all its ups and downs.

Last but not the least; we would like to acknowledge the unquestioning and

tireless support from our families.

Abhijit Karnik Harsh Satyapanthi



FOREWORD:

The word robot was coined by the Czech writer Kapek in his play ‘Rossum's

Universal Robots’. Since then countless devices have been created and have been

associated with the word ‘Robot’. The works of Isaac Asimov have laid the foundation of

sociology pertaining to the use of robots instead of humans and the word ‘Robotics’ was

also coined by him. In today’s world, work on robots, that resemble and look almost

human, and others which don’t resemble humans in any way, progresses in leaps and

bounds. The world has forerunners in this technology like MIT, CMU, Sony, Honda etc.

In this world of ASIMO, AIBO, Packbot etc., we have made an attempt to create

machines which we dare call ‘Robots’.

In this era where organizations like ABU – Asia Pacific Broadcasting Union are

organizing robot contests like Robocon we have made an attempt to make robotic

systems which could send and receive communication signal amongst them and complete

the task assigned to them with coordinated efforts. Today when technology is developing

faster then a blink of an eye and the competition is tough to win at any stage may it be

national or international, we have put in tireless efforts to implement the technology in

simpler and effective form to compete against some of the best in field of robotics in the

country.



INTRODUCTION:

This report is the documentation of all the efforts put into the making of

Autonomous and Semi-autonomous Robots by us as the Participating Team Members of

Robocon 2004 Team of Nirma Institute of Technology. The title of the project was

coined as:

‘Autonomous and Semi-autonomous Robots for Coordinated Task Solving’,

These robots are targeted to perform a coordinated task in the Game Arena of

Robocon ’04 where the task to be performed is common for all the participant teams from

all the institutions and nations. This report explains the technology and heuristics

involved in making of the robots and how the task is planned to be completed using the

same.

The report is divided into 6 sections. Each section deals with the project from a

different viewpoint. The first section deals with the explanation of the Contest Theme of

Robocon 2004 and pertaining details. The second section deals with the purpose of the

robots and the features included in the robots. The third section deals with the operational

description of the different modules of the robot which thereby allow the proper

functioning of the features that we have planned to implement on the robot. The fourth

section is the hardware and software section wherein the mind and the nerve control of

the robot is explained. The fifth section explains how the research and development as

well as heuristics and ideas have played a major role in shaping up this project. The last

section is the annexure containing the selected sections of the datasheets of the electronic

components used in our project, bibliography and the information about the sources of

the systems components.



SECTION 1

ABU – Asia Pacific Robot Contest

Robocon 2004 Seoul

The ABU – Asia Pacific Broadcasting Union has been organizing the Asia Pacific

Robot Contest since 2002 which is better known as ‘Robocon’ in which the teams from

the member nations of the Asia Pacific Broadcasting Union participate.

This contest is being organized in order to create the awareness for the field of

Robotics amongst the students at undergraduate level. The undergraduate students are

encouraged to participate and finally take interest and contribute to the field of Robotics.

The contest is held first at the National level in all the participating countries. In

the national level contest the teams or undergraduate students from various colleges and

institutions participate and the winning team of the contest represents the country at the

international level.

For the contest a theme and rules are declared by the Robocon Committee and the

theme and ruler remain common for all the competitions at national levels in various

countries as well as for the international contest.

Robocon 2004 will be the third consecutive time this contest will take place.

Robocon 2004 is to be held in Seoul, Korea and the Theme and Rules of the contest are

mentioned next.



Theme and Rules – Robocon 2004 Seoul

The aim of this robot contest is to make machines by hand from design to

construction which will be most suitable to compete in the below contest

theme and rules.

Reunion of Separated Lovers, ‘Gyeonwoo and Jiknyeo’

The theme of this contest is based on a love story in Asian legend. A couple

called ‘Gyeonwoo & Jiknyeo’ are forced to be apart from each other with the

Milky Way between them due to their laziness. Magpies and crows which

feel sorry for the couple fly up to the sky and build a bridge with their bodies

to get the couple together. It is called ‘Ojak Bridge’ (Bridge of Crow and

Magpie). The couple get together by crossing ‘Ojak Bridge’ once a year, on

July 7th by lunar calendar. It always rains on this day and we say that it is the

tears of joy from Gyeonwoo and Jiknyeo for their reunion.

The aim of this contest is to compete for accomplishing “Reunion” by

completing the unfinished bridge and carrying Golden Gift by Automatic

Machine from “Gyeonwoo Zone (Zone A)” to “Jiknyeo Zone (Zone B)”.

The duration of each match is three minutes.



1. THE GAME FIELD

The following three pages show and explain the layout and details of

the Game Field to on which the contest takes place.

2. OBJECTS (GIFT/GOLDEN GIFT/BRIDGE)

The details pertaining to the Gift, Golden Gift and the Bridge and

Bridge parts are also mentioned in the floor plan and layout of the game

field in the following three pages.

Manual Machine Common Zone

Gyeonwoo Zone(Zone A)

Jiknyeo Zone(Zone B) 2 Point Scoring Bin

1 Point Scoring Bin

Blue Manual Machine Start Zone

Blue Automatic Machine Start Zone

Golden Gift (EPS)2.3 0.1 kg

Gift (EPS)0.4 0.05 kg

Jiknyeo's Hands

Big Bridge Part (EPS)3.2 0.1 kg Small Bridge Part (EPS)

Smaller Bridge Part (EPS)

Red Manual Machine Start Zone

Red Automatic Machine Start Zone

Ojak Bridge

Red Milky Way Zone

Blue Milky Way Zone

Game Field Big Bridge Part (EPS)

Big Bridge Part (EPS)

A3

SHEET 1 OF 3

ABU Asia-Pacific Robot Contest 2004 Seoul"Reunion of Separated Lovers, Gyeonwoo & Jiknyeo "

A3

SHEET 1 OF 3SCALE:

Project Title

1000 1000

500

2900

30

1200

1200

500

1950 50

3

14.2

5°14

.25°

14.25

°

1000

1000

2000

400

1400

0

14000

896.25

50Outer Wall

5000

1400

1/5

Inner Wall

Game Field (Dimension)

500 100

100

600

400

150Outer Wall

100Inner Wall

100100

10010

A3

SHEET 2 OF 3


A3

SHEET 2 OF 3SCALE:

Project Title

600

400

800

Big Bridge Part

600

385415

Small Bridge Part

400

385

Smaller Bridge Part

1 Point Scoring Bin

Gyeonwoo Zone

Jiknyeo Zone

200

200

Gift

Fixed Ojak Bridge

400

400

Golden Gift

1000

1000

485

485

12001200

10000

10000

5000

1200

1500

500

1000

1500

500

500

500

500

500

500

500

500

500

500

500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500

2000

1400

400

2 Point Scoring Bin

3

1000 100

Mark for Gift Position10 mm wide non-shiny vinyl tape in the same color as Gyeonwoo Zone (Zone A)

30 mm wide white guideline

10

500

100

A3

SHEET 3 OF 3


A3

SHEET 3 OF 3SCALE:

Project Title



3. MACHINES

Each team must design and construct either or both handmade Manual Machine and Automatic Machine(s) to compete in the contest. There is no restriction in the number of Automatic Machine(s) but ONLY ONE Manual Machine is allowed to each team.

(1) Manual Machine

a. Manual Machine has to be operated via remote control using cable connected to the Manual Machine or remote control using infrared rays, visible rays or sound waves. Radio waves are not allowed. Operators are not allowed to ride on the machines.

b. When operating via cable, the connecting point between the Machine and the control box must be placed at least 1000 mm above the ground. Also the length of the cable from the Manual Machine to the control box must not exceed 3000 mm.

c. The team members are not allowed to operate the machines or touch the materials placed on the game field by using cable.

d. Manual Machine or its operator cannot touch “Gyeonwoo Zone (Zone A)’s floor and extend over into “Jiknyeo Zone (Zone B)”.

e. Manual Machine cannot touch the boundary lines or extend over the opponent’s “Milky Way Zone”.

f. Manual Machine cannot touch its own team’s Automatic Machines. g. Manual Machine is allowed to send a signal to an Automatic Machine

only once for communication.

(2) Automatic Machine(s)

a. Automatic Machines have to be autonomous. b. Everything separated from an automatic machine is considered to be

another automatic machine, so it must work as an automatic machine. c. Automatic Machines are allowed to go into any zones except for the

opponent’s “Gyeonwoo Zone (Zone A)”. d. There is no time restriction for the start of Automatic Machines. In

other words, each Automatic Machine can be started at a different time after a game begins.

e. Once a machine starts, the team members are not allowed to touch the machine. But, after a team calls for a “retry” and the referee grants it,



all the team are allowed to reset and restart any Automatic Machines from the start zone.

f. “Retry” is permitted only once per game for each team.

(3) Method of Control

a. Only one operator for each team is allowed to control Manual Machine in the game field.

b. The Automatic Machine operators are allowed to enter the game field only when they start the machines including a “retry”.

c. Each Automatic Machine must be started by one operation.

(4) Power Supply

a. Each team shall prepare its own power source for all its machines during the games.

b. Voltage of the machines’ electrical power source must be below DC24 V.

c. Power source that is considered dangerous or unsuitable by the committee shall not be permitted.

(5) Weight

a. The total sum of weight of all machines must not exceed 50 kg. b. The total weight includes the weight of power sources, cables, remote

controller and other parts of the machines.

(6) Size

a. The total size of Automatic Machines has to fit in the size of 1200 mm x 1200 mm x 1500 mm at the Start Zone.

b. After the game begins, Automatic Machines can be separated and the sizes can be changed freely.

c. The Manual Machine has to fit in the size of 1200 mm x 1200 mm x 1500 mm at the Start Zone.

d. After the game begins, the size of Manual Machine can be changed freely, but it cannot be separated.



Apart from the mentioned technical details in the report there are other numerous facts like scoring methodology, limitations of the robots, violations in the game, decision of winner etc. that could matter during each game to be played for 3 minutes. The details pertaining to the same could be obtained from the following sources. ü QUESTIONS REGARDING THEME AND RULES

Questions regarding theme and rules should be addressed by e-mail to the Committee in English.

E-mail: [email protected] ‘ABU Robocon 2004 Seoul’ http://www.abu.org.my/programme/robocon/robocon.htm http://www.kbs.co.kr/aburobocon2004 The Contest Rules designed by KBS Technical Advisor Group - Prof. Chong Nam Chu, Seoul National University Prof. Dong Sam Park, University of Incheon Dr. Young Soo Lee, Seoul National University Mr. Min Soo Park, Seoul National University & ABU Contest Committee



SECTION 2

PROJECT OBJECTIVES:

As the title of the project along with the game theme suggests there are in total

four robots planned to be placed into the game field in order to complete the required

task. For the proper execution of the strategy for the game the robots are require to work

in coordination and thus the robots are made capable to communicate amongst

themselves as well.

The four robots could be classified into two categories as mentioned below:

1. Semi-autonomous (Manual) Robot - 1

2. Autonomous Robots - 3

Semi-autonomous (Manual) Robot – Viswakarma:

The manual robot is actually the semi-autonomous robot mentioned in the title

which is controlled using a control box attached to the system through cables. There are

various controls in the robot and the electronic system is designed to work in full manual

mode or semi-autonomous manual mode.

Various features of the manual robot are mentioned here:

ü Locomotion Module using Parallel H-Bridge Drive

ü Scissor Mechanism for Single or Half Bridge Part Gripping

ü Lead screw Mechanism for Gripping of two stacked Bridge Parts

ü Hoist Mechanism for Gripped Bridge Parts

ü Flap Mechanism for Reference and Bridge Completion

ü Signaling Mechanism for Intra robot Communication

ü Feedback Mechanisms using Limit Switches



Autonomous Robots:

There are three fully autonomous robots planned to operate in the automatic

machine zone. These three autonomous robots and their features are mentioned here:

Kuber – The Golden Gift Career:

This autonomous robot is designed to grip the Golden Gift placed at the center of

the automatic zone and carry it over the bridge to the Jiknyeo’s hands and accomplish the

reunion.

Various features of the robot are:

ü Line Following and Turning

ü Rotary Switch Feedback in Sweeper Mechanism

ü Vacuum Gripper Mechanism

ü Serial Interface for Program Modification

ü Status Monitoring Module using Serial Interface and LCD

Natraj – The Point Scoring Robot:

This autonomous robot is designed to gather one after another 11 gifts from

various places in the automatic zone into its helical structure and finally deploy the gifts

into the 1 point scoring bin and 2 point scoring bin in order to score points.



ü Rotary Switch Feedback Mechanism in the Rotating Center Shaft

ü Gift Intake and Gift Delivery Mechanism




ü Status Monitoring Module using Serial Interface and LCD

Ganesh – The Multipurpose Robot:

This autonomous robot is designed to be a multipurpose robot which could be

used as a test platform for testing of various programs as well as it could also be used to

perform tasks like gift pick n place and for defense against the attack from opponent’s

automatic robots.



ü Mechanism for Defense




SECTION 3

Function Description:

Various functions of the Semi-autonomous robot are described in the following part of

the section.

Locomotion Module Using Parallel H-Bridge Drive:

This is a very specific feature incorporated in the manual robot due to the high

current requirement of the motors. The Swiss make Faulhaber Motors used for the

locomotion module of the manual robot require high current of above 3 A per motor

where the limitation of the H-Bridge IC LMD18200 comes into picture. This IC could

withstand the maximum current of 3 A. Thus two such ICs have been paralleled in order

to provide the sufficient drive current to one motor without damaging the IC or the

circuitry. In this case the control signals and the supply signals to the IC are the same and

their outputs are connected so that the motors are supplied sufficient current for full high

speed drive.

Scissor Mechanism for Single or Half Bridge Part Gripping:

As per the game theme a total of six bridge parts are required by both the teams

for the completion of the bridge of both the teams but the available full bridge parts are

only five. Thus one of the team might have to use two half bridge parts for the

completion of the bridge gap.

Scissor Mechanism is specially designed for the same. It is capable to grip a

single bridge part or two half bridge parts individually. This mechanism is controlled

using rack n pinion motors used for the automatic door locks of the cars.



Lead screw Mechanism for Gripping of two stacked Bridge Parts:

The stacks of two bridge parts at the extremes of the manual machine common

zone would be used to fill up the remaining two gaps of the bridge. These two bridge

parts would be gripped using a gripper with lead screw mechanism that uses high torque

geared motors to rotate the lead screw and grip the stacked bridge parts.

Hoist Mechanism for Gripped Bridge Parts:

For hoisting the gripped single or half bridge parts thread and pulley are used

where the thread is attached with the high torque geared motor that pulls the thread and

the scissor mechanisms are hoisted along with the bridge part or parts.

Flap Mechanism for Reference and Bridge Completion:

The rotating flaps connected to the slow speed motors are provided on the rear

side of the robot in order to have the reference from the wall so that the bridge parts are

gripped at their centers of gravity as well as while the bridge parts are filled into the

bridge gaps they could be filled properly.

Signaling Mechanism for Intra robot Communication

The manual robot equipped with a signaling device so that when it completes the

bridge, it could signal the automatic robots to continue their tasks further. For the same

the a laser signaling device is mounted onto the robot which while signaling covers a

specific range of angle in order to send the signal to the automatic robot.



Feedback Mechanisms using Limit Switches

As mentioned the manual robot is planned to be semi-autonomous as well. For the

same purpose there are various limit switches mounted onto the robot at various places

which shall detect the positions of the moving parts of the robots such as hoist

mechanism, flaps etc. The on and off signals from the switches going to the

microcontroller shall automatically decide the next operation of the robot. In this case the

manual controller shall not have to control anything apart from the drive of the robot.

Various features of the autonomous robots are further discussed in the following part of

the section.

Line Following and Turning

The autonomous robots are required to perform their respective tasks without any

manual guidance. Thus the technique used to make the robots reach the desired locations

in order to perform their tasks is the white line following, cross detection and turning

technique using the optoelectronic sensors.

These optoelectronic sensors are actually developed during the project using light

to voltage converter IC – OPT101 and LED. These sensors work on the principle of

reflective light amplification. The IC – OPT101 comprised of a photodiode and amplifier.

The light of LED reflects from the surface and falls on to the OPT101 which is amplified

by the amplifier inbuilt the IC. The intensity of the light falling onto the photodiode of IC

depends upon the color of the surface. Thus while the sensor is on the white line it gives

the saturated output voltage where as while not on the white line it gives a low voltage.

This voltage is converted into a digital signal using an analog comparator IC TLC393



where the second input to the IC is a fixed voltage. Thus when the output voltage of the

sensor is below certain level i.e. when the sensor is not on white line it gives ‘0’ as the

output whereas if the output voltage of the sensor is above certain level i.e. when the

sensor is on the white line it gives ‘1’ as the output.

Using six such sensors divided into two rows on in front and one at the rear side

the white line following is achieved. To make the robot follow the white line various

sequences of the possible states of the sensors are considered and depending upon the

same, position of the robot and correction required in the proper direction is analyzed.

Finally on the basis of the required correction, PWM signal is applied to the H-Bridge

drive circuit which uses LMD18200T IC, and the straight line is followed by the robot.

For the motion of the robot high torque Maxon Motors are used with the gearbox having

1:18 ratio of gear reduction.

While the robot follows the white line it is also required for the robot to take 90

degree turn in certain direction. For the same the cross detection is used in which the

robot counts the number of crosses in the grid it passes and when this number matches

with the number of cross where it has to turn or stop, the robot stops the straight line

motion and the by rotating both the motors in the opposite directions it takes the turn in

the desired direction till the desired sensor in the front line of the sensors come onto the

white line.

Rotary Switch Feedback Mechanism

This is a very special feature introduced in the robots in order to reduce the

weight and complexity involved in implementing the stepper motors. This mechanism is

used wherever a part of the robot is desired to be rotated only till certain position is

achieved or only by certain angle.

In this mechanism the shaft of a 12 position rotary switch is coupled with the

rotating member of the robot so that the rotary switch also turns by the angle the rotating



member of the robot rotates. During the same process the position of the rotary switch is

read by the microcontroller and as per the program whenever the rotating element of the

robot reaches the desired position the pertaining position of the rotary switch is read and

the motor is stopped immediately.

Vacuum Gripper Mechanism

Vacuum Gripper is a unique feature incorporated in the golden gift carrying

autonomous robot. In this mechanism a vacuum gripper is used to pick up the golden gift

and this vacuum gripper is actuated using a lead screw mechanism. The prerequisite for

generating vacuum and gripping the gift is that the gripper tool should be in contact with

the surface to be gripped with sufficient pressure and to generate the same another lead

screw mechanism is used which brings the gripping surface of the gripper tool and the

surface of the gift to be gripped in contact with each other with sufficient pressure

required to generate vacuum and grip the gift.

Serial Interface for Program Modification and Status Monitoring

Serial Interface between the Microcontroller and the Computer is established in

order to update the microcontroller program as well as to monitor the status of various

sensors and switches etc. on the robot. This serial communication between the

microcontroller and the computer is done using the trial version of the Procomm

Software.

Serial communication allows the operator to monitor the status of various parts of

the robot especially sensors, limit switches etc. and accordingly verify the functioning of

the robot and its electronic circuitry. This also allows the operators to update the

microcontroller program very fast without detaching it from the circuit as the time

between the two games shall be very less and the program might be required to be

changed as per the change in the strategy for the game.



Status Monitoring using LCD

For the status monitoring purpose apart from the serial interface LCD also is used.

When the computer is not available nearby the testing area of the robot to monitor the

status of various sensors and limit switches mounted on the robots, LCD interface is used.



SECTION 4

HARDWARE

&

SOFTWARE



SOFTWARE

The software programs for the microcontroller have been developed

using Assembly Level Programming language. Microcontroller used in the

project is DS89C420 manufactured by Dallas Semiconductor which is 8052

based microcontroller. Thus for microcontroller software programming

Evaluation Version of Assembler – 8051IDE developed by AceBus has been

used to assemble, compile and simulate the software programs.

The benefit of using DS89C420 microcontroller is that it has a 16kb

of Flash Memory for programs, 1kb of RAM and 256 bytes of SRAM and

also for loading the program into the microcontroller flash memory self

developed serial programmer could be used and the programming is fast due

to flash memory. For loading the program from the computer to the

microcontroller through serial programmer the MTK – Microcontroller Tool

Kit developed by Dallas Semiconductors has been used.



LCD Interface

The LCD interface has been developed in order to monitor the status of various

components, sensors, switches on the robot as well as for microcontroller operation. The

test software for the 16x2 Matrix Intelligent LCD interface with microcontroller is shown

here.

;CONTROL LINES RS EQU P1.0 RW EQU P1.1 EN EQU P1.2 ;DATA PORT --> P3 ORG 0000 START: MOV SP,#80H LCALL PORTCONFIG LCALL READY MOV A,#'R' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'B' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'C' LCALL DISP MOV A,#'O' LCALL DISP MOV A,#'N'



LCALL DISP MOV A,#' ' LCALL DISP MOV A,#'2' LCALL DISP MOV A,#'0' LCALL DISP MOV A,#'0' LCALL DISP MOV A,#'4' LCALL DISP MOV A,#0C0H LCALL CMND MOV A,#'N' LCALL DISP MOV A,#'I' LCALL DISP MOV A,#'T' LCALL DISP PORTCONFIG: ;Configure required Ports as Input or Output MOV P1,#00H MOV P3,#00H RET READY: ;Initialize LCD to be Ready to operate CLR RS CLR RW LCALL CHK MOV A,#80H LCALL CMND MOV A,#01H LCALL CMND MOV A,#03H LCALL CMND MOV A,#3CH LCALL CMND MOV A,#3CH LCALL CMND MOV A,#0FH LCALL CMND MOV A,#06H LCALL CMND SETB RW SETB RS RET CMND: ;Send the Command LCALL CHK MOV P3,#00H MOV P3,A



CLR RS CLR RW SETB EN CLR EN RET DISP: ;Display Character LCALL CHK MOV P3,#00H MOV P3,A SETB RS CLR RW SETB EN CLR EN RET CHK: ;Check the Busy Flag CLR RS SETB RW MOV P3,#0FFH CNT: CLR EN SETB EN JB P3.7,CNT CLR EN MOV P3,#00H RET END



Serial Interface

The Serial Interface is found easier and more suitable for status monitoring as it

could also be used for program modification. Thus compared to LCD Serial Interface is

much more used for program modification and status monitoring purpose.

MSG DECODE1 DECODE2 DECODE3 RESPONSE HHH H H H 'THOR COMMUNICATIONS. LINK OK.' PWx PAGE WRITE NEW PAGE SET PAGESEL=NEW ADDR PRH PAGE READ DON'T CARE SEND CONTENTS OF PAGESEL XAx XRAM LOB WRITE ADDR DATA WRITE x TO PAGESEL+W. RXA READ XRAM LOB OF ADDRESS SEND CONTENTS OF PAGESEL+x SAx SRAM LOB WRITE ADDR DATA WRITE X TO SRAM LOCATION A RSA READ SRAM LOB OF ADDRESS SEND CONTENTS OF SRAM LOCATION A ANY OTHER MESSAGE 'COMMAND SYNTAX ERROR. TRY AGAIN' SAMPLE COMMUNICATION: HHH THOR COMMUNICATIONS. LINK OK HOI COMMAND SYNTAX ERROR. TRY AGAIN PW2 PRF Xa99 Sb88 RXa9 RSb8 HHH THOR COMMUNICATIONS. LINK OK HYU COMMAND SYNTAX ERROR. TRY AGAIN



Program ;DOCUMENTATION

;REGISTERS IN USE:

;R0 FOR COUNTING AND TRANSFERRING DATA

;T1 FOR TIMING THE 9600BPS COUNT

;ADDITIONAL ADDRESSES:

;CRITICAL ADDRESSES:

;#0160H, #0161H, #0162H FOR STORING COMMAND BEFORE PROCESSING

;#0163H, #0164H FOR STORING DPTR FOR ERR AND ACK MESSAGES

;NON-CRITICAL ADDRESSES:

;PAGESEL (41H), TEMP (42H)

;NON-CRITICAL BITS:

;ERR_ON (21H), ACK_ON (22H), P_WR (23H), VBCR (24H), VBLF (25H)

;START ADDRESS: 1000H

;END ADDRESS: 11FDH

;BYTES

PAGESEL EQU 41H

TEMP EQU 42H

;BITS

ERR_ON EQU 21H

ACK_ON EQU 22H

P_WR EQU 23H

VBCR EQU 24H

VBLF EQU 25H

ORG 0000H

LJMP INIT

ORG 0023H

LJMP SER_PROC

ORG 0100H



INIT: ;MASTER INIT ALGOL

MOV SP,#80H ;MASTER INIT DIRECTIVE

;>>>

LCALL SI_INIT ;CALL TO MODULE 'SERIAL INTERFACE'

;>>>

LJMP LOOPINF ;STANDARD IDLE LOOP

ORG 0120H

LOOPINF:

NOP

SJMP LOOPINF

ORG 1001H

MSG: DB 13,10,'THOR COMMUNICATIONS. LINK OK',13,10

ORG 1031H

MSG1: DB 13,10,'COMMAND SYNTAX ERROR. TRY AGAIN',13,10

ORG 1060H

SI_INIT: ;MODULE 'SERIAL INTERFACE'

ORL 0C4H, #03H ;ENABLE SRAM, LOCATION C4H BITS 0 AND 1

MOV PAGESEL,#00H

CLR ERR_ON

CLR ACK_ON

CLR VBCR

MOV R0, #60H

LCALL SER_INIT

RET

ORG 1078H

SER_INIT:

ANL SCON, #00H

SETB SCON.6 ;SCON.7,6=01 => MODE 1

SETB SCON.4 ;SCON.4=REN =>RECEIVER ENABLED



SETB SCON.3 ;SCON.3=1 =>STOP BIT =1

MOV TH1, #0FDH ;RELOAD SETTINGS FOR 9600BPS

ANL TMOD, #0FH ;CLEAR ALL BITS OF TMOD FOR TIMER1

ORL TMOD, #20H ;SET TIMER1 TO MODE 2 AUTORELOAD

SETB TR1 ;START TIMER1

ORL IE, #90H ;SET EA=1 AND ES0=1 TO ENABLE GLOBAL AND SERIAL0

INTERRUPTS

RET

ORG 1098H

SER_PROC:

JNB RI, TXINT

CLR RI

MOV A, SBUF ;LOAD RECEIVED DATA

MOV DPTR, #0160H;SAVE TO #0100H+[R0]

MOV DPL, R0

MOVX @DPTR, A ;SAVE TO XRAM

INC R0

MOV A, R0

CJNE A, #63H, KR ;SEE IF TOTAL 3 BYTE COMMAND HAS BEEN RECVD

LCALL PROC_CMD ;IF YES PROCESS COMMAND

KR: RETI ;ELSE OR THEN DO NOTHING

TXINT: CLR TI ;CLR THE TI INTERRUPT

JNB ERR_ON, TXT1

LCALL ERR_MSG

RETI

TXT1: JNB ACK_ON, TXT2

LCALL ACK_MSG

RETI

TXT2: JNB VBCR, TXT3

SETB VBLF

CLR VBCR

MOV SBUF, #0DH

RETI



TXT3: JNB VBLF, TXT4

CLR VBLF

MOV SBUF, #0AH

RETI

TXT4: MOV R0, #60H

RETI

ORG 10D8H

PROC_CMD:

MOV DPTR, #0160H

MOVX A, @DPTR

CJNE A, #48H, PCM1 ;'H'

INC DPTR

MOVX A, @DPTR

CJNE A, #48H, PCME ;'H'

INC DPTR

MOVX A, @DPTR

CJNE A, #48H, PCME ;'H'

SETB ACK_ON

CLR ERR_ON

MOV DPTR, #1001H

XRL A, A

MOVC A, @A+DPTR

MOV SBUF, A

LCALL SAV_DPTR

RET

PCM1: CJNE A, #50H, PCM2 ;'P'

INC DPTR

MOVX A, @DPTR

CJNE A, #57H, PCM1A ;'W'

SETB P_WR

LCALL PAGE_OPS

RET

PCM1A: CJNE A, #52H, PCME ;'R'



CLR P_WR

LCALL PAGE_OPS

RET

PCM2: CJNE A, #52H, PCM3 ;'R'

INC DPTR

MOVX A, @DPTR

CJNE A, #58H, PCM2A ;'X'

INC DPTR

MOVX A, @DPTR

MOV DPL, A

MOV DPH, PAGESEL

MOVX A, @DPTR

MOV SBUF, A

SETB VBCR

RET

PCM2A: CJNE A, #53H, PCME ;'S'

INC DPTR

MOVX A, @DPTR

MOV R0, A

MOV A, @R0

MOV SBUF, A

SETB VBCR

RET

PCM3: CJNE A, #58H, PCM4 ;'X' [WRITE XRAM]

INC DPTR

MOVX A, @DPTR

MOV TEMP, A

INC DPTR

MOVX A, @DPTR

MOV DPL, TEMP

MOV DPH, PAGESEL

MOVX @DPTR, A ;WRITE TO XRAM

MOVX A, @DPTR

MOV SBUF, A



SETB VBCR

RET

PCM4: CJNE A, #53H, PCME ;'S' [WRITE SRAM]

INC DPTR

MOVX A, @DPTR

MOV R0, A

INC DPTR

MOVX A, @DPTR

MOV @R0, A ;WRITE TO SRAM

MOV A, @R0

MOV SBUF, A

SETB VBCR

RET

PCME: CLR ACK_ON ;COMMAND SYNTAX ERROR SEQUENCE

SETB ERR_ON

MOV DPTR, #1031H ;ERR MSG LOCATION IS #1031H

XRL A, A

MOVC A, @A+DPTR

MOV SBUF, A

LCALL SAV_DPTR

RET

ORG 1168H

PAGE_OPS:

JNB P_WR, POP1 ;CHK IF IT IS PWRITE OR PREAD CMD

INC DPTR ;HERE IF PWRITE

MOVX A, @DPTR

CJNE A, #2FH, POP1A

LJMP POE

POP1A: JB CY, POP1B ;[A]>#2FH THEN NO BORROW=>PROCESS 30->33H

CJNE A, #34H, POP1C

LJMP POE

POP1C: JNB CY, POE ;[A]>#34H THEN NO BORROW=>ERROR

CLR CY



SUBB A, #30H ;HERE MEANS 2FH<[A]<34H

LJMP POP1E

POP1B: CJNE A, #04H, POP1D

LJMP POE

POP1D: JNB CY, POE ;[A]>#04H THEN NO BORROW=>ERROR

POP1E: MOV PAGESEL, A

POP1: MOV SBUF, PAGESEL

SETB VBCR

RET

POE: CLR ACK_ON

SETB ERR_ON

MOV DPTR, #1031H ;ERR MSG LOCATION IS #1031H

XRL A, A

MOVC A, @A+DPTR

MOV SBUF, A

RET

ORG 11A8H

ERR_MSG:

LCALL RD_DPTR

INC DPL

MOV A, DPL

CJNE A, #54H, EMX

CLR ERR_ON

MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION

RET

EMX: XRL A, A

MOVC A, @A+DPTR

MOV SBUF, A

LCALL SAV_DPTR

RET

ORG 11C4H

ACK_MSG:



LCALL RD_DPTR

INC DPL

MOV A, DPL

CJNE A, #21H, AMX

CLR ACK_ON

MOV R0, #60H ;!!!REQUIRED FOR FUTURE COMM RECEPTION

RET

AMX: XRL A, A

MOVC A, @A+DPTR

MOV SBUF, A

LCALL SAV_DPTR

RET

ORG 11E0H

SAV_DPTR:

MOV TEMP, DPH

MOV A, DPL

MOV DPTR, #0163H ;DPL IN #0163H AND DPH IN #0164H

MOVX @DPTR, A

INC DPTR

MOV A, TEMP

MOVX @DPTR, A

RET

ORG 11F0H

RD_DPTR:

MOV DPTR, #0163H

MOVX A, @DPTR ;RETRIEVE DPL

MOV TEMP, A ;SAVE TO TEMP

INC DPTR

MOVX A, @DPTR ;RETRIEVE DPH

MOV DPH, A ;LOAD DPH

MOV DPL, TEMP ;LOAD DPL

RET



White Line Following

As mentioned earlier in the report, straight line following for the white line has

been implemented for the autonomous robots in order to make them reach their desired

positions in the grid of automatic zone to perform their respective tasks automatically.

The test program for the same is included in the following part of the section. Here only

the test program is mentioned but the optimized version of the same with more features in

it also has been developed.

Program:

;BIT ALOCATIONS LDIR EQU P1.0 LDRV EQU P1.1 RDIR EQU P1.2 RDRV EQU P1.3 ORG 0000H LJMP START ORG 0100H START: LCALL PORTCONFIG SLF: MOV A,P2 CPL A MOV P3,A MOV A,P2 ANL A,#0FCH MOV R0,A MOV A,R0 CJNE A,#48H,NXT1 LJMP STRGHT NXT1: MOV A,R0 CJNE A,#4CH,NXT2 LJMP RGHT1 NXT2: MOV A,R0 CJNE A,#58H,NXT3 LJMP LEFT1 NXT3: MOV A,R0 CJNE A,#0CCH,NXT4



LJMP RGHT2 NXT4: MOV A,R0 CJNE A,#78H,NXT5 LJMP LEFT2 NXT5: MOV A,R0 CJNE A,#8CH,NXT6 LJMP RGHT3 NXT6: MOV A,R0 CJNE A,#38H,NXT7 LJMP LEFT3 NXT7: MOV A,R0 CJNE A,#0D8H,NXT8 LJMP RGHT4 NXT8: MOV A,R0 CJNE A,#98H,NXT9 LJMP RGHT5 NXT9: MOV A,R0 CJNE A,#6CH,NXT10 LJMP LEFT4 NXT10: MOV A,R0 CJNE A,#2CH,NXT11 LJMP LEFT5 NXT11: MOV A,R0 CJNE A,#64H,NXT12 LJMP RGHT6 NXT12: MOV A,R0 CJNE A,#0D0H,NXT13 LJMP LEFT6 NXT13: MOV A,R0 CJNE A,#90H,NXT14 LJMP RGHT4 NXT14: MOV A,R0 CJNE A,#24H,NXT15 LJMP LEFT4 NXT15: MOV A,R0 CJNE A,#80H,NXT16 LJMP LEFT7 NXT16: MOV A,R0 CJNE A,#10H,NXT17 LJMP RGHT8 NXT17: MOV A,R0 CJNE A,#20H,NXT18 LJMP RGHT7 NXT18: MOV A,R0 CJNE A,#04H,NXT19 LJMP LEFT8 NXT19: MOV A,R0 CJNE A,#00H,NXT20 LJMP DEFAULT NXT20: LJMP START



PORTCONFIG: MOV P1,#00H MOV P2,#0FFH MOV P3,#0FFH RET STRGHT: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#40H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT1: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#30H LCALL DLY SETB RDRV CLR LDRV MOV R1,#10H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT1: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#30H LCALL DLY CLR RDRV SETB LDRV MOV R1,#10H LCALL DLY



CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT2: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#2BH LCALL DLY SETB RDRV CLR LDRV MOV R1,#15H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT2: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#2BH LCALL DLY CLR RDRV SETB LDRV MOV R1,#15H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT3: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#26H LCALL DLY SETB RDRV



CLR LDRV MOV R1,#1AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT3: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#26H LCALL DLY CLR RDRV SETB LDRV MOV R1,#1AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT4: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#3AH LCALL DLY SETB RDRV CLR LDRV MOV R1,#06H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT4: SETB RDIR SETB LDIR SETB RDRV SETB LDRV



MOV R1,#3AH LCALL DLY CLR RDRV SETB LDRV MOV R1,#06H LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT5: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#33H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT5: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#33H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF



RGHT6: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#36H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF LEFT6: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#36H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0AH LCALL DLY CLR RDRV CLR LDRV MOV R1,#20H LCALL DLY LJMP SLF RGHT7: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#20H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#33H



LCALL DLY LJMP SLF LEFT7: SETB RDIR SETB LDIR SETB RDRV SETB LDRV MOV R1,#20H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#33H LCALL DLY LJMP SLF RGHT8: CLR RDIR CLR LDIR SETB RDRV SETB LDRV MOV R1,#23H LCALL DLY SETB RDRV CLR LDRV MOV R1,#0DH LCALL DLY CLR RDRV CLR LDRV MOV R1,#30H LCALL DLY LJMP SLF LEFT8: CLR RDIR CLR LDIR SETB RDRV SETB LDRV MOV R1,#23H LCALL DLY CLR RDRV SETB LDRV MOV R1,#0DH LCALL DLY



CLR RDRV CLR LDRV MOV R1,#30H LCALL DLY LJMP SLF

DEFAULT:

SETB RDIR SETB LDIR SETB RDRV SETB LDRV

MOV R1,#20H LCALL DLY CLR RDRV CLR LDRV

MOV R1,#40H LCALL DLY

LJMP SLF

DLY: MOV R2,#0FFH

DLYCNT: DJNZ R2,DLYCNT DJNZ R1,DLYCNT



HARDWARE

The hardware implementation in this project is done in a unique way. As the

robots and their design are very complex and the number of inputs and outputs of the

system may vary according to the requirements and change in strategy or design the

PCBs made for the robots are designed to be multipurpose such that the same circuits and

PCBs could be used for all the robots just with minute change and increase or decrease in

the number of components mounted on the PCB.

The Schematics of various circuits are included in the following part of this

section.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+

GREENYELLOWRED

24 V EXT

-

DESIGNER'S NOTES:D1 OF LISTENERLCD/AUX IS USEDFOR READING LCDBUSY FLAG. THEREST CAN BE USEDTO READ 7 OTHERINPUTS

VK.1 1.1

VISHWAKARMA MICROCONTROLLER CARD

A4

1 1Tuesday, April 06, 2004

Title

Size Document Number Rev

Date: Sheet of

SI.TXD

DRVAUXT.LS1DRVAUXT.LS2

LCDT.LS1LCDT.LS2

VCC

SI.RXD

SI.RXD

DRVAUXT.LS1DRVAUXT.LS2LCDT.LS1LCDT.LS2

HB12VT.LS1

HB12VT.LS1HB12VT.LS2

HB12VT.LS2

HMIL.LS3HMIL.LS2

LCDL.LS1

HMIL.LS1

HMIL.LS1

HMIL.LS2HMIL.LS3

HB12VL.LS1

HB12VL.LS1

LCDL.LS1

SI.TXD

AUXL.LS1

AUXL.LS1

DRVAXL.LS2DRVAXL.LS1


VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

J2 LISTENER DRVAX12345678910

D3

LED

D4

LED

J3 LISTENER HB12V12345678910

D5

LED

J1

POWER SUPPLY 1

12

U2

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

R322K

Y111.0592 Mhz

U3 7812/TO1 3

2

VIN VOUT

GN

D

R410K

R55K

C130pF

C230pF

PB

U4 7805/TO1 3

2

VIN VOUT

GN

D

J7 TALKER DRVAX123456789

101112

C710nF

J8 TALKER HB12V123456789

101112

J10 TALKER AUX123456789

101112

J9 TALKER LCD123456789

101112

C610uF

R1100E

J6 LISTENER AUX123456789

10

C410uF

J5 LISTENER LCD12345678910

R210K

C322uF

C52.2uF

D1 DIODED2 DIODE

J4 LISTENER HMI1234567891011121314

U1

DS89C420

2122232425262728 17

16

2930

1110

31

1918

9

3938373635343332

12345678

12131415

P2.0P2.1P2.2P2.3P2.4P2.5P2.6P2.7 P3.7

P3.6

PSENALE/P

P3.1P3.0

EA/VP

X1X2

RST

P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7

P1.0/T2P1.1/T2X

P1.2P1.3P1.4P1.5P1.6P1.7

P3.2P3.3P3.4P3.5

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

MASTER ON IS INPUTON 1ST 74LS373'S D0

23 OTHER INPUTS CANBE THEN READ INTOTHE MICROCONTROLLERUSING THE 3SELECTION LINES

GREEN

VK.4 1.1

VISHWAKARMA HUMAN MACHINE INTERFACE CARD

A4


Title


Date: Sheet of

HMIT.LS3

SPH.DR.TOGGLE

HMIT.LS1

DPG2.TOGGLE

FLAP.TOGGLE

GG.PSHLOCKBUTTON

DPG1.TOGGLE

DIRNCONTROL.LFT.PBDIRNCONTROL.RGT.PB

MASTERON.TOGGLEAUTOMODE.EN.TOGGLE

SPG2.PUSHBUTTONSPG1.PUSHBUTTON

HMIT.LS3

HMIT.LS1DIRNCONTROL.FWD.PBDIRNCONTROL.REV.PB

SIGNAL.PUSHBUTTON

HMIT.LS2HMIT.LS2

GAH.DR.TOGGLE

DPH.ON.TOGGLE

GAH.ON.TOGGLE

SPH.ON.TOGGLE

DPH.DR.TOGGLE

SPEEDCONTROL.SLIDER2SPEEDCONTROL.SLIDER1

VCC

VCC

VCC

VCC

VCC

VCC

J1INTERFACE BUTTONS LANDER

123456789101112131415161718192021222324

D1

LED

J3POWER OUT

12345678910

R1

RESISTOR SIP 10 [10K]

12 3 4 5 6 7 8 9 10

U3

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

J2TALKER

123456789

1011121314

R35K1

R2

10K

U1

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

U2

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LAYOUT CAUTION NOTES:

POWER HEADER , AUX MOTORS HEADER ANDDRV MOTORS HEADER SHOULD BE RATED TOCARRY 10A [MAX]

CHECK FOR CONNECTIONS OF 74LS08 AND74LS373 TO 5V AND NOT TO 24V

DESIGNER NOTES:

Q4 IS INVERTED O/P OF Q5[MASTER ON]

GIFT GRIPPER[GG]

SINGLE PART HOIST[SPH]

DOUBLE PART HOIST[DPH]

GIFT ARM HOIST[GAH]

VK.2 1.0

VISHWAKARMA DRIVE CONTROL & AUXILIARY MOTOR CARD

A3


Title


Date: Sheet of

R.DR

MASTER.ON

L.ONMASTER.IND

L.DR

RM.ON

RM.DR

RM.DR

RM.DR

R.BR

RM.ON

RM.M1

RM.M1

LM.ON

LM.M1

LM.ON

LM.M1

LM.DR

LM.DRLM.ON

LM.M1

LM.M2

LM.M2

LM.M2

RM.M2

RM.M2

RM.M2

L.BR

R.ON

SPH.DR

SPH.DR

GAH.DR

GAH.M1

SPH.M1

SPH.M1

DPH.M1DPH.M2

DPH.M1

GG.M2GG.M1

GG.M2

LM.DR

RM.M1

RM.ON

SPH.M2

SPH.M2

DPH.M2

GAH.M2

GAH.M2

GAH.M1 GG.M1

MASTER.ON

MASTER.ON

MASTER.ON


DRVAXL.LS2

DRVAXL.LS1

SPH.ON

SPH.ONDPH.DR

GAH.DR

SPH.LOWSPH.HGH

DRVAXT.LS1

GG.OL

GAH.LOWDPH.HGH

GAH.HGH

DPH.LOW

GG.CLDRVAXT.LS2

RG1RG2

GG.ON

GG.DRGG.ON

GG.DR

MASTER.ON

DPH.ON

GAH.ON

DPH.DRDPH.ON

GAH.ON

24V

VCC

VCC

24V

24V

24V

24V

24V

24V

24V

24VVCC

VCC

VCC

VCC

U13C

74LS08

9

108

U13B

74LS08

4

56

U13A

74LS08

1

23

U13D

74LS08

12

1311

R3

RESISTOR SIP 101

2 3 4 5 6 7 8 9 10 U9

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

D1 LED

D2

LED

R1

10K

R4RESISTOR SIP 10

1

2 3 4 5 6 7 8 9 10R222K

C1

10nF

U3 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKEC2

10nF

C171000uF

U6 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

U10

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

U1 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE C10

10nF

C910nF

J7AUX MSW LANDER

123456789101112

U7 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C1310nF

U2 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE C14

10nF

U8 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

U5 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE C12

10nF

C1110nF

J3

AUX MOTORS

12345678

U14A

74LS08

1

23

U14B

74LS08

4

56

J6MSW LANDER

123456789101112

U4 LMD18200T

2

10

9

1

11

8

67

35

4

OUT1

OUT2

TH OUT

BS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE C16

10nF

C1510nF

U14C

74LS08

9

108

J4LISTENER

123456789101112

U14D

74LS08

12

1311

U12

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

J2

DRV MOTORS

1234

C3

10nF

C4

10nF

C5

10nF

C6

10nF

C8

10nF

J5TALKER

123456789

10

U11

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

J1

POWER HEADER

12

C7

10nF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

SG22

SG21

SG12

SG11

F2

G2

G1

LAYOUT CAUTION NOTES:1.) RELAY [K1] SHOULD BE 5AMP/CONTACT TYPE2.) THE 12V POWER HEADER [J1] SHOULD BE ABLE TO SOURCE 10AMP [MAX VALUE]3.) MOTORS OUT HEADER [J6] SHOULD BE ABLE TO SUPPLY 1A/PIN [MAX VALUE]4.) ALL BYPASS CAPACITORS SHOULD BE AS CLOSE TO THEIR RESPECTIVE LMD18200sAS POSSIBLE.5.) ALL ELECTROLYTIC CAPS ARE RATED AT 16/25V

DESIGNER NOTES:

Q4 IS INVERTED O/P OF Q5[MASTER ON] [U12]

LSR

F1

A3 VK.3 1.1

VISHWAKARMA 12V H-BRIDGE BOARD

1 1Wednesday, April 14, 2004

Title


Date: Sheet of

SG1.OL

SG2.ON

F2.ON F2.ON

SG2.ONSG2.DR

SG1.DR

SG2.DR

F2.DR F2.DR

SG2.OL

HB12VL.LS1HB12VL.LS2

MASTER.ON

F1.2F2.1

G1.OLF2.2F2.1

G1.STL

G2.STL

F1.1

G2.STL

G1.STL

G1.OL

F1.1

G2.OL G2.OL

F1.2

F2.2

HB12VT.LS1HB12VT.LS1

LSR.DRV

LSR.DRV

LSR.EN

LSR.EN

F1.DR

F1.M2

F1.DRF1.ON

F1.ON

G1.DR

MASTER.IND

G1.DR

SG1.ON

SG1.ON

SG22.M2

LSR.M2

G1.M2

LSR.M1

G2.M1

SG22.M2

LSR.AN

SG21.M1

SG22.M1SG12.M2

SG11.M1

F2.M1

SG12.M2

SG11.M1F2.M2

F1.M2

LSR.CT

F2.M2

SG21.M1

SG12.M1

SG11.M2

F1.M1

F2.M1

SG21.M2

SG21.M2

SG22.M1

SG12.M1

SG11.M2

F1.M1

SG1.DR

LSR.M2

LSR.M1

G2.M1

G1.M2

G1.M1

G1.M1

G2.M2

G2.M2

G1.ON

G1.ONG2.DRG2.ON

G2.DRG2.ON

12V

12V

12V

12V

12V EXT

12V

12V

VCC

12V EXT12V EXT

12V

12V

12V

VCC

VCC

12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC

C4

10uF

C14 10nF

C20 10nF

D5DIODE

R6R

J2MSW LANDER

123456789

101112

J4

LISTENER

123456789

101112

D3

LED

C2710nF

K1

RELAY DPDT

34

5

68

712

J1

12V POWER

12

U7 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

R8R

J3

TALKER

12345678910

C1310nF

Q12N2222

U12

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

C1710nF

U13B

74LS86

4

56

C5

10uF

U13A

74LS86

1

23

R7R

C

R4

RESISTOR SIP 10 [10K]12 3 4 5 6 7 8 9 10

C28 10nF

C3

10uF

U4 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

-

+U14A

TLC393

3

21

U10

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

OELE

Q0Q1Q2Q3Q4Q5Q6Q7

U1 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C24 10nF

U6 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C10 10nF

C8

10uF

C18 10nF

D1

LED C25100uF

C16 10nF

C2

10uF

C7

10uF

R1R

U2 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C2310nF

C910nF

C12 10nF

D4

LED

C1510nF

C1

10uF

U5 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C1110nF

R10

10E

U3 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

U8 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

C22 10nF

R2R

C6

10uF

-

+U14B

TLC393

5

67

R3R

C1910nF

Q22N2222

C26

10uF

C2110nF

D2LED

J6MOTORS OUT

123456789

1011121314151617181920

R9

5K1

U9 LMD18200T2

10

91

11

8

67

35

4

OUT1

OUT2

TH OUTBS1

BS2

CS OUT

VC

CG

ND

DIRPWM

BRAKE

R522K

U11

74LS373

3478

13141718

111

256912151619

D0D1D2D3D4D5D6D7

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Q0Q1Q2Q3Q4Q5Q6Q7

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DIG.1

Digitizer

A4

1 1Monday, May 10, 2004

Title


Date: Sheet of

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

-

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RESISTOR SIP 912 3 4 5 6 7 8 9

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RESISTOR SIP 9 123456789

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J5

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12345678

R4

R8

Q1

2N2222

R10

-

+U8A

3

21

Q4

-

+U9A

3

21

R18

R6

-

+U3B

TLC393

5

67

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5

67

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8 HEADER

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+

C1

U1UA7805/SOT

1

2

3IN

GN

D

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J8

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12345678

J6

8 HEADER

12345678

R3

J1

HEADER 14

123456789

1011121314

R7

R2

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TLC393

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TLC393

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3

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111

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D0D1D2D3D4D5D6D7

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Q2

+

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HEADER 2

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3

21



SECTION 5

Heuristics Design and Development: This whole project in itself has been a mammoth task to complete within a short

time of five months during which the A to Z of the project was supposed to be designed

and developed physically in reliable and working conditions. Due to the same reason a lot

of research oriented activity, new ideas and heuristics designing has been done in order to

minimize efforts, time and at the same time gain more efficiency. In the same process

implementation of certain concepts mentioned below have played and important role in

the formation of this project.

ü Optoelectronic Sensor using OPT101 and LED

ü Multipurpose Schematics and PCB Designs

ü Serial Interface for Status Monitoring and Program Updating

ü LCD interface for Status Monitoring

Optoelectronic Sensor using OPT101 and LED

Using the combination of PDIP IC – OPT101 and LED with the concept of

reflective light amplification as the Optoelectronic sensor has been a totally new

development at student level. This development has been specially beneficial as the

weight constituted by the sensors is much lesser then the commercially available ready

made sensors and also if the sensor fails it is very easy to change the IC or even the

whole set up to make the system working again.



Multipurpose Schematics and PCB Designs

The Schematics and PCB Designs of the Electronic Circuits have been done such

that the PCBs are multipurpose and just with the minute change in the number of

components mounted on the PCB and some change in the interconnections between the

PCBs, they could be used for all the robots. In fact the PCBs are made such that in most

of the general robotic applications these PCBs could be used.

The robotic systems are MIMO – Multi Input Multi Output Systems and the Set

of PCBs is made so flexible that it could be used for sensing 64 Inputs as well as for

sending 48 output signals.

Serial Interface for Status Monitoring and Program Updating

Loading the microcontroller again and again with minute changes in the program

is always a time taking process especially while testing the programs. At the same time

when the program is not performing as per the desire it is necessary to find the flaw in the

program which is possible by monitoring various RAM locations, Registers,

Microcontroller Ports, and Individual Bits etc. on the microcontroller.

Implementing Serial Interface is the solution to both these problems as the

program in the microcontroller could be quickly updated using Serial Interface and at the

same time monitoring status of various memory locations and ports etc. become easy

using the serial communication.

LCD interface for Status Monitoring

Monitoring status is difficult where the serial communication between PC and

microcontroller is not easy as the PC is not nearby. In this case the LCD is interfaced

with the microcontroller in order to monitor the status and debug the program.

________________________________________________________________________ Maxim Integrated Products 1

SECTION 1: INTRODUCTION

Ultra-High-Speed FlashMicrocontroller User’s Guide

DUAL DATAPOINTERS

WITH AUTO-SELECT

INCREMENT/DECREMENT

DUAL SERIALPORTS

HIGH-SPEEDONE CLOCK-CYCLE

8051 MICROPROCESSOR

16kBFLASH MEMORY

1kBSRAM

FOUR8-BIT

PARALLELPORTS

1

5

25

0

33

DS89C420ORIGINAL

8051

MIP

S

DS89C420

Dallas Semiconductor’s DS89C420 is an 8051-compatible micro-controller that provides improved performance and power con-sumption when compared to the original 8051 version. It retainsinstruction set and object code compatibility with the 8051, yetperforms the same operations in fewer clock cycles.Consequently, greater throughput is possible for the same crys-tal speed. As an alternative, the DS89C420 can be run at areduced frequency to save power. The more efficient designallows a much slower crystal speed to get the same results as anoriginal 8051, using much less power.

The fundamental innovation of the DS89C420 is the use of onlyone clock per instruction cycle compared with 12 for the original8051. This results in up to 12 times improvement in performanceover the original 8051 architecture and up to four times improve-ment over other Dallas Semiconductor high-speed microcon-trollers. The DS89C420 provides several peripherals and featuresin addition to all of the standard features of an 80C32. Theseinclude 16kB of on-chip flash memory, 1kB of on-chip RAM, four 8-bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dualdata pointers, an on-chip watchdog timer, five levels of interrupt

priority, and a crystal multiplier. The device provides 256 bytes ofRAM for variables and stack; 128 bytes can be reached usingdirect or indirect addressing, or using indirect addressing only.

In addition to improved efficiency, the DS89C420 can operate ata maximum clock rate of 33MHz. Combined with the 12 times per-formance, this allows for a maximum performance of 33 millioninstructions per second (MIPs). This level of computing power iscomparable to many 16-bit processors, but without the addedexpense and complexity if implementing a 16-bit interface.

The DS89C420 incorporates a power-management mode thatallows the device to dynamically vary the internal clock speedfrom 1 clock per cycle (default) to 1024 clocks per cycle. Becausepower consumption is directly proportional to clock speed, thedevice can reduce its operating frequency during periods of littleswitchback. This greatly reduces power consumption. The switch-back feature allows the device to quickly return to highest speedoperation upon receipt of an interrupt or serial port activity, allow-ing the device to respond to external events while in power-man-agement mode.


_____________________________________________________________________________________________ 10

REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0P0 80h P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0SP 81hDPL 82hDPH 83hDPL1 84hDPH1 85hDPS 86h ID1 ID0 TSL AID — — — SELPCON 87h SMOD_0 SMOD0 OFDF OFDE GF1 GF0 STOP IDLETCON 88h TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0TMOD 89h GATE C/T M1 M0 GATE C/T M1 M0TL0 8AhTL1 8BhTH0 8ChTH1 8DhCKCON 8Eh WD1 WD0 T2M T1M T0M MD2 MD1 MD0P1 90h P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0EXIF 91h IE5 IE4 IE3 IE2 CKRY RGMD RGSL BGSCKMOD 96h T2MH T1MH T0MHSCON0 98h SM0/FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0SBUF0 99hACON 9Dh PAGEE PAGES1 PAGES0P2 A0h P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0IE A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0SADDR0 A9hSADDR1 AAhP3 B0h P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0IP1 B1h — MPS1 MPT2 MPS0 MPT1 MPX1 MPT0 MPX0IP0 B8h — LPS1 LPT2 LPS0 LPT1 LPX1 LPT0 LPX0SADEN0 B9hSADEN1 BAhSCON1 C0h SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1SBUF1 C1hROMSIZE C2h PRAME RMS2 RMS1 RMS0PMR C4h CD1 CD0 SWB CTM 4X/2X ALEON DME1 DME0STATUS C5h PIS2 PIS1 PIS0 — SPTA1 SPRA1 SPTA0 SPRA0TA C7hT2CON C8h TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2T2MOD C9h — — — — — — T2OE DCENRCAP2L CAhRCAP2H CBhTL2 CChTH2 CDhPSW D0h CY AC F0 RS1 RS0 OV F1 PFCNTL D5h FBUSY FERR FC3 FC2 FC1 FC0FDATA D6hWDCON D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWTACC E0hEIE E8h — — — EWDI EX5 EX4 EX3 EX2B F0hEIP1 F1h MPWDI MPX5 MPX4 MPX3 MPX2EIP0 F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2

Note: Shaded bits are timed-access protected.

DS89C420 Special-Function Register Locations


_____________________________________________________________________________________________ 28

LPX0 Least Significant Priority Select Bit for External Interrupt 0. MPX0 is the least significant bit ofBit 0 the bit pair MPX0 (IP1.0), LPX0 that designates priority level for external interrupt 0.

Bits 7–3 These bits are reserved. Read data is 1.

PRAME Program RAM Enable. When set (= 1), the internal 1k RAM is mapped as internal program Bit 3 space between addresses 0400h–07FFh. All program fetches and MOVC accesses are directed

to this 1k RAM. When serving as program memory, the RAM continues to be accessible as MOVX data space (if DME0 = 1). The 1k RAM is not accessible as program space when EA = 0. When clear (= 0), the internal 1k RAM is not accessible as program space.

RMS2–0 ROM Memory Size Select 2-0. This register is used to select the maximum on-chip decoded Bits 2–0 address. Care must be taken that the memory location of the current program counter is valid

both before and after modification. These bits can only be modified using a timed-access procedure.The EA pin overrides the function of these bits when asserted, forcing the device to access externalprogram memory only. Configuring this register to a setting that exceeds the maximum amount of internal memory can corrupt device operation. These bits default on reset to the maximum amount of internal program memory (i.e., 16k for DS89C420).On-Chip ROM Address

CD1, CD0 Clock Divide Control 1-0. These bits select the number of crystal oscillator clocks required to Bits 7, 6 generate one machine cycle. Switching between modes requires a transition through the default

divide-by-1 mode (CD1, CD0 = 10b). Attempts to perform an invalid transition are ignored. For example, going from the crystal multiplier 2X mode to the divide-by-1024 mode would require firstswitching from the 2X crystal multiplier mode to the divide-by-1 mode, followed by the switch fromthe divide-by-1 to the divide-by-1024 mode. These bits cannot be modified when running from theinternal ring oscillator (RGMD = 1). The divide-by-1024 setting (CD1,CD0 = 11b) cannot be selectedwhen switchback is enabled (SWB = 1) and a switchback source (serial port or external interrupt)is active.

The setting of these bits affects timer and serial port operation. Tables located in the SFR decription for CKCON (8Eh) detail the respective operational dependencies on these bits.

CD1,CD0 CLOCK FUNCTION

00 Crystal multiplier (4X or 2X mode as determined by PMR.3)01 Reserved (forced into divide-by-1 mode if set)10 Divide-by-1 (default state)11 Divide-by-1024

.RS2 RS1 RS0 MAXIMUM ON-CHIP ROM ADDRESS

0 0 0 0kB/Disable on-chip ROM0 0 1 1kB/03FFh0 1 0 2kB/07FFh0 1 1 4kB/0FFFh1 0 0 8kB/1FFFh1 0 1 16kB/3FFFh (default)1 1 0 32kB/7FFFh1 1 1 64kB/FFFFh

7 6 5 4 3 2 1 0SFR C2h — — — — PRAME RMS2 RMS1 RMS0

R-1 R-1 R-1 R-1 RT-0 RT-1 RT-0 RT-1R = Unrestricted read, W = Unrestricted write, T = Timed-access write only, -n = Value after reset

ROM Size Select (ROMSIZE)

7 6 5 4 3 2 1 0SFR C4h CD1 CD0 SWB CTM 4X / 2X ALEON DME1 DME0

RW*-1 RW*-0 RW-0 RW*-0 RW*-0 RW-0 RW-0 RW-0

R = Unrestricted read, W = Unrestricted write, -n = Value after reset, * = See description

Power Management Register (PMR)


53 _____________________________________________________________________________________________

UHSM UHSM 8051 8051 UHSM vs.

HEX CLOCK TIME CLOCK TIME 8051 SPEED

INSTRUCTION CODE CYCLES @ 25MHz CYCLES @ 25MHz ADVANTAGE

CJNE A, #data, rel B4 4 160 ns 24 960 ns 6

CJNE Rn, #data, rel B8..BF 4 160 ns 24 960 ns 6

CJNE @Ri, #data, rel B6..B7 5 200 ns 24 960 ns 4.8

DJNZ Rn, rel D8..DF 4 160 ns 24 960 ns 6

DJNZ direct, rel D5 5 200 ns 24 960 ns 4.8

NOP 00 1 40 ns 12 480 ns 12

Table 5-2. INSTRUCTION SPEED SUMMARY

SECTION 6: MEMORY ACCESSThe DS89C420 ultra-high-speed microcontroller supports the memory interface convention established for the industry standard80C51, but also implements two new page mode memory interfaces needed to support ultra-high-speed external operation. Theseexternal page mode interfaces are described later in this section.

INSTRUCTION CATEGORY SPEEDADVANTAGE QUANTITY

Total instructions: 1 byte 4.0 24.8 15.3 16.0 128.0 512.0 2724.0 1

Total instructions: 2 byte 4.0 16.0 278.0 512.0 13

Total instructions: 3 byte 4.8 36.0 58.0 8

Average across all instructions 8.5 111

OPCODE CATEGORYSPEED

ADVANTAGE QUANTITY

Total opcodes: 1 byte 4.0 44.8 15.3 16.0 358.0 512.0 9324.0 1

Total opcodes: two byte 4.0 16.0 428.0 512.0 43

Total opcodes: three byte 4.8 46.0 128.0 8

Average across all opcodes 9.4 255


_____________________________________________________________________________________________ 54

Program and data memory areas can be implemented on-chip, off-chip, or as a combination. When opting not to use the internal mem-ory provided, or when exceeding the maximum address of on-chip program or data memory, the device performs an external mem-ory access using the expanded memory bus on ports 0 and 2. While serving as a memory bus, port 0 and port 2 cannot function asI/O ports. The PSEN signal is driven active low to function as a chip enable or output enable when performing external code memoryfetches. The RD and WR signals serve as enables when accessing external SRAM data memory.

Program execution always begins at the reset vector, address 0000h. If on-chip program memory is enabled, program executionbegins at internal location 0000h; otherwise, external program memory is used. Any reset causes the next program fetch to begin atthis location. Subsequent branches and interrupts determine how program memory fetches deviate from sequential addressing.

INTERNAL FLASH MEMORYThe DS89C420 ultra-high-speed microcontroller contains five physically distinct blocks of embedded flash memory. The two largestblocks, each 8kB, provide a total of 16kB for use as internal program memory. A 64-byte flash security block has been incorporatedto allow encryption during program memory verify operations. To further protect internal code against undesirable access, a three-levellock system has been implemented in a separate flash memory block. This single-byte block contains three lock bits (LB1, LB2, LB3),each of which can individually enable higher lock levels and greater code protection. The fifth flash memory block resident to theDS89C420 is the option control register. This byte contains a bit to enable or disable the watchdog timer reset function (EWT =WDCON.1) on a power-on reset.

The two 8kB program memory blocks form a contiguous 16kB address range extending from 0000h through 3FFFh. The on-chipdecoded address range is controlled in hardware by the EA pin, and in software through the ROMSIZE feature. The EA pin enables ordisables the ability to access internal program memory and overrides any software configured bit settings. The logic state of the EApin should be changed only when the microcontroller is being held in reset. The EA pin is sampled on each exit from the reset state todetermine whether program fetching should begin internally or externally. When the EA pin is low, all code fetches are done external-ly through the expanded bus. When the EA pin is high, code fetches begin from internal program memory. Code fetches exceedingthe maximum address of on-chip program memory cause the device to access off-chip program memory. The maximum on-chipdecoded address is selectable by software using the ROMSIZE feature.

ROMSIZE FEATUREUsing the ROMSIZE feature, software can allow the DS89C420 to behave like a device with less on-chip memory. The maximum mem-ory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, thenrestored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64kBof external memory space to be addressed.

The ROMSIZE feature has two primary uses. In the first instance, it allows the device to act as a bootstrap loader for a flash memoryor nonvolatile SRAM (NVSRAM). The internal program memory can contain a bootstrap loader, which can program the external mem-ory device. Secondly, this method can be used to increase the amount of available program memory from 64kB to 80kB without bankswitching.

The maximum amount of on-chip memory is selected by configuring the ROM size select register bits RMS2, RMS1, RMS0 (ROM-SIZE.2-0). The reset default condition gives access to the maximum on-chip program memory of 16kB. In this configuration, only codeaddresses greater than 16kB result in external program memory accesses. The possible settings for the ROM size select register areshown in the following table.

Table 6-1. ROMSIZE REGISTER SETTINGS

Modification of the ROMSIZE (C2h) special function register requires using the timed access procedure and must be followed by a twomachine cycle delay, such as executing two NOP instructions, before jumping to the new address range. Interrupts must be disabledduring this operation, because a call to an interrupt vector during the changing of the memory map can cause erratic results. To select

RMS2 RMS1 RMS0 MAX ON-CHIP PROGRAM MEMORY0 0 0 0kB0 0 1 1kB (0-03FFh)0 1 0 2kB (0-07FFh)0 1 1 4kB (0-0FFFh)1 0 0 8kB (0-1FFFh)1 0 1 16kB (0-3FFFh) DEFAULT1 1 0 INVALID – RESERVED1 1 1 INVALID – RESERVED


_____________________________________________________________________________________________ 56

the watchdog reset function automatically. Other bits of this register are undefined and are at logic 1 when read. The value of this reg-ister can be read at address FCh in parallel programming mode or by executing the verify option control register instruction in ROMLoader or in-application programming mode.

INTERNAL SRAM MEMORYThe DS89C420 ultra-high-speed microcontroller incorporates an internal 1kB SRAM that is usable as data, program, or merged pro-gram/data memory. Upon a power-on reset, the internal 1kB memory is disabled and transparent to both program and data memorymaps.

When used for data, the memory is addressed through MOVX commands, and is in addition to the 256 bytes of scratchpad memory.To enable the 1kB SRAM as internal data memory, software must set the DME0 bit (PMR.0). After setting this bit, all MOVX accesseswithin the first 1kB (0000h–03FFh) is directed to the internal SRAM. Any data memory accesses outside of this range are still directedto the expanded bus. One advantage of using the internal data memory is that MOVX operations automatically default to the fastestaccess possible. Note that the DME0 bit is cleared after any reset, so access to the internal data memory is prohibited until this bit ismodified. The contents of the internal data memory are not affected by the changing of the data memory enable (DME0) bit. Table 6-3 shows how the DME1, DME0 bits affect the data memory map.

ExternalData

Memory

8kB x 8

Flash Memory

(Program)

1kB x 8SRAM

Data ORprog mem addr from 400–7FF

128 BytesIndirect

Addressing

Bit Addressable

Bank 3Bank 2Bank 1Bank 000

1F202F

7F80

128 Bytes SFR

FF

0000

1FFF

2000

3FFF

INTERNALMEMORY

03FF

0000

FFFF FFFF

4000

00000000

03FF

ExternalProgramMemoryINTERNAL

REGISTERS

8kB x 8Flash

Memory(Program)

SCRATCHPAD

Note: The hatched areas shown on the internal and external memory are disabled on power-up (Default)

Non-usable if Internal SRAM is activated

Figure 6-1. Memory Map


When serving as an I/O port, the drive varies as follows: for logic 0, the port invokes a strong pulldown; for logic 1, the port invokes astrong pullup for two oscillator cycles to assist with the logic transition. Then the port reverts to a weak pullup. This weak pullup is main-tained until the port transitions from logic 1 to logic 0. External circuits can overdrive the weak pullup. This allows the logic 1 outputstate to serve as the input state as well.

Substantial DC current is available in both the high and low levels. However, the power dissipation limitations make it inadvisable to heav-ily load multiple pins. In general, sink and source currents should not exceed 10mA total per port (8 bits) and 25mA total per package.

Input FunctionsThe input state of the I/O ports is the same as that of the output logic 1. That is, the pin is pulled weakly to logic 1. This logic 1 state iseasily overcome by external components. Thus, after software writes a 1 to the port pin, the port is configured for input. When the portis read by software, the state of the pin is read. The only exception is the read-modify-write instructions, discussed earlier. If the exter-nal circuit is driving logic 1, then the pin is logic 1. If the external circuit is driving logic 0, then it overcomes the internal pullup. Thus,the pin is the same as the driven logic state. Note that the port latch is not altered by a read operation. Therefore, if logic 0 is drivenonto a port pin from an external source, then removed, the pin reverts to the weak pullup, as determined by the internal latch.

SECTION 11: PROGRAMMABLE TIMERSThe ultra-high-speed microcontroller incorporates three 16-bit programmable timers and has a watchdog timer with a programmableinterval. Because the watchdog timer is significantly different from the other timers, it is described separately. The 16-bit timers arereferred to as timers.

The three timers offer the same controls and I/O functions that were available in the 80C32. As mentioned, the actual timing of these func-tions is user selectable to be compatible with the instruction cycle of the older generation of 8051 family (12 clocks per tick) or the newgeneration (1 clock per tick). The timing for each of the three timers can be selected independently and can be changed dynamically.

In most modes, the timers can be used as either counters of external events or timers. When functioning as a counter, 1 to 0 transi-tions on a port pin are monitored and counted. When functioning as timers, they effectively count oscillator or system clock cycles. Thetime base for the timer function is detailed later in this section. Because an input clock pulse must be sampled high for two systemclock cycles and low for two system clock cycles in order to be recognized, this sets the maximum sampling frequency on any timerinput at one-fourth of the main system clock frequency.

Since the ultra-high-speed microcontroller timers have a variety of features, the following lists summarize the capabilities:

Timer 0 Timer 1 Timer 2

13-bit timer/counter 13-bit timer/counter 16-bit timer/counter

16-bit timer/counter 16-bit timer/counter 16-bit timer with capture

8-bit timer w/ autoreload 8-bit timer w/ autoreload 1 6-bit autoreload timer/counter

Two 8-bit timer/counters External control pulse timer/counter 16-bit up/down autoreload

External control pulse timer/counter Baud-rate generator Timer/counter

Baud-rate generator

Timer output clock generator

16-BIT TIMERSTimers 0 and 1 are nearly identical. Timer 2 has several additional features such as up/down counting, capture values, and an option-al output pin that make it unique. The following table summarizes the SFR bits that control operation of timers 0, 1, and 2. Detailed bitdescriptions can be found in Section 4. After the table, timers 0 and 1 are described first, followed by a separate description for timer2. As mentioned above, the time base for each timer can be varied, which is discussed in more detail in the following pages.

_____________________________________________________________________________________________ 96

TIMER 0, TIMER 1 MODESTimers 0 and 1 both have three common operating modes. They are 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counterwith autoreload. Timer 0 can additionally be configured to operate as two 8-bit timers. These four modes, controlled by the TMOD reg-ister, are detailed in the following pages.

MODE 0Mode 0 configures either timer 0 or timer 1 for operation as a 13-bit timer/counter. As shown in Figure 11-1, setting TMOD register bitsM1, M0 = 00b selects this operating mode for either timer 0 or timer 1.

When using timer 0, TL0 uses only bits 0 through 4. These bits serve as the 5 LSbs of the 13-bit timer. TH0 provides the 8 MSbs of the13-bit timer. Bit 4 of TL0 is used as a ripple out to TH0 bit 0, thereby completely bypassing bits 5 through 7 of TL0. Once the timer isstarted using the TR0 (TCON.4) timer enable, the timer counts as long as GATE (TMOD.3) is 0 or GATE is 1 and pin INTO is 1. It countsoscillator or system clock cycles if C/T (TMOD.2) is set to a logic 0 and 1 to 0 transitions on T0 (P3.4) if C/T is set to a 1. When the 13-bit count reaches 1FFFh (all ones), the next count causes it to roll over to 0000h. The TF0 (TCON.5) flag is set and an interrupt occursif enabled. The upper 3 bits of TL0 are indeterminate.


97 _____________________________________________________________________________________________

BIT NAMES DESCRIPTION REGISTER LOCATION BIT POSITIONSGATE Gate control enable for INTO pin TMOD – 89h TMOD.3C/T Counter/timer select TMOD – 89h TMOD.2

M1, M0 Timer mode select bits TMOD – 89h TMOD.1,0TF0 Timer overflow flag TCON – 88h TCON.5TR0 Timer run control TCON – 88h TCON.4T0M Input clock select (/4) CKCON – 8Eh CKCON.3

T0MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.3Timer LSB TL0 – 8Ah

TIM

ER

0

Timer MSB TH0 – 8Ch

GATE Gate control enable for INT1 pin TMOD – 89h TMOD.7C/T Counter/timer select TMOD – 89h TMOD.6

M1, M0 Timer mode select bits TMOD – 89h TMOD.5,4TF1 Timer overflow flag TCON – 88h TCON.7TR1 Timer run control TCON – 88h TCON.6T1M Input clock select (/4) CKCON – 8Eh CKCON.4

T1MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.4Timer LSB TL1 – 8Bh

TIM

ER

1

Timer MSB TH1 – 8Dh

TF2 Timer overflow flag T2CON – C8h T2CON.7EXF2 Timer external flag T2CON – C8h T2CON.6RCLK Timer 2 receive serial clock enable T2CON – C8h T2CON.5TCLK Timer 2 transmit serial clock enable T2CON – C8h T2CON.4

EXEN2 External enable for T2EX pin T2CON – C8h T2CON.3TR2 Timer run control T2CON – C8h T2CON.2C/T2 Counter/timer select T2CON – C8h T2CON.1

CP/RL2 Capture/reload select T2CON – C8h T2CON.0T2OE Output enable for T2 pin T2MOD – C9h T2MOD.1DCEN Down count enable T2MOD – C9h T2MOD.0T2M Input clock select (/4) CKCON – 8Eh CKCON.5

T2MH Input clock high-speed select (/1) CKMOD – 96h CKMOD.5Timer LSB TL2 – CChTimer MSB TH2 – CDhTimer capture LSB RCAP2L – CAh

TIM

ER

2

Timer capture MSB RCAP2H – CBh

Table 11-1. Programmable Timers

Using timer 1 in the 8-bit autoreload mode, serial port baud rates for mode 1 or 3 can be calculated using the formula below.

Timer 1 input clock frequency can be found in the previous table, SMOD_x is the logic state of the baud-rate doubler bit for the asso-ciated UART, and TH1 is the user assigned timer 1 reload value.

Often, users already know what baud rate is desired and only need to calculate the timer reload value. An equation to calculate thetimer reload value, TH1, is as follows:

Note that the 8-bit, autoreload mode for timer 1 is the one most commonly used for serial port applications, but that it can actually be configured in any mode, even as acounter.

Using Timer 2 for Baud-Rate GenerationTo use timer 2 as baud-rate generator for serial port 0, the timer is configured in autoreload mode. Then, either the TCLK or RCLK bit(or both) are set to a logic 1. TCLK = 1 selects timer 2 as the baud-rate generator for the transmitter and RCLK = 1 selects timer 2 forthe receiver. Thus, serial port 0 can have the transmitter and receiver operating at different baud rates by choosing timer 1 for one datadirection and timer 2 for the other. RCLK and TCLK reside in T2CON.4 and TCON.5, respectively.

Although the timer 2 input clock can be configured similarly to timer 1, it must be placed into a baud-rate generator mode in order tobe used by serial port 0. Setting either RCLK or TCLK to a logic 1 selects timer 2 for baud-rate generation. When this is done, the timer2 input clock becomes fixed to the oscillator frequency divided by 2. This is compatible with the 80C32. The only exception is whentimer 2 is used for baud-rate generation within power-management mode. For PMM, the system clock (OSC/1024) is used as the inputclock for timer 2. The timer 2 interrupt is automatically disabled when either RCLK or TCLK is set. Also, the TF2 (TCON.7) flag is notset on a timer rollover. The manual reload pin, T2EX (P1.1), does not cause a reload either. Table 12-6 illustrates this relationship.

2 SMOD_x timer 1 input clock frequencyTH1 = 256 - 32 baud rate

2 SMOD_x Timer 1 input clock frequency Modes 1, 3 baud rate = 32 (256 - TH1)

Timer 1 rolloverfrequency

Number of serial bits /Number of timer 1 rollovers


111 ____________________________________________________________________________________________

TIMER 1INPUT CLOCK FREQUENCYSYSTEM CLOCK MODE PMR REGISTER BITS

4X/2X, CD1, CD0T1MH,T1M = 00 T1MH,T1M = 01 T1MH,T1M = 1X

Crystal multiply mode 4X 100 OSC / 12 OSC / 1 OSC / 0.25Crystal multiply mode 2X 000 OSC / 12 OSC / 2 OSC / 0.5

Divide-by-1 (default) X01, X10 OSC / 12 OSC / 4 OSC / 1Power-management mode (/1024) X11 OSC / 3072 OSC / 1024 OSC / 1024

Table 12-5. Timer 1 Input Clock Frequency

SYSTEM CLOCK MODE PMR REGISTER BITS4X/2X, CD1, CD0

TIMER 2 INPUT CLOCK FREQUENCYBAUD-RATE GENERATOR MODE

(RCLK OR TCLK = 1)

Crystal multiply mode 4X 100 OSC / 2Crystal multiply mode 2X 000 OSC / 2

Divide-by-1 (default) X01, X10 OSC / 2Power-management mode (/1024) X11 OSC / 1024

Table 12-6. Timer 2 Baud-Rate Generation


129 ____________________________________________________________________________________________

Serial Program Load OperationProgram loading through a serial port is a convenient method of loading application software into the flash memory or external mem-ory. Communication is performed over a standard, asynchronous serial communications port using a terminal emulator program with8-N-1 (8 data bits, no parity, 1 stop bit) protocol settings. A typical application would use a simple RS-232 serial interface to in-systemprogram the device as part of a final production procedure.

The hardware configuration for the serial program load operation is illustrated in Figure 15-2. A variety of crystals can be used to pro-duce standard baud rates. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, trans-mit, and ground wires are all that are necessary to establish communication with the device.

The serial loader implements an easy-to-use command line interface, which allows an Intel hex file to be loaded and read back fromthe device. Intel hex is the standard format output by 8051 cross-assemblers.

AUTOBAUD-RATE DETECTIONThe serial bootstrap loader can automatically detect, within certain limits, the external baud rate and configure itself to that speed. Theloader controls serial port 0 in mode 1 (asynchronous, 1 start bit, 8 data bits, no parity, 1 stop bit, full duplex), using timer 1 in 8-bitautoreload mode with the serial port 0 doubler bit (PCON.7) set. For these settings, an equation to calculate possible serial loaderbaud rates is provided as a function of crystal frequency and timer reload value. Table 15-1 shows baud rates generated using theequation:

** Timer reload values attempted by the loader:

FF, FE, FD, FC, FB, FA, F8, F6, F5, F4, F3, F0, EC, EA, E8,

E6, E0, DD, D8, D4, D0, CC, C0, BA, B0, A8, A0, 98, 80, 60, 40

When communicating with a PC COM port having a standard 8250/16450 UART, attempt to match the loader baud rate and PC COMport baud rate within 3% in order to maintain a reliable communication channel. If baud rates cannot be matched exactly, it is suggest-ed configuring the loader to the faster baud rate to avoid the possibility of overflowing the DS89C420 serial input buffer.

)(x192

Crystal Frequency

256-Timer ReloadSerial Loader_Baud rate =

TO PC

ROIN

TD

HC/AC125

TOOUTRD

R1IN

DTR

ROOUT

VCC

TOIN

R1OUT

DS232A

DS89C420

T1OUT

RXDO

TXDO

RST

EA

PSEN

T1IN

Figure 15-2. Serial Load Hardware Configuration


135 ____________________________________________________________________________________________

USER CODE IN-APPLICATION PROGRAMMING MODEThe DS89C420 data sheet contains the most comprehensive information relating to the in-application programming mode. Additionalsupporting information can be found in the SFR definitions of FCNTL (D5h) and FDATA (F6h) of this user’s guide.

INTEL HEX FILE FORMATAssemblers that are 8051-compatible assemblers produce an absolute output file in Intel hex format. These files are composed of aseries of records. Records in an Intel hex file have the following format:

<header><hex information><record terminator>

The specific record elements are detailed as follows:

: II aaaa tt dddddd ... dd xx

where:

: Indicates a record beginning

II Indicates the record length

aaaa Indicates the 16-bit load address

tt Indicates the record type

dd Indicates hex data

xx Indicates the checksum = (two’s complement (II+aa+a+tt+dd+dd+...dd)

Record type 00 indicates a data record and type 01 indicates an end record. An end record appears as :00 00000 01 FF. These arethe only valid record types for a NIL hex file. Spaces are provided for clarity.

The following is a short Intel hex file. The data bytes begin at 01 and count up to 2F. Notice the record’s length, beginning address,and record type at the start of each line and the checksum at the end:

REVISION HISTORYJanuary 24, 2001 Original Issue

October 3, 2002 Revision 1

:200000000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F20D0:0F0020002122232425262728292A2B2C2D2E2F79:00000001FF

SLCS115E − DECEMBER 1986 − REVISED JULY 2003

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Very Low Power . . . 110 µW Typ at 5 V

Fast Response Time . . . tPLH = 2.5 µs TypWith 5-mV Overdrive

Single Supply Operation:TLC393C . . . 3 V to 16 VTLC393I . . . 3 V to 16 VTLC393Q . . . 4 V to 16 VTLC393M . . . 4 V to 16 VTLC193M . . . 4 V to 16 V

On-Chip ESD Protection

description

The TLC193 and TLC393 consist of dualindependent micropower voltage comparatorsdesigned to operate from a single supply. Theyare functionally similar to the LM393 but usesone-twentieth the power for similar responsetimes. The open-drain MOS output stageinterfaces to a variety of loads and supplies. Fora similar device with a push-pull outputconfiguration (see the TLC3702 data sheet).

Texas Instruments LinCMOS process offerssuperior analog performance to standard CMOSprocesses. Along with the standard CMOSadvantages of low power without sacrificingspeed, high input impedance, and low biascurrents, the LinCMOS process offers ex-tremely stable input offset voltages, even withdifferential input stresses of several volts. Thischaracteristic makes it possible to build reliableCMOS comparators.

The TLC393C is characterized for operation over the commercial temperature range of TA = 0°C to 70°C. TheTLC393I is characterized for operation over the extended industrial temperature range of TA = −40°C to 85°C.The TLC393Q is characterized for operation over the full automotive temperature range of TA = −40°C to 125°C.The TLC193M and TLC393M are characterized for operation over the full military temperature range of TA = −55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright 1986-2003, Texas Instruments Incorporated !" #!$% &"'&! #" #" (" " ") !"&& *+' &! # ", &" " "%+ %!&"", %% #""'

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

NC2OUTNC2IN−NC

NC1IN−

NC1IN+

NC

NC

1OU

TN

C

2IN

+N

CV N

C

GN

DN

C

NC

DD

D, JG, P, OR PW PACKAGE(TOP VIEW)

1

2

3

4

8

7

6

5

1OUT1IN−1IN+GND

VDD2OUT2IN−2IN+

NC − No internal connection

OUT

symbol (each comparator)

IN+

IN−

FK PACKAGE(TOP VIEW)

LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.

SLCS115D − DECEMBER 1986 − REVISED JULY 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

AVAILABLE OPTIONS

V maxPACKAGES

TAVIOmaxat 25°C SMALL OUTLINE

(D)CHIP CARRIER

(FK)CERAMIC DIP

(JG)PLASTIC DIP

(P)TSSOP

(PW)

0°C to 70°C 5 mV TLC393CD — — TLC393CP TLC393CPWLE

− 40°C to 85°C 5 mV TLC393ID — — TLC393IP TLC393IPWLE

− 40°C to 125°C 5 mV TLC393QD — — — —

− 55°C to 125°C 5 mV TLC393MD TLC193MFK TLC193MJG TLC393MP —

The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC393CDR).

schematicOUT

OPEN-DRAIN CMOS OUTPUT

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VDD (see Note 1) − 0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI − 0.3 V to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO − 0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output current, IO (each output) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total supply current into VDD 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Total current out of GND 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating free-air temperature range: TLC393C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC393I − 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC393Q − 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC393M − 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLC193M − 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range − 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.2. Differential voltages are at IN+ with respect to IN−.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C

POWER RATINGDERATING FACTORABOVE TA = 25°C

TA = 70°CPOWER RATING



D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW

FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW

JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW

P 1000 mW 8.0 mW/°C 640 mW 520 mW —

PW 525 mW 4.2 mW/°C 336 mW 273 mW —

SLCS115E − DECEMBER 1986 − REVISED JULY 2003

3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

recommended operating conditions

TLC393CUNIT

MIN NOM MAXUNIT

Supply voltage, VDD 3 5 16 V

Common-mode input voltage, VIC −0.2 VDD − 1.5 V

Low-level output current, IOL 20 mA

Operating free-air temperature, TA 0 70 °C

electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwisenoted)

PARAMETER TEST CONDITIONS† TTLC393C

UNITPARAMETER TEST CONDITIONS† TA MIN TYP MAXUNIT

V Inp t offset oltageVIC = VICRmin,VDD 5 V to 10 V

25°C 1.4 5mVVIO Input offset voltage VDD = 5 V to 10 V,

See Note 3 0°C to 70°C 6.5mV

I Inp t offset c rrent V 2 5 V25°C 1 pA

IIO Input offset current VIC = 2.5 V70°C 0.3 nA

I Inp t bias c rrent V 2 5 V25°C 5 pA

IIB Input bias current VIC = 2.5 V70°C 0.6 nA

V Common mode inp t oltage range25°C 0 to VDD − 1

VVICR Common-mode input voltage range0°C to 70°C 0 to VDD − 1.5

V

25°C 84

CMMR Common-mode rejection ratio VIC = VICRmin 70°C 84 dBCMMR Common mode rejection ratio VIC VICRmin

0°C 84

dB

25°C 85

kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 70°C 85 dBkSVR Su ly voltage rejection ratio VDD 5 V to 10 V

0°C 85

dB

V Lo le el o tp t oltage V 1 V I 6 mA25°C 300 400

mVVOL Low-level output voltage VID = −1 V, IOL = 6 mA70°C 650

mV

I High le el o tp t c rrent V 1 V V 5 V25°C 0.8 40 nA

IOH High-level output current VID = 1 V, VO = 5 V70°C 1 µA

IDD Supply current (both comparators) Outputs low No load25°C 22 40

µAIDD Supply current (both comparators) Outputs low, No load0°C to 70°C 50

µA

† All characteristics are measured with zero common-mode voltage unless otherwise noted.NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.

®

OPT1011

SPECTRAL RESPONSIVITY

Wavelength (nm)200 300 400 500 600 700 800 900 1000 1100

Vol

tage

Out

put (

V/µ

W)

Using Internal1MΩ Resistor

InfraredUltraviolet

Blu

e

Gre

enY

ello

w

Red

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Pho

todi

ode

Res

pons

ivity

(A

/W)

OPT101

FEATURES SINGLE SUPPLY: +2.7 to +36V

PHOTODIODE SIZE: 0.090 x 0.090 inch

INTERNAL 1MΩ FEEDBACK RESISTOR

HIGH RESPONSIVITY: 0.45A/W (650nm)

BANDWIDTH: 14kHz at R F = 1MΩ LOW QUIESCENT CURRENT: 120µA

AVAILABLE IN 8-PIN DIP, 5-PIN SIP, AND8-LEAD SURFACE MOUNT PACKAGES

MONOLITHIC PHOTODIODE ANDSINGLE-SUPPLY TRANSIMPEDANCE AMPLIFIER

1MΩ

OPT101

3pF

8pF

2 (2)

5

4

(5)

(4)

V+

λ

3(3)8(1)

VB

7.5mV

1

(Pin availableon DIP only.)

(SIP) DIP

®

DESCRIPTIONThe OPT101 is a monolithic photodiode with on-chiptransimpedance amplifier. Output voltage increaseslinearly with light intensity. The amplifier is designedfor single or dual power supply operation, making itideal for battery operated equipment.

The integrated combination of photodiode andtransimpedance amplifier on a single chip eliminatesthe problems commonly encountered in discrete de-signs such as leakage current errors, noise pick-up andgain peaking due to stray capacitance. The 0.09 x 0.09inch photodiode is operated in the photoconductivemode for excellent linearity and low dark current.

The OPT101 operates from +2.7V to +36V suppliesand quiescent current is only 120µA. It is available inclear plastic 8-pin DIP, 5-pin SIP and J-formed DIP forsurface mounting. Temperature range is 0°C to 70°C.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Bl vd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FA X: (520) 889-1510 • Immediate Product Info: (800) 548-6132

APPLICATIONS MEDICAL INSTRUMENTATION

LABORATORY INSTRUMENTATION

POSITION AND PROXIMITY SENSORS

PHOTOGRAPHIC ANALYZERS

BARCODE SCANNERS

SMOKE DETECTORS

CURRENCY CHANGERS

©1994 Burr-Brown Corporation PDS-1257D Printed in U.S.A. March, 1998

SBBS002

®

OPT101 2

SPECIFICATIONSAt TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted.

PHOTODIODE SPECIFICATIONSTA = +25°C, VS = +2.7V to +36V unless otherwise noted.

Photodiode of OPT101P

PARAMETER CONDITIONS MIN TYP MAX UNITS

Photodiode Area (0.090 x 0.090in) 0.008 in2

(2.29 x 2.29mm) 5.2 mm2

Current Responsivity 650nm 0.45 A/W650nm 865 µA/W/cm2

Dark Current VDIODE = 7.5mV 2.5 pAvs Temperature doubles every 7°C

Capacitance 1200 pF

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.

OPT101P, W


RESPONSIVITYPhotodiode Current 650nm 0.45 A/WVoltage Output 650nm 0.45 V/µW

vs Temperature 100 ppm/°CUnit to Unit Variation 650nm ±5 %Nonlinearity(1) FS Output = 24V ±0.01 % of FSPhotodiode Area (0.090 x 0.090in) 0.008 in2

(2.29 x 2.29mm) 5.2 mm2

DARK ERRORS, RTO(2)

Offset Voltage, Output +5 +7.5 +10 mVvs Temperature ±2.5 µV/°Cvs Power Supply VS = +2.7V to +36V 10 100 µV/V

Voltage Noise, Dark, fB = 0.1Hz to 20kHz VS = +15V, VPIN3 = –15V 300 µVrms

TRANSIMPEDANCE GAINResistor 1 MΩTolerance, P ±0.5 ±2 %

W ±0.5 %vs Temperature ±50 ppm/°C

FREQUENCY RESPONSEBandwidth VOUT = 10Vp-p 14 kHzRise Fall Time, 10% to 90% VOUT = 10V Step 28 µsSettling Time, 0.05% VOUT = 10V Step 160 µs

0.1% 80 µs1% 70 µs

Overload Recovery 100%, Return to Linear Operation 50 µs

OUTPUTVoltage Output, High (VS) – 1.3 (VS) – 1.15 VCapacitive Load, Stable Operation 10 nFShort-Circuit Current VS = 36V 15 mA

POWER SUPPLYOperating Voltage Range +2.7 +36 VQuiescent Current Dark, VPIN3 = 0V 120 240 µA

RL = ∞, VOUT = 10V 220 µA

TEMPERATURE RANGESpecification 0 +70 °COperating 0 +70 °CStorage –25 +85 °CThermal Resistance, θJA 100 °C/W

NOTES: (1) Deviation in percent of full scale from best-fit straight line. (2) Referred to Output. Includes all error sources.

®

OPT1013

OP AMP SPECIFICATIONSAt TA = +25°C, VS = +2.7V to +36V, λ = 650nm, internal 1MΩ feedback resistor, and RL = 10kΩ, unless otherwise noted.

OPT101 Op Amp (1)


INPUTOffset Voltage ±0.5 mV

vs Temperature ±2.5 µV/°Cvs Power Supply 10 µV/V

Input Bias Current (–) Input 165 pAvs Temperature (–) Input 1 pA/°C

Input ImpedanceDifferential 400 || 5 MΩ || pFCommon-Mode 250 || 35 GΩ || pF

Common-Mode Input Voltage Range Linear Operation 0 to [(VS) – 1] VCommon-Mode Rejection 90 dB

OPEN-LOOP GAINOpen-loop Voltage Gain 90 dB

FREQUENCY RESPONSEGain-Bandwidth Product(2) 2 MHzSlew Rate 1 V/µsSettling Time 1% 5.8 µs

0.1% 7.7 µs0.05% 8.0 µs

OUTPUTVoltage Output, High (VS) – 1.3 (VS) – 1.15 VShort-Circuit Current VS = +36V 15 mA

POWER SUPPLYOperating Voltage Range +2.7 +36 VQuiescent Current Dark, VPIN3 = 0V 120 240 µA

RL ∞, VOUT = 10V 220 µA

NOTES: (1) Op amp specifications provided for information and comparison only. (2) Stable gains ≥ 10V/V.

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Choice of Eight Latches or Eight D-TypeFlip-Flops in a Single Package

3-State Bus-Driving Outputs

Full Parallel Access for Loading

Buffered Control Inputs

Clock-Enable Input Has Hysteresis toImprove Noise Rejection (’S373 and ’S374)

P-N-P Inputs Reduce DC Loading on DataLines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputsdesigned specifically for driving highly capacitiveor relatively low-impedance loads. Thehigh-impedance 3-state and increasedhigh-logic-level drive provide these registers withthe capability of being connected directly to anddriving the bus lines in a bus-organized systemwithout need for interface or pullup components.These devices are particularly attractive forimplementing buffer registers, I/O ports,bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 aretransparent D-type latches, meaning that whilethe enable (C or CLK) input is high, the Q outputsfollow the data (D) inputs. When C or CLK is takenlow, the output is latched at the level of the datathat was set up.

The eight flip-flops of the ’LS374 and ’S374 areedge-triggered D-type flip-flops. On the positivetransition of the clock, the Q outputs are set to thelogic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system designas ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A bufferedoutput-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logiclevels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus linessignificantly.

OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or newdata can be entered, even while the outputs are off.

Copyright 2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LS373, SN54LS374, SN54S373,SN54S374 . . . J OR W PACKAGE

SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGESN74LS374 . . . DB, DW, N, OR NS PACKAGE

SN74S373 . . . DW OR N PACKAGE(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

8D7D7Q6Q6D

2D2Q3Q3D4D

SN54LS373, SN54LS374, SN54S373,SN54S374 . . . FK PACKAGE

(TOP VIEW)

1D 1Q OC

5Q 5D8Q

4QG

ND C

V CC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OC1Q1D2D2Q3Q3D4D4Q

GND

VCC8Q8D7D7Q6Q6D5D5QC†

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.

†

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

On products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS


6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†(’LS devices)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Off-state output voltage 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions

SN54LS’ SN74LS’UNIT

MIN NOM MAX MIN NOM MAXUNIT

VCC Supply voltage 4.5 5 5 4.75 5 5.25 V

VOH High-level output voltage 5.5 5.5 V

IOH High-level output current –1 –2.6 mA

IOL Low-level output current 12 24 mA

t Pulse durationCLK high 15 15

nstw Pulse durationCLK low 15 15

ns

t Data setup time’LS373 5↓ 5↓

nstsu Data setup time’LS374 20↑ 20↑

ns

th Data hold time’LS373 20↓ 20↓

nsth Data hold time’LS374‡ 5↑ 0↑

ns

TA Operating free-air temperature –55 125 0 70 °C‡ The th specification applies only for data frequency below 10 MHz. Designs above 10 MHz should use a minimum of 5 ns (commercial only).

SN54LS373, SN54LS374, SN54S373, SN54S374,SN74LS373, SN74LS374, SN74S373, SN74S374

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS


7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)

PARAMETER TEST CONDITIONS†SN54LS’ SN74LS’

UNITPARAMETER TEST CONDITIONS†MIN TYP‡ MAX MIN TYP‡ MAX

UNIT

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.7 0.8 V

VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V

VOH High level output voltageVCC = MIN, VIH = 2 V,

2 4 3 4 2 4 3 1 VVOH High-level output voltage CC ,VIL = VIL max,

IH ,IOH = MAX

2.4 3.4 2.4 3.1 V

VOL Low level output voltageVCC = MIN, VIH = 2 V, IOL = 12 mA 0.25 0.4 0.25 0.4

VVOL Low-level output voltage CC ,VIL = VIL max

IH ,

IOL = 24 mA 0.35 0.5V

IOZHOff-state output current, VCC = MAX, VIH = 2 V,

20 20 AIOZH,

high-level voltage appliedCC ,

VO = 2.7 VIH ,

20 20 A

IOZLOff-state output current, VCC = MAX, VIH = 2 V,

20 20 AIOZL,

low-level voltage appliedCC ,

VO = 0.4 VIH ,

–20 –20 A

IIInput current at maximum

VCC = MAX VI = 7 V 0 1 0 1 mAII input voltageVCC = MAX, VI = 7 V 0.1 0.1 mA

IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 A

IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA

IOS Short-circuit output current§ VCC = MAX –30 –130 –30 –130 mA

ICC Supply currentVCC = MAX, ’LS373 24 40 24 40

mAICC Supply current CC ,Output control at 4.5 V ’LS374 27 40 27 40

mA

† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.‡ All typical values are at VCC = 5 V, TA = 25°C.§ Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second.

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

PARAMETERFROM TO

TEST CONDITIONS’LS373 ’LS374

UNITPARAMETER(INPUT) (OUTPUT)

TEST CONDITIONSMIN TYP MAX MIN TYP MAX

UNIT

fmaxRL = 667 Ω CL = 45 pF,

See Note 335 50 MHz

tPLHData Any Q

RL = 667 Ω CL = 45 pF, 12 18ns

tPHLData Any Q L L ,

See Note 3 12 18ns

tPLHC or CLK Any Q

RL = 667 Ω CL = 45 pF, 20 30 15 28ns

tPHLC or CLK Any Q L L ,

See Note 3 18 30 19 28ns

tPZHOC Any Q

RL = 667 Ω CL = 45 pF, 15 28 20 26ns

tPZLOC Any Q L L ,

See Note 3 25 36 21 28ns

tPHZ 15 25 15 28tPHZOC Any Q RL 667 Ω CL 5 pF

15 25 15 28ns

tPLZOC Any Q RL = 667 Ω CL = 5 pF

12 20 12 20ns

tPLZ 12 20 12 20

NOTE 3: Maximum clock frequency is tested with all outputs loaded.fmax = maximum clock frequencytPLH = propagation delay time, low-to-high-level outputtPHL = propagation delay time, high-to-low-level outputtPZH = output enable time to high leveltPZL = output enable time to low leveltPHZ = output disable time from high leveltPLZ = output disable time from low level

LMD182003A, 55V H-BridgeGeneral DescriptionThe LMD18200 is a 3A H-Bridge designed for motion controlapplications. The device is built using a multi-technology pro-cess which combines bipolar and CMOS control circuitrywith DMOS power devices on the same monolithic structure.Ideal for driving DC and stepper motors; the LMD18200 ac-commodates peak output currents up to 6A. An innovativecircuit which facilitates low-loss sensing of the output currenthas been implemented.

Featuresn Delivers up to 3A continuous outputn Operates at supply voltages up to 55Vn Low RDS(ON) typically 0.3Ω per switchn TTL and CMOS compatible inputs

n No “shoot-through” currentn Thermal warning flag output at 145˚Cn Thermal shutdown (outputs off) at 170˚Cn Internal clamp diodesn Shorted load protectionn Internal charge pump with external bootstrap capability

Applicationsn DC and stepper motor drivesn Position and velocity servomechanismsn Factory automation robotsn Numerically controlled machineryn Computer printers and plotters

Functional Diagram

DS010568-1

FIGURE 1. Functional Block Diagram of LMD18200

December 1999

LMD

182003A

,55VH

-Bridge

© 1999 National Semiconductor Corporation DS010568 www.national.com

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Total Supply Voltage (VS, Pin 6) 60VVoltage at Pins 3, 4, 5, 8 and 9 12VVoltage at Bootstrap Pins

(Pins 1 and 11) VOUT +16VPeak Output Current (200 ms) 6AContinuous Output Current (Note 2) 3APower Dissipation (Note 3) 25W

Power Dissipation (TA = 25˚C, Free Air) 3WJunction Temperature, TJ(max) 150˚CESD Susceptibility (Note 4) 1500VStorage Temperature, TSTG −40˚C to +150˚CLead Temperature (Soldering, 10 sec.) 300˚C

Operating Ratings (Note 1)

Junction Temperature, TJ −40˚C to +125˚CVS Supply Voltage +12V to +55V

Electrical Characteristics (Note 5)The following specifications apply for VS = 42V, unless otherwise specified. Boldface limits apply over the entire operatingtemperature range, −40˚C ≤ TJ ≤ +125˚C, all other limits are for TA = TJ = 25˚C.

Symbol Parameter Conditions Typ Limit Units

RDS(ON) Switch ON Resistance Output Current = 3A (Note 6) 0.33 0.4/0.6 Ω (max)

RDS(ON) Switch ON Resistance Output Current = 6A (Note 6) 0.33 0.4/0.6 Ω (max)

VCLAMP Clamp Diode Forward Drop Clamp Current = 3A (Note 6) 1.2 1.5 V (max)

VIL Logic Low Input Voltage Pins 3, 4, 5 −0.1 V (min)

0.8 V (max)

IIL Logic Low Input Current VIN = −0.1V, Pins = 3, 4, 5 −10 µA (max)

VIH Logic High Input Voltage Pins 3, 4, 5 2 V (min)

12 V (max)

IIH Logic High Input Current VIN = 12V, Pins = 3, 4, 5 10 µA (max)

Current Sense Output IOUT = 1A (Note 8) 377 325/300 µA (min)

425/450 µA (max)

Current Sense Linearity 1A ≤ IOUT ≤ 3A (Note 7) ±6 ±9 %

Undervoltage Lockout Outputs turn OFF 9 V (min)

11 V (max)

TJW Warning Flag Temperature Pin 9 ≤ 0.8V, IL = 2 mA 145 ˚C

VF(ON) Flag Output Saturation Voltage TJ = TJW, IL = 2 mA 0.15 V

IF(OFF) Flag Output Leakage VF = 12V 0.2 10 µA (max)

TJSD Shutdown Temperature Outputs Turn OFF 170 ˚C

IS Quiescent Supply Current All Logic Inputs Low 13 25 mA (max)

tDon Output Turn-On Delay Time Sourcing Outputs, IOUT = 3A 300 ns

Sinking Outputs, IOUT = 3A 300 ns

ton Output Turn-On Switching Time Bootstrap Capacitor = 10 nF

Sourcing Outputs, IOUT = 3A 100 ns


tDoff Output Turn-Off Delay Times Sourcing Outputs, IOUT = 3A 200 ns


toff Output Turn-Off Switching Times Bootstrap Capacitor = 10 nF

Sourcing Outputs, IOUT = 3A 75 ns


tpw Minimum Input Pulse Width Pins 3, 4 and 5 1 µs

tcpr Charge Pump Rise Time No Bootstrap Capacitor 20 µs

LMD

18200

www.national.com3

Pinout Description(See Connection Diagram) (Continued)

Pin 6, VS Power Supply

Pin 7, GROUND Connection: This pin is the ground return,and is internally connected to the mounting tab.

Pin 8, CURRENT SENSE Output: This pin provides thesourcing current sensing output signal, which is typically377 µA/A.

Pin 9, THERMAL FLAG Output: This pin provides the ther-mal warning flag output signal. Pin 9 becomes active-low at145˚C (junction temperature). However the chip will not shutitself down until 170˚C is reached at the junction.

Pin 10, OUTPUT 2: Half H-bridge number 2 output.

Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin forHalf H-bridge number 2. The recommended capacitor(10 nF) is connected between pins 10 and 11.

TABLE 1. Logic Truth Table

PWM Dir Brake Active Output Drivers

H H L Source 1, Sink 2

H L L Sink 1, Source 2

L X L Source 1, Source 2

H H H Source 1, Source 2

H L H Sink 1, Sink 2

L X H NONE

Application Information

TYPES OF PWM SIGNALS

The LMD18200 readily interfaces with different forms ofPWM signals. Use of the part with two of the more popularforms of PWM is described in the following paragraphs.

Simple, locked anti-phase PWM consists of a single, vari-able duty-cycle signal in which is encoded both direction andamplitude information (see Figure 2). A 50% duty-cyclePWM signal represents zero drive, since the net value ofvoltage (integrated over one period) delivered to the load iszero. For the LMD18200, the PWM signal drives the direc-tion input (pin 3) and the PWM input (pin 5) is tied to logichigh.

Sign/magnitude PWM consists of separate direction (sign)and amplitude (magnitude) signals (see Figure 3). The (ab-solute) magnitude signal is duty-cycle modulated, and theabsence of a pulse signal (a continuous logic low level) rep-resents zero drive. Current delivered to the load is propor-tional to pulse width. For the LMD18200, the DIRECTION in-put (pin 3) is driven by the sign signal and the PWM input(pin 5) is driven by the magnitude signal.

SIGNAL TRANSITION REQUIREMENTS

To ensure proper internal logic performance, it is good prac-tice to avoid aligning the falling and rising edges of input sig-nals. A delay of at least 1 µsec should be incorporated be-tween transitions of the Direction, Brake, and/or PWM inputsignals. A conservative approach is be sure there is at least500ns delay between the end of the first transition and thebeginning of the second transition. See Figure 4.

DS010568-4

FIGURE 2. Locked Anti-Phase PWM Control

DS010568-5

FIGURE 3. Sign/Magnitude PWM Control

LMD

1820

0

www.national.com 6

NPN SILICON PLANAR SWITCHING TRANSISTORS 2N2221A 2N2222A TO-18

Switching And Linear Application DC And VHF Amplifier Applications

ABSOLUTE MAXIMUM RATINGSDESCRIPTION SYMBOL 2N2221A,22A UNIT

Collector -Emitter Voltage VCEO 40 VCollector -Base Voltage VCBO 75 VEmitter -Base Voltage VEBO 6.0 VCollector Current Continuous IC 800 mAPower Dissipation @Ta=25 degC PD 500 mWDerate Above 25deg C 2.28 mW/deg C @ Tc=25 degC PD 1.2 WDerate Above 25deg C 6.85 mW/deg COperating And Storage Junction Tj, Tstg -65 to +200 deg CTemperature RangeELECTRICAL CHARACTERISTICS (Ta=25 deg C Unless Otherwise Specified)

DESCRIPTION SYMBOL TEST CONDITION VALUEMIN MAX UNIT

Collector -Emitter Voltage VCEO IC=10mA,IB=0 40 - VCollector -Base Voltage VCBO IC=10uA.IE=0 75 - VEmitter-Base Voltage VEBO IE=10uA, IC=0 6.0 - VCollector-Cut off Current ICBO VCB=60V, IE=0 - 10 nA

Ta=150 deg CVCB=60V, IE=0 - 10 uA

ICEX VCE=60V, VEB=3V - 10 nAEmitter-Cut off Current IEBO VEB=3V, IC=0 - 10 nABase-Cut off Current IBL VCE=60V, VEB=3V - 20 nACollector Emitter Saturation Voltage VCE(Sat)* IC=150mA,IB=15mA - 0.3 V

IC=500mA,IB=50mA 1.0 VBase Emitter Saturation Voltage VBE(Sat) * IC=150mA,IB=15mA - 0.6-1.2 V

IC=500mA,IB=50mA - 2.0 V

Continental Device India Limited Data Sheet Page 1 of 3

Continental Device India LimitedAn ISO/TS16949 and ISO 9001 Certified Company

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(8th Semester) Project Report