A 0 18 m CMOS Internally-Compensated Low-Dropout Voltage ... · Internally-Compensated Low-Dropout Voltage Regulator By ... The massive proliferation of battery-operated portable

A 0.18µm CMOSInternally-Compensated

Low-Dropout Voltage Regulator

By

Carlos Felipe Ventura Arizmendi

A Dissertation Submitted to the Program in ElectronicsScience, Electronics Department in partial fulfillment of

the requirements for the degree of:

Master of Science with Major on Electronics

at the

National Institute for Astrophysics, Optics andElectronics

February 2014Tonantzintla, Puebla, Mexico

Advisors:

Dra. Mar ıa Teresa Sanz PascualFull Researcher

Electronics DepartmentINAOE

Dra. Belen Calvo LopezFull Researcher

Electronic Design GroupUniversity of Zaragoza, Spain

c©INAOE 2014The author hereby grants to INAOE permission to

reproduce and distribute copies of this thesis document inwhole or in part.

Acknowledgments

I would like to first thank to life and God for give me the opportunity of studying a

Master degree at INAOE. The study and destiny guided me to meet the love of my life.

I would like to thank Melany for her love, patience and support in hard times. You

are in my heart and mind, always. We did it sweetheart! Also, I would like to thank

my family for all their love and support along my journey in the electronic engineering

profession. To my family and Mel, I owe them my current successes and the success

that will follow in the future.

I must thank to Dra. Marıa Teresa for her expert knowledge and guidance through-

out this thesis work at INAOE. I would also like to thank to Dra. Belen for her en-

couragement and patience during this thesis development at Zaragoza’s University. For

your advices, support and motivation... Thank you! Without your support, this thesis

could not even be finished.

I am also grateful to my colleagues and friends. For sharing scientific and fun mo-

ments, the jokes and companionship. There are some special mentions I would like to

thank: to Nicte-Ha for being a truly friend during this time. Hector, Haiko, Don Gato,

Andres, Manolo, Alejandro for their support and advices, the stay at INAOE would not

have been the same without you. I really appreciate all of you. To the people I met

at Zaragoza’s University: Erick, Rodanas, Cris, Oscar, Carlos... thanks for your help

when it was required. Besides, I thank to my furry friend, “the Flaca”, for its compan-

iii

iv

ionship and selfless love, I wish her to live many years.

I am grateful to the Instituto Nacional de Astrofısica Optica y Electronica (INAOE)

for supporting me during this time, for the services and conferences, for the support to

stay abroad the country, for the daily activities and coffee breaks... Thanks!

Finally, but not less important, I must thank to the Consejo Nacional de Ciencia

y Tecnologıa (CONACyT) 261355 Master Grant for its support during my studies at

INAOE and for the support of CONACyT CB-SEP-2008-01-99901 Research Project .

To all I have mentioned and those I’ve not... Thanks for believing in me!

AbstractThe massive proliferation of battery-operated portable devices, such as cellphones, lap-

tops or wireless sensor networks, has made power management one of the IC industry

major concerns. In this scenario, low-dropout (LDO) voltage regulators have turned

into the preferred choice for low-voltage on-chip power management solutions, be-

cause of their fast response, simplicity and low cost of implementation.

An LDO is a linear voltage regulator with a common source (or common emitter)

output stage, showing improved efficiency over the conventional linear regulators at

the cost of higher complexity. These regulators normally require an external capacitor

of the order of µF to operate properly, which makes them unsuitable deployment in

applications SoC (system on chip). The LDO regulator must supply a constant, noise-

free, accurate and load-independent voltage level, with particular DC, AC and transient

characteristics, such as load and line regulation, stability and transient response, which

will depend on the actual application.

A fully-integrated 0.18µm CMOS Low-Dropout (LDO) Voltage Regulator with

current mode internal frequency compensation suitable for battery-operated systems,

e.g. WSN motes, is presented in this thesis. The regulator provides a maximum out-

put current of 70mA for up to 50pF capacitive load. The regulated output voltage can

be chosen to be either 1.2V or 1.8V , with a supply voltage ranging from 3.3V to 2.1V .

The simulation results showed that the performance of the proposed LDO regulator is

set to the given specifications and even improves some qualities of previously works,

such as line regulation (LNR = 0.24mV/V ).

v

vi

Resumen

Los reguladores de voltaje son bloques esenciales en aplicaciones de diseno analogico

donde se requiere un nivel de voltaje estable y constante a pesar de cambios en la carga

y la temperatura. Hoy en dıa se requieren dispositivos portatiles que funcionen a base

de baterıas, las cuales son fuentes de energıa de corta duracion y que proveen un voltaje

generalmente mayor al requerido por los circuitos electronicos que conforman tales dis-

positivos, por ejemplo: celulares o nodos sensores de transmision inalambrica. Es por

ello que este tipo de reguladores se hacen cada vez mas indispensables para la industria

del diseno analogico.

Los reguladores lineales del tipo low-dropout son usados generalmente en aplica-

ciones de bajo voltaje y de bajo ruido en diseno analogico. Estos reguladores requieren

normalmente de un capacitor externo del orden de µF para operar adecuadamente, lo

que imposibilita su implementacion en aplicaciones SoC (system on chip).

Se presenta el diseno de un prototipo integrable de un regulador de voltaje del tipo

“low-dropout” de bajo consumo estatico en tecnologıa CMOS enfocado a la aplicacion

de nodos sensores de transmision inalambrica. El diseno fue optimizado de forma

que el voltaje de salida regulado fuese igual a 1.8V , una salida alternativa de voltaje

programable de 1.2V , que ocupara la menor cantidad de area de chip posible, que el

consumo estatico de corriente fuese mınimo y que el tiempo de respuesta fuese menor

a 10µs, logrando proveer una corriente elctrica mxima de 70mA. La tecnologıa de in-

vii

viii

tegracion es 1P − 6M UMC 0.18µm y el voltaje de alimentacion mınimo es de 2.1V .

Se realizo por tanto la caracterizacion electrica a nivel esquematico y post-layout.

Los resultados de simulacion mostraron que el desempeno del regulador propuesto se

ajusta a las especificaciones dadas e incluso mejora algunas cualidades de los trabajos

previamente presentados, tales como la regulacion de lınea (LNR = 0.24mV/V ).

Contents

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Resumen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

1 Introduction 1

1.1 Voltage References vs Voltage Regulators . . . . . . . . . . . . . . . . 3

1.1.1 Types of Voltage Regulators . . . . . . . . . . . . . . . . . . . 4

1.2 Low Dropout Voltage Regulators . . . . . . . . . . . . . . . . . . . . . 6

1.2.1 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.2 Pass Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2.3 Feedback Network . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3 LDO Regulator Specifications . . . . . . . . . . . . . . . . . . . . . . 10

1.4 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . . . . 16

1.5 Thesis Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Bibliography 21

2 Stability and Frequency Compensation 23

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2 The stability problem . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3 Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 Frequency compensation . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.5 LDO regulator Stability Analysis . . . . . . . . . . . . . . . . . . . . . 33

ix

x CONTENTS

2.6 External Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.7 Internal Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.7.1 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Bibliography 49

3 LDO Regulator Building Blocks Design 53

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2 Error Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.3 Pass Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Feedback Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5 Compensation circuit (Differentiator) . . . . . . . . . . . . . . . . . . 64

3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Bibliography 75

4 LDO Regulator: Post-layout Simulation Results 77

4.1 LDO Voltage Regulator Characterization . . . . . . . . . . . . . . . . . 78

4.2 Input-output voltage characteristics . . . . . . . . . . . . . . . . . . . . 79

4.3 Frequency compensation analysis . . . . . . . . . . . . . . . . . . . . 81

4.3.1 Power supply rejection (PSR) . . . . . . . . . . . . . . . . . . 84

4.4 Transient Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.4.1 Dependency with the load capacitor (CL) . . . . . . . . . . . . 91

4.4.2 Dependency with temperature . . . . . . . . . . . . . . . . . . 93

4.4.3 Transient behavior under process variations . . . . . . . . . . . 95

4.5 Main characteristics summary . . . . . . . . . . . . . . . . . . . . . . 96

4.5.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.6 Comparison with previously reported works . . . . . . . . . . . . . . . 101

4.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

CONTENTS xi

Bibliography 105

5 Conclusions and Future Work 107

5.1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

xii CONTENTS

Chapter 1

Introduction

“Era una pasion por la mirada, y en su mirada estaban los ojos antes del tiempo;

dice su padre que el tiempo es melancolıa, y cuando se para lo llamamos eternidad”

San Juan de la Cruz

One of the IC industry major concerns nowadays is the conditioning and supply-

ing of energy, also known as power management. It has emerged as an important field

of interest due to the high amount of portable devices currently created and produced,

such as cellphones, laptops and wireless sensor networks (WSN), which cannot operate

without a stable power source. Therefore, it is important to research and develop new

ways to supply and save power, with the purpose of attaining a portable device capable

of operating the longest time possible without increasing the production costs and the

size of power sources.

On the other hand, the growing demand for single chip solutions has caused the

development of new ways to integrate circuits and systems. In a single chip there can

be a wide variety of circuits and different levels of integration, such as:

• System on Chip (SoC).- Includes several circuits integrated in the same chip.

• System in Package (SiP).- Includes many SoC in the same package, that is,

a number of circuits can be integrated in different silicon substrates and then

packaged together.

1

2 Introduction

• System on Package (SoP).- Offers a highly advanced three-dimensional mixed-

signal system integration environment. Generally a multilayer substrate is used.

This thesis focuses on the design of a stable power supply for portable applications,

with the aim to accomplish a SoC solution, that is, integrating the voltage regulator core

as well as the additional circuitry needed in a single chip, avoiding the use of external

components. To this end, the optimal solution in terms of cost is an implementation in

CMOS technology.

The power supply of portable devices is provided by batteries, which deliver vari-

able voltage and current levels as they discharge over time [1]. There are several kinds

of batteries depending on the application. Table 1.1 shows a comparison between the

most commonly in portable applications [2, 3].

Battery Voltage (Cell) Capacity ApplicationLi Ion 2.7-4.2V Variable Portable (Laptops,Cellphones)NiCd 0.9-1.2V 1000-2000mAh Domestic and IndustrialNiMH 0.9-1.2V 800-2900mAh Robots, Vehicles

Zn/MnO2 1.65V 1800-2600mAh Portable (Radio,TV)

Table 1.1: Comparison between Batteries

One of the main aspects in batteries is their operational life, that is related to the

process of charge and discharge of the battery. The battery life in hours is given by:

LIFE(h) =Capacity[mAh]

IDrained(ave)[mA]=

Capacity[mAh]

IQ[mA] + ILoad[mA](1.1)

where capacity is the total current that can be drawn from the battery over one hour.

IDrained(ave) is the average current consumption which involves the quiescent current

(IQ), which is the total current value consumed by the circuit in steady-state, and the

load current (Iload), which is the electric current consumed by the load. An important

aspect can be inferred from equation (1.1): the operational life of the battery can be

1.1 Voltage References vs Voltage Regulators 3

maximized in steady-state, i.e., when the LDO regulator is not providing load current,

keeping a reduced quiescent current.

In this context, it is important to keep a constant voltage level for the electronic

circuits to operate properly. This action can be performed by a voltage regulator, which

is capable of supplying a constant, noise-free, accurate and load independent voltage

level. The aim of a voltage regulator is to provide stable voltage levels for any elec-

tronic circuit or even to an entire electronic system [4]. It is worth mentioning that

every application has different needs in terms of supply voltage and current consump-

tion. In the case of portable applications, a voltage regulator working at low voltage,

compatible with batteries, and with low current consumption, to optimize the portable

device operating life, is required.

1.1 Voltage References vs Voltage Regulators

It is important to distinguish between a voltage reference and a voltage regulator. A

voltage reference can provide a constant, temperature independent voltage level without

supplying high current levels. It is generally used to bias the circuitry in an electronic

system because of the accurate voltage level that it provides. A voltage regulator is a

buffered voltage reference, i.e., it needs a voltage reference to operate and it is able to

provide high current levels to any load while regulating or keeping constant the output

voltage level. Table 1.2 shows a comparison of their performance.

Parameter Voltage Reference Voltage RegulatorFunction Biasing Biasing and supplying current

Input Voltage Variation Small (∼ 200mV ) High (∼ 1.5V )Circuit Complexity Depends on “accuracy” Simple

Output Current Low (∼ µA) High (∼ mA)

Table 1.2: Comparison between a voltage reference and voltage regulator

4 Introduction

1.1.1 Types of Voltage Regulators

Voltage regulators are classified in switching and linear regulators. Switching regula-

tors use passive elements such as inductors and capacitors which usually occupy a large

area [1]. They are noisy due to the switching behavior and their operation is based on

charge transfer. Generally, this kind of regulators is used to couple voltage levels and

reduce a high voltage to a low voltage. Nevertheless, their output voltage is still full of

undesired fluctuations and noise. They are very commonly used in high voltage appli-

cations, where the main concern is the maximum transfer of energy or efficiency.

For applications where low power consumption and low voltage are required, linear

regulators are used. They are capable of satisfying electrical requirements such as low

current consumption, fast loop response to a sudden change in electrical current and

low cost of implementation (chip area). The output can be accurate and noise free.

While switching regulators can operate as a DC-DC, AC-DC, DC-AC, AC-AC con-

verters, linear regulators can only work as DC-DC converters. This is not a disadvan-

tage because the modern IC industry requires DC constant and noise-free voltage levels

to bias the circuits, a characteristic that it is difficult to achieve through a switching reg-

ulator. Figure 1.1 shows an example of a switching and a linear regulator. As it can

be noticed, both of them share some elements: the operational amplifier used as an

error amplifier and a feedback network to keep constant the output voltage. The switch

regulator operation is controlled by a switching frequency produced by a Pulse Width

Modulation (PWM) circuit, which triggers the inductors and capacitors so that they

deliver their accumulated charge. Switching regulators are, therefore, mixed analog-

digital circuits whose time response depends on the capacitors and inductors values.

Usually this kind of regulator shows a slow time response. In contrast, a linear regu-

lator exhibits an extra element called pass device, whose conductance is modulated by

the error amplifier in order to supply the required load current at any particular time.

1.1 Voltage References vs Voltage Regulators 5

+

-

Load

V REF

V IN

Error Amplifier

Pass Device

Power Supply

Feedback Loop

+

- Load

V REF

V IN

Error Amplifier

Power Supply

Feedback Loop

V OUT

PWM

Switches

V OUT

a) b)

Figure 1.1: a)Switching and b) Linear Voltage Regulator

Table 1.3 shows a comparison between those regulators. Sometimes linear and

switching regulators are used simultaneously in order to improve the system efficiency.

While switching regulators reduce the voltage from a transformer with maximum effi-

ciency, linear regulators can take that output as input. In this way, the resulting output

will be constant, regulated and noise free. Also linear voltage regulators are divided

into high and low voltage regulators.

Linear Regulators Switching Regulators“Limited” output Range “Flexible” output range

Low noise High NoiseSimple Circuit Complex CircuitLow Efficiency High efficiency

Fast Transient Response Slow Transient ResponseLow Power Consumption High Power Consumption

Table 1.3: Linear Regulator vs Switching Regulator

6 Introduction

1.2 Low Dropout Voltage Regulators

Low Dropout (LDO) Voltage Regulators are commonly used in IC design because of

their performance, low cost and simplicity [3]. They can be applied to battery-operated

circuits, medical, industrial and automotive applications, among others. Figure 1.2

shows the classical topology of an LDO voltage regulator with a PMOS transistor as

pass device.

+

- REF

V IN

Error Amplifier

Feedback Loop

V OUT

Power Supply

V

Pass Device

I load C C R

R ESR

L

R FB1

R FB2 C L

Figure 1.2: Classical LDO Voltage Regulator

A classical LDO exhibits three operation regions according to the power supply or

input power VIN , as shown in figure 1.3:

• Linear Region.- The output voltage level is high enough for the LDO regulator

to perform correctly, keeping stable the output voltage and delivering the required

current to the load.

• Dropout Region.- The input power is reduced, so the control loop loses gain and

the LDO regulator can not regulate further, as one or more transistors enter the

triode region.

1.2 Low Dropout Voltage Regulators 7

• OFF Region.- The voltage level of the power supply is too low to keep all the

transistors ON and the circuit is cut-off.

Power Supply V IN [ ]

V ] [

V IN

V OUT

OFF REGION

DROPOUT REGION

LINEAR REGION

Ou

tpu

t V

olt

age

Figure 1.3: Input-Output Voltage Regulator Response

There are two main aspects to be considered in the design of an LDO: the block

level configuration and the load conditions, which are established by the application.

As already mentioned, a classical LDO is composed by three essential blocks: an op-

erational amplifier, a pass element and a feedback network. Although out of the scope

of this thesis, the design of the voltage reference, usually a bandgap reference, is also

very important. Next, each building block of the LDO regulator will be introduced.

1.2.1 Error Amplifier

Generally, an Operational Transconductance Amplifier (OTA) is used to work as the

error amplifier due to its ability to drive capacitive loads and the design simplicity. The

OTA must satisfy the following requirements:

• High open-loop gain (AOL).- Load Regulation, as will be shown later, is en-

hanced as the open-loop gain of the system is increased.

8 Introduction

• Low Quiescent Current (IQ).- Quiescent current has to remain low in order to

extend the battery life.

• Operation under low VIN conditions.- The amplifier must operate properly even

if the input voltage supply is low as a consequence of battery discharge.

• High bandwidth (BW).- It is desirable that the bandwidth be large enough to

reach fast time response to abrupt changes in load current.

• High Power Supply Rejection (PSR).- A good PSR means that any fluctuation in

input supply will not be reflected at the output.

• High output voltage swing.- A high output voltage swing is required because the

amplifier drives the pass device to control the current flow that the load demands.

The operational amplifier senses the error of the feedback network and sets the

adequate voltage value at the gate of the pass transistor so that it provides the

required current to the load.

1.2.2 Pass Device

Generally, a transistor is used to work as pass device. Its main function is to drain cur-

rent from the supply to the load. Figure 1.4 shows some possible devices and configu-

rations that can be used, namely: (a) NPN darlington, (b) NPN follower, (c) common

emitter PNP, (d) NMOS follower and (e) common source PMOS [5]. It depends on the

designer to choose the correct configuration according to the required LDO specifica-

tions and the process technology.

Bipolar devices can deliver the highest output currents for a given supply voltage.

However, they require a base current to operate, so the error amplifier must be capable

of providing it. While the base current in an NPN transistor flows to the output, the base

current in a PNP transistor flows to ground, which means an increase in the quiescent

current. Therefore, in order to minimize the current consumption, the NPN structure

should be chosen. In contrast, PNP vertical structures are faster than PNP lateral and

1.2 Low Dropout Voltage Regulators 9

V IN V IN V IN

V IN V IN

V OUT

V OUT V OUT

V OUT V OUT

+

-

+

2V BE

+

-

+

-

+ V BE

+

-

+

+

-

V EC V DS

V GS

V SD

(a) (b) (c) (d) (e)

Figure 1.4: Pass Devices Configurations

NPN devices, so the time response may be improved by using PNP vertical transistors.

In addition, PNP vertical structures can achieve the lowest dropout voltage (VDO=VCE),

approximately 100mV to 400mV . PMOS transistors also provide dropout voltages in

the same range if properly designed. The NPN Darlington, NPN and NMOS transistors,

however, involve at least one base-emitter voltage (or gate-source voltage in the case of

NMOS) and one emitter-collector voltage (drain-source voltage in the case of NMOS),

so the dropout voltage increases up to the range of 800mV to 1200mV . Therefore, P

type transistors are probably the best option as pass devices and PMOS transistors are

preferred because they yield a good trade-off between dropout voltage, quiescent cur-

rent flow, output current and speed. To sum up, table 1.4 shows a comparison between

the most important parameters to consider in the selection of a pass device [5].

Structure / Parameter Iload IQ VDO SpeedDarlington High Medium VCE+2VBE Fast

NPN High Medium VCE+VBE FastPNP (lateral) High Large VEC SlowPNP (vertical) High Large VEC Fast

NMOS Medium Low VDS+VGS MediumPMOS Medium Low VSD Medium

Table 1.4: Comparison of pass device structures

10 Introduction

1.2.3 Feedback Network

A control loop is formed between the operational amplifier and the pass transistor

through the feedback network. It counteracts the effects of load current and also biases

the pass transistor. A couple of resistors (RFB1 andRFB2 in Fig. 1.2) are generally used

to perform this task. The IC technologies allow to include resistors made of polysilicon

but, due to the high resistance values, they occupy too much area.

1.3 LDO Regulator Specifications

There are mainly three aspects to take into account in the characterization of a regula-

tor: DC-AC regulating performance, power consumption and operation requirements.

The first one includes load and line regulation, power supply rejection, temperature

drift, transient load-dump variations and dropout voltage.

In an integrated circuit the load includes the interconections, and the load element,

which can be a capacitor, a resistor or a complete circuit or system. The parasitic

devices cause negative effects on DC, transient and efficiency performance. That is

the main reason why the designer must be aware of the load environment of the LDO

regulator and design it according to application-specific cases. As for the input voltage,

it is generally low and can be obtained from a battery or from a switching regulator,

which defines the input voltage range. Finally, the following parameters must be taken

into account:

• Load Regulation (LDR).- It is the change in the output voltage as a result of

changes in the load current at a constant input voltage. The load regulation is

essentially the LDO regulator output resistance, and can be defined as:

LDR =∆Vout∆Iload

(1.2)

1.3 LDO Regulator Specifications 11

where ∆Vout is the DC change in the output due to a change in the load current

Iload. A widely variable load would cause considerable voltage swings at the

LDO regulator internal nodes, and these changes would be reflected at the output

node. This parameter is highly dependent on the LDO regulator open-loop gain,

the equivalent resistance at the output node and the input-offset voltages. Usually,

the LDO open-loop gain must be increased and the output resistance decreased

in order to improve the load regulation.

• Line Regulation (LNR).- It is the change in the output voltage caused by changes

in the input voltage at a constant load current. Line Regulation is also a DC pa-

rameter described by:

LNR =∆Vout∆VIN

(1.3)

Power supply variations (∆VIN ) can be produced in two ways: directly and indi-

rectly. The first one considers variations through the supply itself, which can be

a noisy power source as a battery or the output of another regulator. The indirect

way is through changes in the voltage reference (VREF ). The closed-loop gain of

the regulator is expressed by:

ACL =VoutVREF

=RFB2

RFB1

+ 1 (1.4)

It can be noticed that any variation in VREF will be amplified and reflected at the

output.

• Power Supply Rejection (PSR).- It is the rejection to changes in the input sup-

12 Introduction

ply voltage. Power Rejection Supply is an AC parameter which expresses the

immunity of the circuit to variations in the input supply and is described by the

following equation:

PSR =VoutVIN

(1.5)

• Temperature Drift.- It is the change in the output voltage due to changes in tem-

perature. The LDO regulator must be immune to temperature drift. In fact, tem-

perature variations could affect the LDO regulator circuitry. Voltage references

can be proportional to absolute temperature (PTAT ) and complementary to ab-

solute temperature (CTAT ). The voltage generated by them is highly tempera-

ture dependent but if both references are combined in a proper way, the bandgap

voltage reference emerges as a solution immune to temperature. The temperature

changes may affect the voltage levels of the transistors, thus, one or more of them

may switch from its proper operation region. Consequently, the LDO regulator

may be not working adequately.

• Transient load-dump variations.- These are undershoots and overshoots present

at the output as a result of abrupt changes in the load current. Transient varia-

tions are all systematic by nature and can be produced by power supply noise, a

switching supply, a switching load and so on. Inherent shot, thermal and flicker

noise are normally not as important and are often neglected.

The LDO regulator transient response is usually asymmetrical due to the charge

and discharge processes experimented by the load capacitance and to the error

amplifier ability to charge and discharge the pass transistor gate capacitance. A

symmetrical response is possible using class B and class AB output stages but


they require more silicon area and complex circuitry, while increasing noise. The

main parameter to characterize transient response is the settling time. Faster re-

sponse time can be achieved at the expense of quiescent current to increase slew-

rate. This results in reduced power efficiency and battery life. There are two

ways to reduce transient variations in the LDO regulator classical topology: us-

ing an external high frequency output capacitor, which has low equivalent series

resistance (ESR) and is more expensive, or increasing the quiescent current.

• Dropout Voltage.- It is the difference between the input supply voltage and

the output voltage (VDO =VIN -Vout). This parameter is important because it is

closely related to the efficiency. In fact, it is often the limiting factor in efficiency

performance of LDO regulators.

• Efficiency (η).- It is defined as the ratio of delivered energy (Eload) to stored

energy (Esource) or, in other words, the fraction of source energy that actually

reaches the load. It is given by:

η =EloadEsource

(1.6)

The energy is defined as how much power P is transferred over intervals of time

t:

E =

∫P · dt (1.7)

Considering that the power is kept constant through time, the efficiency can be

expressed by:

η =EloadEsource

=Pload · tPsource · t

=PloadPsource

=IloadVoutIINVIN

(1.8)

14 Introduction

where Eload is the energy required by the load, Esource is the energy provided by

the source, Pload is the power consumed by the load, Psource is the power supplied

by the source, Iload is the electrical current required by the load and VIN and

IIN are the steady-state input supply voltage and its associated current, which

includes Iload and IQ. Vout is the output voltage of the circuit. From equation

(1.8) a parameter known as current efficiency ηI can be defined:

ηI =IloadIIN

=Iload

Iload + IQ(1.9)

Efficiency is an extremely important parameter in the world of portable electron-

ics because it determines operational life of the battery powered devices. Hence,

using equations (1.8) and (1.9) the following expression is obtained:

η =VoutIload

VIN(Iload + IQ)=VoutVIN

ηI (1.10)

If the quiescent current (IQ) is low, the operational life of the battery and the

voltage regulator efficiency will be maximized. Remembering that VDO = VIN−Vout:

η =(VIN − VDO)

VINηI =

[1 − VDO

VIN

]ηI (1.11)

As it can be noticed, high efficiency can be achieved in portable applications with

VIN in the order of 2.7 − 4.2V with dropout voltages order of hundreds of mV ,

e.g. 200 − 300mV .

Generally, different circuits in a system operate under different voltage and current


conditions. If this is the case, it is necessary to have different stages to provide different

voltage levels, as depicts the example shown in the diagram in figure 1.5.

Dropping Voltage Stage

Load Dropping Voltage Stage

3.3V

Power Supply

3.7V

Dropping Voltage Stage

1V

1.8V

Load

Load

Figure 1.5: Example of a power efficient system

To choose a voltage regulator it is important to define first:

• the application (automotive, industrial or medical),

• the power source and the input voltage level, and

• the number of stages.

The operation environment determines the choice of the input supply and the load

current value. Generally, these are the limiting factors in the LDO regulator operation.

In the case of the input supply, it is necessary to define the voltage range where the LDO

regulator will operate, that is, the maximum and minimum input voltages. The load

current value, in turn, determines how large the pass transistor must be. Although not

mentioned so far, compensation plays an extremely important role because it provides

stability to the LDO regulator. This issue will be discussed in depth in Chapter 2.

16 Introduction

1.4 Motivation and Objectives

As recent technologies tend to integrate more and more circuits in a single chip, tech-

nology scaling also leads to circuits operating under lower voltage values. This trend

has also fostered the proliferation of portable systems supplied with batteries [6]. A

remarkable example are Wireless Sensor Networks (WSNs), which have emerged as

an attractive approach in a certain kind of medical, disaster prevention, environmental

monitoring and navigation applications, among others. Figure 1.6 shows an specific

application where the WSNs were designed for active vibration control in automobile

structures [7].

Wireless sensor networks use batteries to supply power to the whole system: trans-

mission and reception circuits, conditioning circuits, sensors and so on. For this reason,

the network performance is dependent on the life-time, performance and efficiency of

the battery, and therefore, it is desirable that the WSN be simple and consume low

power.

Batteries provide a higher voltage than the required value and present voltage fluc-

tuations as they discharge. A low dropout voltage regulator provides a constant supply

voltage and the current required by the system, as well as fast time response and good

line and load regulation. Figure 1.7 illustrates that several LDO regulators may be

required, as each block handles different voltage levels.

For illustrative purposes, table 1.5 depicts the performance of some previously re-

ported CMOS LDO voltage regulators which could be suitable for our target applica-

tion. The aim of table 1.5 is to show some meaningful DC parameters used in the LDO

characterization with their respective values. An extensive comparison is performed in

Chapter 4.

It can be noticed that all the LDO regulators operate in a flexible input voltage range,

most exhibit dropout voltages below 360mV , quiescent current values around 100µA

1.4 Motivation and Objectives 17

Figure 1.6: Example of a WSN application [7]

MEMORY PROCESSOR

SENSORS TRANSMISSION /

RECEPTION

POWER SUPPLY

LDO VOLTAGE REGULATORS

MICROCONTROLLER

Figure 1.7: LDO regulators operating in a WSN node

(only [11] has a low quiescent current of 40µA) and load currents of 50 − 100mA. In

addition, it can be observed that the settling time is in the order of µs and it is lower

than 15µs in all the works. For example, in [8] and [11] the settling time is lower than

5µs while the higher settling time is exhibited by [9].

18 Introduction

Parameters Yuan’02 [8] Maloberti’05 [9] Xiangning’10 [10] Lovaraju’13 [11]CMOS Technology (µm) 0.25 0.35 0.18 0.18

Input Voltage VIN (V ) 2.3 − 5.0 3.1 − 3.6 2.1 − 3.6 1.4 − 1.8Output Voltage Vout (V ) 2.0 2.8 1.8 1.2Vout @ Iload,max (V ) 1.94 2.8 1.8 1.2

Dropout Voltage VDO @ Iload,max (mV ) 360 300 300 200Line Regulation (mV

V) 0.3 − − −

Load Regulation (mVmA

) 0.004 − − −Settling time @0.1% and CL (µs) ≤ 5 ≤ 12.5 − ≤ 1.2

PSR @1kHz (dB) −58 −70 − −Compensation capacitance Cc Int.0.5pF Int.− Ext.10µF Int.−

Quiescent current IQ (µA) 99.6 − 100 40Maximum current load Iload,max (mA) 100 100 50 100

Load capacitance CL 300pF 1µF 10µF 100pFArea without PADS (mm2) 0.017 0.26 0.416 0.044

Table 1.5: Some previously reported CMOS LDO voltage regulators

The commonly way to compensate an LDO regulator is using an external load ca-

pacitor in the order of µF as in [9, 10]. Nevertheless, these capacitors cannot be inte-

grated in a single chip manufactured by the actual CMOS technologies. For that reason,

to achieve a fully integrated solution, special internal compensation techniques need to

be considered. However, this increases the circuit complexity and the current consump-

tion.

The aim of this work is to design a fully-integrated LDO voltage regulator to supply

a WSN node, compatible with the actual CMOS technology, optimizing the power

and chip area consumption while keeping an adequate performance in terms of the

meaningful parameters.

General Objective

• To design an internally-compensated Low Dropout Voltage Regulator in a 0.18µm

CMOS standard process exhibiting a good trade-off between its meaningful pa-

rameters, such as the dropout voltage, line regulation, load regulation and settling

time, while optimizing its power consumption. All of these parameters have to

be compared with the previous reported works, in order to have a benchmark.

1.5 Thesis Structure 19

Specific Objectives

• Frequency analysis of LDO voltage regulators and study of the different fre-

quency compensation techniques in order to choose a proper compensation for

the regulator.

• Design of the frequency compensation block chosen, in order to complete a SoC

solution fulfilling the requirements previously mentioned.

• To design at transistor level the internally compensated LDO voltage regulator

in 0.18µm CMOS technology with the following goal specifications: an input

voltage range from 2.1V to 3.3V ; also it has to include a programmable output, so

that the output can be chosen between two values: 1.2V and 1.8V . The values of

load and line regulation should be less than 1mV/mA and 1mV/V , respectively.

In addition, it must be current efficient, that means a quiescent current below

100µA, be compact in terms of chip area and have a good time response to abrupt

changes in current load (≤ 10µs).

• To design a full-custom layout in order to send it to manufacture. In this aspect,

the layout of the pass transistor is crucial because of its rather large size needed

to drive the high load current.

• To characterize the design in post-layout level and to make a comparison with

previously implementations, to better show the contribution of this work.

1.5 Thesis Structure

This thesis is divided in 5 chapters; in all of them, a section is reserved at the end

for the employed bibliography. Chapter 1 is a brief introduction to voltage regulators,

their characteristics and system-level considerations. Also, the objectives of the thesis

are presented here. Chapter 2 shows how the LDO voltage regulator achieves stability

through either external (classical approach) or internal compensation. A brief review of

20 Introduction

previous works is also presented. Chapter 3 illustrates the block level composition of

the proposed LDO voltage regulator, describing how each block was designed and their

performance. Chapter 4 introduces the complete LDO voltage regulator with its post-

layout characterization, taking into account the most important parameters mentioned

in Chapter 1. Finally, Chapter 5 presents the conclusions and final remarks of this work.

Bibliography

[1] G.A. Rincon-Mora, Analog IC Design with Low-Dropout Regulators, Mc Graw

Hill, ISBN 978-0-07-160893-0, 2009.

[2] D. Linden, T.B. Reddy, Handbook of Batteries, Mc Graw Hill, ISBN 0-07-135978-

8, 2002.

[3] G. A. Rincon-Mora, P. E. Allen, A low-voltage, low quiescent current, low drop-out

regulator, IEEE Journal of Solid-State Circuits, vol. 33, pp. 36-44, January 1998.

[4] G.A. Rincon-Mora. Current Efficient, Low Voltage, Low Drop-out regulators, PhD

Thesis, Georgia Institute of Technology, November 1996.

[5] G. A. Rincon-Mora and P. E. Allen. Study and design of low drop-out regulators,

Unpublished article, School of Electrical and Computer Engineering, Georgia In-

stitute of Technology, 1996.

[6] D. Evans, M. McConnell, P. Kawamura, L. Krug. SoC Integration Challenges for

a Power Management/Analog Baseband IC for 3G Wireless Chipsets, Proceedings

of International Symposium on Power Semiconductor Devices and ICs, pp. 77-80,

May 2004.

[7] F. Mieyeville, M. Ichchou, G. Scorletti, D. Navarro and Wan Du, Wireless sensor

networks for active vibration control in automobile structures, IOPscience, Journal

of Smart Materials and Structures, Vol. 21, No. 7, June 2012.

21

22 BIBLIOGRAPHY

[8] Shan Yuan, B. C. Kim, Low Dropout Voltage Regulator for Wireless Applications,

IEEE 33rd Annual Power Electronics Specialists Conference, vol. 2, pp. 421-424,

June 2002.

[9] S.K. Hoon, S. Chen, F. Maloberti, J. Chen, B.A. Aravind, A Low Noise, High

Power Supply Rejection Low Dropout Regulator for Wireless System-on-Chip Ap-

plications, Proceedings of the IEEE Custom Integrated Circuits Conference, pp.

759-762, September 2005.

[10] Fan Xiangning, Bao Kuan, Huang Yanli, Design and Test of a 0.18µm CMOS

Low Dropout Voltage Regulator for WSN RF Chip, International Symposium on

Signals Systems and Electronics, pp. 1-4, September 2010.

[11] C. Lovaraju, A. Maity, A. Patra, A Capacitor-less Low Drop-out (LDO) Regu-

lator with Improved Transient Response for System-on-Chip Applications, 26th

International Conference on VLSI Design and the 12th International Conference

on Embedded Systems, pp. 130-135, January 2013.

Chapter 2

Stability and Frequency Compensation

“No hay un solo tema cientıfico que no pueda ser explicado a nivel popular”.

Carl Sagan

2.1 Introduction

An important issue in LDO voltage regulator design is stability, which is achieved

through appropriate compensation techniques. Compensation can be external or in-

ternal. Generally, external compensation is achieved with a high value capacitor in

the order of µF. As for internal compensation, Miller compensation is one of the most

widely used techniques [1], but other approaches can be found in literature [2]. In this

chapter, the stability issue is introduced and compensation techniques are presented.

2.2 The stability problem

Linear time-invariant (LTI) systems are expected to exhibit two important properties

in its behavior-linearity and time invariance. Linearity of a system refers to its property

of additive superposition. This means that if an input signal x is applied to the system

in order to get an output as X , then the same system with an input signal y achieves

Y . Therefore, the system will yield an output response of magnitude (X + Y ) when

the inputs are x and y together, i.e. (x + y) input. On the other hand, a system is time

invariant if its main parameters do not change over time. It is said that an LTI system

23

24 Stability and Frequency Compensation

is stable if:

• a delimited input applied to the LTI system produces a delimited output re-

sponse.

• an impulse input applied to the LTI system induces an output response which

tends to zero through time.

• all the transfer function poles have real negative part, i.e., they are located in the

left half of the s-plane.

In addition, an LTI system can exhibit relative stability [3]. This kind of stability

measures how fast the system transient response approaches to zero. The shorter the

settling time, the more relatively stable is the system. In this context, a linear voltage

regulator exhibits relative stability. Figure 2.1 illustrates shows the transient behavior

of the circuit if the poles are located (a) in the left half-plane s (LHP ), (b) in the right

half-plane s (RHP ) and (c) on the jω axis.

Stability can be studied by using the Bode plots. It can be determined if a circuit

is stable or not by examining its open-loop gain and phase as a function of frequency.

In the Bode plot analysis, two concepts emerged: gain margin and phase margin. The

gain margin represents the amount by which the open-loop gain can be increased while

stability is maintained. It is the difference between unity gain and the actual gain of

the amplifier at the frequency where the phase reaches 180. The phase margin, in

turn, represents the difference between the phase angle at unity gain frequency and

180. Generally, the amplifier is said to be stable if the gain margin is greater than

6dB and the phase margin is higher than 45 [4]. If at unity gain frequency the phase

exceeds 180, the amplifier will be come unstable. Figure 2.2 shows the Bode plot for

an open-loop amplifier, illustrating the definitions of gain and phase margins.

2.2 The stability problem 25

s plane

s plane

s plane

σ

ω j

ω j

ω j

σ

σ

time

time

time

(a)

(b)

(c)

Figure 2.1: Relationship between pole location and transient response: (a) in the lefthalf-plane, (b) in the right half-plane, (c) on the jω axis

Frequency (Hz)

0 0°

360°

270°

180°

90° Pha

se a

ngle

(de

g)

100

50

0

-50

-100

Mag

nitu

de (

dB)

10 2

10 4

10 6

10 8

10

f u

f 180

Gain margin

Phase margin

d

Figure 2.2: Bode plot of an open-loop amplifier illustrating the gain and phase margin


2.3 Feedback

Although operational amplifiers are designed to have a high open-loop gain, they are

usually used in a negative feedback loop configuration to trade off gain for other more

desirable properties, such as:

• Gain desensitization.- It generates a gain less sensitive to variations in the device

parameters.

• Nonlinearity reduction.- It makes the system more linear.

• Control of input and output impedances. Depending on the feedback topology,

the impedance increases or decreases.

• Increase in bandwidth of the amplifier.

The general structure of a negative feedback loop is depicted in figure 2.3.

Σ +

-

Source A Load

β

x s x i

x f

x o

Figure 2.3: General structure of negative feedback

Four blocks can be distinguished: the signal source, a gain block A, the feedback

block β and the load. Every x represents a signal which can be either a voltage or a

current, depending on the feedback topology. The signals going in and out from the A

and β blocks are given by:

xo = Axin (2.1)

2.3 Feedback 27

xf = βxo (2.2)

In the sum point, xf is substracted from the source signal xs producing:

xin = xs − xf (2.3)

The combination of equations (2.1), (2.2) and (2.3) provides the gain of the feedback

system:

Afeedback =xoxs

=A

1 + Aβ(2.4)

where the quantity Aβ is called the loop gain and the quantity 1 + Aβ is called the

amount of feedback. A case of special interest is when Aβ >> 1, which produces

Afeedback = 1/β, resulting that the gain of the feedback amplifier is entirely deter-

mined by the feedback network [4].

Generally, the type of negative feedback used in the design of LDO voltage regula-

tors is the series-shunt feedback topology, as shown in figure 2.4.

Here, the feedback network consists of resistors RFB2 and RFB1, resulting:

β =VrefVout

=RFB1

RFB2 +RFB1

(2.5)

Therefore, if the open-loop gain of the LDO voltage regulator is high enough and

Aβ >> 1, the closed-loop gain of the LDO regulator is given by:

ACL =VoutVref

=1

β=RFB2

RFB1

+ 1 (2.6)


+

- REF

V IN

Error Amplifier

V OUT

Power Supply

V

Pass Device

I load C C R

R ESR

L

R FB1

R FB2 C L

A

β LOAD

Figure 2.4: LDO classical topology observed as a feedback structure

2.4 Frequency compensation

Amplifiers with a single-pole behavior in the frequency domain are always stable be-

cause their phase margin is never lower than 90. In the case of multi-pole amplifiers,

stability might be compromised and the amplifier could be come unstable. For that

reason, there are some methods that modify the open-loop transfer function (A block)

in order to turn the amplifier stable, which is called frequency compensation.

For illustrative purposes, the simplified schematic diagram of a two-stage amplifier

without compensation is presented in figure 2.5.

V in V out

R C 1 1 R 2 C 2

-gm 1 -gm 2

Figure 2.5: Two-stage amplifier schematic diagram without Miller compensation

2.4 Frequency compensation 29

The location of the poles is given by:

p1 = − 1

R1C1

(2.7)

p2 = − 1

R2C2

(2.8)

The Miller compensation technique consists of adding a compensation capacitor Cc

between the gain stages gm2 and gm1 as shown in figure 2.6.

V in V out

R C 1 1 R 2 C 2

-gm 1 -gm 2

C c

Figure 2.6: Two-stage amplifier schematic diagram illustrating the Miller compensation

The transfer function of the circuit is obtained by drawing the small-signal equiva-

lent as shown in figure 2.7:

V in V out

R C 1 1 R 2 C 2

C c

gm 1 V in gm 2 V 1

V 1

Figure 2.7: Two-stage amplifier small signal equivalent

VoutVin

=gm1R1R2(gm2 − sCc)

1 + sgm2R1R2Cc + s2R1R2[C1C2 + (C1 + C2)Cc](2.9)


The location of the poles and the zero is obtained from eq. (2.9) as:

pd = − 1

gm2R1R2Cc(2.10)

pnd = − gm2CcC1C2 + (C1 + C2)Cc

(2.11)

z =gm2

Cc(2.12)

As it can be seen, the presence of the compensation capacitor Cc produces a pole

splitting, which improves the open-loop phase margin and, therefore, the closed-loop

stability. However, a transmission zero is also added. The zero is located in the right

half-plane s, thus compromising stability. Figure 2.8 shows the location of the poles

and how the Miller compensation splits them.

s plane

σ

ω j

Poles split

gm 2 - R 2 C 2

1 - C 1 + C 2

- R 1 C 1

1

- R 2 C c

1 gm 2 R 1

Figure 2.8: Pole splitting using the Miller compensation

There are three ways to cancel the effect of the zero in the right half-plane: Miller

compensation using a compensation resistor, a voltage follower or a current follower in

series with Cc.

Basically, Miller compensation using either a compensation resistor Rc adds an

2.4 Frequency compensation 31

additional high frequency pole, whereas the dominant and non-dominant poles remain

almost constant and the zero is moved towards:

z =1

Cc(g−1m2 −Rc)

(2.13)

Here, the zero depends on the Rc value and two possibilities arise: if Rc > 1/gm2 then

the zero moves from the RHP to LHP and if Rc = 1/gm2 then the zero moves from the

RHP to high frequencies in the same plane, so that its effect can be neglected. Also, a

pole-zero cancellation can be performed if pnd = z, resulting in:

1

Cc(g−1m2 −Rc)

= − gm2

C1 + C2

(2.14)

Solving this equation, the adequate value of Rc for pole-zero cancellation is found to

be:

Rc ≈C1 + C2 + Cc

gm2Cc≈ C2 + Cc

gm2Cc(2.15)

Miller compensation using a current follower is shown in Fig. 2.9b. It provides almost

the same location for the dominant and non-dominant poles, but it is possible to achieve

a higher bandwidth and the effect of the zero can be canceled by the first non-dominant

pole, as in the former cases. Miller compensation using a voltage follower is shown in

Fig. 2.9c. It provides practically the same location for the dominant and non-dominant

poles, but the zero is now located in the LHP and could also be used to cancel the first

non-dominant pole.

Miller compensation using a voltage or a current follower shows some advantages

but also increases the current consumption and the chip area.


V in V out

R C 1 1 R 2 C 2

-gm 1 -gm 2

C c R c

(a)

V in V out

R C 1 1 R 2 C 2

-gm 1 -gm 2

C c

A I

(b)

V in V out

R C 1 1 R 2 C 2

-gm 1 -gm 2

C c

A V

(c)

Figure 2.9: Three main cases of Miller compensation using: (a) resistor (Rc), (b) cur-rent amplifier (AI) and (c) voltage amplifier (AV )

2.5 LDO regulator Stability Analysis 33

2.5 LDO regulator Stability Analysis

For an LDO voltage regulator to be considered stable, the phase margin has to remain

higher than 20 [5, 6]. Fig. 2.10 shows the LDO regulator scheme. It exhibits two

major poles: the first pole is determined by the error amplifier (EA) output and the

gate capacitance of the pass transistor PT; the second pole is due to the PMOS pass

transistor drain capacitance and the load impedance Zout, i.e., it is load dependent.

+

- REF

V IN

EA

V out

V

PT

R FB1

R FB2

Z OUT

Pole 1

Pole 2

Figure 2.10: LDO Voltage Regulator Scheme

Thus, the LDO voltage regulator exhibits two major poles which are load depen-

dent. Figure 2.11 illustrates the Bode plot analysis of this uncompensated LDO voltage

regulator. It can be observed that the output pole moves towards the origin as a conse-

quence of load changes causing a loss in phase and, thus, instability. A case of special

interest is when the LDO regulator output current demanded by the load is zero. The

reason is that, when the demanded output current decreases, the pole moves towards

the origin, thus reducing the phase margin and, eventually, leading to instability. On

the other hand, when the output current increases, the pass transistor output resistance

decreases, causing that the pole moves away from the origin and the LDO regulator DC


Frequency (Hz)

0 0

360

270

180

90

100

50

0

-50

-100

DC Gain Reduction

Zero Output Current Maximum Output Current

Output Pole Movement

10 2

10 4

10 6

10 8

10

Pha

se (

deg)

M

agni

tude

(dB

)

d

Figure 2.11: Uncompensated LDO regulator Frequency Response

gain reduction. Also, the zero located in the right half-plane causes a loss in phase. Be-

sides, if the LDO regulator reaches 180 in the open-loop Bode plot analysis, stability

is compromised.

The transient response of the uncompensated LDO regulator is depicted in figure

2.12. It is important to remember that the LDO regulator exhibits relative stability,

that is, the circuit transient response establishes at an adequate value after a certain

time due to the feedback loop. However, the transient response exhibits a very large

spike (undershoot) which almost reaches zero voltage. Consequently, it is necessary

to compensate the LDO voltage regulator somehow in order to avoid stability issues as

reduced phase margin and spikes in the transient response. There are two possible ways

to do so: externally and internally. There is a trade-off between them, while external

2.6 External Compensation 35

Out

put C

urre

nt (

mA

)

60

50

40

30

20

10

0

Out

put V

olta

ge (

V)

2.25

1.50

0.75

0.0

time (µs)

20 40 60 80 100

d

Figure 2.12: Uncompensated LDO regulator transient response under loading conditionchanges

compensation requires a huge capacitor at the output node, the internal compensation

consumes more current and chip area but it has the advantage of being fully integrated.

2.6 External Compensation

The simplest method to compensate an LDO regulator classical topology is using a

huge capacitor (approximately µF ) at the output node. For convenience, the topology

is depicted again in figure 2.13a and its open-loop equivalent circuit is shown in figure

2.13b.

As already discussed, the LDO voltage regulator exhibits two major poles. The first

pole is determined by the output resistance and capacitance of the error amplifier and


+

- REF

V IN

Error Amplifier

Feedback Loop

V OUT

Power Supply

V

Pass Device

C L R

R ESR

L

R FB1

R FB2

(a)

+

- REF V

V IN

V OUT

C L

R ESR

Power Supply

R FB1 R FB2 R L

R FB1

R FB2

EA Output Pole

PT Output Pole

r oEA C PT

(b)

Figure 2.13: (a) LDO voltage regulator and (b) equivalent open-loop circuit

capacitance of the pass transistor gate (roEA, CPT ) and the second pole is due to the

output resistance of the PMOS pass transistor (rPT ) along with the feedback resistors

(RFB1,FB2), the load capacitor (CL) and the load resistor (RL). The equivalent series

resistance (rESR) of the load capacitor adds a zero to the loop. The following equations

express the approximate location of the poles and zero:

fpEA =1

2πroEACPT(2.16)

fpout =1

2π(rPT + rESR)CL(2.17)

fzload =1

2πrESRCL(2.18)

As explained in Section 2.5, the most critical case is when the LDO regulator is not

providing current. Figure 2.14 shows the Bode plot analysis of the uncompensated


(dashed line) and the externally compensated (solid line) LDO regulator. It can be

observed that a pole-zero cancellation is performed between the output pole and the

zero generated by the output capacitorCL and its rESR. The values of the load capacitor

are chosen to be in the order of µF and with very small values of the rESR in the order

of mΩ or Ωs. Usually, a minimum value of capacitance is specified. Also, a range of

rESR is specified [7].

Frequency (Hz)

0 0°

360°

320°

280°

240°

Pha

se (

deg)

60

40

20

0

-20

Mag

nitu

de (

dB)

10 2

10 4

10 6

10 8

10

f u

ZERO OUTPUT CURRENT

EXTERNAL ZERO

Uncompensated External compensation

d

Figure 2.14: Classical LDO regulator frequency response under zero output current

If the LDO voltage regulator is analyzed by stages, the open-loop transfer function

of the system can be approximated by:

TFs = GEAGPTGFB

1 + s2πfzload(

1 + s2πfpEA

)(1 + s

2πfpPT

) (2.19)

whereGEA is the error amplifier open-loop gain, whose typical value ranges from 40dB


to 60dB. GPT is the pass transistor open loop gain; since it is a PMOS transistor, its

gain is relatively low, typically 10−20dB. GFB is the gain of the feedback network and

depends on the voltage divider, whose value is calculated from the output and reference

voltage (Vout,Vref ). fpEAis the frequency location of the error amplifier pole, fpPT

is

the frequency location of the pass transistor output and, finally, fzload is the frequency

location of the output zero.

For illustrative purposes, it follows an example. The parameters involved in the

poles and zero calculation are shown in table 2.1, as well as the corresponding values.

Parameter roEA rPT rESR CPT CLValue 7.2kΩ 2.8kΩ 2Ω 87pF 10µF

Table 2.1: Component Values

If the output voltage value is settled to 1.8V and the reference voltage in 1.2V

(typical silicon Bandgap Voltage), GFB can be obtained from:

GFB =VrefVout

=1.2V

1.8V=

2

3≈ 0.7 ≈ −3dB (2.20)

In this case, the values of GEA and GPT , were considered to be 50dB and 12dB,

respectively. Finally, equation (2.19) must be solved to obtain the Bode plot of the

open-loop system, as shown in Fig. 2.15.

Figure 2.15 shows that the LDO voltage regulator is stable, and achieves a min-

imum phase margin value of 20. It can be noticed that the phase margin increases

when the LDO regulator reaches the unity gain frequency. This kind of compensation

is called pole-zero compensation, as the zero introduced by the external capacitor series

resistance is used to cancel the second pole effect.

In this case, the zero and pole locations are found to be:


100

101

102

103

104

105

106

−180

−135

−90

−45

0

Pha

se (

deg)

Frequency (Hz)

−100

−50

0

50

100

Mag

nitu

de (

dB)

Figure 2.15: Example: Transfer Function Bode Plot

fpEA =1

2πroEACPT≈ 254kHz (2.21)

fpPT =1

2π(rPT + rESR)CL≈ 5Hz (2.22)

fzload =1

2πrESRCL≈ 8kHz (2.23)

It can be inferred that the compensation capacitor sets the dominant pole at the output

node. Consequently, the relation fpPT<< fpEA

has to be accomplished. The compo-

nent and gain values are taken from a previous design, from which further information

can be found in Chapter 3. The poles and zero movement through the s plane, when

the demanded output current is zero, is shown in figure 2.16.

If the output current increases, the dominant pole (Pd) moves towards the origin

while the zero (Zex) and the first non-dominant pole (Pnd) move far away from the ori-

gin, thus improving the phase margin.

To verify that the transient response is acceptable, an analysis was performed ap-


s plane

σ

ω j

Poles movement

P nd Z ex P d

Figure 2.16: Poles and zero movement in the external compensation

plying a current step at the output node. Figure 2.17 depicts the transient response of

the externally compensated LDO voltage regulator.

time (µs)

Cur

rent

(m

A)

Out

put V

olta

ge (

V)

2.25

1.50

0.75

0.0

60

50

40

30

20

10

0

20 40 60 80 100

d

Figure 2.17: External Compensation Transient Response

The transient response exhibits an oscillation that decays during the abrupt current

changes. The undershoot and overshoot presented are relatively low, about 300mV


in the worst case. However, this kind of compensation presents the slowest settling

time because of the high output capacitor. Therefore, an extra loop or element may be

needed in order to improve the transient response [8].

To sum up, the use of an external capacitor is very effective for frequency compen-

sation. Some advantages and disadvantages of the use of the external compensation

are:

Advantages

• It is the simplest and most versatile way of compensating an LDO regulator.

• The quiescent current (IQ) of the voltage regulator depends only on the error

amplifier, pass transistor and feedback network current specifications.

• Stability is guaranteed in all the current range required by the load.

Disadvantages

• It requires an external pin to connect the compensation capacitor in the board

(PCB area consumption).

• Its implementation into very small and lightweight portable equipments, such as

cellphones, WSN sensors, GPS and so on, is not possible.

• The rESR value and the characteristics of the capacitor change with frequency,

so its exact value is not guaranteed. This could modify the AC response as well

as the transient response.

External compensation of LDO voltage regulators has been widely used in literature

[9–13]. Nevertheless, it still has the drawback of the integration on SoC because the

external capacitor cannot be integrated along with all the LDO circuitry. In addition,

the rESR value varies depending on the capacitor. For example, a tantalium capacitor is


suitable for this kind of purposes because the value of its rESR does not vary as much

other capacitors like aluminum. Also, it has to be considered the PCB area consumption

and to be selected a good capacitor.

2.7 Internal Compensation

External compensation is practical and very useful only in applications where the PCB

area consumption is not a problem. Also, it is very helpful for general purpose ap-

plication. However, current research is focused on removing the external capacitor

while maintaining stability, good transient response and high PSR performance. The

internally-compensated LDO regulators often are called capacitorless LDOs. Internal

compensation allows the LDO regulator to be fully-integrated with other circuits in the

same system on chip (SoC). This technique does not depend on a huge capacitor at the

output neither on its equivalent series resistance (rESR). In addition, it improves the

transient response of the LDO regulator. The main goal of internal compensation is to

remove the external capacitor from the LDO regulator so as to obtain a fully-integrated

solution while preserving stability.

Let us consider again the uncompensated LDO voltage regulator shown in Fig.

2.10. It is usually desirable to design a singe-pole error amplifier in order to achieve

stability easily. Thus, the configuration has two major poles: one at the LDO regulator

output and other at the error amplifier output, and both are totally load dependent. The

approximated location of the poles is expressed by:

fpout =1

2πReqCL(2.24)

fpEA=

1

2πroEACPT

(2.25)

2.7 Internal Compensation 43

where Req is the equivalent resistance formed by the parallel of the pass transistor

output resistance, the feedback resistance and the load resistance, CL is the load capac-

itance. The roEAis the error amplifier output resistance and CPT is the total equivalent

capacitance at the pass transistor gate. In contrast with the external compensation,

where the output pole is forced to be the dominant pole, internal compensation forces

the error amplifier pole to be the dominant one. Thus, to achieve stability the output

pole has to be placed beyond unity gain frequency (fpout>>fpEA).

Remember from the discussion about the uncompensated LDO regulator that, if the

load current is settled to its minimum value the phase margin is decreased. The output

pole frequency reduces at a faster rate than the error amplifier pole frequency when

reducing load current. Therefore, stability is a major concern for light load conditions.

Internal compensation of LDOs is achieved through Miller and other compensation

techniques. Compensation based on a single active loop needs at least three gain stages

to increase the open loop gain of the LDO, whereas multiple loop configurations are

used to enhance slew rate at the pass transistor gate [14–16]. Next, some internal

compensation techniques are reviewed.

2.7.1 State of the Art

Figure 2.18 shows a basic circuit to provide regulation with an internal Miller compen-

sation capacitor Cm. It can be observed that there is a single loop and the dominant

pole is determined by the Miller capacitor. The first amplifier (A1) is used as the error

amplifier and thus provides regulation. The second amplifier (A2) has two main uses: to

provide the necessary current to charge and discharge the pass transistor and to amplify

the Miller capacitance in order to set the dominant pole. This topology is compensat-

ing the high parasitic capacitance at the pass transistor gate, so the Miller capacitor has

to be very large, e.g. 20 − 50pF [16, 17]. Therefore, the required chip area is highly

increased. An alternative to reduce the required compensation capacitance is to employ

indirect compensation as proposed in [16] and shown in figure 2.19.


REF

V IN

V OUT

Power Supply

R R FB1

R FB2

V

L

A 2 A 1

C m

p 1 p 2

p 3

Figure 2.18: Miller compensation used in LDO regulators

+

- REF

V IN

Error Amplifier

V OUT

Power Supply

V

Pass Device

I load C L R L

R FB1

R FB2

A I

C c

Current Amplifier

i c

V OEA

V F B

Figure 2.19: Miller compensation using capacitance multiplier

The compensation network now includes a current amplifier which amplifies the

current flowing through the Miller capacitorCf and, therefore, its equivalent value. The

capacitance reacts to changes in the output voltages produced by a change in the load


current, generating an equivalent current change flowing through the capacitor. As a

result, the generated current is injected into the pass transistor gate capacitance. The use

of the current amplifier with the Miller capacitor produces a block called differentiator

or derivator. It works as a capacitance multiplier allowing to use a small capacitor and

thus to save a lot of chip area. This block has some advantages like providing AC

compensation and enhancing the load transient response by reducing the undershoots

and overshoots. The small-signal equivalent for this circuit is depicted in figure 2.20.

V g V out

C EA R eq C L

C c

gm 1 V ref gm PT V g

r oEA

A I

Figure 2.20: LDO using capacitance multiplier small-signal equivalent

The locations of the dominant (pd) and first non-dominant (pnd) poles and the zero

(z) are given by:

pd = − 1

roEACEA + (Cceff + CL)Req + gmPT roEAReqCceff(2.26)

pnd = − gmPTCceff(CL + Cceff )CEA

(2.27)

z = − 1

rACceff(2.28)

where roEA and CEA are the equivalent output resistance and capacitance at the output

node of the error amplifier, respectively, CL is the load capacitance, Req is the equiva-

lent resistance at the output node, gmPT is the transconductance of the pass transistor


and rA is the equivalent output resistance of the frequency compensation block. Cceff

is the effective capacitance produced by the compensation capacitor (Cc) multiplied by

the gain of the current amplifier (AI). A pole-zero cancellation can be performed to

improve phase margin and thus provide faster time response to abrupt changes in the

required output current. Figure 2.21 illustrates the poles and zero movement over the s

plane.

s plane

σ

ω j

Poles movement

P nd

Z P d

Figure 2.21: Poles and zero movement when the output current raises

It can be observed that the poles and zero movement is similar to the presented in

the external compensation, as the frequency compensation block is introducing a zero

in the loop too. Also note that there is a trade-off between the current amplifier gain

and its quiescent current, and therefore the transient response. The LDO regulator pro-

posed in this thesis is based on this principle of operation seeking to optimize area and

quiescent current consumption while preserving good line and load regulation, as well

as fast dynamic response.

Finally, let us point out that there are other compensation techniques that avoid the

external capacitor, such as those based on Flipped Voltage Follower (FV F ) [18,19] or

those based on Slew-Rate enhancement circuits which are designed to improve tran-

sient response [20]. However, the FV F is used to control the pass transistor in an


unity closed-loop gain, which means that the output voltage entirely depends on the

reference voltage. On the other hand, the current consumption and the circuit complex-

ity increases using Slew-Rate enhancement circuits.

The main advantages and disadvantages of internal compensation may be summa-

rized as follows:

Advantages

• It provides AC stability and improves transient response.

• It can be fully-integrated in a system on chip (SoC).

Disadvantages

• Current consumption is increased due to the extra block (the current amplifier or

the slew rate enhancement circuit).

• Chip area is increased.


2.8 Conclusions

In this chapter the two main approaches to compensate the LDO voltage regulator have

been reviewed: external and internal. External compensation exhibits great perfor-

mance in current consumption and can reach stability easily. Nevertheless, its use and

implementation is becoming less popular due to the integration levels. Internal com-

pensation has become more popular in modern systems which try to fully integrate the

LDO in great scale systems. In addition, internal compensation provides good perfor-

mance in load and line regulation as well as in transient response.

It depends on the designer to choose a topology and the most adequate compensation

for an LDO voltage regulator. In this thesis, Miller compensation with current ampli-

fication is used as compensation technique since it exhibits the best trade-off between

performances and added circuit complexity.

Bibliography

[1] B. Razavi, Design of Analog CMOS Integrated Circuits, International Edition,

McGraw-Hill, ISBN: 0-07-118815-0, 2001.

[2] B.K. Ahuja, An improved frequency compensation technique for CMOS oper-

ational amplifiers, IEEE Journal of Solid State Circuits, Vol. 18, pp. 629-633,

December 1983.

[3] K.Ogata, Modern Control Engineering, Fourth Edition, Prentice Hall Inc, ISBN:

0-13-060907-2, 2003.

[4] A.S. Sedra, K.C. Smith, Microelectronic Circuits, Fifth Edition, Oxford Univer-

sity Press, ISBN: 0-19-514252-7, 2004.

[5] C. Simpson, A user’s guide to compensating Low-Dropout regulators, Conference

Proceedings Wescon, pp. 270-275, November 1997.

[6] Application Report SNVA020B, AN-1148 Linear Regulators, Theory of Opera-

tion and Compensation, Texas Instruments, pp. 7, May 2013.

[7] E. Rogers, Stability analysis of low-dropout linear regulators with a PMOS pass

element, Application note, Texas Instruments Inc, pp. 10-13, August 1999.

[8] R.J. Milliken, A capacitor-less low drop-out voltage regulator with fast transient

response, Master Thesis, Texas A&M University, December 2005.

49

50 BIBLIOGRAPHY

[9] L. Mays, Intelligent LDO Regulator with External Bypass Control, Application

Note, ON Semiconductor, April 2002.

[10] C. Simpson, LDO Regulator Stability Using Ceramic Output Capacitors, Appli-

cation Note, National Semiconductor, May 2006.

[11] C. Simpson, Linear and Switching Voltage Regulator Fundamentals, Application

Note, National Semiconductor, 2011.

[12] K. Nang Leung, P. K. Mok, Sai Kit Lau, A low-voltage CMOS Low-Dropout

regulator with enhanced loop response, International Symposium on Cicuits and

Systems, Vol. 1, p.p. I-385-I388, May 2004.

[13] Liang-Guo Shen, Xing Zhang, Yuan-Fu Zhao, Tie-Jun Lu, Design of Low-Voltage

Low-Dropout Regulator with Wide-Band High-PSR Characteristic, 8th Interna-

tional Conference on Solid-State and Integrated Circuit Technology, pp. 1751-

1753, October 2006.

[14] K.N. Leung and P.K.T. Mok, A capacitor-free CMOS low-drop-out regulator with

damping-factor-control frequency compensation, IEEE Journal of Solid State Cir-

cuits, Vol. 38, No. 10, pp. 1691-1702, October 2003.

[15] S.K. Lau, P.K.T. Mok and K.N. Leung, A low-dropout regulator for SoC with

Q-reduction, IEEE Journal of Solid State Circuits, Vol.42, No. 3, pp. 658-664,

March 2007.

[16] R.J. Milliken, J. Silva Martınez, E. Sanchez Sinencio, Full On-Chip CMOS Low-

Dropout Voltage Regulator, IEEE Transactions on Circuits and Systems, Vol. 54,

No.9, p.p. 1879-1890, September 2007.

[17] G. Giustolisi, G. Palumbo, E. Spitale, Robust Miller Compensation With Current

Amplifiers Applied to LDO Voltage Regulators, IEEE Transactions on Circuits

and Systems, Vol. 59, No. 9, pp. 1880-1893, September 2012.

BIBLIOGRAPHY 51

[18] R. Gonzalez Carvajal, J. Ramırez-Angulo, A.J. Lopez Martın, A. Torralba, J.A.

Gomez Galan, A. Carlosena, F. Muoz Chavero, The Flipped Voltage Follower: A

Useful Cell for Low-Voltage Low-Power Circuit Design, IEEE Transactions on

Circuits and Systems I: Regular Papers, Vol. 52, No. 7, pp. 1276-1291, July 2005.

[19] Tsz Yin Man, Ka Nang Leung, Chi Yat Leung, P. K. Mok, Mansun Chan. Devel-

opment of Single-Transistor-Control LDO Based on Flipped Voltage Follower for

SoC, IEEE Transactions on Circuits and Systems I, Regular papers, Vol. 55, No.

5, pp. 1392-1401, June 2008.

[20] M. Mojarad, M. Yavari, A Novel Frequency Compensation Scheme for On-Chip

Low-Dropout Voltage Regulators, 18th IEEE International Conference on Elec-

tronics, Circuits and Systems, pp. 318-321, December 2011.

52 BIBLIOGRAPHY

Chapter 3

LDO Regulator Building Blocks

Design

“La mayor parte de las ideas fundamentales de la ciencia son esencialmente sencillas y,

por regla general, pueden ser expresadas en un lenguaje comprensible para todos”.

Albert Einstein

3.1 Introduction

In this chapter the LDO regulator design methodology is described. Each section of the

chapter presents how every single block was designed, illustrating the design consid-

erations as well as the main parameters taken into account. The essential blocks that

make up the LDO regulator are the error amplifier, the pass transistor, the feedback net-

work and the frequency compensation block. It is important to mention that there exist

other extra circuits, such as current limiter circuits, which provide overcurrent protec-

tion, or electrostatic discharge (EDS) protection circuits. The aim of this chapter is to

describe, characterize and optimize each block and then verify how the blocks behave

together within the LDO regulator.

The whole design was implemented in a 1P − 6M 0.18µm CMOS standard process.

The transistors provided operate under two different voltages: 1.8V and 3.3V . In addi-

53

54 LDO Regulator Building Blocks Design

tion, within the two level voltages there are transistors with different threshold voltage

(Vt): low Vt, nominal Vt and zero Vt. The transistors selected in this design have low

Vt and nominal Vt. Table 3.1 illustrates their main parameters. The constant parameter

K ′ = µCox has the same value for all transistors in the technology: K ′n=160µAV 2 and

K ′p=40µAV 2 .

Transistor/Parameter Nominal Vt [V] Low Vt [V] Minimum W [µm] Minimum L [µm] Maximum W [µm] Maximum L [µm]PMOS (3.3V ) −0.662 −0.423 0.24 0.34 100 50NMOS (3.3V ) 0.594 0.314 0.24 0.34 100 50PMOS (1.8V ) −0.427 −0.225 0.24 0.18 100 50NMOS (1.8V ) 0.302 0.016 0.24 0.18 100 50

Table 3.1: Main technology parameters

Next, each building block of the LDO voltage regulator will be described, designed

and characterized.

3.2 Error Amplifier

The error amplifier is one of the most important blocks in the LDO regulator design. Its

main function is to provide regulation through a feedback network, in other words, it

senses the difference between a voltage used as reference and the voltage provided by

the feedback network, providing a stable and constant output proportional to the ampli-

fier’s gain and the voltage difference. There are some cases where the error amplifier

is used in a unit gain loop [1]. Equation (3.1) describes the output voltage of an ideal

error amplifier.

Vout = AV (V + − V −) (3.1)

Generally, an operational transconductor amplifier (OTA) is used as error amplifier,

such as a basic differential pair [2], a folded-cascode amplifier [3], a symmetric OTA

[4], a two-stage amplifier [5] and class AB amplifiers [6]. The gain of single-stage

amplifiers is limited to a value around 30 − 50dB and, as reviewed in Chapter 1, in

3.2 Error Amplifier 55

order to improve line and load regulation a high gain value is required. Therefore, the

use of a two-stage amplifier is proposed here. In figure 3.1 the two-stage OTA used in

the proposed LDO regulator is depicted.

V IN

V IN

V - V +

V Bias V Bias

M C C C

V IN

M 5

M 1 M 2

M 3 M 4

M 7

M 6

V O,EA

Figure 3.1: Two-Stage OTA

It consists of an N-input differential pair and a PMOS common-source output stage.

Frequency compensation is performed through a Miller capacitor in series with a MOS

transistor operating as a resistor. Important aspects here are the OTA current consump-

tion and the open-loop gain. The amplifier is designed to achieve high open-loop gain

with the lowest possible current consumption.

Table 3.2 shows the bias currents and transistor sizing in the designed error ampli-

fier. The channel length was chosen almost five times the minimal size, L = 1.8µm,

in order to increase the output resistance (ro) and, therefore, the gain of the amplifier.

Also, possible variations in current or voltage due to the channel length modulation are

reduced in this way. The error amplifier was designed to be compact and as square as

possible, with a total current consumption of 16.4µA, flowing 3.3µA through M5 and

13.1µA through M6.

Figure 3.2 illustrates the error amplifier layout. The so called interdigitated layout


Transistor Channel Width (W) Operation RegionM1,2 16µm SaturationM3,4 8µm SaturationM5 5µm SaturationM6 16µm SaturationM7 16µm LinearMc 2µm Linear

Table 3.2: Error Amplifier Transistors Sizes

technique was used to improve the matching between transistors. PMOS transistors

(M1,2,7) are located at the top of the layout and NMOS transistors (M3,4,5,6) at the

bottom. The compensation capacitor Cc and the compensation transistor Mc are on

the right. Cc occupies most of the area dedicated to the error amplifier. The most

important parameters obtained from post-layout simulations at minimum VDD = 2.1V

are summarized in table 3.3.

Figure 3.2: Two-Stage OTA Layout (134.06µmx53.27µm)

3.2 Error Amplifier 57

Open-Loop Voltage Gain (AOL) 60dBBandwidth (BW ) 1.5kHz

Gain-Bandwidth product (GBW ) 2.5MHzPhase Margin (φ) 90

Output Resistance (Rout) 1.8 MΩCompensation MOS resistor (Mc) Req ≈150kΩ

Compensation Capacitor (Cc) 1.2pF

Table 3.3: Error Amplifier main parameters at VDD = 2.1V

The error amplifier is over compensated, with a phase margin of 90. This is nec-

essary in order to easily achieve the LDO regulator stability. From table 3.3, it can

be observed that the open-loop gain is somewhat lower than the typical two-stage OTA

gain (> 60dB). This reduced gain is due to the fact that the PMOS transistor of the sec-

ond stage, M7, operates in the linear region when the load current is zero (Iload=0mA).

When the LDO regulator needs to provide current, the source-gate voltage of the pass

transistor connected at the output of the error amplifier increases, that is, the output

voltage VoEA is reduced and M7 enters the saturation region. Therefore, the error am-

plifier open-loop gain and, in consequence, the LDO regulator open-loop gain increase.

Thus, the load and line regulation are improved in the worst dynamic case of operation,

that is, when the LDO regulator is supplying the maximum current value. At this point,

it is important to remember the feedback formula, where the gain block A has to be

high enough in order to get the closed-loop gain given by β. In addition, the low value

of the open-loop gain is large enough to maintain a good performance at low current

load conditions.

To sum up, the error amplifier was designed to operate within a voltage regulator, with

the ability to increase its open-loop gain at great load current conditions, to operate

under a supply voltage range ranging from 2.1V to 3.3V and with low current con-

sumption of 16.4µA. Also the error amplifier layout was done to consume the lowest

possible chip area. In addition, post-layout simulations showed that the error amplifier

main parameters do not vary with changes in VDD.


3.3 Pass Transistor

The pass transistor, shown in Fig. 3.3 was chosen to be a PMOS device because of its

low dropout and low current consumption, as opposed to bipolar and NMOS imple-

mentations.

V IN

V OUT

V O,EA

Figure 3.3: PMOS transistor as pass device

The design constraints are: supply voltage range VDD = 2.1 − 3.3V , maximum

load current Iload = 70mA and bias current Ib = 10µA. As the output voltage is set to

1.8V , the minimum dropout voltage is VDO = 300mV . With all these parameters, it is

possible to estimate the required transistor size. The channel length has to be minimum,

Lmin = 0.34µm (see table 3.1), in order to reduce the parasitic capacitances [4,5]. The

channel width is calculated from:

W =2IloadLminK ′p(VDO)2

(3.2)

W =2(70mA)(0.34µm)

(40µAV 2 )(300mV )2

= 13, 222.22µm (3.3)

The required channel width is therefore 13, 222.22µm, which highly increases the

area of the integrated LDO regulator. In order to have a compact layout, it is necessary

to reduce the transistor channel width (W ). The idea is to build the pass transistor with

several interconnected unit cells of width Wu = 100µm. Thus, a square with eleven

transistors per side, forming a huge transistor with equivalent 12,100µm of channel

3.3 Pass Transistor 59

width, was implemented. Although the channel width from the initial calculations was

reduced, the LDO regulator output performance does not seem to be affected and two

important things are achieved: chip area is reduced and parasitic capacitances are de-

creased.

Figure 3.4 shows the layout of the pass transistor. It consists of groups of six tran-

sistors. This is due to the design rule which dictates the maximum separation between

each transistor and its biasing contacts. Table 3.4 summarizes the most significant pa-

rameters of the pass transistor.

Figure 3.4: Pass transistor layout (244.65µmx211.06µm)

Input Voltage (VIN ) 2.1V − 3.3VMaximum Output Current (Iload) 70mA

Bias current (Ibias) 10µAChannel Width (W ) 12, 100µmChannel Length (L) 0.34µm

Table 3.4: Pass Transistor Parameters


3.4 Feedback Network

Generally, the feedback network consists of two or more resistors operating as a voltage

divider to set the voltage reference. This design in based on two resistors called RFB1

and RFB2, as shown in figure 3.5.

+

- REF

V IN

EA

V out

V

Pass Transistor

R FB1

R FB2

Z OUT

I Req

Figure 3.5: Feedback Network in a LDO regulator schematic

An important issue is the current flowing through them, which has to be minimized

in order to decrease the power consumption. Equation (3.4) illustrates the voltage di-

vider transfer function and equation (3.5) shows the relation between the resistors and

the current flowing through them.

VoutVref

=(Rfb1 +Rfb2)

Rfb1

(3.4)

IReq =Vout

(Rfb1 +Rfb2)(3.5)

where Vout is the LDO regulator output voltage, Vref is the voltage reference and IReq

3.4 Feedback Network 61

is the current through the resistors, which is provided by the pass transistor. It is,

therefore, the minimum current which will drive the pass transistor. Typically, the

current of 10µA is chosen in order to facilitate the switching between operation regions,

in this case, from sub-threshold to saturation region. If equations (3.4) and (3.5) are

solved by replacing Vout=1.8V , Vref=1.2V and IReq=10µA the values for the resistors

are obtained as follows:

RFB1 =VoutIReq

=1.2V

10µA= 120kΩ (3.6)

RFB2 =VoutIReq

−RFB1 =1.8V

10µA− 120k = 60kΩ (3.7)

The 0.18µm CMOS UMC technology provides resistors made of high resistivity (HR)

polysilicon. However, if the resistors were implemented with HR polysilicon the chip

area used would be about 50µmx50µm and it requires matching between resistors.

This approximation was made taking into account that the minimum width for the re-

sistor allowed by the technology is 0.18µm. Typically, as for transistors, the minimum

width is not used in order to avoid changes in the resistor values due to the peripheral

fluctuations and other undesirables effects generated by the fabrication process. In or-

der to build a 60kΩ resistor (RFB2 value), it is approximately needed a width of 1µm

and a length of 56µm. Thus, taking unit squares of 1µmx1µm, the resistance obtained

is R = 900Ω. Placing the unit squares in an array of 8x8, the RFB2 area would be

about 8µmx8µm. Since RFB1 = 2RFB2, the area is duplicated and the approximated

consumption would be 16µmx16µm. The dimensions of geometries fabricated in sil-

icon never exactly match those in the layout, the geometries shrink or expand during

photolithography, etching, diffusion and implantation. Thus, due to the resistors values

depends on their length and width, it has to be include the additional unit squares in

order to get an adequate matching between resistors, the area would be approximated

to 50µmx50µm. So, in order to save area and avoid undesirable effects produced by


the fabrication process, resistors were instead implemented with PMOS transistors con-

nected as diode, as shown in Fig. 3.6 [7]. Transistors in the feedback network belong to

the Low Vt class transistors (VDD = 3.3V and Vt = −0.42V ). The transistors operate

in the saturation region and, because of the diode connection, VSD ≈ Vt +Vov. Assum-

ing that gmRFB1 = gmRFB2 = gmRFB3 = gmRFB, the equivalent series resistance is

Reqf = 3gmRFB

. In each transistor the voltage drop has to be VSD = 600mV and the

current flowing 10µA. As each PMOS device is built in its own N-Well, connection

between the bulk and the source of the transistor is possible, i.e., VSB = 0V and body

effect is eliminated. Replacing the known parameters into MOS quadratic equation and

establishing a channel length of 1µm, a channel width of 12.5µm is obtained. After

simulation, the channel width was adjusted to 10µm in order to obtain the required

VSD = 600mV .

V OUT

M RFB1

M RFB2

M RFB3

V Ref

M S

ENABLE

I bias

Figure 3.6: Feedback Network Schematic

As shown in Fig. 3.6, a Low Vt NMOS transistor operating as a switch was con-

nected in parallel with MRFB1. This transistor allows to select between two voltages

levels, namely 1.2V and 1.8V . When Ms is OFF the network operates as explained,

setting an output voltage of 1.8V . On the other hand, when Ms is ON the transistor

MRFB1 enters the cutoff region and sets the output voltage to 1.2V , that is, equal to

the reference voltage (Vref ). In this way, the proposed LDO regulator is able to provide

3.4 Feedback Network 63

high current and two different output voltages depending on the supply voltage required

by the circuit or system it is meant to drive.

An external signal is necessary to enable the programmable function, switching Ms

according to the needs of the application. Figure 3.7 shows the layout of the feed-

back network. Common-centroid and interdigitated techniques were used in order to

improve matching between transistors. The layout does not show the NMOS transis-

tor operating as a switch, which was included as an extra block in the complete LDO

regulator layout. Table 3.5 summarizes the main parameters of the feedback network.

Figure 3.7: Feedback Network Layout (31.01µmx34.05µm)

Voltage Reference (Vref ) 1.2VOutput Voltage (Vout) 1.8V/1.2V

Bias current (IReq) 10µAChannel Width (W ) 10µmLength Width (L) 1µm

Table 3.5: Feedback network main parameters

The reduction in area consumption when compared to the HP resistors approach is

from 0.0025mm2 for the polysilicon resistors to 0.0009mm2 for the MOS resistors.


3.5 Compensation circuit (Differentiator)

As explained in Chapter 2, a compensation circuit is required to ensure stability and

improve the LDO regulator transient response. The frequency compensation block

consists of a current amplifier, in this case a current mirror, and a compensation capac-

itance. In order to select the appropriate current mirror, simple, cascode and improved

Wilson current mirrors, shown in Fig. 3.8, were tested.

M CM2

V D D

I bias

M CM1

V

bias

D D

I

M CCM1 M CCM2

M CCM3 M CCM4

V D D

bias I

M IWCM4

M IWCM1

M IWCM3

M IWCM2

a) b) c)

I in

I out

I out

I in I in

I out

Figure 3.8: a) Simple , b) Cascode and c) Improved Wilson current mirror

The simple current mirror, shown in fig. 3.8 (a) , is the basic circuit to copy cur-

rent through its branches. Let us assume that transistors MCM1 and MCM2 operate in

saturation region and both have infinite output resistance. The output current Iout is

controlled by VGSCM1, which is equal to VGSCM2. The VGSCM2 can be expressed as

the sum of the threshold voltage (VthCM2) and the overdrive voltage (VovCM2). Thus,

VovCM2 is given by:

VovCM2 = VGSCM2 − VthCM2 =

√2ICM2LCM2

k′WCM2

(3.8)

If both transistors have the same threshold voltage, then VthCM2 = VthCM1. As VGSCM2 =

3.5 Compensation circuit (Differentiator) 65

VGSCM1 it can be inferred that the overdrive voltage of MCM2 is equal to that of MCM1

and therefore:

VGSCM2 = VGSCM1 (3.9)

VthCM2 +

√2ICM2LCM2

k′WCM2

= VthCM1 +

√2ICM1LCM1

k′WCM1

(3.10)

2ICM2LCM2

k′WCM2

=2ICM1LCM1

k′WCM1

(3.11)

Taking into account that ICM2 = Iout and ICM1 = Iin, the output current value is

obtained:

Iout =(W/L)CM2

(W/L)CM1

Iin (3.12)

Ideally, for identical devices where (W/L)CM1 = (W/L)CM2, the gain of the simple

current mirror is unity and VovCM2 should be equal to VovCM1. Here it can be estab-

lished that the gain is dependent of the transistors ratio. Nevertheless, some factors

affect the mirror accuracy, such as channel length modulation, parasitic resistances,

imperfect geometrical matching and the difference between the overdrive voltages of

MCM2 and MCM1. For instance, the input voltage in the simple current mirror is given

by VGSCM1 = VthGSCM1 + VovCM1 whereas the output voltage is given by VDSCM2,

which depends on the generated current and the load connected to the output.

The cascode current mirror, shown in fig. 3.8 (b), exhibits an accurate current gain

and higher output resistance without feedback, but its output swing is limited. From

fig. 3.8 (b), the small-signal output resistance is given by:


ro = roCCM3 [1 + (gmCM3 + gmbCM3) roCCM2] + roCCM2 (3.13)

and the drain to source voltage of M1, VDSCCM1 is expressed as:

VDSCCM2 = VGSCCM1 + VGSCCM4 − VGSCCM3 (3.14)

Thus, if VDSCCM1 = VGSCCM1 and if VGSCCM3 = VGSCCM4 then VDSCCM2 = VDSCCM1.

Under this condition the gain error of the cascode current mirror is zero. However, in

practice, although the transistors are perfectly matched, VGSCCM3 is not exactly equal

to VGSCCM4 unless Vout = VIN because of channel-length modulation. This represents

a systematic error in the current mirror gain.

The input voltage of the cascode current mirror is given by:

VIN = VGSCCM1 + VGSCCM4 (3.15)

Writing VGSCCM1 as a function of the threshold and overdrive voltage, the input

voltage can be rewritten as:

VIN = VthCCM1 + VovCCM1 + VthCCM4 + VovCCM4 (3.16)

Neglecting the body effect and assuming that VovCCM1 = VovCCM4 = Vov and VthCCM1 =

VthCCM4 = Vth, the expression can be reduced to:

VIN = 2(Vth + Vov) (3.17)

On the other hand, the minimal output voltage (Voutmin) required for MCCM3 and


MCCM2 to operate in saturation region is:

Voutmin = VDSCCM2 + VovCCM3 (3.18)

If all transistors have the same overdrive and threshold voltage (ignoring body effect),

then:

Voutmin ≈ Vth + 2Vov (3.19)

One important advantage in the cascode current mirror is that the output resistance

can be increased adding extra cascode stages, which also increases the gain. Never-

theless, adding extra cascode devices increases the input voltage (by another threshold

and overdrive voltage) and the threshold voltage of cascode transistors increases as the

body effect increases. In fact, cascode devices are not suitable for low-voltage applica-

tions.

As for the improved Wilson current mirror, shown in fig. 3.8 (c), it does not exhibit

a systematic error in the current gain but it requires a higher voltage for the sensing

branch. The output resistance in this case is approximately given by:

ro = (2 + gmWM3roWCM1)roWCM3 (3.20)

The systematic error in the current mirror gain is zero due to the insertion of MWCM3.

Neglecting the body effect and assuming equal overdrive and threshold voltages on all

transistors, the minimum output voltage in the improved Wilson current mirror is given

by:


Voutmin = Vth + 2Vov (3.21)

and the input voltage is:

VIN = 2(Vth + Vov) (3.22)

Table 3.6 presents a comparison between the current mirrors taking into account the

typical parameters as current gain (ACA), output swing (∆Vout) and output resistance

(ro) [8].

Configuration Current gain Input Voltage Output Swing Output ResistanceSimple gmCM2

gmCM1VGSCM1 Vov ro

Cascode gmCCM3

gmCCM42(Vth + Vov) Vth + 2Vov gmr2o

Improved Wilson gmWCM3

gmWCM42(Vth + Vov) Vth + 2Vov gmr2o

Table 3.6: Comparison between current mirrors

Although the output swing and output resistance parameters are the same for the

cascode and improved Wilson current mirror, the latter exhibits better performance in

gain because it is not sensitive to changes in the output voltage.

Figure 3.9 shows the IV characteristic for the three mentioned current mirrors. The

channel width and length for all transistors for the current mirrors shown in figure 3.8

is 1µm and 0.8µm, respectively. The input current used in the simulation is 1µA. It

can be observed that the output current is barely the same for the three current mirrors.

However, for the simple current mirror, the slope is higher, which implies a lower

output resistance. For the cascode current mirror, the output current is lower than the

ideal value because of the systematic gain error, but the output resistance increases with

respect to the simple mirror. Finally, as expected the improved Wilson current mirror

shows the best output behavior: high output impedance and no systematic gain error.

For this reason, the improved Wilson current mirror was selected as current amplifier


for the implementation of the compensation block.

Output Voltage V out [ ]

Ou

tpu

t C

urr

ent

[ I o

ut ]

Simple Current Mirror

Improved Wilson Current Mirror Cascode Current Mirror

out V (min)

out V (min)

ov V

Figure 3.9: Output characteristic of the mentioned current mirrors

The current gain and the current consumption must be taken into account in the

design of the differentiator, and clearly represent a trade-off: the higher the gain, the

higher the current consumption. As explained in Chapter 2, current gain is needed to

reduce the required compensation capacitance value, but gain can only be increased at

the expense of power consumption. Figure 3.10 shows the schematic diagram of the

compensation circuit (differentiator), which consists of an NMOS improved Wilson

current mirror and a PMOS simple current mirror, used to obtain the proper current

flow direction (the poles of the current mirror must be far away from the zero generated

by the differentiator and from the dominant pole of the LDO regulator in order to not

affect the frequency response).

It is now necessary to determine the required capacitance value to compensate the

LDO regulator and to scale that value so as to minimize the chip area consumption of

the compensation capacitor. The change in current through the pass transistor is given

by:

∆Imax = ∆VGgmpass (3.23)


M

C c

A1 M A2

M A3 A4

A5 M A6

V IN V IN

M

M

I c

I CA

I BIASc

1:1

40:1

V OUT

V O,EA

Figure 3.10: Frequency compensation Schematic Diagram

where ∆VG is the variation of the voltage at the pass transistor gate and gmpass is the

pass transistor transconductance. If there is a change in voltage at the pass transistor

gate, then the parasitic capacitance CG at the gate suffers a charging process:

∆IGS = ∆VGCG (3.24)

where ∆IGS is the current charging CG. The ∆IGS current is also equal to the current

Ic through the compensation capacitance Cc and is given by:

Ic = ∆IGS = ∆VoutCc (3.25)

where ∆Vout is the change in output voltage due to the change in output current. Using

equations (3.24) and (3.25) and solving for Cc:

Cc =∆VGCG∆Vout

(3.26)

Since ∆VG = ∆Imax/gmpass, according to equation (3.23):


Cc =∆ImaxCG

∆Voutgmpass(3.27)

where CG is the parasitic gate capacitance, which depends on the pass transistor size

(W,L), ∆Vout is the maximum regulated output voltage spike and finally gmpass is the

transconductance value of the pass transistor.

In order to find out the required compensation capacitance, the particular values in

the proposed designed must be considered: ∆Imax is set to be 70mA and the minimum

value of ∆Vout is required to be roughly 200mV as the maximum variation at the output

voltage. CG changes according to the operation region of the pass transistor. When the

pass transistor is cut-off (zero current load):

CG ≈ Cgs + AMpCgd + CEAo ≈ CgsoW + AMpCgdoW + CEAo (3.28)

where Cgdo and Cgso are values provided by the technology. In addition, CEAo is in the

order of femtofarads, so it can be neglected. Cgs and Cgd are the gate-source and gate-

drain capacitance of the pass transistor, respectively. AMP is the open-loop gain of the

pass transistor with typical values in the order of 10dB − 20dB [4]. In this particular

case the open-loop gain of the pass transistor is 12dB. Therefore, the gate capacitance

of the pass transistor in cut-off region is found to be:

CG ≈ CgsW (1 +AMp) + CEAo ≈ (12, 100µm)(2.6 ∗ 10−10 Fm)(1 + 4) ≈ 15.73pF (3.29)

On the other hand, the CG value when the pass transistor is in saturation region (maxi-

mum current load) is:


CG ≈ Cgs + AMpCgd + CEAo ≈2

3CoxWL+ AMpCgdoW + CEAo (3.30)

Replacing the known values in (3.30):

CG ≈ 2

3(4.93 ∗ 10−3 F

m2)(12, 100µm)(0.34µm) + (4)(2.6 ∗ 10−10 F

m)(12, 100µm) (3.31)

CG ≈ 26.10pF (3.32)

As for the pass transistor transconductance, gmpass it changes according to the output

current, which ranges from 0mA to 70mA. To estimate the compensation capacitance,

the worst case, i.e., maximum load current, is considered:

Cc ≈(70mA)(30pF )

(200mV )(400mAV

)≈ 26pF (3.33)

Now, in order to reduce the chip area consumption, this capacitance must be scaled by

a constant value, which will be equal to the required gain (ACA) of the current mirror.

The chosen values for the capacitance and the gain were 1.5pF and 30dB, respectively,

to achieve a good trade-off between area and current consumption. The entire gain is

given by the improved Wilson stage.

The minimum bias current required by the current mirror to operate in saturation

was found to be 0.5µA, so IBIASc = 0.5µA (see figure 3.10). The total current con-

sumption of the mirror is 21.11µA. In table 3.7 the size of the transistors is shown.

A DC analysis by simulation provides the current mirror gain as a relation between

transconductances of transistors MA5 and MA6. If VGSA3=VGSA4 then VDSA5=VGSA6


Transistor Width (W) Large (L)MA1,MA2 2µm 0.8µmMA3,MA6 1µm 0.8µmMA4,MA5 22µm 0.8µm

Table 3.7: Current mirror Transistor Size

and the ratio between Iout and IBIASc is:

IoutIBIASc

=gmA5gmA6

≈ 40 (3.34)

Figure 3.11: Frequency compensation circuit layout (107.76µmx54.150µm)

In figure 3.11 the layout of the compensation circuit is depicted. Post-layout sim-

ulations show a current gain of 30dB and a current consumption of 21.11µA. The

transistor sizing represents a good trade-off between chip area and power consump-

tion. The minimum input voltage where the current mirror operates properly is 2.1V

(minimum value from the input voltage supply). The minimum output voltage is about

1.4V , considering both the threshold voltage of the NMOS transistors and the over-

drive voltage. Finally, the output resistance obtained was 313.86MΩ. At this point, the


designed improved Wilson current mirror satisfies the requirements mentioned and it

represents, together with the compensation capacitor, a good alternative as frequency

compensation block due to the area-power consumption tradeoff.

3.6 Conclusions

In this chapter, the design of each building block of the LDO voltage regulator was

presented. The error amplifier is based on a two-stage OTA. The PMOS transistor at the

output stage operating at triode-edge region. Also, the error amplifier operates under

an input voltage range of 2.1V − 33.V and it has low current consumption. The pass

transistor is huge in order to drive such output current. The layout of the pass transistor

is compact in terms of chip area. Also, transistors that make up the pass transistor are

matched and distributed in a common-centroid configuration. The feedback network

is implemented with PMOS transistors connected as diodes in order to save area and

do not suffer changes in the network as seen previously. The circuit compensation

was based on Miller compensation multiplier capacitance. The current amplifier was

implemented with an improved Wilson current mirror, which compared with the others

simple and cascode mirror, exhibited proper operation under input voltage changes.

Bibliography

[1] T.Y. Man, K.N. Leung, C.Y. Leung, P.K. Mok, M. Chan, Development of Single-

Transistor-Control LDO Based on Flipped Voltage Follower for SoC, IEEE Trans-

actions on Circuits and Systems I, Regular papers, Vol. 55, No. 5, pp. 1392-1401,

June 2008.

[2] R. Tantawy, E. J. Brauer, Performance Evaluation of CMOS Low Drop-Out Volt-

age Regulators, The 47th IEEE International Midwest Symposium on Circuits

and Systems, Vol. 1, pp. I-141-144, July 2004.

[3] P.C. Crepaldi, T.C. Pimenta, R.L. Moreno, E.C. Rodriguez, A Low Power CMOS

Voltage Regulator for a Wireless Blood Pressure Biosensor, IEEE Transactions

on Instrumentation and Measurement, Vol. 61, No. 3, pp. 729-739, March 2012.


Dropout Voltage Regulator. IEEE Transactions on Circuits and Systems, Vol. 54,

No. 9, pp. 1879-1890, September 2007.

[5] C.K. Chava, J. Silva-Martınez, A Frequency Compensation Scheme for LDO

Voltage Regulators, IEEE Transactions on Circuits and Systems I, Regular pa-

pers, Vol. 51, No. 6, pp. 1041-1050, June 2004.



and Systems, Vol. 59, No. 9, pp. 1880-1893, September 2012.

75

76 BIBLIOGRAPHY

[7] V. Majidzadeh, A. Schmid, and Y. Leblebici, A Fully On-Chip LDO Voltage Reg-

ulator for Remotely Powered Cortical Implants, Proceedings of European Solid-

State Circuits Conference, p.p. 424-427, September 2009.

[8] P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and design of analog

integrated circuits, John Wiley & Sons Inc., ISBN 0-471-32168-0, 2001.

Chapter 4

LDO Regulator: Post-layout

Simulation Results

“Lo que importa es el valor del experimento, no su numero”.

Isaac Newton

In this chapter the LDO voltage regulator post-layout simulation results are pre-

sented. Basically, three types of analyze were performed in order to verify the LDO

regulator performance: AC, DC and transient analyze. AC analysis gives information

about the small-signal behavior of the LDO regulator, such as the open-loop gain and

the phase margin, which in turn provide information about the stability of the regulator.

In addition the power supply rejection of the LDO regulator was tested. The DC anal-

ysis provides information about important parameters such as the dropout voltage, the

load and line regulation, the DC performance under changes in temperature and qui-

escent current consumption. The transient analysis gives information about the LDO

regulator output behavior under changes in load current, such as undershoot/overshoot

and settling time. Wherever the results depend on the output voltage Vout, post-layout

simulation results are provided for both possible values Vout = 1.8V and Vout = 1.2V .

77

78 LDO Regulator: Post-layout Simulation Results

4.1 LDO Voltage Regulator Characterization

Figure 4.1 shows the schematic diagram of the LDO voltage regulator. It consists of:

an error amplifier, a pass transistor, a feedback network and a frequency compensation

block, made of a compensation capacitor and a current amplifier.

V IN

V IN

V V

V Bias V Bias

M C C C

V IN

M 5

M 1 M 2

M 3 M 4

M 7

M 6

V OUT

V IN

M PMOS

Bias

M

V

C f

A1

M AB

M A2

M A3 M A4

REF FB

M RFB1 M RFB2 M RFB3

ENABLE

M A5

M S

M A6

V IN V IN

Error amplifier

Feedback network

Frequency compensation

PT

Figure 4.1: Internally-Compensated LDO voltage regulator

Table 4.1 shows the specifications for which the LDO regulator was designed,

which were already considered in the design of each building block.

Parameter ValueInput Voltage Range VIN 2.1V − 3.3V

Output Voltage Vout 1.2V , 1.8VDropout Voltage VDO 900mV , 300mV

Quiescent Current (IQ) ≤ 100µALoad Current (Iload) 70mA

Table 4.1: LDO Voltage Regulator expected parameters

Figure 4.2 illustrates the layout of the complete LDO voltage regulator. The total

4.2 Input-output voltage characteristics 79

chip area consumption is about 0.62mm2 with PADS and 0.17mm2 without PADs. As

it can be noticed, the element which occupies most of the area is the pass transistor.

Figure 4.2: LDO voltage regulator layout (EA: error amplifier; FCB: frequencycompensation block; FBN : feedback network) (with PADs=786µmx800µm, withoutPADs≈450µmx450µm)

The performance of the LDO regulator will be evaluated through post-layout simu-

lations in the next sections. However, it is important to mention that the LDO regulator

elements were placed aligned to the center in order to have a compact and square layout.

4.2 Input-output voltage characteristics

The input-output characteristics of the LDO regulator is obtained by sweeping the DC

input voltage supply, as shown in Fig. 4.3. The characteristics are obtained under


maximum load current conditions (Iload = 70mA) in order to verify the dropout voltage

value.

0 0.5 1 1.5 2 2.5 30

0.5

1

1.5

2

2.5

3

Power Supply (VIN) [V]

OutputVoltage[V

]

VIN

VOUT@70mA

LINEARREGION

VDO = 342mV

VOUT = 1.758V

VDO = 160mV

DROPOUTREGION

(a)

0 0.5 1 1.5 2 2.5 30

0.5

1

1.5

2

2.5

3


OutputVoltage[V

]VOUT@70mA

VIN

VDO = 534mV

VOUT = 1.166V

DROPOUTREGION

VDO = 217mV

LINEARREGION

(b)

Figure 4.3: Input-output characteristics when the output voltage is set to: (a) Vout =1.8V and (b) Vout = 1.2V

It can be observed from Fig. 4.3 that the output voltage remains regulated for an

input voltage ranging from 1.95V to 3.3V , when the output is set to 1.8V , and from

1.6V to 3.3V when it is set to 1.2V .

The dropout voltage can also be extracted from Fig. 4.3. It is a parameter that

provides information about the LDO regulator efficiency. The dropout voltage value

was obtained both the dropout region (VDO = 160mV@V out = 1.5V and VDO =

217mV@Vout = 1.0V ) and at the beginning of linear region (VDO = 342mV@Vout =

1.758V and VDO = 534mV@Vout = 1.166. Recalling Chapter 1, it is said that the

LDO regulator is in the linear region when the output voltage level is high enough so

the LDO regulator can perform its main functions: keep stable the output voltage and

deliver the required current to the load.

4.3 Frequency compensation analysis 81

4.3 Frequency compensation analysis

Although the LDO regulator operates in a DC domain it is important to perform an AC

analysis in order to verify the open-loop gain and the phase margin value. This analysis

provides information about the stability of the regulator and its regulatory capacity

(line and load regulation), due to the feedback topology. Recall from Chapter 2 that the

closed-loop gain is given by the β factor if the open-loop gain is high enough. Thus,

the higher the open-loop gain, the better the regulatory capacity of the LDO voltage

regulator.

+

- REF

V IN

Error Amplifier

V OUT

Power Supply

V

Pass Device

C L R L

A I

C C

Current Amplifier

M RFB1 M RFB2 M RFB3

ENABLE

M S

+

- V

C BIG

L BIG

INP V fb V

AC IN

Figure 4.4: LDO regulator circuit under AC analysis

Figure 4.4 shows the circuit under the AC test. In order to perform this analysis, it

is necessary to consider some extra elements such as, an AC voltage supply, a capacitor

and an inductor. Both the capacitance and the inductor values must be large. The

reason is that the capacitor serves as DC-decoupling between the VINP node and the AC

voltage supply and the inductor serves as a DC-coupling and AC-decoupling between


the VINP node and the Vfb node. This is important because the right LDO regulator the

DC operation point is provided to the regulator whereas the loop is open in AC so as to

analyze the open-loop gain and phase. Figure 4.5 shows the LDO regulator frequency

response at an input supply voltage of (a) 2.1V and (b) 3.3V , load currents of 0mA and

70mA and output voltage set to 1.8V .

100

101

102

103

104

105

106

107

−50

0

50

100

150

Frequency [Hz]

Open

-loopgain

[dB]

100

101

102

103

104

105

106

107

−150

−100

−50

0

50

100

150

200

Frequency [Hz]

Phase

[degrees]

Zero Load Current70mA Load Current

(a)

100

101

102

103

104

105

106

107

−50

0

50

100

150

Frequency [Hz]

Open

-loopgain

[dB]

100

101

102

103

104

105

106

107

−150

−100

−50

0

50

100

150

200

Frequency [Hz]

Phase

[degrees]


Frequency [Hz]

(b)

Figure 4.5: LDO regulator frequency response at (a) VIN = 2.1V , (b) VIN = 3.3V , setboth to Vout = 1.8V , Iload = 0mA (solid line) and 70mA (dashed line)

Unlike other LDO regulators where the open-loop gain is reduced at the maximum

load current [3], the open-loop gain is increased from 90dB to 110dB, providing an

improvement in the load regulation, line regulation and time response. The increase in

gain is due to the output stage of the error amplifier. The output common-source PMOS

is biased in the triode region, at the edge of saturation. Therefore, as the load current

increases, so does the error amplifier open-loop gain.

Table 4.2 illustrates some important data extracted from figure 4.5. The unity gain

frequency (UGF ) increases as the load current increases because of the output pole

4.3 Frequency compensation analysis 83

VIN = 2.1V VIN = 3.3VParameter Iload = 0mA Iload = 70mA Iload = 0mA Iload = 70mA

DC gain ADC (dB) 90 110 88 120Bandwidth BW (Hz) 200 15 275 11

Unit gain frequency UGF (kHz) 800 950 600 812Phase margin PM (Degrees) 40 90 12 56

Table 4.2: AC important parameters from Fig. 4.5

movement, shifting from 800kHz to 950kHz at VIN = 2.1V and from 600kHz to

812kHz at VIN = 3.3V . The UGF indicates the LDO regulator ability to respond fast

to abrupt changes in load current. In fact, the response time is related to the reciprocal

of the UGF , e.g. if UGF = 800kHz then the regulator settling time is approximately

1.25µs [3].

Let us now examine what happens when the LDO regulator is operating with the

maximum input voltage VIN = 3.3V . Figure 4.5 (b) shows the regulator frequency

response in this case. Note that the phase margin for zero load current is reduced to

12. As will be shown later, this results in slower transient response with higher over-

shoot/undershoot and ringing. It can be observed from table 4.2 a pole movement due

to the increase in the input voltage from 2.1V to 3.3V . At VIN = 3.3V the UGF is

lowered down to 600kHz at zero load current, so a settling time in the order of 1.66µs

is expected.

Let us now consider the case when the output voltage is set to Vout = 1.2V . Figure

4.6 shows the regulator frequency response and table 4.3 summarized some important

data.

Although the undershoots observed during the transient response increase, the LDO

regulator operates properly, as will be shown next. In addition, in order to set Vout =

1.2V , the open-loop gain is decreased a little and so is the UGF . In this case, (Vout =

1.2V and VIN = 3.3V ), the LDO regulator stability is compromised, as the phase


100

101

102

103

104

105

106

107

−50

0

50

100

150

Frequency [Hz]

Open

-loopgain

[dB]

100

101

102

103

104

105

106

107

−150

−100

−50

0

50

100

150

200

Frequency [Hz]

Phase

[degrees]


(a)

100

101

102

103

104

105

106

107

−50

0

50

100

150

Frequency [Hz]

Open

-gain

loop[dB]

100

101

102

103

104

105

106

107

−150

−100

−50

0

50

100

150

200

Frequency [Hz]

Phase

[degrees]


(b)

Figure 4.6: LDO regulator frequency response at (a) VIN = 2.1V , (b) VIN = 3.3V , setboth to Vout = 1.2V , Iload = 0mA (solid line) and 70mA (dashed line)

VIN = 2.1V VIN = 3.3VParameter Iload = 0mA Iload = 70mA Iload = 0mA Iload = 70mA

DC gain ADC (dB) 88 117 87 120Bandwidth BW (Hz) 275 15 323 11

Unit gain frequency UGF (MHz) 1 2.8 0.8 1.1Phase margin PM (Degrees) 24 90 2 60

Table 4.3: AC important parameters from Fig. 4.6

margin is only 2.

4.3.1 Power supply rejection (PSR)

Remembering Chapter 1, the PSR is the rejection to changes in the input supply volt-

age. Power Rejection Supply is an AC parameter which expresses the immunity of the

circuit to variations in the input supply and is described by the following equation:

PSR =VoutVIN

(4.1)

4.4 Transient Analysis 85

Figure 4.7 illustrates the PSR of the proposed LDO voltage regulator at (a) VIN =

2.1V and (b) VIN = 3.3V .

100

101

102

103

104

105

106

107

−70

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

Magnitude[dB]

Vout = 1.8V

Vout = 1.2V

(a)

100

101

102

103

104

105

106

107

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

Frequency [Hz]

Magnitude[dB]

Vout = 1.8V

Vout = 1.2V

(b)

Figure 4.7: LDO regulator PSR at (a) VIN = 2.1V , (b) VIN = 3.3V

It can be noticed that the LDO regulator exhibits a PSR value of −57dB at 1kHz

when Vout = 1.8V and −67dB at 1kHz when Vout = 1.2V . On the other hand, taking

VIN = 3.3V and the frequency of interest is 1kHz, the PSR increases until −90dB for

Vout = 1.8V and −95dB for Vout = 1.2V .

4.4 Transient Analysis

In order to verify the LDO regulator transient performance it is necessary to observe

how the output voltage settles when the load current changes. First, the LDO regulator

was tested under minimum input voltage (VIN = 2.1V ) and the current required from

the load changing from 0 to 1mA. Figure 4.8 (a) shows the transient response. It can

be observed that it exhibits an undershoot value of 100mV and an overshoot of 60mV .

The output settling time observed from Fig. 4.8 a) is almost 2µs in the low (L) to

high(H) load current transition and almost 5µs in the H to L transition. Here, it can

be concluded that the settling time is asymmetric due to the UGF shifting, as it was


explained previously.

Fig. 4.8 b) shows the LDO regulator transient response under a load current of

70mA. The large undershoot presented in the current transition from L to H is due

to the fact that the pass transistor has to leave the sub-threshold region and enter the

saturation region. In addition, as it was observed in the AC analysis, the phase margin is

90 which means an increase in the undershoot value. Nevertheless, it can be observed

that the LDO regulator has the ability to respond adequately in less than 2µs in the

worst case from L to H transition and in less than 5µs in the H to L case.


0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.7

1.75

1.8

1.85

OutputVoltage[V

]

a)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.7

1.75

1.8

1.85

OutputVoltage

[V]

d)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

OutputVoltage

[V]

b)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

2.1

2.2

OutputVoltage

[V]

e)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.6

1.65

1.7

1.75

1.8

1.85

1.9

1.95

2

OutputVoltage

[V]

c)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.6

1.65

1.7

1.75

1.8

1.85

1.9

1.95

2

OutputVoltage

[V]

f)

Figure 4.8: Transient response under loading conditions, Vout = 1.8V ; VIN = 2.1V : a)0− 1mA, b) 0− 70mA, c) 1− 70mA; VIN = 3.3V : d) 0− 1mA, e) 0− 70mA, f) 1− 70mA


It can be inferred that the settling time in this case is similar when the load current

is 1mA. Therefore, under an input voltage of 2.1V (minimum input voltage supply)

the settling time will be the same or less for all load current values (from 0 to 70mA).

In addition, simulations were performed under the maximum operation voltage

which value is 3.3V . Figure 4.8 from d) to f) illustrates the obtained results. It can

be observed from d) that the settling time obtained in the current transition from H to

L is approximate the double compared with the above cases. Here, it is observed that

for the H to L current transition presented, the settling time has increased, approxi-

mately from 10µs to 20µs.

Finally, the LDO regulator transient response is verified from a minimum load cur-

rent (1mA) to the maximum load current (70mA) in order to observe what happens

under these transitions. Figure 4.8 c) shows the simulation result under an input volt-

age supply of 2.1V . It can be noticed that the LDO regulator transient response is

improved in the HL current transition case, being the settling time approximately 4µs,

while in the LH current transition, the settling time remains barely in the same order

value. Figure 4.8 f) illustrates the LDO regulator transient response under a load cur-

rent transition from 1mA to 70mA and an input voltage supply of 3.3V . It is similar to

the transient response when the input voltage is 2.1V . Table 4.4 summarizes the data

extracted from figure 4.8 from a) to f).


Case VIN [V ] Iload [mA] Undershoot [mV ] Overshoot [mV ] Tsettling [µs]a) 2.1 (LH) 0-1 100 10 ≤ 2

(HL) 1-0 30 60 ≤ 5b) 2.1 (LH) 0-70 550 0 ≤ 2

(HL) 70-0 100 290 ≤ 5c) 2.1 (LH) 1-70 140 0 ≤ 3

(HL) 70-1 50 110 ≤ 4d) 3.3 (LH) 0-1 120 50 ≤ 2

(HL) 1-0 65 80 ≤ 10e) 3.3 (LH) 0-70 540 40 ≤ 2

(HL) 70-0 210 250 ≤ 20f) 3.3 (LH) 1-70 150 0 ≤ 3

(HL) 70-1 40 160 ≤ 4

Table 4.4: LDO regulator transient parameters, Vout = 1.8V

So far, the 1.8V output has been described and analyzed, however, the LDO regula-

tor has the feature of selecting two output voltages of 1.8V and 1.2V . Next simulations

describe and analyze the LDO regulator transient behavior for the 1.2V case. Figure

4.9 shows the LDO regulator transient response at Vout = 1.2V . Here the transistor MS

of the circuit in figure 4.4 is ON , through a gate voltage equivalent to the input voltage

supply (in this case of simulation VIN = 2.1V ).

It can be noticed from figure 4.9 a) that the settling time obtained in the H to

L current transition is about 6µs. Figure 4.9 c) shows the LDO regulator transient

response at VIN = 2.1V , VENABLE = 2.1V and Iload = 70mA. This can be considered

the worst case of simulation likewise the cases above. Here, it can be observed that the

undershoot obtained in the L toH current transition is about of the same order that the

obtained in the previous cases. It is important to mention that the settling time, so far, it

has been remained constant as it has been observed in the previous simulation results.


0 10 20 30 40 50 60 70 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.05

1.1

1.15

1.2

1.25

1.3

1.35

OutputVoltage

[V]

a)

0 10 20 30 40 50 60 70 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.05

1.1

1.15

1.2

1.25

1.3

1.35

OutputVoltage[V

]

d)

0 10 20 30 40 50 60 70 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 800.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

OutputVoltage

[V]

b)

0 10 20 30 40 50 60 70 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 800.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

OutputVoltage

[V]

e)

0 10 20 30 40 50 60 70 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

OutputVoltage

[V]

c)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

OutputVoltage

[V]

f)

Figure 4.9: Transient response under loading conditions, Vout = 1.2V ; VIN = 2.1V : a)0− 1mA, b) 0− 70mA, c) 1− 70mA; VIN = 3.3V : d) 0− 1mA, e) 0− 70mA, f) 1− 70mA


Figure 4.9 from d) to f) shows the simulation results at VIN = 3.3V at different load

conditions. It can be noticed from Fig. 4.9 b) that the settling time in the H to L case

has increased to 12µs. In addition, the oscillation presented in this current transition is

larger, however, the damping process is performed very fast. Here it can be concluded

that at VIN = 3.3V the oscillation process has increased due to the increase in VIN ,

causing that the time required for the damping is larger than the other cases previously

presented. Figure 4.9 e) presents the worst case of simulation where the LDO regulator

is providing the maximum output current of 70mA. It can be noticed that the settling

time for the L toH case is remained constant and the settling time for theH to L case is

greater than 25µs. The settling time for the H to L case does not exhibit improvement

unlike the other simulation cases previously presented. Table 4.5 summarizes the data

extracted from figure 4.9 from a) to f).

Case VIN [V ] Iload [mA] Undershoot [mV ] Overshoot [mV ] Tsettling [µs]a) 2.1 (LH) 0-1 87.5 25 ≤ 2

(HL) 1-0 25 25 ≤ 6b) 2.1 (LH) 0-70 550 0 ≤ 2

(HL) 70-0 90 250 ≤ 6c) 2.1 (LH) 1-70 125 0 ≤ 3

(HL) 70-1 60 80 ≤ 2d) 3.3 (LH) 0-1 110 20 ≤ 2

(HL) 1-0 55 55 ≤ 12e) 3.3 (LH) 0-70 550 50 ≤ 2

(HL) 70-0 150 290 ≤ 30f) 3.3 (LH) 1-70 150 0 ≤ 3

(HL) 70-1 60 140 ≤ 2

Table 4.5: LDO regulator transient parameters, Vout = 1.2V

4.4.1 Dependency with the load capacitor (CL)

Remembering Chapter 2, the output capacitor is a crucial element in the output pole

movement. In this case, the LDO regulator transient performance was tested at VIN =

2.1V , Iload = 1mA and 70mA when Vout = 1.8V , using a 100pF load capacitor in


both cases. In addition, the performance was tested when there is no load capacitor at

the output node. Figure 4.10 shows the simulation results.

It is important to mention that the LDO regulator operates properly in this range

of values. Nevertheless, the LDO regulator exhibits a poor behavior at the maximum

input voltage range (VIN = 3.3V ) when there is no load capacitor at the output node.

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.7

1.75

1.8

1.85OutputVoltage

[V]

a)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 80

1.7

1.75

1.8

1.85

OutputVoltage

[V]

b)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage

[V]

c)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage

[V]

d)


0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.1

1.15

1.2

1.25

1.3

OutputVoltage[V

]

e)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 800.9

1

1.1

1.2

1.3

1.4

1.5

OutputVoltage[V

]

f)

Figure 4.10: LDO regulator performance at VIN = 2.1V , Iload = 1mA: (a) CL = 0pF ,(b) CL = 100pF , (e) Vout = 1.2V , CL = 100pF and Iload = 70mA: (c) CL = 0pF ,(d) CL = 100pF , (f) Vout = 1.2V , CL = 100pF

It can be noticed that the transient performance is barely the same as the previous

cases. Also, as it was expected, the undershoot value decreased using a larger output

capacitor, being the latter 300mV .

4.4.2 Dependency with temperature

Remembering Chapter 1, it is important to verify the LDO regulator performance under

temperature variations. In this case, the LDO regulator was tested over a temperature

range of −40C to 120C, taking −40C as the minimal temperature value, 0C as

a chosen temperature value, 60C is taken as a nominal operation value (simulations

already made) and finally, 120C is the maximum temperature value. Simulations were

performed at VIN = 2.1V and at Iload = 1mA and Iload = 70mA. Figure 4.11 shows

the simulation results.


0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

1.9

OutputVoltage[V

]

a)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

OutputVoltage[V

]

b)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

1.9

OutputVoltage

[V]

c)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

OutputVoltage

[V]

d)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

1.9

OutputVoltage

[V]

e)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.4

1.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage

[V]

f)

Figure 4.11: LDO regulator temperature performance at VIN = 2.1V , Iload = 1mA:(a) T = −40C, (b) T = 0C, (c) T = 120C and Iload = 70mA: (d) T = −40C, (e)T = 0C, (f) T = 120C

It can be noticed that the LDO transient performance does not seem affected by the

temperature at different load current conditions.


4.4.3 Transient behavior under process variations

It is important to verify the LDO regulator proper operation under process variations.

The process corners fast-fast (FF ), slow-slow (SS), fast N-slow P (FNSP ) and slow

N-fast P (SNFP ) were taken as simulation parameters in order to verify the LDO

transient performance. The LDO performance was tested at VIN = 2.1V and at the

minimal output current Iload = 1mA and the maximum output current Iload = 70mA,

due to this cases are of special interest. Figure 4.12 shows the simulation results.

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

OutputVoltage

[V]

a)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage

[V]

b)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

OutputVoltage

[V]

c)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage

[V]

d)


0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

OutputVoltage[V

]

e)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

Load

Current[m

A]

0 10 20 30 40 50 60 70 801.5

1.6

1.7

1.8

1.9

2

2.1

OutputVoltage[V

]

f)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

0.25

0.5

0.75

1

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.7

1.75

1.8

1.85

OutputVoltage

[V]

g)

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 800

10

20

30

40

50

60

70

Time [µs]

LoadCurrent[m

A]

0 10 20 30 40 50 60 70 801.4

1.5

1.6

1.7

1.8

1.9

2

OutputVoltage

[V]

h)

Figure 4.12: LDO regulator performance at VIN = 2.1V , Iload = 1mA: (a) FF corner,(c) FNSP corner, (e) SNFP corner, (g) SS corner and Iload = 70mA: (b) FF corner,(d) FNSP corner, (f) SNFP corner, (h) SS corner

As it has been reviewed, the LDO transient performance does not seem affected

by the process variations. The case of concern is the corner process SS exhibiting the

largest ringing in the L−H current transition.

4.5 Main characteristics summary

Figure 4.13 illustrates the load regulation VIN = 2.1V and VIN = 3.3V under maxi-

mum load current conditions (Iload = 70mA). The load regulation (LDR) is defined as

the change at the output voltage due to a change at the load current keeping the input

voltage constant:

4.5 Main characteristics summary 97

0 10 20 30 40 50 60 701.755

1.76

1.765

1.77

1.775

1.78

1.785

1.79

1.795

1.8

1.805

Load Current [mA]

OutputVoltage[V

]

Vout= 1.801V

Vout= 1.758V

(a)

0 10 20 30 40 50 60 70

1.165

1.17

1.175

1.18

1.185

1.19

1.195

1.2

1.205

Load Current [mA]

OutputVoltage[V

]

Vout= 1.201V

Vout= 1.165V

(b)

Figure 4.13: LDO regulator load regulation at a) Vout = 1.8V and b) Vout = 1.2V

LDR =∆Vout∆Iload

(4.2)

Solving (4.2) with values from the curves in Fig. 4.13 results in a load regulation

LDR = 0.6mV/mA for Vout = 1.8V and LDR = 0.5mV/mA for Vout = 1.2V , when

the load current changes from 0mA to 70mA.

The line regulation (LNR) is defined as the change at the output voltage in response

to a change in the input voltage at a constant load current. This parameter is usually

tested under the maximum load current, in this case 70mA. The line regulation value

can be extracted from:

LNR =∆Vout∆VIN

(4.3)

Fig. 4.14 shows how the output voltage changes with the input voltage when the LDO

works in the linear region (regulating region). Solving (4.3) with values from the curves


2.2 2.4 2.6 2.8 3 3.21.7578

1.7578

1.7579

1.7579

1.758

1.758

1.7581


OutputVoltage[V

]

(a)

Vout= 1.7580757 V

Vout= 1.7580757 V

2.2 2.4 2.6 2.8 3 3.21.1659

1.166

1.166

1.1661


OutputVoltage[V

](b)

Vout= 1.1660866 V

Vout= 1.1659619 V

Figure 4.14: LDO regulator line regulation at a) Vout = 1.8V and b) Vout = 1.2V

in Fig. 4.14 results in LNR = 0.24mV/V for Vout = 1.8V and LNR = 0.1mV/V for

Vout = 1.2V , at a constant load current of 70mA. Table 4.6 summarizes the quiescent

current consumption of each block. Although the circuit blocks were optimized to

consume the lowest current possible. The current amplifier shows the highest current

consumption due to the required trade-off between stability and power consumption, as

explained in Chapter 2.

Circuit Block Error amplifier PMOS PT Current Amplifier LDO regulator (Total)IQ 16µA 9.66µA 21µA 47µA

Table 4.6: Current consumption of each block

So far, the most important characteristics of the LDO regulator have been evaluated.

It is worth to remember that there is a trade-off between many of these characteristics:

the larger the open-loop gain, the better the line and load regulation; the larger the cur-

rent gain, and therefore the current consumption, in the compensation block, the better

the transient response and the lower the undershoots and overshoots; the higher the

load provided to the current, the larger the pass transistor and the higher the area con-

4.5 Main characteristics summary 99

sumption; and so on. So, to better show the performance of the proposed regulator

a Figure of Merit (FOM ) which relates the settling time (tsettling), the quiescent cur-

rent (IQ), the output current (Iload), the output capacitance (CL) and the compensation

capacitance (Cc) is used [4]:

FOM = tsettling ×IQIload

× CcCL

(4.4)

Table 4.7 shows a summary of all the characteristics of the LDO regulator, both when

the output voltage is set to 1.8V and when it is set to 1.2V at VIN = 2.1V .

Post-layout characteristics Vout = 1.8V Vout = 1.2V

Dropout Voltage VDO @ Iload,max (mV ) 342 940Line Regulation (mV

V) 0.24 0.10

Load Regulation (mVmA

) 0.6 0.5Settling time @0.1% and CL = 50pF (µs) ≤ 5 ≤ 6

Quiescent current IQ (µA) 47 47Maximum current load Iload,max (mA) 70 70

FOM (ns) 0.335 0.402

Table 4.7: LDO voltage regulator DC meaningful parameters, VIN = 2.1V

The LDO regulator exhibits similar DC characteristics independently of the selected

output voltage. However, the transient response is degraded for Vout = 1.2V because

compensation is not effective enough, the phase margin is low and settling time in-

creases. This is also reflected in a worse FOM .

4.5.1 Efficiency

Remembering Chapter I, an important parameter in the LDO regulator characterization

is the current efficiency, which is defined as follows:

ηI =IloadIIN

=Iload

Iload + IQ(4.5)


In this case, replacing Iload = 70mA and IQ = 47µA in equation 4.5, the current

efficiency for the proposed LDO voltage regulator is about 99.93%.

If the quiescent current (IQ) is low, the operational life of the battery and the voltage

regulator efficiency will be maximized. Thus the LDO regulator efficiency is given by:

η =(VIN − VDO)

VINηI =

[1 − VDO

VIN

]ηI (4.6)

Replacing VIN = 2.1V and VDO = 350mV in equation 4.6 the LDO regulator effi-

ciency is about 83.27%.

4.6 Comparison with previously reported works 101

4.6

Com

pari

son

with

prev

ious

lyre

port

edw

orks

Inor

der

tove

rify

the

LD

Ore

gula

tor

perf

orm

ance

itis

nece

ssar

yto

mak

ea

com

pari

son

betw

een

the

mos

tmea

ning

fulp

aram

eter

s

ofth

epr

opos

edL

DO

regu

lato

rand

thos

epr

evio

usly

repo

rted

inth

elit

erat

ure.

Para

met

ers

Cha

va’0

4[1

]L

eung

’04

[2]

Mill

iken

’07

[3]

Giu

stol

isi’

12[4

]Y

inM

an’0

8[5

]M

ing’

12[6

]*P

ropo

sed

LD

OC

MO

STe

chno

logy

(µm

)0.

50.

60.

350.

350.

350.

350.

18In

putV

olta

geVIN

(V)

3.3

1.5−

4.5

31.

2−

1.5

1.2−

1.5

2.5−

42.

1−

3.3

Out

putV

olta

geVout

(V)

2.8

1.3

2.8

1.0

1.0

2.35

1.8

Vout

@I load,max

(V)

2.6

1.29

2.76

0.93

0.98

62.

271.

75D

ropo

utVo

ltageVDO

@I load,max

(mV

)70

021

024

027

020

015

035

0L

ine

Reg

ulat

ion

(mV V

)−

1.23

11−

181

0.24

Loa

dR

egul

atio

n(m

VmA

)−

0.00

850.

8−

0.28

0.08

0.71

4Se

ttlin

gtim

e@

0.1%

andCL

(µs)

≤30

<1

≤15

≤4

<1

<1

≤5

Loa

dca

paci

tanc

eCL

2.2µF

10µF

100pF

1nF

10µF

100pF

50pF

PSR

@1k

Hz

(dB

)−

−−

58−

−−

−57

Com

pens

atio

nca

paci

tanc

eCc

Int.(≤

7pF

)E

xt.(1

0µF

)In

t.(≤

23pF

)In

t.(≤

41pF

)−

Int.

(≤7.

5pF

)In

t.(≤

5pF

)Q

uies

cent

curr

entI

Q(µA

)25

2865

4595

747

Max

imum

curr

entl

oadI load,max

(mA

)16

010

050

5050

100

70A

rea

with

outP

AD

S(mm

2)

−0.

30.

289

0.4

0.04

480.

064

0.17

FOM

(ns)

4.68

70.

280

4.48

40.

147

N/A

0.01

0.33

5∗

Post

-lay

outs

imul

atio

ns.

Tabl

e4.

8:C

ompa

riso

nw

ithpr

evio

usly

repo

rted

LD

Ovo

ltage

regu

lato

rs


The proposed LDO voltage regulator in comparison with previous works exhibits

the lowest line regulation (LNR) and a good FOM value. In addition, the compensa-

tion capacitance is the lowest compared to the other techniques where this capacitance

is required. It is interesting to note that [5] does not use any compensation capacitance;

however, it shows the worst line regulation and the highest power consumption.

Other important parameter is the settling time, which for every work here presented

is about of the same order. It is important to mention that this characterization param-

eter was characterized at the worst case where the LDO regulator is operating at the

lowest input voltage supply and the highest load current consumption. The largest set-

tling time is presented in [1] due to the high load capacitance and the high load current

that provides.

Finally, it is important to notice that all regulators seek to improve the capacity of

providing the highest output current and to reduce the chip area and quiescent current

consumption.

4.7 Conclusions 103

4.7 Conclusions

In this chapter the LDO regulator post-layout simulation results were presented. The

proposed LDO regulator is a versatile option in portable applications because it is able

to provide two output voltages. As it has been proved, the LDO regulator shows an

adequate phase margin for the Vout = 1.8V at all load current conditions. However,

the phase margin degrades at low load current consumption, which results in larger

undershoot/overshoot values. Nevertheless, the regulator settling time is still short,

being the LDO capable of responding adequately to abrupt current changes.

The LDO was also compared with other implementations previously reported in

literature. The proposed LDO regulator exhibits the lowest LNR, which makes it a

proper choice in battery-powered portable applications, where the input voltage VIN is

changing due to the battery discharging. In addition, it presents the lowest compensa-

tion capacitance (Cc) and its quiescent current consumption (IQ) is comparable to the

other works. A Figure of Merit (FOM ) which establish a trade-off between the steady-

state current consumption, the chip area and the transient response, was defined. The

lowest the FOM , the better the trade-off between power consumption, chip area and

settling time, which in turn are directly related to cost, useful life of the battery and fast

response of the LDO.


Bibliography

[1] Chaitanya K. Chava, Jose Silva-Martınez. A Frequency Compensation Scheme

for LDO Voltage Regulators. IEEE Transactions on Circuits and Systems I, Reg-

ular papers, Vol. 51, No. 6, p.p. 1041-1050, June 2004.

[2] K. Nang Leung, P. K. Mok, Sai Kit Lau, A low-voltage CMOS Low-Dropout

regulator with enhanced loop response, International Symposium on Cicuits and

Systems, Vol. 1, p.p. I-385-I388, May 2004.


Dropout Voltage Regulator, IEEE Transactions on Circuits and Systems, Vol. 54,

No.9, p.p. 1879-1890, September 2007.



and Systems, Vol. 59, No.9, p.p. 1880-1893, September 2012.

[5] Tsz Yin Man, Ka Nang Leung, Chi Yat Leung, P. K. Mok, Mansun Chan. Devel-

opment of Single-Transistor-Control LDO Based on Flipped Voltage Follower for

SoC. IEEE Transactions on Circuits and Systems I, Regular papers, Vol. 55, No.

5, 1392-1401, June 2008.

[6] Xin Ming, Qiang Li, Ze-kun Zhou, Bo Zhang, An Ultrafast Adaptively Biased Ca-

pacitorless LDO With Dynamic Charging Control, IEEE Transactions on Circuits

and Systems II, Express Briefs, Vol. 59, No. 1, p.p. 40-44, January 2012.

105

106 BIBLIOGRAPHY

Chapter 5

Conclusions and Future Work

“Cualquier persona que se ha visto seriamente comprometida en el trabajo cientıfico de

cualquier tipo, se da cuenta de que en las puertas de entrada del templo de la ciencia estan

escritas las palabras: debes tener fe. Es una virtud que los cientıficos no pueden prescindir”

Max Planck

In this thesis, an internally compensated Low-Dropout (LDO) voltage regulator was

proposed and designed in a 0.18µm CMOS process.

First, internal and external compensation techniques were studied. External com-

pensation was avoided due to the required high value external capacitor (∼ µF ). In-

ternal compensation, in turn, is the best choice for a SoC system. However, the deal

is to find some technique achieving a good trade-off between the current and chip area

consumption as well as proper operation under low voltage conditions.

As frequency compensation technique, Miller compensation based on current-mode

multiplier capacitance was used. The proper selection of the current amplifier and

Miller capacitor implicates a chip area and current consumption trade-off.

The improved Wilson current mirror exhibited the best performance over the simple

and cascode current mirrors in terms of output resistance and gain accuracy. In this par-

ticular case, a simple PMOS current mirror connected to the improved Wilson current

107

108 Conclusions and Future Work

mirror is necessary to invert the current from the compensation capacitor. The current

gain (AI) of the current amplifier is determined by the required compensation capaci-

tance Cc. In this case, the gain was set to AI = 30dB and the capacitance Cc = 1.5pF ,

to achieve a good area-power consumption trade-off.

The proposed LDO voltage regulator consist of an error amplifier, a pass transistor,

a feedback network and the frequency compensation block. Two output voltages can

be selected depending on the input voltage of the load circuits either 1.2V or 1.8V . The

design and post-layout characterization were performed in 0.18µm CMOS technology.

The input voltage is VIN = 2.1V − 3.3V with a Vref = 1.2V . The load and line

regulation are LDR = 0.714mA/V and LNR = 0.24mV/V . The dropout voltage

is 350mV , the quiescent current is IQ = 47µA and PSR = 57dB@DC. Effective

frequency compensation results in good transient response. Settling time was found to

be lower than 20µs in all cases.

Finally, a comparison between previously reported works and the proposed LDO

voltage regulator was done. It was found that the proposed LDO exhibits the best

line regulation and the smallest compensation capacitance, which implies reduced chip

area. A Figure of Merit representing the trade-off between area, power consumption

and settling time also shows that the proposed LDO is competitive with the state-of-

the-art implementations.

5.1 Future work 109

5.1 Future work

• Perform the experimental characterization of the integrated prototype to verify

its proper operation and main characteristics.

• Design an over-current protection circuit which operates only if the current de-

manded by the load is higher than the output current that the LDO regulator can

provide.

• Explore different alternatives to compensate the LDO regulator either using cur-

rent amplifiers, feedforward configurations or Miller variations, aiming to in-

crease the phase margin which directly impacts the transient response.

110 Conclusions and Future Work

List of figures

1.1 a)Switching and b) Linear Voltage Regulator . . . . . . . . . . . . . . 5

1.2 Classical LDO Voltage Regulator . . . . . . . . . . . . . . . . . . . . . 6

1.3 Input-Output Voltage Regulator Response . . . . . . . . . . . . . . . . 7

1.4 Pass Devices Configurations . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 Example of a power efficient system . . . . . . . . . . . . . . . . . . . 15

1.6 Example of a WSN application [7] . . . . . . . . . . . . . . . . . . . . 17

1.7 LDO regulators operating in a WSN node . . . . . . . . . . . . . . . . 17

2.1 Relationship between pole location and transient response: (a) in the

left half-plane, (b) in the right half-plane, (c) on the jω axis . . . . . . . 25

2.2 Bode plot of an open-loop amplifier illustrating the gain and phase margin 25

2.3 General structure of negative feedback . . . . . . . . . . . . . . . . . . 26

2.4 LDO classical topology observed as a feedback structure . . . . . . . . 28

2.5 Two-stage amplifier schematic diagram without Miller compensation . . 28

2.6 Two-stage amplifier schematic diagram illustrating the Miller compen-

sation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.7 Two-stage amplifier small signal equivalent . . . . . . . . . . . . . . . 29

2.8 Pole splitting using the Miller compensation . . . . . . . . . . . . . . . 30

2.9 Three main cases of Miller compensation using: (a) resistor (Rc), (b)

current amplifier (AI) and (c) voltage amplifier (AV ) . . . . . . . . . . 32

2.10 LDO Voltage Regulator Scheme . . . . . . . . . . . . . . . . . . . . . 33

111

112 LIST OF FIGURES

2.11 Uncompensated LDO regulator Frequency Response . . . . . . . . . . 34

2.12 Uncompensated LDO regulator transient response under loading con-

dition changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.13 (a) LDO voltage regulator and (b) equivalent open-loop circuit . . . . . 36

2.14 Classical LDO regulator frequency response under zero output current . 37

2.15 Example: Transfer Function Bode Plot . . . . . . . . . . . . . . . . . . 39

2.16 Poles and zero movement in the external compensation . . . . . . . . . 40

2.17 External Compensation Transient Response . . . . . . . . . . . . . . . 40

2.18 Miller compensation used in LDO regulators . . . . . . . . . . . . . . 44

2.19 Miller compensation using capacitance multiplier . . . . . . . . . . . . 44

2.20 LDO using capacitance multiplier small-signal equivalent . . . . . . . . 45

2.21 Poles and zero movement when the output current raises . . . . . . . . 46

3.1 Two-Stage OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.2 Two-Stage OTA Layout (134.06µmx53.27µm) . . . . . . . . . . . . . 56

3.3 PMOS transistor as pass device . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Pass transistor layout (244.65µmx211.06µm) . . . . . . . . . . . . . . 59

3.5 Feedback Network in a LDO regulator schematic . . . . . . . . . . . . 60

3.6 Feedback Network Schematic . . . . . . . . . . . . . . . . . . . . . . 62

3.7 Feedback Network Layout (31.01µmx34.05µm) . . . . . . . . . . . . . 63

3.8 a) Simple , b) Cascode and c) Improved Wilson current mirror . . . . . 64

3.9 Output characteristic of the mentioned current mirrors . . . . . . . . . . 69

3.10 Frequency compensation Schematic Diagram . . . . . . . . . . . . . . 70

3.11 Frequency compensation circuit layout (107.76µmx54.150µm) . . . . . 73

4.1 Internally-Compensated LDO voltage regulator . . . . . . . . . . . . . 78

4.2 LDO voltage regulator layout (EA: error amplifier; FCB: frequency

compensation block; FBN : feedback network) (with PADs=786µmx800µm,

without PADs≈450µmx450µm) . . . . . . . . . . . . . . . . . . . . . 79

LIST OF FIGURES 113

4.3 Input-output characteristics when the output voltage is set to: (a) Vout =

1.8V and (b) Vout = 1.2V . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.4 LDO regulator circuit under AC analysis . . . . . . . . . . . . . . . . . 81

4.5 LDO regulator frequency response at (a) VIN = 2.1V , (b) VIN = 3.3V ,

set both to Vout = 1.8V , Iload = 0mA (solid line) and 70mA (dashed

line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.6 LDO regulator frequency response at (a) VIN = 2.1V , (b) VIN = 3.3V ,

set both to Vout = 1.2V , Iload = 0mA (solid line) and 70mA (dashed

line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.7 LDO regulator PSR at (a) VIN = 2.1V , (b) VIN = 3.3V . . . . . . . . . 85

4.8 Transient response under loading conditions, Vout = 1.8V ; VIN = 2.1V : a)

0−1mA, b) 0−70mA, c) 1−70mA; VIN = 3.3V : d) 0−1mA, e) 0−70mA,

f) 1− 70mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.9 Transient response under loading conditions, Vout = 1.2V ; VIN = 2.1V : a)

0−1mA, b) 0−70mA, c) 1−70mA; VIN = 3.3V : d) 0−1mA, e) 0−70mA,

f) 1− 70mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.10 LDO regulator performance at VIN = 2.1V , Iload = 1mA: (a) CL =

0pF , (b) CL = 100pF , (e) Vout = 1.2V , CL = 100pF and Iload =

70mA: (c) CL = 0pF , (d) CL = 100pF , (f) Vout = 1.2V , CL = 100pF 93

4.11 LDO regulator temperature performance at VIN = 2.1V , Iload = 1mA:

(a) T = −40C, (b) T = 0C, (c) T = 120C and Iload = 70mA: (d)

T = −40C, (e) T = 0C, (f) T = 120C . . . . . . . . . . . . . . . . 94

4.12 LDO regulator performance at VIN = 2.1V , Iload = 1mA: (a) FF

corner, (c) FNSP corner, (e) SNFP corner, (g) SS corner and Iload =

70mA: (b) FF corner, (d) FNSP corner, (f) SNFP corner, (h) SS

corner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.13 LDO regulator load regulation at a) Vout = 1.8V and b) Vout = 1.2V . . 97

4.14 LDO regulator line regulation at a) Vout = 1.8V and b) Vout = 1.2V . . 98

114 LIST OF FIGURES

List of tables

1.1 Comparison between Batteries . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Comparison between a voltage reference and voltage regulator . . . . . 3

1.3 Linear Regulator vs Switching Regulator . . . . . . . . . . . . . . . . . 5

1.4 Comparison of pass device structures . . . . . . . . . . . . . . . . . . . 9

1.5 Some previously reported CMOS LDO voltage regulators . . . . . . . . 18

2.1 Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.1 Main technology parameters . . . . . . . . . . . . . . . . . . . . . . . 54

3.2 Error Amplifier Transistors Sizes . . . . . . . . . . . . . . . . . . . . . 56

3.3 Error Amplifier main parameters at VDD = 2.1V . . . . . . . . . . . . 57

3.4 Pass Transistor Parameters . . . . . . . . . . . . . . . . . . . . . . . . 59

3.5 Feedback network main parameters . . . . . . . . . . . . . . . . . . . 63

3.6 Comparison between current mirrors . . . . . . . . . . . . . . . . . . . 68

3.7 Current mirror Transistor Size . . . . . . . . . . . . . . . . . . . . . . 73

4.1 LDO Voltage Regulator expected parameters . . . . . . . . . . . . . . . 78

4.2 AC important parameters from Fig. 4.5 . . . . . . . . . . . . . . . . . 83

4.3 AC important parameters from Fig. 4.6 . . . . . . . . . . . . . . . . . 84

4.4 LDO regulator transient parameters, Vout = 1.8V . . . . . . . . . . . . 89

4.5 LDO regulator transient parameters, Vout = 1.2V . . . . . . . . . . . . 91

4.6 Current consumption of each block . . . . . . . . . . . . . . . . . . . . 98

115

116 LIST OF TABLES

4.7 LDO voltage regulator DC meaningful parameters, VIN = 2.1V . . . . 99

4.8 Comparison with previously reported LDO voltage regulators . . . . . . 101

Documents

A 0 18 m CMOS Internally-Compensated Low-Dropout Voltage ... · Internally-Compensated Low-Dropout Voltage Regulator By ... The massive proliferation of battery-operated portable