IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1281

A 110-nm CMOS 0.7-V Input Transient-EnhancedDigital Low-Dropout Regulator With 99.98%

Current Efficiency at 80-mA LoadTak-Jun Oh and In-Chul Hwang, Member, IEEE

Abstract— This paper presents a digital low-dropout regulator(D-LDO) with a proposed transient-response boost technique,which enables the reduction of transient response time, as well asovershoot/undershoot, when the load current is abruptly drawn.The proposed D-LDO detects the deviation of the output voltageby overshoot/undershoot, and increases its loop gain, for thetime that the deviation is beyond a limit. Once the outputvoltage is settled again, the loop gain is returned. With theD-LDO fabricated on an 110-nm CMOS technology, we measuredits settling time and peak of undershoot, which were reducedby 60% and 72%, respectively, compared with and withoutthe transient-response boost mode. Using the digital logic gates,the chip occupies a small area of 0.04 mm2, and it achievesa maximum current efficiency of 99.98%, by consuming thequiescent current of 15 µA at 0.7-V input voltage.

Index Terms— Current efficiency, cyclic TDC, digitallow-dropout regulator (D-LDO), fast transient response,transient-response boost mode (TRBM), voltage-to-timeconverter (VTC).

I. INTRODUCTION

AS PORTABLE and battery-powered devices are requiredto include more various applications than ever, SOCs

for this purpose are competing with each other to integratemore features at less power consumption, even aided by energyharvesting, because the total energy available from a batteryis limited in capacity [1], [2]. This trend imposes a greaterdesign burden on the power management unit (PMU), becauseit should drive superthreshold to subthreshold logic gatesaccording to various power-saving techniques with its availablepeak power efficiency.

The on-chip LDO regulators are gaining more attention asa dedicated PMU for the near-threshold/subthreshold logiccircuits [3], since they can supply more stable and precisevoltage despite lower power efficiency, compared with theswitching regulators [4], [5].

Manuscript received January 16, 2014; revised May 12, 2014; acceptedJune 23, 2014. Date of publication July 16, 2014; date of current versionJune 23, 2015. This work was supported by the Basic Science ResearchProgram through the Ministry of Education, National Research Foundationof Korea, under Grant 2014R1A1A4A01008906.

T.-J. Oh was with the Department of Electrical Engineering, KangwonNational University, Chuncheon 200-701, Korea. He is now withMagnachip Semiconductor Corporation, Seoul 100-712, Korea (e-mail:tjoh@kangwon.ac.kr).

I.-C. Hwang is with the Integrated Circuits and Systems Laboratory,Department of Electrical Engineering, Kangwon National University,Chuncheon 200-701, Korea (e-mail: ihwang@kangwon.ac.kr).

Digital Object Identifier 10.1109/TVLSI.2014.2333755

The power efficiency of an LDO regulator is decided by thedrop-out voltage and its current efficiency, given by the ratiobetween quiescent current and load current. Conventionalanalog LDO regulators (A-LDO) exhibit difficulties inmaintaining the low drop-out voltage when driving thenear-threshold and subthreshold logic circuits, because thestacked transistors are needed for high precision. To makematters worse, the quiescent current should be increased inproportion to the load current, because more bias current isconsumed to drive bigger power transistors [6].

The D-LDO regulators offer better opportunity in terms ofthese issues due to the use of digital logic gates, continuouslyenhanced by process scaling [4]–[11].

Also, the digital segmentation of a big power transis-tor enables for D-LDO to avoid the consumption of staticquiescent current for static load current, because the minimizednumber of bits are toggled to keep the output voltage once theD-LDO is settled to a target value, so it makes the quiescentcurrent independent of load current.

For the power-efficient D-LDO, a simple structurecomposed of binary comparator and shift register is widelyused, due to the low-level quiescent current [4]–[7]. But, thissuccessive approximation register (SAR)-like operation causesslow loop-tracking speed, because the loop value is updatedby a small fixed step at every clock. Therefore, the onlysolution to speed up transient response, is to increase theclock frequency [10]. The work in [7] solves this problem,using the asynchronous shift register, instead of the typicalsynchronous shift registers. But, it still has a problem, inthat circuit operation is too sensitive to PVT variation, to getconstant performance between chips.

A multibit ADC can provide faster loop operation throughdirect measurement of the voltage difference. Also, it allowsfor designers to implement the algorithms of more complexloop compensation and loop acceleration [8]–[10].

The work in [8] is designed with a direct conversion ofA-LDO into D-LDO using a SAR-type ADC and a separateDAC driving a single power transistor. But, this design isnot power-efficient because its complex design consumesadditional quiescent current. Another work in [9] employsa TDC-based 4-b ADC and a PID controller for stabilitycompensation. In this design, the performance of fast transientresponse is achieved through dynamic clock scaling fromnormally 250 MHz to 1 GHz.

Thus, it consumes big quiescent current of 2.5 mA. In [10],the three-level ADC designed with TDC provides the control

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1282 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 1. (a) Block diagram of the proposed D-LDO. (b) Operational waveform.

of charging, discharging, and holding the gate of the powerMOS, respectively, without a PID controller. But, highervoltage ripple is caused by the insufficient resolution of powerMOS.

Therefore, the D-LDOs focused on low-level quiescentcurrent have a limit to improve the driving capability andtransient response, on the contrary, the schemes having high-level driving capability consume more quiescent current thanneeded.

In this paper, we propose a new scheme of power-efficientdigital linear LDO regulator based on a multibit cyclicTDC for high-level current efficiency, while targeting ondriving super-to-near-threshold logic gates. To compensate forthe degraded transient performance, we propose a transient-response boost circuit, which detects undershoot/overshootduring transient response, and creates additional asynchronousclocks only during that time.

The overall structure and operation principle are presentedin Section II. Section III presents the implementation ofmajor circuits. The measurement results and conclusions aredescribed in Sections IV and V, respectively.

II. PROPOSED D-LDO REGULATOR WITH

TRANSIENT- RESPONSE BOOST MODE

A. Structure and Principle of Operation

Fig. 1(a) shows a block diagram of the proposedD-LDO, which consists of a voltage-to-time converter (VTC),phase and polarity detector (PPD), a cyclic TDC, anUP/DN counter, and a 9-b binary-weighted pMOS array.With the time resolution of logic gates enhanced more indeep-submicrometer CMOS processes, a time-domain ADCcan provide higher resolution at low power and small area,than a voltage-mode or a current-mode ADC.

Fig. 2. Tradeoff issue between transient response and voltage ripple.

For power-efficient design, we employ a multibit cyclicTDC, since it provides fine resolution with less quiescentcurrent and smaller area, than a flash-type TDC.

First, in this diagram, Vref and Vout are converted to apair of pulse streams, φref and φout, through the proposedVTC, where the duty of each pulse is linearly modulated,according to the magnitude of the input voltage. Fig. 1(b)shows a set of the operational waveforms, starting from theoutput of the VTC. The time difference between φref and φout,implying the voltage difference between Vref and Vout, ismeasured by the phase detector as φerr, and then digitized bythe cyclic TDC. In operation detail, the cyclic TDC repeatedlyshrinks the pulsewidth of φerr once a cycle of referenceclock, until the pulsewidth fully disappears. The entire numberof cycles operated in this way is stored in the followingUP/DN counter, and controls the binary-weighted 9-b switchtransistors. In our design, the UP/DN counter is not reset tozero, but keeps the previous counted value at the end of thereference cycle in our design, and thus, it works as a low-passfilter, as well as a part of the cyclic TDC.

B. Transient-Response Boost Mode (TRBM) Operation

Fig. 2 illustrates a typical response of digital regulators toa step change of the load current. When the load current(IL ) jumps up from a steady-state condition, as shown inFig. 2, Vout is instantly dropped, since the current is drawnfrom CL , which is much faster than adjusting the gate of thepower transistor, through the loop response operating at clockfrequency.

The D-LDO takes over the loop control, to correct Voutafter the delay of τ f , inversely proportional to the closed-loop bandwidth. With this property, we need to increase thebandwidth to reduce τ f , and to reduce the peak undershootat the same time. This goal can be achieved by increasingthe overall size of the pMOS transistors, assuming that all theother loop conditions are kept unchanged. However, it causesthe voltage ripple to increase, which is unavoidable in suchD-LDO regulators.

To solve this tradeoff issue, we employed a gain-boostingtechnique activated only for the transient period, whichis named the transient-response boost mode (TRBM). TheTRBM detector [Fig. 1(a)] monitors the magnitude of theundershoot/overshoot, then it controls our D-LDO to increase

OH AND HWANG: 110-nm CMOS 0.7-V INPUT TRANSIENT-ENHANCED D-LDO REGULATOR 1283

Fig. 3. Circuit diagram of the proposed VTC.

Fig. 4. Circuit diagram of PPD.

the loop gain as needed, if Vout goes beyond a predeterminedboundary condition. Once Vout is reduced to within the bound-ary values, the loop gain returns to smaller normal value.

III. CIRCUIT DESIGN

A. Voltage-to-Time Converter

Fig. 3 shows a simplified circuit diagram of the proposedVTC, which consists of a half-period sawtooth generator, and avoltage comparator. While ck is low, C1 and C2 are charged byIM2 and IM3, until Va and Vb reach VDD, and then Va and Vb

are reset to zero as ck goes high.Using the half-period sawtooth clocks generated in this

block, the comparators create the clocks of φref and φout, withtheir duty ratio modulated by Vref and Vout, respectively.

With this circuit, Vout is settled to the following value, sincethe rising edges of φref and φout are forced to be aligned inphase by the following PPD:

Vout = IM3 · C1

IM2 · C2Vref . (1)

As given above, the ratio between IM2 and IM3 determinesthe output voltage, assuming the use of the same capacitors.This design offers a good solution to trimming Vout with fineresolution, as it is enabled in the current-mode DACs.

B. Phase and Polarity Detector

Fig. 4 shows a three-state phase-frequency detector (PFD)with polarity detector. The PFD is composed of two D flip-flops with asynchronous reset, AND, and OR gates. If φref goes

Fig. 5. Block diagram of cyclic TDC and the TRBM detector.

to HIGH, while all the D flip-flops keep LOW, Q of DFF0 israised to HIGH. If this event is followed by a rising transitionon φout, Q of DFF1 goes to HIGH as well, then the AND gateresets both the flip-flops (DFF0 and DFF1) to LOW after thebuffer delay of τd , an intentionally made delay, to remove thedead-zone problem in the cyclic TDC. The polarity detectoris implemented with a single D flip-flop (DFF2). This circuitdiscerns the first-coming clock between φref and φout, whichrepresents that the corresponding voltage is lower than theother. As an example, if φref is faster than φout, i.e., Vref islower than Vout, the output of up/down is set to LOW, so thatthe counter is decremented.

C. Cyclic TDC and TRBM Detector

Fig. 5 shows a circuit detail of the cyclic TDC and theTRBM detector.

The TRBM detector triggers the output (boost) HIGH, whenthe time difference between φref and φout is increased beyondτD or more, which means that Vout deviates from a presetboundary, because of the overshoot/undershoot during thetransient response. If we assume that C1, C2 have a commonvalue of CC , and IM2, IM3 have a common value of IC ,respectively, τD can be converted back to voltage difference,as Vτ D

Vτ D = IC

CCτD. (2)

Therefore, Vref ± Vτ D is the upper and lower boundaryvoltage to trigger TRBM. The cyclic TDC consists of theeight-stage delay cells (D 0–D7, among which one cell hasthe delay skew by Tres, between its rising and falling delays.Therefore, the pulsewidth of φerr is shrunk by Tres per rotation.

In normal mode, the cyclic TDC produces a single pulse perturn of the delay loop, and thus the number of clock pulsesrepresents the cycles for which φerr are rotated through thedelay chain, until the pulse on φ7 disappears [11].

Sharing the delay cells for resolution of each bit in this wayresults in good linearity, as well as the basic advantage of thepower and area efficient design, since the mismatch betweendelay cells is repeated equally for each bit. Also, it providesa wide dynamic range, because the dynamic range is limited

1284 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 6. Small-signal model for the proposed D-LDO.

by the number of bits in the UP/DN counter, not by the totaldelay range of TDC.

Once TRBM is entered, the number of pulses in φcnt ismultiplied four times, by tapping the nonoverlapped clocks(D1, D3, D5, and D7) from the intermediate nodes of thedelay chain. This leads to effectively increasing the loop gainby four times, and thus accelerating the loop operation.

With this scheme, we can reduce the overshoot/undershooton Vout, without any detrimental effect on the ripple after theloop settles down. It should be noted that this performanceis achieved by just an UP/DN counter, not by more complexadders and multipliers.

D. Small-Signal Analysis

Fig. 6 shows the small-signal model for the proposedD-LDO, where Cc and Ic are the common values in VTCas assumed above, and Tres represents the resolution of theTDC. Using this model, we can get the steady-state open-looptransfer function O(s) in s-domain, as follows:

O(s) = H0e−s/ fref

s

1 + s/z1

1 + s/p1(3)

H0 = Cc

Ic

fck

Tres

gm

gdsKbst (4)

p1 = 1/C0(RESR + 1/gds) (5)

z1 = 1/(RESRCo) (6)

where RESR represents ESR of Co, gm is the transconduc-tance of an LSB switch transistor, and gds is the sum ofthe output conductance of the switch transistors at steadystate. The term of Kbst represents the incremental gain atthe boost mode, which is set to 4 at the boost mode andreturns to 1 at the normal mode. A conventional cyclic TDCproduces its value in every reference clock cycle. For thispurpose, the counter should be reset to zero, before it entersnext cycle.

However, our design reuses the counter, to implement anaccumulator as a low-pass filter without reset operation, andthus it results in an integrator in the transfer function. Also,the conventional pole made in the gate of pMOS is moved toa frequency that is high enough to be ignored, because of thelow output resistance of the digital inverters driving it.

With this understanding, Fig. 7 shows the effect of theaccumulator that adds one more pole (p0) at dc on the loopgain. Fig. 7(a) shows the loop gain for a case that C0 is small

Fig. 7. Bode plots for two cases according to p1 and z1. (a) H0 < p1, z1.(b) H0 > p1, z1.

Fig. 8. Chip microphotograph.

enough to be excluded in the stability analysis. In this case,the unity gain frequency (UGF) is determined as H0, whichcorresponds to the dc gain of the transfer function without theeffect of the accumulator. The loop stability can be alwayssecured if UGF is placed apart below p1, because O(s) can beapproximated as a first-order system in that region

UGF = H0

(= Cc

Ic

fck

Tres

gm

gdsKbst

). (7)

This equation indicates that for higher UGF, we need to usea higher frequency clock, or to improve the time resolution ofthe path of VTC to TDC, which is made possible by reducingTres, or increasing the rate by Cc/Ic.

Fig. 7(b) shows the plot for another case that C0 is muchlarger and ESR cannot be ignored, while H0 is maintainedconstant. In this case, UGF is reduced from H0 by p1/z1 andits stability need to be compensated by ESR.

IV. EXPERIMENTAL RESULTS

The proposed D-LDO regulator, targeting on 80 mA at0.5-V output for the maximum load current, has been imple-mented on an 110-nm CMOS process. Fig. 8 shows a die

OH AND HWANG: 110-nm CMOS 0.7-V INPUT TRANSIENT-ENHANCED D-LDO REGULATOR 1285

Fig. 9. Measurement of Vout and IQ versus Vin, at various sets of clockfrequency.

Fig. 10. Vout versus the current ratio between IM2 and IM3.

photograph of the designed chip, which occupies the activearea of 0.04 mm2.

The proposed D-LDO offers loop stability over a wide rangeof clock frequency, once pole, and zero exist far enough out-side the frequency. This property is useful for the functionalityof scalable quiescent current, which is enabled by scaling fck,depending on the requirement of load current.

Fig. 9 shows Vout and IQ in a single plot for 0.5-V targetvoltage, while VIN and fck are swept from 1 V down to 0.6 V,and from 1 MHz down to 14 kHz, respectively. As a result,our D-LDO consumes the quiescent current of 15 μA, whenfck is normally at 1 MHz with VIN of 0.7 V. Also, a sleepmode with fck scaled down to 50 kHz can be assigned so thatit can drive the always-on circuits, such as power on reset,brownout detector, memory data retention, and sleep timer,just with the low quiescent current of 1.5 μA. When fck isscaled down more to 14 kHz, the quiescent current tends tobe increased again. Under 14 kHz, it fails to provide the targetvoltage, because it loses stability.

Fig. 10 shows the plot of Vout versus the current ratio ofIM2/IM3 inside the VTC, which indicates that Vout can beadjusted linearly enough with the current ratio, replacing theresistors.

Fig. 11 shows the performance of the load regulationmeasured when the load current alternates between 0 and80 mA, and fck is set to 1 MHz. This plot indicates that the

Fig. 11. Measured load regulation of Vout.

Fig. 12. Measured load transient response for a different mode. (a) 80-mAstep-top load. (b) 80-mA step-bottom load.

load regulation is 24 mV at 80-mA load current, including theresistance of the package and the PCB line, and the voltageripple is <4 mV, when a 1-nF load capacitor is used.

Fig. 12 compares transient responses with and with-out TRBM, to clarify the effect of the TRBM on under-shoot/overshoot at a transient response. Under the conditionthat the load current rises to 80 mA, as shown in Fig. 12(a),it is observed that the settling time and the peak of theundershoot are reduced by 60% and 72%, respectively. Also,the settling time and the peak of overshoot are commonlyreduced by 60%, for the load current falling to zero, as shownin Fig. 12(b).

Table I compares the basic performance metrics betweenour design, and other recent works. For fair comparison,

1286 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE I

PERFORMANCE COMPARISON OF LDOS

we employed the widely used FOM, as follows [12]:FOM = COUT · �VOUT

IMAX· IQ

IMAX(8)

where COUT is the output capacitor, �VOUT is the maximumtransient output-voltage variation, IOUT is the maximum loadcurrent, and IQ is the quiescent current. As listed in Table I,the digital regulator achieves the smallest FOM.

V. CONCLUSION

The proposed transient-boost technique solves the tradeoffissue between transient response and ripple at steady state,one of the structural problems in D-LDO regulators, andthus it enables a reduction of the transient response time by60%, without affecting the ripple. Also, the designed regulatorachieved the maximum current efficiency of 99.98%, and itproduced a wide range of output voltage from 0.5–0.9 V, dueto the low-voltage operation at 0.7 V, which is caused by theuse of logic gates.

REFERENCES

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[2] J.-W. Lai et al., “A world-band triple-mode 802.11a/b/g SOC in 130-nmCMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2911–2921,Nov. 2009.

[3] E. Alon and M. Horowitz, “Integrated regulation for energy-efficientdigital circuits,” IEEE J. Solid-State Circuits, vol. 43, no. 8,pp. 1795–1805, Aug. 2008.

[4] Y. Okuma et al., “0.5-V input digital LDO with 98.7% current efficiencyand 2.7-μA quiescent current in 65 nm CMOS,” in Proc. IEEE CustomIntegr. Circuits Conf. (CICC), Sep. 2010, pp. 1–4.

[5] M. Lüders et al., “A fully-integrated system power aware LDO forenergy harvesting applications,” in Proc. IEEE Symp. VLSI Circuits,2011, pp. 244–245.

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[12] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, andS. Borkar, “Area-efficient linear regulator with ultra-fast load regulation,”IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005.

Tak-Jun Oh received the B.S. and M.S. degreesfrom Kangwon National University, Chuncheon,Korea, in 2011 and 2013, respectively.

He has been a Research Staff Engineer withMagnaChip Company, Ltd., Seoul, Korea, since2013. His current research interests include high-precision CMOS temperature sensors and dc–dcconverters.

In-Chul Hwang (S’93–M’95) received the B.S.,M.S., and Ph.D. degrees from Korea University,Seoul, Korea, in 1993, 1995, and 2000, respectively.

He was a Research Staff with the CoordinatedScience Laboratory, University of Illinois at Urbana-Champaign, Champaign, IL, USA, from 2000 to2001. From 2001 to 2007, he was a Senior Engineerwith Samsung Electronics, Kiheung, Korea, wherehe was involved with CMOS RFIC developmenttargeting for GSM/EDGE/WCDMA RF transceivers.In 2007, he joined the faculty of the Department

of Electrical and Electronics Engineering, Kangwon National University,Chuncheon, Korea, where he is currently an Associate Professor. His currentresearch interests include CMOS RFIC, LED driver ICs, and power- andfrequency-management ICs.