A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal ...€¦ · ADC is fabricated in 130-nm CMOS process with a core area of 0.16 mm2. The measurement results show that the ADC

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 2, FEBRUARY 2019 477

A Low Power 12-bit 1-kS/s SAR ADC forBiomedical Signal Processing

Wei Mao , Student Member, IEEE, Yongfu Li , Senior Member, IEEE,

Chun-Huat Heng , Senior Member, IEEE, and Yong Lian, Fellow, IEEE

Abstract— In this paper, a 12-bit 1-kS/s successive approxi-mation register analog-to-digital converter (ADC) is presentedfor biomedical signal processing system. A multi-segmentationdigital-to-analog converter architecture and a hybrid switchingscheme are proposed to reduce the total unit capacitor count.A new ultra low-leakage switch is proposed for sample-and-hold and capacitor control switch blocks in order to improveconversion accuracy and reduce leakage current. The proposedADC is fabricated in 130-nm CMOS process with a core areaof 0.16 mm2. The measurement results show that the ADCachieves 10.47 ENOB and consumes 110-nW power at a samplingrate of 1 kS/s with 1.0-V supply voltage. A Walden figure of meritof 76 fJ/conversion-step is obtained.

Index Terms— SAR ADC, ultra-low speed, multi-segmentation,split-capacitive DAC, switching method, leakage power.

I. INTRODUCTION

WEARABLE sensors are envisaged to play an importantrole in the future for preventive-oriented healthcare.These sensors can be attached to the body to form a bodysensor network for continuous monitoring of critical vitalsigns. A typical wearable sensor block diagram is shownin Fig. 1. The analog-to-digital converter (ADC) acts asthe interface between analog frontend and digital processingunit. The ADC resolution, power consumption, and areaare important considerations in the design of an ADC forwearable sensors. The high resolution is necessary to caterfor large changes in signal due to body movement. The lowpower consumption helps to extend the battery life consideringthe small size of wearable devices. The small area reducesthe cost, which makes the sensor affordable. The successiveapproximation register (SAR) ADC is an ideal candidate forwearable sensors with its moderate accuracy and excellentpower performance [1], [2].

Manuscript received January 6, 2018; revised June 18, 2018 andJuly 16, 2018; accepted July 20, 2018. Date of publication August 13, 2018;date of current version January 18, 2019. This work was supported in partby the Singapore A�STAR BMRC under Grant 1610500027, in part by theNational Key Research and Development Program of China under Grant2016YFE0116900, and in part by the Natural Science Foundation of Chinaunder Grant 61474074. This paper was recommended by Associate EditorP. Rombouts. (Corresponding author: Yongfu Li.)

W. Mao is with HiSilicon Technologies Co., Ltd., Shenzhen 518129, China(e-mail: [email protected]).

Y. Li and Y. Lian are with the School of Microelectronics, Shanghai JiaoTong University, Shanghai 200240, China (e-mail: [email protected]).

C.-H. Heng is with the Department of Electrical and Computer Engineer-ing, National University of Singapore, Singapore 119077 (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2018.2859837

Fig. 1. Simplified block diagram of the wireless sensor system.

Although there are several low power SAR ADC designsavailable [1]–[24], the design of a 12-bit SAR ADC forbiomedical signal processing remains challenging due to thefollowing reasons. Firstly, the area of a conventional binary-weighted (CBW) digital-to-analog converter (DAC) arrayincreases exponentially with increasing resolution. The overallperformance including linearity, speed and power consumptionis also primarily determined by the capacitive DAC array.Secondly, SAR ADCs for biomedical applications mostlyoperate in the ultra-low speed range from few tens Hz toseveral kHz. Hence, the discharge of the sampled voltagethrough the leakage current of the sampling switch duringthe long conversion period would result in nonlinearity. Thus,maintaining the sampled voltage is one of the key designconsiderations for ADCs in low sampling rate applications [3].In addition, the leakage power consumption becomes a bigconcern within this frequency range [4].

Several methods have been proposed to address aforemen-tioned challenges. For optimized high resolution DAC struc-tures, the binary-weighted split-capacitive-array with attenu-ation capacitor (BWA) DAC has been used as an alternativeof the CBW capacitive array [5]–[12]. By inserting attenua-tion capacitors Ca to segment the CBW structure, the BWAstructure employs much fewer count of the unit capacitorCu than the CBW structure. To keep the binary-weightedratio, a fractional attenuation capacitor is commonly usedin the conventional BWA DAC to achieve excellent powerand area savings. However, the implementation of accuratefractional Ca is not practical in the layout because of thefinite manufacturing grids, which results in poorer matchingperformance with other capacitors and more sensitivity to theparasitics. Thus, an additional calibration block is required toimprove the linearity performance.

The switching methods for controlling the capacitorstates have also been optimized to reduce the total unitcapacitor count and power of the capacitive DAC [13]–[20].

1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

https://orcid.org/0000-0003-2527-6778https://orcid.org/0000-0002-6322-8614https://orcid.org/0000-0002-5696-8403

478 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 2, FEBRUARY 2019

Fig. 2. Block diagram of the proposed 12-bit SAR ADC.

In [13]–[17], the most-significant-bit (MSB) capacitor is elim-inated to achieve 50% reduction of the total capacitor countby using the set-and-down and Vcm-based switching methods,respectively. However, set-and-down method suffers from thechanging common-mode voltage Vcm of the DAC differentialoutputs, which causes large signal-dependent dynamic offsetof the comparator [13]. The Vcm-based methods result in addi-tional power and area penalty for providing an accurate refer-ence voltage Vcm [14]–[17]. For [18]–[20], a charge-averagingmethod is implemented to achieve excellent power-efficientperformance while eliminating the Vcm voltage referencegenerator.

In terms of the leakage current, the stacked transmissiongate is proposed as the sample-and-hold (S&H) switch toreduce the leakage current by 1/3 compared to the conven-tional single transmission gate [3]. The bootstrapped switchesare also designed with boosted control voltages to improvethe turn-on conductance and reduce the off-state leakagecurrent [21]. In addition, asynchronous clock mode is alsocommonly used for SAR control logic to deal with the leakageissue. By employing intrinsically high-speed building blocks,the ADC system changes to power-saving mode after finishingthe conversion work to avoid the long conversion period of asynchronous SAR ADC [22], [23].

In this paper, we propose three techniques to addressthe issues in the low-speed SAR ADC. First, a multi-segmentation non-fractional binary-weighted split-capacitive-array with attenuation capacitor (NFBWA) DAC is proposed.The new DAC has significantly reduces the total unit capacitorcount compared to the CBW DAC and improves the DAC’slinearity compared to the conventional BWA DAC. Second,a hybrid switching method combining complementary andmonotonic switching mechanisms is introduced to reduce theunit capacitor count with no additional reference voltage andnearly constant Vcm. Third, an ultra low-leakage switch circuit

for S&H and capacitor control switch blocks is designed forthe improvement of the conversion accuracy and the leakagepower consumption for synchronous SAR ADC. These threetechniques are verified by measurement results.

The paper is organized as follows. Section II describes theproposed ADC detailing the novel DAC array design and theswitching method. Section III covers the circuit implementa-tion and design considerations. Section IV shows the overallmeasurement results, followed by the conclusion in Section V.

II. THE PROPOSED ARCHITECTURE

The block diagram of the proposed 12-bit SAR ADC isshown in Fig. 2. A fully differential structure is employedto achieve good common-mode rejection ratio (CMRR) andpower supply rejection ratio (PSRR) performance.

A. Multi-Segmentation Split-Capacitive DAC

A single-ended N-bit multi-segmentation NFBWA DACarchitecture is shown in Fig. 3, where the attenuation capaci-tors are integer multiples of the unit capacitor to improve themismatch tolerance. The whole DAC array is split into threesubarrays with bit-width ratio of m : n : l. The MSB subarrayhas m bits with the corresponding capacitors Cn+1∼Cn+m.The less-MSB (LMSB) subarray has n bits with capacitorsC1∼Cn. The LSB subarray uses a 1-bit LSB segmentation toachieve the highest linearity in the DAC [25]. The value ofeach capacitor in this architecture is given by

Ci =

⎧⎪⎨

⎪⎩

2i-2Cu, n + 1 ≤ i ≤ m + n2i-1Cu, 1 ≤ i ≤ nCu, i = 0

(1)

Ca1 = 2Cu, (2)Ca2 = 2nCu, (3)

MAO et al.: LOW-POWER 12-bit 1-kS/s SAR ADC FOR BIOMEDICAL SIGNAL PROCESSING 479

Fig. 3. Schematic diagram of the proposed N-bit 3-segmentation NFBWA DAC with m-bit MSB subarray, n-bit LMSB subarray and 1-bit LSB subarray.

TABLE I

PERFORMANCE SUMMARY OF THE PROPOSED 12-bit 3-SEGMENTATIONNFBWA DACS WITH VARIOUS SEGMENTATION RATIOS

where Cu represents the capacitance of a unit capacitor.Equation (1) gives the capacitances corresponding to particulardigital bits. As indicated in (2) and (3), the attenuationcapacitors Ca1 and Ca2 are integer multiples of Cu, whichdiffers from the fractional value in the conventional BWA DACarchitecture.

The design strategy of the proposed architecture is explainedas follows. As shown in Fig. 3, the left and right parts of Ca1are LSB and LMSB subarrays while the left and right partsof Ca2 are LMSB and MSB subarrays, respectively. Withineach subarray, all the capacitors are assigned according to theradix-2 ratio. For the attenuation capacitor Ca1, its value is setto the equivalent capacitance of all capacitors within the LSBsubarray. At the same time, the leftmost capacitor C1 withinthe LMSB subarray is set to half of Ca1. This ensures thatthe series connection of LSB subarray and Ca1 matches C1.Similarly, the value of Ca2 is set to the equivalent capacitanceof all the capacitors on its left side ( Ca1, LSB and LMSBsubarrays). The leftmost capacitor Cn+1 within MSB subarrayis set to half of Ca2. This sets the series connection of Ca2 andall the capacitors on its left side to match Cn+1. In this way,the bit-related capacitors C0∼Cn+m can generate voltages inradix-2 form while avoiding the use of fractional attenuationcapacitors.

In the following part, the analysis of the unit capacitorcount, power and linearity performance for the proposed 12-bitDAC is presented. The unit capacitor counts are derivedfrom (1)∼(3). For each segmentation ratio, the correspondingunit capacitor count is provided in column 2 of Table I.As shown, the data indicates that the unit capacitor count

is increasing with decreasing MSB bits, which ranges from1030 to 2563. Compared to a CBW DAC, the correspondingunit capacitor count which equals 4096 is reduced by 1.6× to4×. In terms of the power performance, the estimation of theaverage switching energy for the proposed NFBWA DAC isderived from the methodology in [9]. The results are presentedin column 3 of Table I. As shown, the average switchingenergy is also increasing with decreasing MSB bits, whichranges from 683 to 1152 CuV 2REF.

For a capacitive DAC with the BWA structure, the linearityperformance is mainly affected by the parasitics and mismatchissues. The parasitic capacitance on the top plate of eachsubarray results in a gain error problem. As shown in Fig. 3,the parasitic capacitances of the LSB, LMSB and MSBsubarrays in the proposed structure are represented as Cp0, Cp1and Cp2, respectively. For the MSB subarray, the gain errorcaused by Cp2 does not affect the linearity performance [25].In the following part, the gain errors of the LMSB and LSBsubarrays are analyzed by taking the gain of the MSB subarrayas reference without considering the capacitor mismatch. Thegain error ge can be calculated by

ge_LSB =Ca1||CL

2(Ca1||CL+CLM) · 2n-1CuCtotal

− Cu22Ctotal

Cu22Ctotal

, (i = 0) (4)

ge_LMSB =2i-1Cu

Ca1||CL+CLM · 2n-1CuCtotal

− 2i-2CuCtotal2i-2CuCtotal

, (1 ≤ i ≤ n) (5)

where CL, CLM and CM represent the total capacitanceson the top plates of the LSB, LMSB and MSB sub-arrays, which equal 2Cu + Cp0, (2n-1)Cu + Cp1 and(2m+n-1-2n-1)Cu + Cp2, respectively. Ctotal represents the totalcapacitance at the VDAC node. By substituting the subarraycapacitances into (4) and (5), the equations can be simplifiedas

ge_LSB =(

Cp04+Cp0 + 1) · 2nCu

Cp04+Cp0 + 2nCu + Cp1

− 1

= − (1 − 2n)Cp0 + 4Cp1 + Cp0Cp1

2n+2Cu + (2n + 1)Cp0 + 4Cp1 + Cp0Cp1 , (6)

ge_LMSB = 2nCu

Cp04+Cp0 + 2nCu + Cp1

− 1

= − Cp0 + 4Cp1 + Cp0Cp12n+2Cu + (2n + 1)Cp0 + 4Cp1 + Cp0Cp1 . (7)


Fig. 4. The SNDR performance for a 12-bit SAR ADC using (a) the FBWA DAC, (b) the proposed DAC, for different distribution of bits in the MSBsubarrays.

By comparing two equations (6) and (7), ge_LSB is largerthan ge_LMSB by 2nCp0/(2n+2 +(2n +1)Cp0 +4Cp1 +Cp0Cp1).Thus, the LSB subarray is more sensitive to the parasiticcapacitance than the LMSB subarray. By using 1-bit LSBsegmentation, the nonlinearity caused by ge_LSB is minimized.As for the pure C-2C structure, the whole structure can besplit into N subarrays. There is only one MSB bit, for whichthe gain error has no effect on the ADC’s linearity. From theabove analysis, the effects of the gain errors of less-significant-bit subarrays would get worsen on the linearity performance.Thus, it is impractical for high resolution DAC with strictlinearity requirement to use the C-2C structure.

To quantify the effect of the mismatch issue and theparasitic capacitances on the overall linearity, signal-to-noiseand distortion ratio (SNDR) performance is evaluated forthe proposed DAC. SNDR is a measurement of the purityof the ADC’s output signal and it provides a good indi-cation of the linearity and dynamic performance of theADC. In this analysis, the SNDR performance of the pro-posed DAC with all the segmentation ratios is simulated.The SNDR performance of the conventional fractional BWA(FBWA) DAC is also provided for comparison. For betterevaluation, the minimum value of unit capacitor Cu needsto be determined. Monte Carlo simulations in [8] indicatedthat 12-bit CBW DAC using unit capacitor with 1% mis-match σ can achieve SNDR mean μSNDR of 71.87 dB(11.64-bit ENOB) with a standard deviation σSNDR of 1.07 dB.Therefore, unit capacitor Cu with σ equal to 1% is appliedto the FBWA and proposed DACs. For the parasitic issue,the top and bottom plates of all the capacitors are modeledby adding 5% and 10% parasitic capacitances to ground,respectively [26].

In Fig. 4, the simulation results are provided based on1000 Monte Carlo simulations. The μSNDR and σSNDR fora 12-bit FBWA DAC are presented in Fig. 4(a). The SNDRimproves with an increasing number of bits m in the MSBsubarray. The traditional approach of choosing equal MSB andLSB bits (“6:6” segmentation ratio) is not able to meet the

requirement without calibration, instead MSB bits of ten andabove is required. Fig. 4(b) shows the SNDR performance ofthe proposed DAC. The SNDR improvement shows the sametrend with the FBWA one. However, for the same numberof bits in the MSB subarrays, the proposed work achievesbetter SNDR performance with higher μSNDR and smallerσSNDR. Especially from 6 MSB bits, the proposed one achievecomparable performance to the FBWA one with 2 MSB bitslarger. When the MSB bits increase to 8 bits, the SNDR per-formance of the proposed one has saturated with comparablevalue to that of 10-MSB-bit design and meet the linearityrequirement for 12-bit SAR ADC. The advantage is resultedfrom the enlarged MSB subarray and attenuation capacitor.From equation (1), the LSB capacitor of the MSB subarrayfor the proposed structure is 2n-1Cu while the LSB capacitorof MSB subarray for FBWA structure is Cu. By enlargingthe MSB subarray by 2n-1×, the proposed structure is lesssensitive to the mismatch and parasitic issues, and providesbetter linearity performance. For the attenuation capacitor,Ca2 in the proposed structure and Ca in the FBWA structureare 2nCu and 2

N−m2N−m−1 Cu, respectively. With the attenuation

capacitor about 2n× larger, the LSB and LMSB subarrayswhich are connected in series with Ca2 are less sensitive tothe mismatch when compared to the FBWA one with the samecapacitors in the LSB subarray.

For this work, “10:1:1” segmentation ratio of the proposedDAC is chosen by considering capacitor count, power, andlinearity performance. In Table II, the performance of theCBW DAC, the FBWA DAC [5] and the NFBWA DAC [8] arecompared with the proposed architecture. All the DACs use thesame bottom-sampling binary-search switching method [27].The unit capacitors of all DACs are set with mismatch σequal to 1% and the same parasitic effects. By performingMonte Carlo simulations for the BWA and NFBWA DACs,the optimum segmentation ratios of 10:2 and 8:4 are neededto meet the linearity requirement, respectively. The resultingSNDR, average switching energies and areas are summa-rized in Table II. The Walden figure-of-merit (FOM) is also


TABLE II

PERFORMANCE COMPARISON OF 12-bit CAPACITIVE DACS WITH VARIOUS STRUCTURES

employed for the overall performance comparison [28]:

FOM = Powerfs × 2ENOB . (8)

For equation (8), the switching power divided by fs equalsaverage switching energy. Thus, the FOM value can beobtained by dividing the averaged switching energy by 2ENOB.In Table II, the FOM ratios are calculated by taking theproposed one as the reference. As shown, the proposed designcan achieve the best FOM performance. It improves the FOMperformance by 1.18× and 1.92× relative to the conventionalFBWA and NFBWA DACs, respectively. To evaluate the per-formance comparison further, the performance summary of theDACs designed according to the similar linearity performanceis given. For the BWA DACs, the total unit capacitor countsof the MSB subarrays can be reduced when compared to thecounts of the capacitors with the same MSB bits in the CBWDAC. In [11], the unit capacitor of the BWA DACs shouldbe scaled up with the same count-reduction ratio to achievesimilar linearity performance with the CBW DAC. Based onthe chosen segmentation for each DAC, the unit capacitorratio which equals the count-reduction ratio is provided. Withenlarged unit capacitors, the corresponding power, area, linear-ity and FOM values are recalculated. From the table, the CBWDAC shows better performance than the BWA DACs due tono drawbacks from the attenuation capacitors and parasiticcapacitances. However, it suffers from large unit capacitorcount. For the proposed NFBWA DAC, best performance isachieved among the BWA DACs without calibration block.

B. Hybrid Switching Method

In this work, the top-plate sampling mode is employed.The differential analog input signals Vip and Vin are storeddirectly on the top plate of the capacitors in the DAC arraythrough two S&H switches on each side. Compared to thebottom-plate sampling mode, the top-plate sampling avoidsthe S&H switches for each subarray capacitor and MSBswitching [29]. During the 1st conversion phase, the DACoutputs are compared directly by the comparator to determinethe MSB bit without changing the states of the capacitors.During each of the subsequent xth (2≤x≤N) conversion phase,the capacitor states are toggled to add ±(1/2)x−1VDD voltageoffset to the DAC differential output based on the determinedbN-x+1 value. Then the corresponding bit bN-x is generatedaccording to the DAC output comparison result. After passingN conversion phases, the total N digital bits are generated andthe next sampling phase begins.

Fig. 5. The structures and the corresponding switching mechanisms forgenerating voltage offset of (a) the MSB-presetting method and (b) themonotonic set-and-down method.

The MSB-presetting and monotonic set-and-down methodsare commonly used for the top-sampling mode SAR ADCwithout the reference voltage Vcm (i.e., VDD/2) [3], [13].In Fig. 5, the simplified N-bit SAR ADC structures forthese two methods are shown. The corresponding switchingmechanisms for generating ±(1/2)x−1VDD voltage offset arealso illustrated below the structures. For the MSB-presettingmethod, the voltage offsets are added by toggling the capac-itor states complementarily within the two binary-weightedcapacitor pairs. During the xth (2≤x≤N) conversion phases,the corresponding capacitor pairs (Cp,N-x+1, Cn,N-x+1) and(Cp,N-x, Cn,N-x) are toggled to add offset of ±(1/2)x VDD toVDACP and VDACN, respectively. This is equivalent to addingoffset of ±(1/2)x−1VDD to the differential DAC output. Theunit capacitor count on each side is 2N for a N-bit MSB-presetting DAC. For the set-and-down method, the voltageoffsets are added by toggling the capacitor state within onecapacitor pair. During the xth (2≤x≤N) conversion phases,the corresponding capacitor pairs (Cp,N-x, Cn,N-x) are toggledto add ±(1/2)x−1VDD for single output and the differentialoutput. The unit capacitor count on single side is now reduced


Fig. 6. The working procedure of the hybrid switching method for a 3-bit SAR ADC example.

by half, which is 2N−1 for a N-bit set-and-down DAC.By comparing these two methods, the MSB-preset switchingmethod can achieve constant common-mode output voltageof Vcm while suffering from doubling the total unit capacitorcount. On the other hand, the set-and-down method achievesless capacitor count while suffering from varying Vcm duringthe conversion phases, which results in large signal-dependentdynamic offset in the comparator and nonlinearity issue.In [30], [31], the effect of Vcm variation on dynamic offsethas been quantified. Compared to the set-and-down method,7-dB SNDR improvement could be achieved by maintaining aconstant VCM for an 11-bit ADC with a conventional latch-based comparator.

A hybrid switching method combining the above two meth-ods is presented in this work. The working procedure followsthe MSB-presetting method in all phases except for the lastconversion phase where the set-and-down method is combined.For the last conversion phase, the voltage offset is addedby toggling the LSB capacitor pair complementarily whiletoggling the dummy capacitor pair (Cp,D,Cn,D) unilaterallyas the set-and-down method. Because the last dummy pair isemployed, the total unit capacitor count can be the same withthe set-and-down approach. Although varying Vcm is observedduring the last conversion phase, its small fluctuation wouldnot induce significant dynamic offset.

In Fig. 6, the working procedure of the proposed methodis illustrated with a simplified 3-bit differential SAR ADC.Firstly, the ADC samples the differential analog inputs andgenerates the MSB bit during the sampling phase and con-version phase 1, respectively. During conversion phase 2,the states of MSB capacitor pair (Cp,1, Cn,1) and LSB capacitor

pair (Cp,0, Cn,0) are changed according to the 1st comparisonresult to add ±(1/2)VDD voltage offset. During conversionphase 3, if VDACP>VDACN, the states of the LSB capacitorpair (Cp,0, Cn,0) remains unchanged while the state of thedummy capacitor Cp,D is changed to VGND. If VDACP


A. Capacitive DAC Design

The area of the unit capacitor is designed to fulfill the noiseand linearity requirement. The unit capacitor should be set assmall as possible to achieve most power- and area-saving per-formance. The minimum value of the unit capacitor is mainlydetermined by the kT/C noise and linearity requirements. C isdefined as the total input capacitance. As for the kT/C noiserequirement, the resulting ENOB reduction should be less than0.5 bit [32]. Thus, the noise voltage should be smaller thanthe quantization noise voltage:

√kT

C≤ VDD

2N√

12. (9)

In this work, N equals 12, and VDD is set to 1 V. From (9),the total input capacitance C should be at least 0.8 pF. As thetotal input capacitance C equals 512Cu, thus the required valueof unit capacitor Cu should be larger than 1.57 fF.

For the linearity requirement, the mismatch of the unitcapacitor is determined by the differential nonlinearity (DNL)constraints [33]. The 3σDNL should be less than 1/2 LSB.In [11] and [33], the expression of the maximum σDNL forthe conventional BWA DAC is given:

σDNL_MAX = 2N− m2 · σuCu

LSB, (10)

where m and σu represent the MSB bit width and the standarddeviation of unit capacitor Cu, respectively. For the proposedwork, the unit capacitor of the MSB subarray is enlarged by2n+l−3 when compared with the conventional BWA structure.Thus, σDNL for the proposed work is derived as

σDNL_MAX = 2N− m2

2n+l−3

2

· σuCu

LSB = 2 N+32 · σuCu

LSB. (11)

According to the DNL constraints, the maximum value of(σu/Cu) is derived as

σu

Cu<

1

3 × 2 N+52. (12)

Besides, (σu/Cu) is determined by the Pelgrom coefficientKσ and the unit capacitor area A [3]. The equation can beexpressed as

σu

Cu= Kσ√

2A, (13)

where the parameter Kσ equals 1.2 %μm for 130-nm CMOSprocess we used. In this work, a differential DAC array isimplemented, which relaxes the (σu/Cu) constraint by

√2 for

unit capacitor. By substituting (13) in to (12) while consideringabove conditions, the area A of unit capacitor should be largerthan 42.5 μm2. For square capacitors, the width should belarger than 6.5 μm. In this process, the capacitance densityfor the metal-insulator-metal (MIM) capacitor is 1.12 fF/μm2.Thus, the unit capacitance and the total input capacitance forthe proposed structure should be 47.7 fF and 24.42 pF, respec-tively. The unit capacitance is much larger than the kT/Cnoise requirement. For the CBW DAC, the unit capacitor areacan be determined by using equations (10) and (13) withMSB bit width m equal to N under the DNL constraints.

Fig. 7. S&H part with bootstrapped MOS switch model at “on” states.

Fig. 8. Low-leakage switch designs: (a) stacked transistors [3], (b) proposedtwo stack transistors with internal capacitor CI.

Fig. 9. The leakage current versus the input voltage for 3 switch structures.

The unit capacitor area and total capacitor area should be5.31 μm2 and 0.0218 mm2, respectively. The correspondingunit capacitance and the total input capacitance should be5.96 fF and 24.42 pF. Although the total input capacitances arethe same for the proposed design and the conventional CBWmethod, the proposed work reduces the total unit capacitorcount by 8×, which simplifies the layout and reduces therouting parasitics. In this work, a 55-fF MIM capacitor is usedas the unit capacitor with 7μm×7μm dimension. The totalinput capacitance is 28.2 pF for each side of the proposedDAC.

B. Sample-and-Hold Circuit Design

The model of the S&H circuit is shown in Fig. 7. The inputsignal is sampled and held on the top plates of the capacitorarray CDAC though the sampling switch. The VDAC accuracyduring the sample phase and the leakage issue during theconversion phase are the key design considerations for theswitch. For the low and medium resolution (≤10 bit) SARADC, the complementary transmission gate is commonly usedas the sampling switch [3]. Owing to its simple structure, lowpower and small area are achieved. However, this structure


Fig. 10. Layout design of the proposed 12-bit capacitive DAC array on each side. C10∼C0 represent the subarray capacitors. CM and CL represent theattenuation capacitors. CD represents the dummy capacitors.

suffers from signal-dependent on-resistance and results in har-monic distortion, which impacts the ADC performance [34].In this work, the bootstrapped switch is employed. Thebootstrapped switch ensures that the gate voltage VG tracks(VIN + VDD) during the sampling phase. At the same time,the source and drain voltages VS and VD track VIN. Hence,signal-independent on-resistance can be obtained due to theconstant VGS and VGD [35].

For the SAR ADC operating at ultra-low speed, the keychallenge in achieving good linearity performance is reducingthe leakage current through the sampling switch during thelong conversion period. The stacked transistors are commonlyused for leakage reduction as shown in Fig. 8(a) [3], [36].In our design, we propose a new structure, as shownin Fig. 8(b), where an internal capacitor CI is introduced totwo stack transistors. During the conversion phase, the leakagecurrent affects the voltage of CI first. VDAC is only affectedwhen the voltage difference between CI and the OUT nodebecomes large. In addition, the added CI coupled with thecapacitor DAC array and switches form a second-order lowpass filter. This minimizes the interference of the input signalon the sampled voltage during the conversion phase.

To evaluate the leakage reduction performance, three switchstructures including single transistor with 2Lmin channellength, two-transistor design and the proposed design withLmin for each channel length are simulated. The transistorsare all NMOS type and the widths are all set to the minimumvalue of 150 μm. The internal capacitor CI is set to 100 fF.For the simulation, both the input and output nodes areconnected to ramping voltage source changing from 0 to1 V and fixed voltage source of 0.5 V, respectively. Theinternal node of the two-transistor design and the proposeddesign are also precharged to 0.5 V to imitate the samplingphase. The leakage current is measured from the OUT voltagesource. The simulated leakage currents versus the input voltageof 3 structures are shown in Fig. 9. The leakage currents areaveraged over 1 ms. From the simulation results, the leakage

current of the two-transistor design is about 2/3 of the single-transistor switch. For the proposed work, the leakage currentis reduced by more than half, especially in the input voltagerange from 0 ∼ 0.2 V.

To meet the linearity requirement for an N-bit ADC, the set-tling error during the sampling period should be smaller than1/2 LSB, which is defined as the frequency domain equationin [37]:

f3dBfclk

≥ (N + 1) × ln 2π

. (14)

For this work, one clock cycle is for sampling and 12 clockcycles are for conversion. Thus, if the system sampling fre-quency is set to 1 kHz, the system clock frequency should be13 kHz, which is represented as fclk in (14). f3dB representsthe cutoff frequency of the sampling switch. From the calcu-lation, f3dB should be larger than 37.3 kHz for the proposed12-bit 1-kS/s ADC. For the proposed S&H and DAC array,the circuit topology can be modeled as a second-order lowpass filter. The transfer function of this model is derived as:

Transfer function = 1R2CICDACS2 + R(CI + 2CDAC)S + 1 .

(15)

CDAC represents the input capacitance of the DAC array,which is 28.2 pF. R represents the resistance of each transistor.During the sampling and the conversion phases, the transistorsare in the “on" and “off" states with on-resistance Ron and off-resistance Roff, respectively. Ron should be small enough toreduce the settling error and Roff should be large enough toreduce the interference of the input signal on the sampledvoltage during the conversion phase. By considering thesedesign issues, the W/L sizes of both HVT NMOS transistorsof the sampling switch are set to 0.4 μm/0.6 μm. The internalcapacitor CI is set to 55 fF, which equals one Cu. From thesimulation, the poles of the transfer function during the sam-pling phase are 0.330 MHz and 92.92 MHz, which are much


Fig. 11. Die photograph of the ADC in 0.13-μm CMOS technology.

larger than the required cutoff frequency. The poles during theconversion phases are around 0.015 Hz and 4.189 Hz, whicheffectively minimizes the coupling of the input signal to thesampled voltage. The dynamic performance of the sampledvoltage at the end of each conversion period is also simulated.With an input signal of near-Nyquist frequency, the SNDR is72.84 dB (11.81 ENOB), which is acceptable for a 12-bit SARADC.

C. SAR Logic

In this work, synchronous SAR logic is chosen as thecontrol block to evaluate the proposed designs. Based onthe hybrid switching method, the SAR logic generates thesampling control signals for the S&H switch and controlsignals for the DAC switch drivers in the differential capacitiveDAC. Besides, the proposed ultra-low-leakage switch structureis also applied to the DAC switch driver to reduce the leakagepower consumption.

D. Layout Strategy

For a high resolution SAR ADC, the overall performanceis also affected by the layout floorplan of the capacitiveDAC array. In order to minimize the systematic and ran-dom mismatches of the DAC array, a careful layout thatapplies multiple weighting methods [38] to the proposed3-segmentation DAC is designed to achieve good matchingperformance. Fig. 10 illustrates the layout design of the DACarray for a single side. Both sides have identical layout design.The subarray capacitors C10∼C0, attenuation capacitors Ca1and Ca2, and dummy capacitors CD are represented by squares(unit capacitors) in different colors. The peripherals of thelayout are filled with dummy capacitors CD to minimizethe proximity effects and second-order lithographic errors.In addition, the diagonal wiring method and shielding metallayer are adopted to achieve symmetrical routing with reducedparasitics.

IV. MEASUREMENT RESULTS

The proposed differential 12-bit SAR ADC is fabricatedin 130-nm CMOS process, the die photograph is shownin Fig. 11. The core area is 0.16 mm2.

Fig. 12. Measured DNL and INL results.

Fig. 13. Measured FFT spectrum at 1 kS/s with 476.9-Hz input signal.

For the measurement, the analog differential sinusoidalinputs and the clock signal are generated by using StanfordDS360 function generator and Keysight 81150A pulse gener-ator, respectively. The digital and analog powers are suppliedby separate low noise battery boards.

For the static linearity performance, a histogram test isimplemented [39]. A differential sinusoidal input with 1Vamplitude at near DC frequency was sent to the 1-kS/sADC. In Fig. 12, the measured peak DNL and INL valuesare +0.35/−0.41 LSB and +0.60/−0.74 LSB, respectively.The dynamic performance is also evaluated by using tonetesting. In Fig. 13, the fast Fourier transform (FFT) of theproposed ADC sampled at 1-kS/s frequency with 476.9-Hzinput frequency is shown. The measured SNDR and SFDRwith a near Nyquist-frequency input are 64.8 dB and 78.5 dB,respectively. Hence, the ENOB is 10.47 bit. Fig. 14 shows thedynamic performance of this ADC with respect to the inputfrequency, where the SFDR and SNDR values remain almostconstant over the entire bandwidth.

To investigate the power consumption accurately, the ADCis divided into 3 blocks with individual power supplies. Theyare SAR logic block, DAC block, and analog block includingcomparator and S&H switch. From the measurement result,the total power consumption is only 110 nW. As illustrated


TABLE III

PERFORMANCE SUMMARY AND COMPARISON OF THE ULTRA-LOW-SPEED SAR ADCS

Fig. 14. Measured SFDR and SNDR versus input frequency.

Fig. 15. The percentages of measured power consumption for analog block(comparator and S&H switch), digital block (SAR logic), and DAC block.The total power is 110 nW at 1-kS/s operation speed.

in Fig. 15, the power breakdown shows that the digital,DAC and analog blocks consume 36.7%, 48.2% and 15.1%,respectively.

The measurement results are summarized in Table III. Thistable also presents the performance of state-of-the-art SARADCs with a sampling rate ≤ 10 kS/s for comparison. Fromthe table, half of the SAR ADCs employ asynchronous clockmode in the SAR logic for saving power. In [1], [4], [12], [21],and [22], the ADCs are designed using 65-nm process. Withthe advanced process, the ADCs using smaller unit capacitorsand reduced supply voltages show better FOM performancethan most of the other ADCs designed in a 130-nm process

and above in the table. Compared to the ADCs with 130-nmprocess and above, the proposed work achieves comparableFOM performance. The ADCs in [10] and [11] show betterFOM performance, which in part benefit from the customizedtiny unit capacitors.

V. CONCLUSION

In this paper, a 12-bit 1-kS/s SAR ADC is presented forbiomedical signal processing. By combining the proposed3-segmentation NFBWA DAC and hybrid switching methodtogether, the total unit capacitor count of the DAC part canbe reduced by 87.4%. In addition, the proposed ultra-low-leakage switch design is employed in the S&H block and thedigital control part to maintain the sampled voltage and lowerthe leakage power consumption during the long conversionperiod. The measurement results show that the fabricated ADCachieves an ENOB of 10.47 bit and consumes only 110-nWpower at 1-kS/s sampling rate.

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Wei Mao (S’13) received the B.Eng. degree inelectronic science and technology from SoutheastUniversity, Nanjing, China, in 2011, and the Ph.D.degree in electrical engineering from the NationalUniversity of Singapore (NUS), Singapore, in 2017.

From 2016 to 2017, he was a research engineerwith NUS. Since 2017, he has been with HiSiliconTechnologies Co., Ltd., as an Analog IC Designer.His research interests include data converters andmixed signal circuits.

Yongfu Li (S’09–M’15–SM’18) received the B.Eng.and Ph.D. degrees in electrical and computing engi-neering from the National University of Singapore(NUS), Singapore, in 2009 and 2014, respectively.

He was a Research Engineer with NUS, wherehe was involved in satellite transceiver design from2013 to 2014. He was a Member of Technical Staffwith GLOBALFOUNDRIES, where he was involvedin design-to-manufacturing (DFM) computer-aideddesign (CAD) software development, from 2014 to2018. He is currently with Shanghai Jiao Tong

University. His research interests include analog/mixed signal circuits, dataconverters, power converters, and DFM CAD.


Chun-Huat Heng (S’96–M’04–SM’13) receivedthe B.Eng. and M.Eng. degrees from the NationalUniversity of Singapore in 1996 and 1999, respec-tively, and the Ph.D. degree from the Universityof Illinois at Urbana–Champaign, in 2003. He hasbeen working on CMOS integrated circuits involv-ing synthesizer, delay-locked loop, and transceivercircuits.

From 2001 to 2004, he was with Wireless InterfaceTechnologies, which was later acquired by Chrontel.Since 2004, he has been with the National University

of Singapore, where he is currently an Associate Professor. He is currentlya Technical Program Committee Member of the International Solid-StateCircuits Conference and the Asian Solid-State Circuits Conference. He iscurrently a Technical Program Committee Member of the International Solid-State Circuits Conference and the Asian Solid-State Circuits Conference. Hehas received the NUS Annual Teaching Excellence Award in 2008, 2011, and2013, respectively, and was in the ATEA Honor Roll in 2014. He has alsoreceived the Faculty Innovative Teaching Award in 2009. He was an AssociateEditor of the IEEE TRANSACTION ON CIRCUITS AND SYSTEMS–II.

Yong Lian (M’90–SM’99–F’09) received theB.Sc. degree from the College of Economicsand Management, Shanghai Jiao Tong University,Shanghai, China, in 1984, and the Ph.D. degree fromthe Department of Electrical Engineering, NationalUniversity of Singapore (NUS), Singapore, in 1994.

He spent nine years in industry and joined NUSin 1996. He was appointed as the first Provost’sChair Professor at the Department of Electrical andComputer Engineering, NUS, in 2011. His researchinterests include biomedical circuits and systems andsignal processing.

Dr. Lian has received many awards including the IEEE Circuits and SystemsSociety’s Guillemin-Cauer Award in 1996, the IEEE Communications SocietyMultimedia Communications Best Paper Award in 2008, the Institution ofEngineers Singapore Prestigious Engineering Achievement Award in 2011,the Hua Yuan Association/Tan Kah Kee International Society OutstandingContribution Award in 2013, the Chen-Ning Franklin Yang Award in Scienceand Technology for New Immigrant in 2014, and the Design Contest Awardin 20th International Symposium on Low Power Electronics and Designin 2015. He received the University Annual Teaching Excellent Award asan Educator in two consecutive academic years from 2008 to 2010 and manyother teaching awards from the Faculty of Engineering. Under his guidance,his students have received many awards, including the Best Student PaperAward in ICME 2007, winner of the 47th DAC/ISSCC Student Design Contestin 2010, and Best Design Award in the A-SSCC 2013 Student Design Contest.

Dr. Lian is the President of the IEEE Circuits and Systems (CAS) Society,and a Steering Committee member of the IEEE TRANSACTIONS ON BIOMED-ICAL CIRCUITS AND SYSTEMS. He is a fellow of the Academy of EngineeringSingapore. He was the Editor-in-Chief of the IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS–II: Express Briefs for two terms from 2010 to 2013.He was the Guest Editor for eight special issues of the IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS–I: Regular Papers, the IEEE TRANSACTIONSON BIOMEDICAL CIRCUITS AND SYSTEMS, and the Journal of Circuits,Systems, and Signal Processing. He was the Vice President for Publicationsof the IEEE CAS Society from 2013 to 2015, the Vice President for the AsiaPacific Region of the IEEE CAS Society from 2007 to 2008, an AdCommMember of the IEEE Biometrics Council from 2008 to 2009, the CAS SocietyRepresentative to the BioTechnology Council from 2007 to 2009, the Chairof the BioCAS Technical Committee of the IEEE CAS Society from 2007 to2009, the Chair of the DSP Technical Committee of the IEEE CAS Societyfrom 2010 to 2011, a member of the IEEE Medal for Innovations in HealthcareTechnology Committee from 2010 to 2012, and a Distinguished Lecturerof the IEEE CAS Society from 2004 to 2005. He is the Founder of theInternational Conference on Green Circuits and Systems, the Asia PacificConference on Postgraduate Research in Microelectronics and Electronics,and the IEEE Biomedical Circuits and Systems Conference.

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A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal ...€¦ · ADC is fabricated in 130-nm CMOS process with a core area of 0.16 mm2. The measurement results show that the ADC