A Miniature Q-band CMOS LNA with Triple-cascode Topology

Bo-Jr Huang, Huei Wang and Kun-You Lin

Dept. of Electrical Engineering and Graduate Institute of Communication Engineering

National Taiwan University, 1 Roosevelt Road, Sec. 4, 10617 Taipei, Taiwan, R. O. C.

Abstract — In this paper, a miniature Q-band low noise

amplifier (LNA) is demonstrated using 0.13μm CMOS technology. The triple-cascode topology is utilized to achieve a high gain performance with a compact size. In addition, two inductors are placed between the cascode devices to reduce the noise and enhance the stability of the LNA. The LNA presents a maximum small signal gain of 12.6 dB and a minimum noise figure of 4 dB at 38 GHz, with a power consumption of 24 mW. The chip size is only 0.42 0.6 mm2, including all the testing pads. To the best of our knowledge, this is the first triple-cascode LNA in millimeter-wave (MMW) regime reported to date. Index Terms — Low noise amplifier, cascode, CMOS, MMIC.

I. INTRODUCTION

In RF front-end of a receiver, the LNA contributes most of the noise figures. Therefore, the design and optimization in the noise figure, gain, and power consumption for a CMOS LNA becomes the major concern in millimeter-wave integrated circuits (MMICs). In the conventional designs, the common-source configuration is usually used to implement a CMOS LNA [1]-[2]. In order to make the best trade-off between the maximum small signal gain and the minimum noise figure, the inductive source degeneration [3] and the transformer feedback [4] structures were reported. However, a single-stage common-source LNA can not provide high gain, especially in MMW bands. Consequently, multiple cascade stages for the LNA are required to achieve the gain performance. This will also increase the power consumption, chip size and noise figure. In recently reported papers, the LNAs with the cascode device [5]-[9] become popular. The cascode structure is composed of a common-source and a common-gate transistor. It has the advantages of high gain and compact size. In [10], the triple-cascode topology was proposed to implement a high gain power amplifier at 2.4 GHz. Nevertheless, as the operation frequency increases to MMW bands, the common-gate stage will contribute a considerable noise, and thus results in high noise figure of a cascode or triple-cascode structure in MMW LNA design. In [11], the parallel resonant inductor was used to reduce the noise of the cascode device, but a large inductor and bypass capacitor are required.

In this paper, another approach is proposed to reduce the noise of the triple-cascode configuration at MMW frequencies. Two series small inductors are designed and placed between

the cascode devices to minimize the noise figure and enhance the stability of the LNA. Based on the triple-cascode structure with noise reduced technique, a single-stage CMOS LNA achieves a small signal gain of 12.6 dB and NF of 4 dB at 38 GHz, with a miniature chip size of 0.420.6 mm2. The total power consumption is 24 mW. This is the first triple-cascode LNA in MMW regime reported to date. Fig. 1. (a) Cascode device, (b) triple-cascode device.

II. CIRCUIT DESIGN

The LNA is fabricated in TSMC commercial 0.13-μm MS/RF purpose CMOS technology, that provides one-poly-eight-metal (1P8M), with ultra thick metal of 3.3-μm. Metal-insulator-metal capacitors and polysilicon resistors are available. The fmax and fT of the CMOS process are 108 GHz and 91 GHz, respectively [9].

In general, the cascode structure features a higher maximum stable power gain (MSG) than the common-source configuration. Also, the triple-cascode configuration presents a higher MSG than the cascode cell. The schematics of the cascode and the triple-cascode device are shown in Fig. 1. The triple-cascode cell consists of a common-source transistor, M1, and two common-gate transistors, M2, and M3. The combinations of the device size are chosen similar to the method reported in [9]. The transistor M1 is selected to be 16 finger NMOS with total gate width of 40 μm. M2 and M3 are

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24 finger NMOS with total gate with of 60 μm and 32 finger NMOS with total gate width of 80 μm, respectively.

Under class-A bias condition, the simulated MSG/MAG and minimum noise figure (NFmin) of the cascode devices are shown in Fig. 2. It is observed that the triple-cascode device presents a MSG of 21.5 dB and a NFmin of 3.5 dB at 40 GHz. The cascode device has a MSG of 15.3 dB and a NFmin of 2.8 dB. Despite the triple-cascode device shows better MSG than the cascode device, it suffers higher NFmin than the cascode device. In the mean while, the triple-cascode configuration is more unstable due to its high gain.

Fig. 2. Simulated MSG/MAG and NFmin of the cascode and triple-cacode device.

To reduce the noise contributed by M2 and M3, two inductors, L1 and L2, are designed and placed between the cascode devices, as shown in Fig. 3. At MMW bands, the parasitic capacitances (Cp1~Cp4) of M2 and M3 will cause excess noise at the output port. By adding the inductors to the cascode cell, L1 and L2 incorporate with the parasitic capacitances to be a resonator, so that the parasitic capacitances of the common-gate stages can be eliminated. Figure 4 presents the MSG and NFmin versus the operation frequency with various L1 and L2. It is observed that with L1

0.3 nH and L20.25 nH the triple-cascode cell is stable above 40 GHz. However, the triple-cascode cell still retains its MSG below 40 GHz. In the mean while, the NFmin is reduced from 3.5 dB to 2.6 dB. With L1 and L2, the noise figure is minimized and the triple-cascode configuration can be applied to implement the Q-band LNA.

Fig 3. The triple-cascode cell with noise reduced inductors.

(a)

(b) Fig. 4. (a) Simulated MSG/MAG, and (b) NFmin versus frequency of the triple-cascode cell with various combinations of L1 and L2.

0 10 20 30 40 50 60 70 800

1

2

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6

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9

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NF

min(d

B)

Frequency (GHz)

L1=0.1nH, L1=0.1nH L1=0.2nH, L1=0.15nH L1=0.3nH, L2=0.25nH Without inductor

0 10 20 30 40 50 60 70 800

10

20

30

40

50

MS

G/M

AG

(dB

)

Frequency (GHz)

L1=0.1nH, L

2=0.1nH

L1=0.2nH, L

2=0.15nH

L1=0.3nH, L

2=0.25nH

0 20 40 60 80 1000

10

20

30

40

Cascode Triple-cascode

Frequency (GHz)

MS

G/M

AG

(dB

)

0

1

2

3

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5

6

7

8

9

10

NF

min (d

B)

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Fig. 5. Circuit schematic of the proposed Q-band LNA.

Figure 5 shows the circuit schematic of the proposed Q-band LNA with single-stage triple-cascode topology. Each gate is biased through a 5-kΩ resistor. T-networks are utilized to simplify and implement the input and output matching circuits. The input network is matched for the minimum noise figure, and the output is conjugately matched for the maximum small signal gain. All the matching networks are formed with thin-film microstrip lines, so that they can be easily meandered to achieve a compact layout [9]. The chip photograph is presented in Fig. 6 with a die size of 0.42 0.6 mm2, including all the testing pads.

III. MEASUREMENT

The triple-cascode LNA was measured via on-wafer probing using Agilent HP8510 test set. Figure 7 plots the measured small signal gain and return losses of the proposed LNA. It is observed that the LNA has a measured peak gain of 12.6 dB at 38 GHz, with the input return loss of 8 dB and the output return loss of 11.8 dB. The 3-dB bandwidth is from 35 to 43 GHz. Over the 3-dB bandwidth, the input and output return losses are better than 6 and 5 dB, respectively. The measured reverse isolations are all better than 30 dB from 35 to 43 GHz. Figure 8 illustrates the measured NF. The LNA has a NF of 3.8 to 4.5 dB from 35 to 43 GHz. At 38 GHz, the measured 1-dB compression point (P1dB) is shown in Fig. 9. The LNA has an output P1dB of -2.2 dBm with a total power consumption of 24 mW.

Table I summarizes the previously reported CMOS and SOI Q-band LNAs, and compares with this work. The single-stage triple-cascode LNA achieves a miniature size and high gain performance with very low noise figure and power consumption. Moreover, it is the first triple-cascode LNA in MMW regime reported to date.

Fig. 6. Chip photograph of the LNA with the area of 0.252 mm2. Fig. 7. Measured small signal gain and return losses of the proposed LNA. Fig. 8 Measured NF of the proposed LNA.

0 10 20 30 40 50 60-20

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-5

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all S

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Frequency (GHz)

M1

M2

M3

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VG2

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L1

L2

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Fig. 9. Measured 1-dB compression.

IV. CONCLUSION

A miniature Q-band LNA with triple-cascode topology was designed and fabricated in TSMC commercial MS/RF 0.13-μm 1P8M CMOS process. Based on the triple-cascode configuration with noise reduced inductors, the proposed LNA has a measured peak gain of 12.6 dB and a NF of 4 dB at 38 GHz. This LNA achieves an excellent performance with 3-dB bandwidth from 35 to 41 GHz among all the CMOS Q-band LNAs reported to date. Besides, the CMOS LNA presents a low power dissipation of 24 mW, with a chip size of 0.252 mm2.

ACKNOWLEDGEMENT

The chip was fabricated by Taiwan Semiconductor (TSMC)

through Chip Implementation Center (CIC) of Taiwan. This work was supported in part by the National Science Council of Taiwan, R.O.C. (NSC 96-2219-E-002-015, NSC96-2219-E-002-020) and NTU Excellent Research Projects (95R0062-AE00-01, 97R0062-03, 97R0533-1).

REFERENCES

[1] Jeng-Han Tsai, et al., “A miniature Q-band low noise amplifier using 0.13μm CMOS technology,” IEEE MWCL, vol. 16, no. 6, pp. 327-329, June 2006.

[2] M.A. Masud, et al., “90 nm CMOS MMIC amplifier,” in IEEE RFIC Symp. Dig., June 2004, pp. 201-204.

[3] Shih-Chieh Shin, et al., “A 3.9-dB NF low-noise amplifier using 0.18μm CMOS technology,” IEEE MWCL, vol. 15, no. 7, pp. 448-450, July 2005.

[4] Antonio Liscidini, et al., “Common gate transformer feedback LNA in a high IIP3 current mode RF CMOS front-end,” IEEE 2006 CICC Proc., Sep. 2006, pp. 25-28.

[5] Kuo-Jung Sun, et al., “A noise optimization formulation for CMOS low-noise amplifiers with on-chip low-Q inductors,” IEEE T-MTT, vol. 54, no. 4, pp. 1554-1560, Apr. 2006.

[6] H. Shigematsu, et al., “Millimeter-wave CMOS circuit design,” IEEE T-MTT, vol. 53, no. 2, pp. 472-477, Feb. 2005.

[7] F. Ellinger, “26-42 GHz SOI CMOS low noise amplifier,” IEEE JSSC, vol. 39, no. 3, pp. 522-528, Mar. 2004.

[8] C. H. Doan, et al., “Millimeter-wave CMOS design,” IEEE JSSC, vol. 40, no. 1, pp. 144-155, Jan. 2005.

[9] Chieh-Min Lo, Chin-Shen Lin, and Huei Wang, “A miniature V-band 3-stage cascode LNA in 0.13μm CMOS,” ISSCC Dig. Tech. papers, pp. 402-403, Feb. 2006.

[10] Hyoung-Seok Oh, et al., “A fully-integrated +23-dBm CMOS triple cascode linear power amplifier with inner-parallel power control scheme,” in IEEE RFIC Symp. Dig., June 2006, pp. 4-7.

[11] Kuo-Jung Sun, et al., “A 10.8-GHz CMOS low-noise amplifier using parallel-resonant inductor,” IEEE MTT-S IMS, Dig., 2007, pp. 1795-1798.

[12] M. Varonnen, et al., “Millimeter-wave integrated circuits in 65-nm CMOS,” IEEE JSSC, vol. 43, no. 9, pp. 1991-2002, Sep. 2008.

TABLE I COMPARISON TABLE OF PREVIOUSLY REPORTED Q-BAND LNAS AND THIS WORK

Process Topology Peak Gain (dB) NF (dB) PDC (mW) Size (mm2) Reference 0.18-μm

CMOS

3-stage Cascode

7@40GHz N/A 300 2.04 [6]

90-nm

CMOS

2-stage

CS

7.3@35GHz N/A 10.5 N/A [2]

90-nm

SOI

1-stage

Cascode

11.9@35GHz 3.6@35GHz 40.8 0.18 [7]

0.13-μm

CMOS

3-stage

Cascode

19@40GHz N/A 36 1.43 [8]

0.13-μm

CMOS

3-stage

CS

20@43GHz 6.3@41GHz 36 0.525 [1]

65-nm

CMOS

2-stage

CS

14.3@42GHz 6@50GHz 43.2 0.286 [12]

0.13-μm CMOS

1-stage Triple-cascode

12.6@38GHz 4@38GHz 24 0.252 This Work

-30 -25 -20 -15 -10 -5

-16

-14

-12

-10

-8

-6

-4

-2

0

2

4

6

8

10

12

Output Power (dBm)

Input Power (dBm)

Gain (dB)

680

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