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A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Author: J. Kim, C. Nicopoulos (Dept. of CSE, PSU) Speaker: Po-Shan Huang ISCA’07. Outline. Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion. Outline. - PowerPoint PPT Presentation
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EE&CSIE
National
Taiwan
University
ARCHIARCHIARCHIARCHI LabLabLabLab
A Novel Dimensionally-Decomposed Router for On-Chip
Communication in 3D Architectures
Author: J. Kim, C. Nicopoulos (Dept. of CSE, PSU)Speaker: Po-Shan HuangISCA’07
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
OutlineOutline
Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
OutlineOutline
Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
IntroductionIntroduction
a new 3D NoC router architecture Partially-connected Dimensionally-Decomposed (Dim
De) Router
Characteristics True 3D crossbar structure Varying the number of vertical connections Segmented vertical links in the partially-connected cro
ssbar Hierarchical arbitration scheme for inter-strata transfe
rs Similar to the Row-Column (RoCo) Decoupled Router
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Face-to-Back bondingFace-to-Back bonding
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OutlineOutline
Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
Area and Power Comparisons of the Crossbar Switches
Area and Power Comparisons of the Crossbar Switches
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3D Symmetric NoC Architecture3D Symmetric NoC Architecture
7x7 crossbar
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3D NoC-Bus Hybrid Architecture3D NoC-Bus Hybrid Architecture
6x6 crossbar
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A True 3D NoC RouterA True 3D NoC Router
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A True 3D NoC Router (cont.)A True 3D NoC Router (cont.)
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OutlineOutline
Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
3D DimDe NoC Architecture3D DimDe NoC Architecture
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EE&CSIE
Taiwan
University
3D DimDe NoC Architecture3D DimDe NoC Architecture
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
3D DimDe NoC Architecture3D DimDe NoC Architecture
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
OutlineOutline
Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion
ARCHIARCHIARCHIARCHI LabLabLabLab
National
EE&CSIE
Taiwan
University
Simulation PlatformSimulation Platform
Server workloads TPC-C SAP
Memory traces SPLASH
Simulator Simics
The baseline configuration Solaris 9 Operating system eight UltraSPARC III cores
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Simulation Platform (cont.)Simulation Platform (cont.)
Energy Model Register-Transfer Level (RTL) Verilog Synopsys Design Compiler
TSMC 90 nm standard cell library
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Impact of the Number of Vertical Bundles on Performance
Impact of the Number of Vertical Bundles on Performance
Two vertical links instead of more
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Simulation ResultSimulation Result
Latency and throughput improvements of over the other 3D architectures
Latency Throughput
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ConclusionConclusion
Energy reduction within Slight performance overhead Small crossbar and simple design reduce about
26% in terms of EDP Within 5% overhead
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