Master of Science ThesisStockholm, Sweden 2013

TRITA-ICT-EX-2013:130

T O B I A S K U R E M Y R

A Study on Linearity of Mixers forHomodyne Receivers

K T H I n f o r m a t i o n a n d

C o m m u n i c a t i o n T e c h n o l o g y

A Study on Linearity of Mixers

for Homodyne Receivers

Tobias Kuremyr

Examiner: Prof. Ana Rusu

Supervisor: Dr. Håkan Bengtsson

A thesis submitted for the degree of

Master of Science

Stockholm 2013

Acknowledgements

I would like to thank the people at the Ericsson AB RFASIC group for giving me the opportunity and tools toperform the research detailed in this thesis. In particular Iwould like to thank my supervisor Dr. Håkan Bengtsson forvaluable discussions and calling me out when my thoughtshave been in error.

Abstract

In this thesis the linearity characteristics of passive mixersfor wide band homodyne receivers are studied. The circuitsare simulated using Cadence Spectre with models from a65 nm RF/Analogue CMOS process. Linearity dependenceof common mode voltage, load impedance, switch networkarrangement and local oscillator drive circuitry is stud-ied and analysed. The thesis also covers methods for thelinearisation of baseband ampliers. Three linearised am-pliers for frequencies down to DC are demonstrated. Thelinearised ampliers are then used in passive mixer circuitsto analyse the eects of baseband linearity improvement oncomplete mixer linearity. The results from this test showthat improving the open loop linearity of the baseband am-plier has an appreciable impact on mixer linearity. Thework presented in this thesis was performed at Ericsson ABin Kista, Stockholm, Sweden during the period January toJune 2013.

Contents

1 Introduction 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Problem Description . . . . . . . . . . . . . . . . . . . 3

1.3 Study areas . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Research method . . . . . . . . . . . . . . . . . . . . . 4

1.5 Delimitations . . . . . . . . . . . . . . . . . . . . . . . 4

1.6 Contributions . . . . . . . . . . . . . . . . . . . . . . . 5

1.7 Thesis organisation . . . . . . . . . . . . . . . . . . . . 6

2 Background 7

2.1 Radio receiver circuits . . . . . . . . . . . . . . . . . . 7

2.2 Mixer topologies . . . . . . . . . . . . . . . . . . . . . 8

2.3 Nonlinearity in mixers . . . . . . . . . . . . . . . . . . 11

2.3.1 Linearity gures of merit . . . . . . . . . . . . . 12

2.3.2 MOSFET nonlinearity . . . . . . . . . . . . . . 13

2.3.3 Device mismatch induced nonlinearity . . . . . 15

2.3.4 Noise in mixer circuits . . . . . . . . . . . . . . 15

2.4 Nonlinearity of cascaded systems . . . . . . . . . . . . 16

3 The passive mixer 18

3.1 Explanation of mixing action . . . . . . . . . . . . . . 18

3.2 Conversion loss in the passive mixer . . . . . . . . . . . 20

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3.3 Current-mode passive mixers . . . . . . . . . . . . . . . 21

3.4 Variations on the basic passive mixer circuit . . . . . . 22

3.4.1 CMOS transmission gates . . . . . . . . . . . . 22

3.4.2 Resistive degeneration of mixer switches . . . . 23

3.4.3 Charge injection cancellation . . . . . . . . . . . 24

3.4.4 Mixing using switched current mirrors . . . . . 25

4 Baseband ampliers 26

4.1 Derivative superposition . . . . . . . . . . . . . . . . . 27

4.1.1 Designing derivative superposition ampliers . . 28

4.2 Post distortion . . . . . . . . . . . . . . . . . . . . . . 30

5 Simulation results 32

5.1 Passive mixer core . . . . . . . . . . . . . . . . . . . . 32

5.1.1 On-conductance nonlinearity . . . . . . . . . . . 33

5.1.2 Mixer linearity versus LO duty cycle . . . . . . 35

5.1.3 Complementary switch networks in voltage-modemixers . . . . . . . . . . . . . . . . . . . . . . . 37

5.1.4 Complementary switch networks in current-modemixers . . . . . . . . . . . . . . . . . . . . . . . 39

5.1.5 Eects of baseband gain in current-mode mixers 40

5.1.6 Resistive degeneration of mixer switches . . . . 41

5.1.7 Charge injection cancellation . . . . . . . . . . . 42

5.2 Linearised baseband ampliers . . . . . . . . . . . . . . 44

5.2.1 Derivative superposition using common modevoltage shift . . . . . . . . . . . . . . . . . . . . 44

5.2.2 Derivative superposition using cross coupled dif-ferential pair . . . . . . . . . . . . . . . . . . . . 46

5.2.2.1 Implications of dierential pair DC char-acteristics . . . . . . . . . . . . . . . . 46

5.2.2.2 Simulation data . . . . . . . . . . . . . 47

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5.2.3 Derivative superposition using PMOS auxiliarytransistor . . . . . . . . . . . . . . . . . . . . . 49

5.2.4 Post distortion using folded PMOS common gateamplier . . . . . . . . . . . . . . . . . . . . . . 51

5.2.5 Output stage nonlinearity and matching char-acteristics . . . . . . . . . . . . . . . . . . . . . 52

5.3 LO driver circuit used in simulations . . . . . . . . . . 53

5.4 Complete mixer circuit . . . . . . . . . . . . . . . . . . 54

5.4.1 Current-mode mixers using linearised BB am-pliers . . . . . . . . . . . . . . . . . . . . . . . 55

5.4.2 Voltage-mode mixers using linearised BB ampli-ers . . . . . . . . . . . . . . . . . . . . . . . . 57

6 Final results 59

6.1 Linearity of the passive mixer core . . . . . . . . . . . 59

6.2 Techniques for improving amplier linearity . . . . . . 60

6.3 Complete circuit considerations . . . . . . . . . . . . . 61

7 Conclusions and future work 63

7.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 63

7.2 Suggestions for future work . . . . . . . . . . . . . . . 65

References 67

A Source impedance model 71

B Complete schematics for studied circuits 72

B.1 NMOS derivative superposition amplier using DC shift 73

B.2 NMOS derivative superposition amplier using crosscoupled dierential pair . . . . . . . . . . . . . . . . . . 74

B.3 CMOS derivative superposition amplier using PMOSauxiliary transistor . . . . . . . . . . . . . . . . . . . . 75

B.4 Post distortion amplier using folded PMOS commongate post distorter . . . . . . . . . . . . . . . . . . . . 76

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C Possible denition of input and output power 77

D Low frequency distortion current in MOS switches 79

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List of abbreviations

3G Third generation cellular communications technology

4G Fourth generation cellular communications technology

ADC Analogue to digital converter

ASIC Application specic integrated circuit

BB Base band

IF Intermidiate frequency

IIP Input referred intercept point

LNA Low noise amplier

LO Local oscillator

OIP Output referred intercept point

PSP Physical surface potential based MOSFET model

RF Radio frequency

SNDR Signal to noise and distortion ratio

SNR Signal to noise ratio

TIA Transimpedance amplier

WLAN Wireless local area network

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List of Figures

1.1 Illustration of a hypothetical homodyne receiver . . . . 2

2.1 Block diagram of a simplied quadrature radio-transceiver 8

2.2 Pseudo dierential Gilbert-cell active mixer implementedusing NMOS transistors . . . . . . . . . . . . . . . . . 9

2.3 Double balanced passive mixer implemented using NMOStransistors. . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Transconductance and derivatives for a 65 nm CMOSprocess high performance analogue, extra low VTH andhigh output impedance, NMOS transistor,W/L = 33 ×2/0.14 µm. VDS = 0.3 V . . . . . . . . . . . . . . . . . . 14

2.5 Nonlinearity of gds with varying VDS, UMC 90 nm pro-cess, W/L = 20/0.08µm, VGS = 0.5V, gure from [1]. . . . 14

3.1 Conceptual view of a voltage-mode sampling passivemixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Time domain waveforms in voltage-mode sampling pas-sive mixer. . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3 Frequency domain translation of RF input signal in adown conversion mixer. . . . . . . . . . . . . . . . . . . 20

3.4 Illustration of a current-mode passive mixer. . . . . . . 21

3.5 Current mirror mixer similar to the circuit from [2] . . 25

4.1 Concept for DC-implementation of derivative superpo-sition ampliers where a) is an NMOS based amplierwith VGS shifted by a voltage source and b) a CMOSimplementation inspired by the Gilbert mixer in [3]. . . 28

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4.2 Amplier used to measure the transconductance char-acteristics of Fig. 4.3 . . . . . . . . . . . . . . . . . . . 29

4.3 Dierential gm and its derivatives for the amplier inFig. 4.2. Voltage on the vertical axis is peak to peakdierential input voltage. . . . . . . . . . . . . . . . . . 30

4.4 Post distortion amplier using a PMOS common gateIM3 sinking device . . . . . . . . . . . . . . . . . . . . 31

5.1 Double balanced passive mixer implemented using NMOStransistors. Reprise of Fig. 2.3 from Chapter 2. . . . . 33

5.2 On state conductance of 7 × 1/0.06 µm NMOS/PMOStransistors, VGS = 0.6V, VDB = VSB = 0.6V. . . . . . . 34

5.3 NMOS based current-mode mixer used as simulationbenchmark, input capacitors are for AC coupling. . . . 36

5.4 Nonlinearity and output power of a simplied NMOSmixer as a function of LO duty cycle. fLO = 4GHz andf1,2 = 4.6GHz, 4.60314GHz. . . . . . . . . . . . . . . . 37

5.5 Performance comparison of dierent switch arrangementsin a voltage-mode passive mixer for fLO = 4GHz andf1,2 = 4.6GHz, 4.60314GHz. . . . . . . . . . . . . . . 38

5.6 Performance comparison of dierent switch arrangementsin a voltage-mode passive mixer for fLO = 4GHz andf1,2 = 4.6GHz, 4.60314GHz with a capacitive load of50 fF on each output . . . . . . . . . . . . . . . . . . . 38

5.7 Performance comparison of dierent switch arrangementversus common mode voltage for a current-mode mixer.fLO = 4GHz and f1,2 = 4.6GHz, 4.60314GHz. . . . . . 40

5.8 Linearity as function of BB amplier gain for the NMOSpassive mixer of Fig. 5.3. fLO = 4GHz and f1,2 =4.6GHz, 4.60314GHz. . . . . . . . . . . . . . . . . . . 41

5.9 OIP3 for a current-mode mixer with dierent series de-generation resistors. fLO = 4GHz and f1,2 = 4.6GHz,4.60314GHz. . . . . . . . . . . . . . . . . . . . . . . . 42

5.10 Implementation sketch for NMOS charge injection can-celling mixer . . . . . . . . . . . . . . . . . . . . . . . . 43

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5.11 Output current and dierential transconductance withderivatives for the NMOS derivative superposition am-plier using ideal DC shift. . . . . . . . . . . . . . . . . 45

5.12 a) Dierential output current from a pseudo dierentialpair in weak inversion, detail from Fig. 5.11. b) Detailfrom Fig. 4.3. . . . . . . . . . . . . . . . . . . . . . . . 47

5.13 Dierential output current and transconductance withderivatives for the derivative superposition amplier us-ing a PMOS auxiliary transistor. . . . . . . . . . . . . 50

5.14 Schematic for the derivative superposition amplier us-ing a PMOS auxiliary transistor . . . . . . . . . . . . . 51

A.1 Output impedance model used in passive mixer simu-lations . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

B.1 Schematic for the NMOS derivative superposition am-plier using ideal DC shift . . . . . . . . . . . . . . . . 73

B.2 Schematic for the NMOS derivative superposition am-plier using a cross coupled dierential pair . . . . . . 74

B.3 Schematic for CMOS derivative superposition amplierusing a PMOS auxiliary transistor . . . . . . . . . . . . 75

B.4 Schematic for the post distortion amplier using PMOScommon gate post distorter . . . . . . . . . . . . . . . 76

C.1 Voltage to power conversion . . . . . . . . . . . . . . . 77

C.2 Current to power conversion . . . . . . . . . . . . . . . 78

D.1 Setup for the Gummel symmetry test . . . . . . . . . . 79

D.2 Current waveforms for the symmetry tested switch . . 80

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Chapter 1

Introduction

1.1 Background

Over the last decade the potency of cellular networks has increasedwith new standards such as third generation (3G) and fourth genera-tion (4G) cellular networks being introduced [4]. The newly deployednetwork standards provide increased datarates compared to previousgenerations such as GSM [4]. As datarates in wireless systems increasethe requirements for low noise and high linearity is simultaneously in-creased. This is as predicted by the Shannon capacity expression [5]increased datarate requires either improved signal to noise ratio (SNR)or channel bandwidth. Meanwhile there is a continuing desire to mi-grate analogue and radio frequency (RF) systems from bipolar andRF processes such as Gallium-Arsenide to CMOS technology. Thistransition is driven by lower processing costs, the increasingly hightransition frequency, fT , of short channel CMOS and the possibilityof integrating digital circuitry on the same die as RF and analoguecircuits. However, the move towards CMOS does come with its ownset of challenges such as low supply voltage and limited amplicationfactor, µ1 [8, 9, 6].

A simple RF receiver circuit consists of ve important parts: an-tenna, low noise amplier, mixer, local oscillator and demodulator [10].

1The transistor parameter µ is sometimes called intrinsic gain and is dened asµ = ro · gm [6, 7]. This parameter is useful for estimating gain per stage and canalso be used to treating the transistor as a voltage amplication device for smallsignal analysis. The letter µ is sometimes used for other purposes such as mobilityfactor in [7] but in this thesis µ is always dened as the device voltage gain.

1

LNA

Localoscillator

ADC Digital SignalProcessing

Down-conversion mixer

Amp

Channel select filter

Distortion rejection filter

Baseband amplification and low pass filter

ADC and digital demodulation

Antenna

Low-noise amplifier

Figure 1.1: Illustration of a hypothetical homodyne receiver

Fig. 1.1 illustrates a hypothetical homodyne receiver with digital de-modulation. In the receiver of Fig. 1.1 the antenna receives the signalwhich is then amplied by the low noise amplier (LNA) whereafterit is frequency translated to a lower frequency by the mixer and -nally demodulated to extract the received information. Intermingledwith the active stages are band-pass and low-pass lters to removeout of band noise, interfering signals and distortion harmonics. Theperformance of the complete RF receiver is of course determined byall of these parts in combination. However this thesis focuses on thelinearity performance of the down-conversion mixer. Mixer linearitygreatly inuences receiver sensitivity in the presence of blocking sig-nals which if they are mixed with the signal of interest, as occurs inany nonlinear system [10], may end up in the signal band thus loweringsignal to noise and distortion ratio (SNDR).

The homodyne receiver architecture, which is the main focus of thisthesis, operates with no intermediate frequency (IF) as opposed toa heterodyne receiver [10]. That the received signal is immediatelyconverted to baseband (BB) reduces power consumption, as fewerstages are required to operate at RF/IF-frequencies. However, thisalso means that low frequency noise and distortion components ap-pearing at low frequencies will interfere the received signal. Thus, thehomodyne receiver is sensitive to icker noise and second order inter-modulation distortion, both of which appear at low frequencies [10].

During recent years a lot of research has been done MOS passive mix-ers due to their low icker noise [11, 12], high linearity [13] and com-patibility with CMOS process technology. Furthermore, as the passivemixer consumes no DC-current [14], this is described in greater detaillater in this thesis, the power consumption of the passive mixer canbe made very small. While being comparatively more linear than the

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Gilbert-cell active mixer several papers have been published on furtherimproving passive mixer linearity [14]. Techniques such as the use ofcomplementary switch networks [13, 15], signal level tracking throughbootstrapping circuits [16] or resistive degradation of the switch tran-sistors [17] among others are proposed to reduce the distortion causedby nonlinearity in the switch devices.

1.2 Problem Description

This thesis studies the linearity characteristics of the passive mixerand also the eectiveness of techniques proposed in recent publicationsfor improving the linearity of the passive mixer. Furthermore thethesis studies techniques for improving the linearity of the base bandamplier used in the passive mixer circuit.

Questions answered in this thesis are:

How does circuit parameters, such as common mode voltage leveland load impedance, aect passive mixer linearity?

What methods have been proposed to improve passive mixerlinearity and how eective are they?

What are the eects of BB-nonlinearity on passive mixer linear-ity?

What techniques can be used to improve the open loop linearityof BB-ampliers?

Answering these questions is important as modern cellular communic-ations technology requires high receiver performance. Moreover, thedesire for higher levels of integration means that the receiver architec-ture must be compatible with the technology used for digital circuitry.This combined with decreasing permissible total power dissipation aschip sizes scale, due to nite W

mm2 , promotes the passive mixer as alow power and standard CMOS-process compatible alternative to theon-chip Gilbert mixer.

While short channel CMOS as previously mentioned does provide avery high fT [18], issues such as low µ [9, 18], nonlinear output con-ductance [1] and limited supply voltage [18] need to be managed when

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moving RF and analogue circuits to short channel technologies. Notethat in this thesis a complete passive mixer is dened as the combin-ation of a passive-mixer-core and a BB-amplier [10].

1.3 Study areas

This thesis studies the properties of the passive mixer for use in homo-dyne receivers. The topics covered in this thesis include linearity andgain of the passive mixer core in dierent congurations, the impactof nonlinearity in the BB-amplier as well as techniques for improvingthe linearity of wide band ampliers working at frequencies down toDC.

1.4 Research method

This thesis is separated into two distinct parts. Initially a survey ofrecent publications in the eld of passive mixers for RF receivers andDC compatible linearisation techniques for ampliers is conducted.This part of the thesis is conducted as a literature review. Chapters 2to 4 contain the results from the literature review. The later part ofthe thesis focuses on implementations of passive mixers and base bandampliers where dierent congurations and techniques are implemen-ted and compared to each other. Comparisons are done between dier-ent implementations of mixer core, baseband amplier and completemixer circuits to identify promising methods for designing linear directconversion receivers. The later part of the thesis is based on simula-tions performed using Cadence Spectre RF version 7.1 and models fora 65 nm RF/analogue CMOS process. The models used are either ofthe physical-surface-potential (PSP) or BSIM type [19]. PSP mod-els are used whenever available and are particularly important to usewhen simulating the passive mixer core where VDS ≈ 0 due to theBSIM model being discontinuous under these conditions [12, 19].

1.5 Delimitations

As described in Section 1.1 the mixer is but one part of a RF receiver.However, this thesis only covers the mixer core and BB amplier.

4

A further delimitation is that this thesis only covers passive mixerproperties and no techniques for improving the performance of activemixers are considered, active mixers are only included for completenessin a brief comparison of the mixer types in Chapter 2. The thesis ispurely theoretical in the sense that the designs presented here arenot intended to full any wireless standard nor t any specic linkbudget. This has the eect that all circuits are optimised for relativeimprovement in linearity compared to a simple non linearised case andnot optimised toward a set of goals or constraints.

With regards to the circuits studied it should also be noted that simu-lations are only performed at the schematic level. Therefore no layoutparasitics or process induced variability is included and only parasiticsincluded in the transistor model are present. Furthermore, all simu-lations use ideal capacitors and resistors. This is done to simplify thedesign process and as there is no aim of achieving a manufacturableimplementation. Additionally, passive components in modern mixedsignal CMOS technologies, polysilicon resistors and metal-insulator-metal (MIM) capacitors specically, are suciently close to their idealcounterparts that using ideal components does not sacrice validity ofinitial test. None the less, if any of the circuits presented in this thesiswere to be prepared for manufacturing, the use of appropriate modelsfor the passive components and inclusion of layout eects is necessary.

Finally, this thesis aims to study the linearity characteristics of thepassive mixer and linearisation techniques for the passive mixer sys-tem rather than designing a product. This means that the absolutevalue of the performance metrics studied are not of interest but ratherthe relative improvement from the linearised case. The relative im-provement in linearity is expected to be independent of absolute mixerperformance. Therefore, the circuits are not optimised for perform-ance but rather relative improvement in linearity. This means thatcomparisons with performance gures of merit presented by other au-thors is not relevant, as published results are for optimised circuits.Considering this, there is no attempt to compare the results from thisthesis with performance gures presented in literature.

1.6 Contributions

This thesis summarises the properties of passive mixer circuits fordirect conversion receivers. A particularly important contribution is

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the demonstration of the relation between base band linearity andcomplete mixer circuit linearity. The mixer sensitivity to load imped-ance and how this property will inuence the performance relationshipbetween complementary and non complementary switch arrangementsare also demonstrated. A technique for the linearisation of base bandampliers by using a cross coupled dierential pair presented in thisthesis shows promise as a possible approach for improving the linearityof the complete passive mixer circuit.

1.7 Thesis organisation

This thesis is divided into seven chapters. The rst and second chaptercontains background information on mixer circuits and nonlinearity.Chapter three contains an intuitive overview of how the passive mixerworks along with techniques suggested in recent literature for the im-provement of passive mixers. Chapter four presents the results fromthe performed literature review on suggestions for improving linearityof base band ampliers. In chapter ve simulations of passive mixercircuits and linearised base band ampliers as well as complete mixercircuits containing a passive mixer core and a base band amplier arepresented.

Chapter six contains a summary of the results from the work presentedin this thesis. Finally, chapter seven contains the conclusions drawnand suggestions for areas of interest for future studies within this eld.

The thesis has four appendices which contain, in order of appearance,the source impedance model used in the simulations performed in thethesis, the full schematics for the linearised BB ampliers, a descrip-tion of conversion between current/voltage and power and nally timedomain waveforms from the transmission gate symmetry test discussedin Section 5.1.1.

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Chapter 2

Background

This chapter serves as an overview of radio receiver circuits in general,mixers in particular and the impact and origins of nonidealities onreceiver performance.

2.1 Radio receiver circuits

Wireless communication has been an important part of modern societysince the wide spread adoption of telegraphy and radio during thelate 19:th and early 20:th century. Of course this means that a widearray of circuits have been in use for transmission and reception of RFsignals. It is outside the scope of this thesis to describe all possiblereceiver circuits1 however for the sake of completeness a brief overviewof an example RF-transceiver is given in this section. Note that thetransceiver illustrated is not to be seen as an example of a functionalreceiver but rather show the mixers place and function within the RFreceiver. The focus of this thesis is on circuits homodyne receivers, anexample can be seen in Fig. 1.1, why the illustrated transceiver hasonly a single mixer.

Fig. 2.12 illustrates a simplied quadrature, or IQ, modulation basedradio transceiver. Quadrature modulation is illustrated since this kind

1The interested reader can instead refer to The Design of CMOS Radio-

Frequency Integrated Circuits by Thomas H. Lee [9] which has very enjoyablechapter on the history of radio.

2The gure is based o the gure on page 5 in [10].

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PA

LNA

Localoscillator

ADC

DAC

Digital SignalProcessing

I+I-Q+Q-

I+I-Q+Q-

Down-conversion mixer

Up-conversion mixer

Figure 2.1: Block diagram of a simplied quadrature radio-transceiver

of modulation is utilised in modern high data rate wireless communic-ation standards such as 802.11 a/g/n for wireless local area network(WLAN) and 3G/4G cellular telephony networks [4]. In the trans-ceiver of Fig. 2.1, the transmitter chain is highly simplied and isincluded only for the sake of completeness. The receiver chain whichis of greater interest consists of a low noise amplier (LNA) fed bythe receiving antenna. Further the LNA is connected to the mixerthrough a band pass lter. The band pass lter removes any out ofband blockers or distortion present in the received signal. The thenmixer performs an analogue multiplication between the incoming RFsignal and a signal generated by the local oscillator (LO).

The mixer exploits the fact that multiplication in the time domain isequivalent to convolution in the frequency domain [20] thus allowing atime domain multiplication to shift the centre frequency of the incom-ing RF signal. The output from the down-conversion mixer is thenconverted into the digital domain by an analogue to digital converter(ADC) and processed digitally for extraction of the received data. Adetailed description of RF transceiver circuitry is found in books suchas RF Microelectronics by Behzad Razavi [10] and Radio FrequencyIntegrated Circuit Design by John W. M. Rogers and Calvin Plett

2.2 Mixer topologies

In today's RF receivers, two mixer topologies are dominant [10, 14],the active current commutating Gilbert-cell mixer and the other thepassive switch based mixer [10, 14]. An active mixer is illustrated in

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LO-

ZL

LO+

ZL

IF- IF+

RF+ RF-M1 M2

M3 M4 M5 M6

Figure 2.2: Pseudo dierential Gilbert-cell active mixer implementedusing NMOS transistors

Figure 2.2 and the circuit can be interpreted as follows. TransistorsM1 and M2 convert the incoming RF-voltage into a current whichis then switched back and forth between the two cascode transistors,M3/M4 for M1 and M5/M6 for M2, controlled by the LO-voltage.Acknowledging that in a dierential system the currents from M1 andM2 are complements of each other the output signal is then IIF =gmM1,2

·VRF ·VLO where VLO is a square wave toggling between ±1. Thiscorresponds to the desired multiplication between the input signal andLO. The load impedance ZL is responsible for converting the down-converted current to voltage and can either be in the form of a resonanttank for narrow bandwidth applications or a real valued load such asa resistance or MOS current source for wideband applications.

Key aspects of the Gilbert-cell mixer are the fact that the stacking ofMOS-devices consumes voltage headroom, in order to keep all devicesin the saturation region of operation where VGS − VTH < VDS [14],and that the mixer carries a DC biasing current. A passive mixer,illustrated in Figure 2.3, on the other hand carries no DC current andhas no transistors biased in the saturation region of operation whichallows the mixer to operate with low supply voltage [14].

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N_ LO+ N_LO-

IN+

IN-

OUT+

OUT-

Zload

Zload

Figure 2.3: Double balanced passive mixer implemented using NMOStransistors.

The passive mixer can either be operated with a low source imped-ance and high load impedance corresponding to voltage-mode or witha high source impedance and small load impedance corresponding tocurrent-mode. These two implementation have dierent linearity char-acteristics and circuit requirements. For instance, the current-modemixer should ideally have no voltage swing at the output node as theBB current is sunk into a low impedance node. This means that theeective overdrive voltage of the mixer switches is independent of thesignal amplitude. This improves linearity of the receiver but demandsthat the BB amplier is designed so as to achieve a very low inputimpedance.

The voltage-mode mixer on the other hand suers from voltage swingat both input and output nodes. However, as the BB impedance isnot required to be low, implementation of the BB amplier is lessconstrained than in the current-mode case. The main concern forvoltage-mode circuits is that the BB impedance needs to be high overthe whole signal band, which implies that the capacitive load at theBB nodes will give the mixer core a low pass response. Passive mixersare discussed further in Chapter 3.

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2.3 Nonlinearity in mixers

In a general case the signal processed in a RF receiver circuit is nota single tone. Rather the signal is comprised of several frequencies ofvarying amplitudes. In the receiver chain this presents an interestingfeature. As, in a general sense, any amplier device has a transfercharacteristic of the form:

Vout = DC + a1 · Vin + a2 · V 2in + a3 · V 3

in + · · · , (2.1)

where Vin is the input signal. Considering Vin as comprised of n tones,Vi where i = 1, 2, ..., n, then V 2

in will be equivalent to

V 2in = (V1 + V2 + · · ·+ Vn) 2 (2.2)

which in the case of n = 2 expands to:

(V1 + V2)2 = V 2

1 + 2 · V1V2 + V 22 . (2.3)

The resulting frequency domain convolution of V1and V2, in the term2 · V1V2, will generate a signal at the sum and dierence of their re-spective frequencies3 [10]. This also holds for the higher order termswhich are all present in the intermodulation distortion generated bythe mixing action, which happens due to the nonlinear transfer func-tion. The third order distortion is particularly troublesome as forn = 2 the frequencies 2 ·fV1−fV2 and 2 ·fV2−fV1 are generated. If thedierence between fV 1 and fV 2 is small then these intermodulationproducts will end up within the signal band. Consequently, attenu-ation of third order distortion is dicult to achieve through ltering.

Hence to avoid in-band distortion components it is required that allcircuits are designed for high linearity, or equivalently minimise coe-cients a2, a3, · · · , an. To do this it is necessary to determine the originof nonlinearity in down conversion mixers.

In the simulations performed in this thesis, the output referred inter-cept points are often used as a measure of circuit linearity [10]. Whencomputing the output referred intercept point the linear extrapolation

3Using the trigonometric identity sin (ω) sin (φ) = cos(ω−φ)+cos(ω+φ)2 is also pos-

sible and will yield the same results as performing the frequency domain convolu-tion.

11

method described in [10] is used. This method is described in detailin the next section. As the circuits studied are dierential and sim-ulated without process induced mismatch any even order distortiongenerated in the circuits will be cancelled. Therefore, whenever evenorder nonlinearity is measured, the measurements are done for thesingle-ended version of the circuit.

2.3.1 Linearity gures of merit

To facilitate comparisons of the linearity of the studied circuits theoutput and input referred intercept points, abbreviated OIP and IIPrespectively, are used. The intercept points are the linear extrapol-ation of nonlinearity at signal levels far from the −1 db compressionpoint [10]. From Equation 2.1 it is seen that the second order dis-tortion increases by the square of the output voltage and the thirdorder distortion by the cube. This is under the assumption that theamplier characteristics are constant for dierent input signal levels.

Equivalently to above, if the output voltage amplitude increases by1 dB then the second order distortion increases by 2 dB and the thirdorder distortion by 3 dB [10]. Consequently, the output level wherefundamental and second order distortion tones are equal sized is:

OIP2 = Vfund −∆fund-IM2, (2.4)

as for every dB of increase in the fundamental level, the dierence∆fund-IM2 decreases by 1 dB. Similarly, for third order nonlinearity:

OIP3 = Vfund − 0.5 ·∆fund-IM3. (2.5)

The input referred intercept point is calculated using the same meth-ods but is compensated for system gain by:

IIPx = OIPx − AV. (2.6)

It should be noted that the circuit will not be able to operate atsignal levels close to the output referred intercept point as this levelis commonly above the −1 dB compression point. Another interestingproperty of the use of OIP and IIP as performance metrics is the eectof linear gain and loss. From Equation 2.6 it is seen that if Av increasesthen IIPx decreases which implies that IIPx can be maximised byheavily attenuating the signal. Considering this, the use of IIPx andOIPx as gures of merit should only be done in conjunction with thecircuit gain.

12

2.3.2 MOSFET nonlinearity

The dominant sources of nonlinearity in the mixer core are dierent forpassive and active mixers implementations. However, their origins arealways the same. For MOSFETs in the saturation region of operationboth the transconductance, gm, and on-conductance, gds, are nonlinearand contributes to the generation of distortion [12]. For active mixersthe dominant source of nonlinearity is transconductance nonlinearitywhereas in passive mixer on-conductance is dominant [12, 14].

To a rst approximation [7], the current through a MOSFET in thesaturation region follows a square law relationship to the gate voltage.Hence, the output current for large signals is approximately the squareof the input voltage or equivalently a2 from (2.1) is large. In spite ofthis, for small movements around the bias point, which is the funda-mental assumption in small signal analysis, a square law device is closeto linear. This is understood by considering the equation (2.1) as asimplied notation for a Taylor series which, for suciently small Vin,as is the case for any Taylor series, is accurate using only the linearterm [20].

The real MOSFET is however not a pure square law device but ratherhas a higher order nonlinear voltage to current relationship [3, 21]where g

′m is dominant in generation of second order distortion whereas

g′′m generates third order distortion. The magnitudes of gm, g′m and

g′′m vary dependent on the operating point chosen for the transistor.The variation of g′m and g′′m with VDS held constant is as illustratedin Fig. 2.4. From Fig. 2.4 it is seen that the magnitudes of the higherorder transconductance derivatives vary for dierent amplier biaspoints.

Moreover, considering other sources of nonlinearity such as gds which,similarly to gm is dependent on the transistor bias point, it is easilyunderstood that gds characteristics will contribute to nonlinearity inMOSFET circuits [13]. The nonlinearity of the on-conductance is ofincreasing importance for short channel devices and is an importantcontributor to distortion in passive mixers [13, 22, 1].

Furthermore device capacitances vary nonlinearity with VGS and VDS,particularly at higher frequency [1], which also generates distortion [12].However this eect is limited and according to [12] it is not as import-ant to consider as nonlinearity due to gm or gds.

13

0

2

4

6

8

10

12

0 100 200 300 400 500

I DS [

mA

]

VGS [mV]

IDS

0

5

10

15

20

25

30

35

40

0 100 200 300 400 500

gm

[m

A/V

]

VGS [mV]

gm

0

20

40

60

80

100

120

140

0 100 200 300 400 500

gm

' [m

A/V

2]

VGS [mV]

gm'

-600

-400

-200

0

200

400

600

800

1000

1200

0 100 200 300 400 500g

m'' [

mA

/V3]

VGS [mV]

gm''

Figure 2.4: Transconductance and derivatives for a 65 nm CMOSprocess high performance analogue, extra low VTH and high outputimpedance, NMOS transistor,W/L = 33× 2/0.14 µm. VDS = 0.3 V

ZHANG AND SÁNCHEZ-SINENCIO: LINEARIZATION TECHNIQUES FOR CMOS LOW NOISE AMPLIFIERS: A TUTORIAL 33

Fig. 20. Vector diagram showing the 180 out-of-phase contribution of term on the upper and lower IM3 components [38].

Fig. 21. NMOS output conductance nonlinearity characteristics (UMC 90 nmCMOS process, , , ).

Another major contributor to this dependence is the IM3asymmetry, also called “sideband asymmetry.” IM3 asymmetryis attributed to various types of memory effects [37]–[40], butfor CMOS LNAs specifically, it is because the reactive part ofthe circuit impedance (e.g., termination impedance) athas a 180 -out-of-phase contribution to the IM3 components at

and . This concept is qualitatively illus-trated by the vector diagram in Fig. 20 [38], where therefers to the first-, second-, and third-order Volterra-Series co-efficients. The IM3 components at andhave different imaginary parts (i.e., reactance), resulting in IM3asymmetry.

Note that this IM3 asymmetry depends on bias and frequency.For very small two-tone spacing, it is hard to see any IM3 asym-metry since the reactive-impedance effect at is negligible;but for larger , the reactive impedances at the second-har-monic frequency also contribute differently to the lower/upperIM3 components, which worsens the IM3 asymmetry [7] andalso indicates a more obvious IIP3 dependence on two-tone-spacing. However, proper bias can reduce this IM3 asymmetry[40]. Note that in the multitone case, Adjacent channel powerratio (ACPR) asymmetry is defined correspondingly.

IV. LNA LINEARIZATION IN DSM TECHNOLOGY

A. Nonlinearity From Output Conductance

Distortion of MOS transistors is mainly caused by the non-linear transconductance and output conductance .Previously published linearization techniques mainly focus onlinearizing , assuming that (1) drain current is controlledonly by the gate-source voltage , and (2) nonlinearityis negligible. These assumptions are valid for small load resis-tance, small voltage gain, small input signal, and a drain-sourcevoltage sufficiently large that the small-signal variationof does not appreciably perturb the bias point.

However, as technology scales down, the nonlinearity be-comes more prominent. Current is controlled not only bybut also the , which can be approximated by the two-dimen-sional Taylor series [29], [44]

(30)

where is the -order transconductance as defined in (6);represents the nonlinear output conductance effect which is pro-portional to the derivatives with respect to ; is thecross modulation term describing the dependence of onor on , as formulated in (31)

(31)

To characterize the nonlinearity for a single transistor, we fixits , and sweep the , by taking the first three derivatives ofthe drain-source dc current with respect to [as defined in(31)] at every dc bias point, we can obtain Fig. 21. It is observedthat the drain current is modulated a lot by . is largewhen the transistor operates at small ; while it decreases forlarge values.

Here we assume a negligible nonlinearity contribution from, otherwise three-dimensional Taylor series should be used

instead.From (30), the distortion is contributed by four parts.

1) nonlinearity due to nonlinear relation.2) nonlinearity from channel length modulation effect.

Note that contributes less nonlinearity when device op-erates deeper into saturation region.

3) the dependence of on , (partially due to the draininduced barrier lowering (DIBL) effect [29].

4) the dependence of on , especially in saturation re-gion [44].

The cross modulation effect remains fairly constant for abroad range of , while is more linear and becomesmore nonlinear as increases, decreases, and transistorsoperate close to the linear region. In [29] the . crossterm cancels the intrinsic second-order distortion toobtain an amplifying stage with high IIP2. Note that when

nonlinearity dominates (i.e., output limited), the tradeoffbetween gain and linearity becomes more severe.

Figure 2.5: Nonlinearity of gds with varying VDS, UMC 90 nm process,W/L = 20/0.08µm, VGS = 0.5V, gure from [1].

14

2.3.3 Device mismatch induced nonlinearity

In a dierential circuit any even order distortion components will endup at the positive and negative outputs in phase. This means that inthe mismatch free scenario even order distortion would only appear asa common mode signal which is rejected by the dierential operation.However, device mismatch and layout eects will make the dierentialpaths unequal which in turn will limit the eectiveness of even orderdistortion cancellation.

In a passive mixer, threshold voltage mismatch among the switcheswill cause the on state conductance to vary among the switches aswell as the eective LO-duty cycle [23]. This aects both conversiongain and mixer linearity. Hence techniques to limit the amount ofmismatch between the dierential paths are key high IP2 designs.

2.3.4 Noise in mixer circuits

Considering the Gilbert mixer given in Fig. 2.2, in this circuit noise isprimarily contributed by the transconductance transistor and the loadimpedance. In the Gilbert mixer the switching transistors are operat-ing as cascodes which means that they do not contribute signicantlyto the total output noise [7]. Noise is contributed by the transcon-ductance transistor through two mechanisms. At low frequencies thedominant source is icker noise, the origin or which is not yet com-pletely understood [24], whereas at high frequencies thermal noise isdominant [7].

The thermal noise current generated by a MOSFET operating in thesaturation region of operation is proportional to its transconduct-ance [24] which for a Gilbert mixer is rmly connected to bandwidthand gain. However, it should be noted that while the absolute noisecurrent increases with increasing transconductance, the input referrednoise voltage will decrease provided that amplier gain increases. Theicker noise current on the other hand shows a quadratic dependence ofthe quiescent current in the device [24]. As previously mentioned, thequiescent current directly aects transconductance, bandwidth andlinearity for a transistor of a given size. With this in mind, it can easilybe seen that the designer has to face a noise/bandwidth/gain/linearitytrade-o when designing Gilbert mixers and that the quiescent currentowing through the transconductance device will cause a considerableamount of icker noise at the output node.

15

The passive mixer avoids the issue of icker noise as the switch tran-sistors do not carry any DC current. This means that the amountof generated icker noise will be minimal [11, 24]. Furthermore, thethermal noise generated by the switch transistors is dependent onlyon on-conductance which is largely determined by transistor size [24].This implies that the passive mixer has the potential to be less noisythan the Gilbert mixer. This is particularly the case for low frequen-cies where icker noise is dominant. In direct conversion receivers thisaspect is worth considering as interesting signal may end up close tothe icker noise corner frequency after down conversion.

It should not be forgotten that while the passive mixer core is intrins-ically low noise the fact that the signal passing through the mixersuer from conversion loss [10] means that the mixer will typically befollowed by a gain stage which will contribute to system noise factor.In some cases the BB amplier in the passive mixer will dominate thenoise gure of the complete mixer circuit [17].

2.4 Nonlinearity of cascaded systems

When cascading several stages of ampliers or frequency converters,as is the case with the passive mixer where the mixing action occursin a separate stage from the BB amplication, it is of interest to de-termine which stage that dominates system nonlinearity. As describedin [10], the IIP of a stage in a receiver when seen from the input of thesignal chain is determined by the amount of preceding gain. Basicallythis comes from the expression in Equation 2.6 if IIPx is referred tothe input of the signal chain. Therefore, the input referred interceptpoint of the complete signal chain can not be higher than that of theamplier stage which has the smallest input referred intercept pointwhen computed using this method.

For the passive mixer which in general has a conversion gain closeto −4 dB [10] the IIP of the succeeding stage is in fact scaled up by4 dB when referenced to the input of the mixer. Hence, if the IIPof the passive mixer core is close to that of the BB-amplier thenlinearisation of the passive mixer core will have the most impact onmixer performance. That is as the eective IIP of the BB-amplierincreases by the loss in the passive mixer core.

However, it should also be noted that as the passive mixer linearity isvery dependent on load and source impedance, the BB amplier has an

16

even greater impact than just its intrinsic linearity [12]. Additionally,as the passive mixer core is in itself very linear, relative to the activemixer [14], the open loop linearity of the BB amplier is likely to havea considerable impact on complete circuit linearity.

17

Chapter 3

The passive mixer

This chapter discusses the basic working principles of the passive mixeras well as methods proposed in literature for the improvement of pass-ive mixer performance. The structure of a single-ended voltage-modesampling passive mixer is shown in Fig. 3.1.

3.1 Explanation of mixing action

Considering the circuit of Fig. 3.1 and assuming that the source atthe RF terminal has zero output impedance and the load in the IFterminal has an innite impedance, so that no current is drawn fromCBB. Under these assumptions it is easily seen that when the switchis closed the voltages at the IF and RF nodes are identical. When theswitch opens, the RF voltage is sampled and stored on CBB. In Fig. 3.2the time domain waveforms of this system are illustrated, where a high

RF IF-AV

LOZ

f

RF IF

LO

CBB

Figure 3.1: Conceptual view of a voltage-mode sampling passivemixer.

18

-1

0

1

VRF

0

0,5

1

VLO

-1

0

1

VIF

Figure 3.2: Time domain waveforms in voltage-mode sampling passivemixer.

LO voltage implies that the switch is closed. The frequencies fLO andfRF in the gure have the relation fLO = 5

3fRF .

The frequency translation is not evident from the illustration. How-ever, considering that the output waveform can be described, ignoringthe hold capacitor for simplicity, as a multiplication between VRF andthe VLO toggling between 0 and 1.Thus:

VIF = VLO · VRF , (3.1)

which as described previously in this thesis, and in [20, 10, 7], corres-ponds to the frequency domain convolution:

fIF = fLO ∗ fRF . (3.2)

As explained in Section 2.3 this will generate the frequencies:

f1 = fRF − fLO & f2 = fRF + fLO, (3.3)

one of which is at a lower frequency than fRF and the other at a higherfrequency than fRF . Schematically, if fLO is close to fRF , the fre-quency domain operation will be as illustrated in Fig. 3.3. In Fig. 3.2

19

fRF f

LO≈fRF

freq freq

freq

power

powerpower

fIF ≈0

Figure 3.3: Frequency domain translation of RF input signal in a downconversion mixer.

the resultant frequencies are 25fRF and 8

5fRF . If FLO is identical to

fRF , as is the case in homodyne receivers, then the base band signalwill appear at frequencies around 0. This means that the signal nowappears at frequencies where it can be fed straight to an analogue todigital converter for digital processing as illustrated in 2.1.

3.2 Conversion loss in the passive mixer

As the output of the passive mixer core is either identical to the inputsignal, when the switch is closed, or a static voltage sampled at the endof the LO period, it is also possible to have the mixer return to zeroafter each LO period but this gives even more loss [10]. From this itis understandable that the conversion gain must be unity or less thanunity. The actual conversion loss will not be derived here but in [10]it is shown to be between 1

π, for single ended passive mixers stemming

from the amplitude of the square wave fundamental [10], and unity,for mixers with an LO that is an ideal impulse train [20, 10].

Most commonly, the passive mixer is used in a dierential congur-ation which gives the conversion gain of 2

πand 2·

√2

π, −4 and −1 dB,

for 50% and 25% duty cycle mixers, respectively [10]. Note that theconversion gain is the same for mixers having both dierential andsingle ended inputs.

20

RF IF-AV

LOZ

f

RF IF

LO

CBB

Figure 3.4: Illustration of a current-mode passive mixer.

3.3 Current-mode passive mixers

The passive mixer can also be congured to operate in current-mode,determined largely by the relationship between source and load im-pedances [10], as illustrated in Fig. 3.4. In the current-mode mixer,the source has a large output impedance whereas the load has an inputimpedance that is small, ideally zero. This implies that the voltageswings in a current-mode passive mixer will be small.

Small voltage swings indicates that the eects of MOSFET nonlineartransconductance and on-conductance will be small. Intuitively, thecurrent-mode mixer should therefore be more linear than its voltage-mode counterpart [10]. Another eect of the current-mode passivemixer is that if the feedback impedance, Zf in Fig. 3.4, has a low passcharacteristic, as is desired to lter out the up-mixed terms and highorder harmonics, then the input impedance will have a bandpass char-acteristic [10]. This lack of isolation between RF and BB impedancescan be used for matching the passive mixer to the RF source, evenallowing for passive mixer rst receivers [25].

With regards to the mixing action the current-mode mixer worksidentically to the voltage-mode mixer described in Section 3.1. How-ever, the current output from the mixer core will have a return tozero characteristic [10] if the feedback impedance does not have acuto frequency much lower than the LO frequency. If this is thecase, the output will be an integrated version of the input currentwaveform.

21

3.4 Variations on the basic passive mixer

circuit

This section describes modications of the simple NMOS based passivemixer core presented in recent literature. Additionally the conceptof charge injection induced nonlinearity is discussed. The section isdivided into subsections each describing a proposed variation on thepassive mixer core proposed in recent literature.

3.4.1 CMOS transmission gates

As discussed in Section 2.3 important contributors to MOSFET non-linearity are the derivatives of gm and gds. Therefore, any method thatkeeps gm or gds constant will improve mixer linearity. In a recent pa-per [13], passive mixers utilising a complementary switch network, inpractice CMOS transmission gates, were proposed to improve the lin-earity of the mixer core by cancelling transconductance nonlinearity.This concept has previously been discussed and implemented by otherauthors [15, 16]. However the claimed results, obtained through sim-ulation and computation, presented by [13] are very impressive witha claimed IIP3 improvement in the range of 10 − 15 dB whereas [15]and [16] primarily claims an improvement of IIP2. Improvement ofIIP2 would appear from the same mechanisms and in particular mak-ing the switch characteristics symmetrical around the bias point.

The reason for the supposed linearity improvement when using CMOStransmission gates instead of a pure NMOS or PMOS based mixer isunderstood by considering the VGS ↔ gm relationship. As gm is de-pendent on VGS any variation around the bias point will modulate theswitch transistor gm. This means that for an NMOS based mixer theswitch transconductance will decrease for high signal amplitude whichcompress the signal. However a PMOS mixer will suer from the sameeects but in reverse, decreasing common mode voltage decreases VGSand gm. In a transmission gate on the hand, the total transconduct-ance will be relatively constant over common mode voltage. Intuitivelythis is understood by considering the complementary behaviour of theNMOS and PMOS transistors gm. This means that for the matchedtransmission gate both g′m and g′′m are small giving suppression of dis-tortion [13].

22

The validity of the explanation given in [13] is questionable as thetransistors of a passive mixer work in the triode region and thus thetransconductance is less important than the on-conductance. This isstudied in further detail in Chapter 5 where the connection betweenon-conductance characteristics and nonlinearity is studied.

An alternative approach to using complementary switch networks forcancelling out gds ←→ VGS dependence is to make the gate bias voltagetrack the down converted voltage using a technique called bootstrap-ping [16]. This can be accomplished by resistive coupling of the outputnode to the gate of the switch device [16], while feeding the LO througha capacitor. This, will make the gate bias a low pass ltered versionof the output voltage. However, this will also mean that if the LOhas full rail to rail voltage swing then the resulting LO waveform atthe switch transistor gate will risk going above or below the supplyrails. While it is possible to drive the transistor gate outside the sup-ply rails, provided that no part of the switch transistor is driven intobreakdown, doing so should be done with caution. Considering this,the bootstrapping technique is not studied further in this thesis.

3.4.2 Resistive degeneration of mixer switches

As described in Section 2.3.3 variation of threshold voltage and switchon-conductance amongst the switches will give rise to second ordernonlinearity in dierential passive mixers, by limiting the eective-ness of dierential operation. To counteract these issues techniquessuch as digital calibration of switch gate bias [23], not covered in thisthesis, or connection of degeneration resistors in series with the mixerswitches [17] have been proposed.

The main idea behind the degeneration resistors is to swamp out vari-ation in on-conductance amongst the mixer switches by connectingresistors in series with the mixer switches. The series resistors canbe made to match closely by using appropriate layout techniques andhave a highly linear voltage to current characteristic. If the seriesresistors are large in comparison to the on-conductance the switchcharacteristics will then be largely dened by the resistors. The de-generation resistors are very linear and if well matched will help reducegain mismatch between I and Q channels. This should, provided thatthe current source feeding the mixer can drive the increased inputimpedance, make the input current independent of transistor nonlin-earity and switch mismatch. This circuit modication is targeted at

23

current-mode mixers having a mixer core followed by a transimped-ance amplier (TIA) that converts the downconverted current intovoltage.

A further improvement is that the series resistors give the mixer corea higher output impedance as seen from the input of the TIA whichlowers its noise contribution [17]. It should however not be forgottenthat the resistor itself will contribute to noise in the mixer circuitwhich may degrade the total noise gure.

3.4.3 Charge injection cancellation

A passive mixer with a less than 50% duty cycle LO is eectively atrack and hold circuit. This is especially true in the case of a voltage-mode mixer with capacitive load, as illustrated in Chapter 3, but alsofor current-mode mixers where the output time constant is much largerthan the LO period. As is known, the accuracy of a track and holdcircuit suers from the channel charge being injected into the holdcapacitor when the switch device turns o [26].

For the passive mixer amplitude accuracy is not crucial but the peri-odic charge injection will cause an approximately square shaped wave-form to be superimposed on the down mixed signal. In the singleended case this will cause energy to appear at the LO frequency inthe downconverted signal, which is of course cancelled to a limited ex-tent by dierential operation. Furthermore as the charge stored in thechannel is dependent on transistor capacitances which are nonlinearthe charge injection error will vary nonlinearly with the input signal.Note that as the channel charge will always push the stored voltage inone direction it is expected that charge injection primarily generateseven order distortion.

To suppress charge injection eects a common approach is to add adummy switch device sized to half the size of the primary switchdevice [26]. By switching the dummy device out of phase with themain device any charge injected into the hold node will be absorbed bythe dummy device, which shares the operating conditions of the mainswitch, reducing the eects of charge injection. The eectiveness ofcharge injection cancellation in passive mixers is studied with furtherdetail in Chapter 5.

24

LO+ LO-

IIF-

IIF+

IRF+

IRF-

Iq

Iq

Figure 3.5: Current mirror mixer similar to the circuit from [2]

3.4.4 Mixing using switched current mirrors

Another recent paper [2] presents a novel approach to the passivemixer where the switches in the passive mixer are embedded within acurrent mirror arrangement. The primary improvements claimed bythe authors are wide bandwidth and low-noise. This circuit does notappear to be highly linearity. According to the comparison in [2], themixer has an IIP3 which is more than10 dB lower than those to whichit is compared. However, the current mirror arrangement allows forcurrent multiplication and low power.

While this circuit is identical to a voltage amplier using diode con-nected PMOS loads feeding a sampling passive mixer the matchingof the mirror devices provide interesting opportunities. The size ratiobetween the diode load and the load transistors, those connected tothe output of the mixer core, allows for current multiplication to occur.Current multiplication is ideally linear as it is only a function of therelative sizes of the mirror transistors. Additionally, if the transcon-ductance transistors in the circuit presented in [2] were to be replacedwith a current source this approach could be utilised for a currentin - current out mixer. Avoiding the common source gm stage usedin [2] allows for higher linearity as the nonlinear transconductance isavoided. This mixer idea is illustrated in Fig. 3.5. The circuit whilenovel is not included in this thesis as the circuit is very dierent com-pared to the common mixer core + TIA conguration which is themain focus of this thesis. Therefore, the circuit is left as a subject forfuture studies in this area.

25

Chapter 4

Baseband ampliers

As the signal passing through a passive mixer suers from conversionloss there is an apparent need for additional amplication. Dependingon the mixer implementation, voltage or current mode, the amplic-ation is done either by a pure voltage amplier or a TIA. The TIA isconveniently implemented using an operational amplier with resistivefeedback [17, 27]. In order for the TIA to have low input impedance,as is desired in current mode mixers, the operational amplier needs alarge amount of gain. To achieve high gain, the operational ampliercan be constructed using a multi stage approach [28, 17]. However,multistage designs require extensive frequency compensation to main-tain stability which limits achievable bandwidth [7].

In this thesis, the designed mixers and ampliers are not measuredagainst any specication. However, focus is on BB ampliers witha −3 dB bandwidth of approximately 1 GHz. The high bandwidthalong with the stability issues in multi stage designs, due to the ad-ditional poles, makes single stage designs the only ones considered inthis part of the thesis. This does limit the achievable gain as µ fora short channel MOSFET is approximately 20 dB [18]. Furthermore,this limits the achievable gain in feedback conguration and possibledistortion suppression by negative feedback [29]. Considering this,methods for improving the open loop linearity of the base band amp-lier are studied in this chapter. Open loop linearity is studied asclosed loop linearity shows a superlinear dependence on open loop lin-earity [29]. This is particularly the case for 3rd-order distortion [29]. Itshould however be noted that techniques for increasing the open loopgain of the base band amplier are also viable ways for improving

26

closed loop linearity, provided that this technique does not excessivelydegrade open loop linearity.

4.1 Derivative superposition

Recognising the impact of transconductance nonlinearity, the derivat-ive superposition technique seeks to null out this nonlinearity. This isdone by connecting an auxiliary linearising transistor in parallel withthe main amplifying transistor [1, 21]. In practice the derivative su-perposition technique seeks to broaden the area in Fig. 2.4 where g′′mis zero. This area is called the moderate inversion region [30]. In thederivative superposition amplier nulling of g′′m is achieved by biasingthe main and auxiliary transistors in dierent operating points so thattheir g′′m have opposite signs, as per Fig. 2.4. By sizing the transistorscorrectly, the eective g′′m of the composite transistor can be reduced toalmost zero [1, 21]. The input bias range where this occurs is limitedwhen using a single auxiliary transistor. If a wider input bias range isdesired then connecting multiple auxiliary transistors in parallel withthe main device can give a wider g′′m null at the expense of increasedcapacitive load on both input and at the drain of the amplicationtransistor [31].

For dierential ampliers it is possible to get a similar eect by drivingthe auxiliary transistors with an out of phase signal and biasing themso that g′m and g′′m have identical signs as the main transistor. Thisallows for minimisation of both third and second order nonlinearityin dierential operation. In practice this widens the allowable inputoset voltage for which second order nonlinearity is cancelled by thedierential operation.

In RF or microwave circuits, biasing transistors is typically done throughresistive coupling to the gate from the bias generation circuitry [1, 21].The signal is then fed to the amplier through AC-coupling capacit-ors. As there is no DC connection between the gates of the main andauxiliary transistor, their biasing conditions can be set independently.

This is however not possible in a direct conversion receiver where thefrequency of the down-converted signal may reach as far down as toDC which prevents AC coupling the input signal. Therefore, it isnecessary to use some other way of establishing separate biasing forthe transistors in the derivative superposition amplier. One way of

27

a)

MA

MX

MC

IA

IC I

X

Vshift

Rload

VbiasC

IN

OUT

b)

MA

IA

IX

MX

IC

MC

VX R

load

VbiasC

IN

OUT

Figure 4.1: Concept for DC-implementation of derivative superposi-tion ampliers where a) is an NMOS based amplier with VGS shiftedby a voltage source and b) a CMOS implementation inspired by theGilbert mixer in [3].

doing this is to introduce a non degenerative DC shift connected to thesource of the auxiliary transistor or using a PMOS [3] device connectedto positive supply. These two methods are illustrated in Fig. 4.1.Implementation of the source connected DC shift can be done witha tail current source for dierential circuits with some limitations asoutlined in Section 5.2.2.1.

4.1.1 Designing derivative superposition ampliers

As the concept of derivative superposition ampliers is derived fromthe low frequency large signal behaviour of the MOS transistor design-ing such an amplier is initially done using DC-analysis as outlined in,albeit for an alternative structure, [32]. The rst step of designing aderivative superposition amplier is to select the amplier transistor,MA in Fig. 4.1, size and bias current to achieve the desired gm, noiseand bandwidth. Next, the auxiliary transistor,MX in Fig. 4.1, is sizedby sweeping the gate bias voltage and measuring the currents IX , IAand IC as labelled in Fig. 4.1.

By computing the numerical derivatives of the currents IX , IA andIC the transconductance and its derivatives are obtained. For the

28

MA1

MX1

MC1

MC2

MA2

MX2

MTail

MSP1,2

VbiasSP

VbiasC V

biasC

IN+ IN-

- + OUT

Rload

Rload

Figure 4.2: Amplier used to measure the transconductance charac-teristics of Fig. 4.3

amplier of Fig. 4.2 the corresponding transconductance and deriv-atives is as illustrated in Fig. 4.3. The plots shown in Fig. 4.3 arethe dierential transconductances. Dierential transconductance ismeasured as for dierential circuits this quantity denes the transfercharacteristics. Single ended or common mode linearity is primarily ofinterest when considering mismatch which should be minimised as wellby using this technique. Considering this, it is preferable to constructcircuits using dierential transconductance derivatives to predict openloop linearity.

Fig. 4.3 shows an example where both g′m and g′′m of the main and aux-iliary transistors are well matched. However, as previously described,if this was not the case then tuning the size and/or bias current ofthe auxiliary transistor, MX , so that its g′m and g′′m are well matchedto that of the primary transistor, MA, would be possible. This is un-derstood as both g′m and g′′m for the auxiliary transistor have oppositesigns when cross connecting the transistors as in Fig. 4.2. Dependingon the topology used the nulling of g′m and g′′m may come at the ex-pense of loosing some transconductance, this is the case for the circuitof Fig. 4.2 whereas a non cross coupled circuit such as those in Fig. 4.1would not suer transconductance loss.

29

-400

-300

-200

-100

0

100

200

300

400

-50 -25 0 25 50

gm

' [m

A/V

2]

ΔVin [mV]

gm' Ma

Mx

Mc

-10

0

10

20

30

40

50

-50 -25 0 25 50

gm

[m

A/V

]

ΔVin [mV]

gm

MaMxMc

-50

-40

-30

-20

-10

0

10

-50 -25 0 25 50

gm

'' [

A/V

3]

ΔVin [mV]

gm''

Ma

Mx

Mc

Figure 4.3: Dierential gm and its derivatives for the amplier inFig. 4.2. Voltage on the vertical axis is peak to peak dierential inputvoltage.

When constructing a derivative superposition amplier it is desirableto connect the drains of the auxiliary and primary transistor to a lowimpedance node. This is to ensure that the voltage swing across thenonlinear gds of the transistor is kept low which ensures that gm non-linearity is the primary source of nonlinearity in the transconductancestage of the amplier. Furthermore, a low impedance node allows theoutput currents to sum with minimal disturbance by gds due to currentdivision, making the implementation closer to an ideal summation.

4.2 Post distortion

A technique which is similar to derivative superposition is post dis-tortion where an auxiliary device is added after the main amplifyingdevice to cancel the intermodulation distortion. The circuit of Fig. 4.4is discussed in [1] and [32]. The circuits bias the common gate tran-sistor MA so that it sinks distortion current generated by the primarytransistor MA. This improves the linearity of the equivalent transcon-ductance stage as seen from the source of MC .

Unfortunately the PMOS common gate post distorter steals some of

30

VgP

VbiasC

MA1

MX1

MC1

Rload

VbiasSP

IN+ IN-

-OUT+

VbiasC

VbiasSPR

load

MA2

MX2

MC1

MSP2M

SP1

VgP

VbiasSN

MSN1,2

MSF1

MSF2

Figure 4.4: Post distortion amplier using a PMOS common gate IM3sinking device

the signal current, which reduces the amplier gain. To alleviate thisissue, current sources can be added in parallel to the load resistorsas the transistors MSP in Fig. 4.4. This is the same approach asin the amplier in Fig. 4.2. The current source allows for the loadresistor Rload to be increased in size whilst still being the main cur-rent to voltage conversion device. Provided that the current sourcehas a high enough output impedance the amplier gain will still begmeff

· Rload, where gmeffis the eective transconductance of the lin-

earised transconductance stage. However, as the output impedanceof short channel CMOS is limited, nonlinear gds will still contributeload nonlinearity in the circuits of Fig. 4.2 and 4.4. This limits theeectiveness of the transconductance linearisation. This is studied ingreater detail in Chapter 5.

31

Chapter 5

Simulation results

This chapter covers simulation congurations and results for the mix-ers and ampliers designed in this thesis. The chapter is subdividedin three parts. Simulations of the properties of the passive mixer core,design and simulations of linearised BB ampliers and the perform-ance of passive mixers incorporating linearised BB ampliers is treatedeach in their own section. For all mixers and ampliers presented inthis chapter the substrate connection of all transistors is tied to supply,negative supply for NMOS transistors and positive supply for PMOStransistors. This is not explicitly shown in schematics to facilitatereadability.

All mixer simulations in this chapter are run at 4 GHz LO frequency.This frequency is chosen as 3G uses frequencies around 2 GHz [4]which is doubled to put further strain on the mixer. In general, anyfrequency close to 4 GHz could be used for the simulations presentedand would yield similar results. However, as stated, results are onlypresented for the case of a 4 GHz LO.

5.1 Passive mixer core

To study the eects of using complementary switches in the passivemixer, the basic circuit from Fig. 2.3, reprised here as Fig. 5.1, is used.The load marked ZL in the gure is the sum of all loads on the mixer.In the tests performed in this section this is just device capacitances,i.e. no additional load connected, or a sampling capacitor. For thecurrent-mode mixers the load is that of the TIA input impedance. In

32

N_ LO+ N_LO-

IN+

IN-

OUT+

OUT-

Zload

Zload

Figure 5.1: Double balanced passive mixer implemented using NMOStransistors. Reprise of Fig. 2.3 from Chapter 2.

Fig. 2.3, the mixer output nodes are biased either through the TIAinput reference voltage or by direct coupling the signal to the mixerand DC-shifting it to the desired common mode level.

For the dierent congurations, only the transistors are changed andof course LO-polarity, which means that the mixers are tested underidentical conditions. One interesting property of this circuit is that itis very easy to study the impact of load impedance on the circuit. Thisis as there are no other non ideal components apart from the mixercore. Therefore the load impedance is solely determined by what isconnected to the output node of the mixer.

5.1.1 On-conductance nonlinearity

In a passive mixer, the switch transistors should either be in the ostate or the triode region of operation. Any time spent outside thesetwo regions of operation, as during LO transitions, will generate anonlinear transfer characteristic as the switch transistor has a nonconstant conductance under these conditions. However, ignoring thiseect it can also be observed that the transistor on-conductance showsa nonlinear dependence to conducted current, or equivalently voltageapplied across the drain and source terminals. By performing a test

33

0,5

1,0

1,5

2,0

2,5

3,0

3,5

-50 -25 0 25 50

gd

s [

mA

/V]

Vds [mV]

gds

NMOS gds

PMOS gds

-3

-2

-1

0

1

2

3

-50 -25 0 25 50

gd

s' [m

A/V

2]

Vds [mV]

gds'

NMOS gds'

PMOS gds'

Tgate gds'

-150

-100

-50

0

50

100

150

-50 -25 0 25 50

gd

s'' [

mA

/V3]

Vds [mV]

gds''

NMOS gds''

PMOS gds''

Tgate gds''

Figure 5.2: On state conductance of 7× 1/0.06 µm NMOS/PMOS tran-sistors, VGS = 0.6V, VDB = VSB = 0.6V.

which is similar to the Gummel symmetry test [33] the on state res-istance and its linearity characteristics can be studied.

Fig. 5.2 shows the results of such a test where the on-conductancewith derivatives is studied. The test is performed for equal sized,both 7× 1/0.06 µm, NMOS and PMOS transistors operated at 600mVcommon mode voltage. The symmetrical nature of the on resistancewill, for small Vds, give rise odd order distortion as an applied sinus-oidal voltage be compressed or expanded symmetrically around 0 V.Another notable aspect is that the PMOS and NMOS conductancederivatives are almost mirror images of each other even though theon-conductances magnitudes are not matched. The conductance de-rivatives of a transmission gate is also shown in Fig. 5.2 drawn as asolid line.

It is seen that the transmission gate has a considerably more linear,or equivalently constant, conductance over the range of inputs smallerthan about ±25mV. This agrees with the results in [13] but herethe same results are obtained by considering the on-conductance asopposed to switch transconductance. Furthermore, this test uses themore accurate PSP model for MOS transistors instead of the inferiorBSIM1 model [33, 13].

34

It should however be noted that while the plots of Fig. 5.2 look ap-pealing, it comes at the cost of doubled area and capacitive load onthe LO compared to an implementation using just 7×N- or PMOSswitch devices. Furthermore the results are valid only when the LOhas reached its peak values. Appendix D.2 show the resultant timedomain waveforms when applying a sinusoidal waveform across thetransmission gate. The results presented in Appendix D.2 show thatfor a transmission gate the peak current deviation from a constant res-istance, tted at 0V input, is reduced by 100 times compared to theindividual transistors. This eect reduces harmonic distortion consid-erably but is expected to occur only when LO transition times arenegligible in comparison to the LO period.

5.1.2 Mixer linearity versus LO duty cycle

The gain of the passive mixer is as derived in [10] dependent on theLO duty cycle. Therefore, as the linearity characteristics are typicallymeasured in terms of input or output referred intercept points, thelinearity gures are directly aected by the LO duty cycle [10]. Chan-ging the LO duty cycle will also inuence the distribution betweenthe on and o periods which changes the average, over one LO period,transistor characteristics. This should aect the magnitude and dis-tribution, even/odd, of the harmonics generated.

To study this eect as well as to get a benchmark to compare thecomplete mixer solutions of Section 5.4.1 with the circuit of Fig. 5.3is used. The transimpedance ampliers are implemented using idealinverting voltage ampliers with an open loop gain of 10, 20 dB. 20 dBis chosen as this is close to the NMOS µ in the technology used.Transistor µ is used as a gauge of achievable gain in a single stage noncascoded amplier, which is the design targeted in this thesis. Thefeedback network Rfb ‖ Cfb used is 2 kΩ ‖ 40 fF which gives a low-pass BB transimpedance of roughly 66 dB for low frequencies with acut o frequency of 2GHz. Note that the actual transimpedance willdier from this value due to the limited amplier gain. Additionalinformation regarding the simulation setup and assumptions is foundin Appendix A.

Mixer linearity dependence on LO duty cycle is illustrated in Fig. 5.4.There it can be seen that for this mixer conguration the use of sub50% duty cycle does aect linearity and gain. Unfortunately, the

35

M3

M4

M1

M2

IN+

N_ LO+ N_LO-

IF+

IF-

-AV

-AV

IN-

Cfb

Rfb

Cfb

Rfb

Figure 5.3: NMOS based current-mode mixer used as simulationbenchmark, input capacitors are for AC coupling.

mixer third order nonlinearity is not strongly aected by decreasingthe duty cycle apart from an area around 32% where linearity is su-perior to that achieved at 50%. Second order nonlinearity is howeverdegraded by reducing. In Fig. 5.4 it is also seen that the output powerdecreases with decreasing LO duty cycle. The cause of the droppingoutput power is that the input impedance of the mixer increases withdecreasing duty cycle. This will reduce the eective input current asthe signal source has a nite output impedance. This counteracts theincreasing conversion gain for smaller duty cycle described in [10].

It should be noted that in the case of a quadrature receiver the switchoverlap when using a duty cycle of more than 25% will create cur-rent division induced I-Q gain mismatch. Furthermore the presenceof switch overlap will increase the mixer noise gure as the DC-osetbetween BB amplier inputs will cause a DC current to ow betweenamplier inputs which in turn increases the level of icker noise. Fur-thermore, in non quadrature receivers the absence of switch overlapwhich may appear in mixers utilising a 50% duty cycle avoids currentdivision between positive and negative paths which would otherwiseinduce second order nonlinearity.

36

0

5

10

15

20

25

30

35

40

45

10 20 30 40 50

Po

we

r [d

Bm

]

LO duty cycle [%]

OIP3 differential

OIP2 single ended

Output power

Figure 5.4: Nonlinearity and output power of a simplied NMOSmixeras a function of LO duty cycle. fLO = 4GHz and f1,2 = 4.6GHz,4.60314GHz.

5.1.3 Complementary switch networks in voltage-

mode mixers

Using the circuit of Fig. 2.3, the performance of passive voltage-modemixers is studied. Comparisons are performed for mixers which haveswitches sized 7×1/0.06µm. The reason for selecting 7×1/0.06 µm is thatthis size was determined to be large enough to drive input capacitancesof the ampliers designed in this thesis whilst being small enough tonot have excessive internal capacitance.

For the transmission gate, mixer the same switch area is distributedequally between the NMOS and PMOS parts of the transmissiongate. This arrangement is chosen to avoid eects that arise due toincreased on-conductance when connecting additional transistors inparallel. Which would be the case if the transmission gate was intotal 14 µm wide compared to the 7 µm of the NMOS or PMOS im-plementations as would have been the case if simply connecting thetested N- and PMOS mixers in parallel. Fig. 5.5 shows that no im-provement in 3rd order nonlinearity is gained by using transmissiongates as switch devices when the mixer is loaded only by the switchtransistors' intrinsic capacitances. If instead the mixer is loaded by50 fF capacitors, the dierences between the transmission gate solutionand the NMOS or PMOS versions is more pronounced. The choice of50 fF load capacitance is arbitrary however the input capacitance ofthe BB ampliers designed in this thesis is in that range.

The results from the test using capacitive output load is shown inFig. 5.6 where two minor peaks in linearity with respect to third order

37

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0,0 0,2 0,4 0,6 0,8 1,0 1,2

Co

nv

ers

ion

ga

in [

dB

]

Vcm[V]

GC

NMOSPMOSTgate -50

-40

-30

-20

-10

0

10

20

30

0,0 0,2 0,4 0,6 0,8 1,0 1,2

OIP

3 [

dB

m]

Vcm [V]

OIP3

NMOSPMOSTgate

-40

-30

-20

-10

0

10

20

30

40

50

0,0 0,2 0,4 0,6 0,8 1,0 1,2OIP

2 [d

Bm

]

Vcm [V]

OIP2

NMOSPMOSTgate

Figure 5.5: Performance comparison of dierent switch arrange-ments in a voltage-mode passive mixer for fLO = 4GHz and f1,2 =4.6GHz, 4.60314GHz.

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0 0,2 0,4 0,6 0,8 1 1,2

Co

nv

ers

ion

ga

in [

dB

]

Vcm [V]

GC

NMOS

PMOS

Tgate -50

-40

-30

-20

-10

0

10

20

30

0 0,2 0,4 0,6 0,8 1 1,2

OIP

3 [

dB

m]

Vcm [V]

OIP3

NMOS

PMOS

Tgate

-40

-30

-20

-10

0

10

20

30

40

0 0,2 0,4 0,6 0,8 1 1,2

OIP

2 [

dB

m]

Vcm [V]

OIP2

NMOS

PMOS

Tgate

Figure 5.6: Performance comparison of dierent switch arrange-ments in a voltage-mode passive mixer for fLO = 4GHz and f1,2 =4.6GHz, 4.60314GHz with a capacitive load of 50 fF on each output

38

distortion are visible around 300mV and 700mV respectively. One ofthese peaks overlap the peak in linearity with respect to second orderdistortion at 700mV. This shows that considering the loading of themixer core is crucial when studying the linearity impact of dierentswitch arrangements. Preferably, the circuit should be loaded by anas close equivalent to the actual BB amplier as possible.

The noticeable improvement in gain for high common mode voltagesfor NMOS mixers and at low voltages for PMOS mixers, is probablycoming from the decrease in switch on time that occurs when thecommon mode voltage increases. In [7] it is claimed that for unitytime sampling, the conversion gain would be 0 dB which might be theeect seen in Fig. 5.5.

5.1.4 Complementary switch networks in current-

mode mixers

To study the eect of using complementary switch networks in current-mode passive mixers a circuit like that of Fig. 5.3 is used. The switchesare similarly to the previous section implemented as either NMOS,PMOS or transmission gates. The conguration studied has a 2 kΩ ‖40 fF feedback at the TIA giving a low-pass response with a pole at2GHz. The amplier used has a gain of 20 dB mimicking a highbandwidth single stage amplier. By running the same common modevoltage sweep as in the previous section the curves in Fig. 5.7 areobtained.

The very high values for output intercept points should not be inter-preted as the mixer being very linear in comparison to the voltage-mode mixer. This is as the current-mode mixer has a high conversiontransimpedance stemming from the TIA stage which will raise theoutput referred intercept point, particularly in this case as the TIAis completely linear. To compare the voltage and current-mode mix-ers in a fair way the input referred intercept points need to be used.However this requires the translation of measurements to a commonunit such as power. One way of accomplishing this is discussed inAppendix C but this denition is not used for any comparisons in thisthesis as it is doubtful whether or not the comparison would be fairor not.

39

0

5

10

15

20

25

30

35

40

45

50

0,00 0,40 0,80 1,20

OIP

3 [

dB

m]

Vcm [V]

OIP3

NMOS

PMOS

Tgate

-40

-20

0

20

40

60

80

0,0 0,4 0,8 1,2

OIP

2 [

dB

m]

Vcm [V]

OIP2

NMOSPMOSTgate

50

55

60

65

70

75

0,0 0,4 0,8 1,2

Co

nv

ers

ion

tra

ns

imp

ed

an

ce [

dB

]

Vcm [V]

RC

NMOSPMOSTgate

Figure 5.7: Performance comparison of dierent switch arrangementversus common mode voltage for a current-mode mixer. fLO = 4GHzand f1,2 = 4.6GHz, 4.60314GHz.

5.1.5 Eects of baseband gain in current-mode mix-

ers

As the amount of BB gain directly sets the load impedance seen bythe passive mixer, through the miller eect making Zload = Zfb

AV, it is

important to nd the amount of gain where mixer linearity no longerimproves from increased BB gain. Based on previous discussions thecurrent-mode mixer should reach optimum linearity when there is novoltage swing at source nor drain terminals. This happens when theload impedance is zero, consequently for large amounts of BB gain.

To study this eect the mixer of Fig. 5.3 is used where the feedbackcomponents are 2 kΩ and 40 fF as for all the current-mode simulationsdescribed in this chapter. A common mode level of 200mV was usedand identical frequencies for the LO and input RF tones as per previ-ous tests. Fig. 5.8 illustrates the results of this test and it is evidentthat for baseband gains larger than about 10 to 20 the improvementof third order nonlinearity is very small. Second order nonlinearitycontinues to improve up to a gain of approximately 100 whereafter italso levels o.

In essence, these results indicate that for the passive mixers construc-

40

20

30

40

50

60

70

80

90

1 10 100 1 000

OIP

3/2

[d

Bm

], R

c [d

B]

BB gain

RcOIP2OIP3

Figure 5.8: Linearity as function of BB amplier gain for theNMOS passive mixer of Fig. 5.3. fLO = 4GHz and f1,2 =4.6GHz, 4.60314GHz.

ted in this thesis a gain of 10 to 20, as achievable in a single stageamplier [18], is sucient for the current-mode passive mixer to oper-ate at close to optimum linearity with respect to third order distortion.This also implies that reduction of BB amplier nonlinearity will havenoticeable impact on mixer performance if the amount of open loopgain is in this range.

5.1.6 Resistive degeneration of mixer switches

As described in [17], the addition of degeneration resistors or seriesresistors, to the switches in a passive mixer can reduce the amountof second order nonlinearity. This eect is primarily due to improvedmatching between positive and negative paths as well as between theI and Q channels. This eect will not be studied within the context ofthis thesis as only nominal process parameters are considered whichmeans that no mismatch induced second order distortion is generated.

Besides the eects on second order nonlinearity demonstrated in [17]there is also the potential of improving third order nonlinearity dueto swamping out conductance nonlinearity. These eects are shownin Fig. 5.9 where it is seen that for a passive mixer with a BB gain of10 the improvement of third order nonlinearity is negligible. However,if the BB gain is 100 then a roughly 2 dB improvement of OIP3 isachieved when using a degeneration resistance of 190 Ω. This showsthat the previously discussed concept of the series resistors swampingout transistor nonlinearities is valid.

41

29

30

31

32

33

34

35

36

37

38

0 50 100 150 200 250 300 350 400

OIP

3 [

dB

m]

Series resistance [Ω]

OIP3, BB gain 100

OIP3, BB gain 10

Figure 5.9: OIP3 for a current-mode mixer with dierent series de-generation resistors. fLO = 4GHz and f1,2 = 4.6GHz, 4.60314GHz.

5.1.7 Charge injection cancellation

To study the eects of charge injection cancellation in passive mixersthe simple mixer implementations of Figures 2.3 and 5.3 are used.The eects of charge injection in passive mixers is studied only for thecase of an NMOS based mixer core. It is reasonable to expect thatfor a PMOS based mixer the eects will be the same. The tests areperformed at a common mode voltage of 250mV. 25% LO duty cycleis is used when studying charge injection eects. In fact, operatingthe mixer at 50% duty cycle accomplishes charge injection cancellationwithout extra transistors as charge is simply pumped between the twoswitch transistors sharing a common node.

To generate appropriate waveform for the charge injection cancellationswitches a simple NOR-gate implementation, as in Fig. 5.10, can beused. However, the NOR-gate will need to be carefully designed forthe switching of the dummy devices to be synchronous with the mainswitch devices.

The eects of charge injection cancellation for a NMOS based voltage-mode mixer is given in Table 5.1. For current-mode mixers, no resultsare presented here as the eects of charge injection cancellation forwas negligible. One notable feature is that charge injection cancel-lation gives a considerable improvement in second order nonlinearity.This is to be expected as the charge injection will modulate the ef-fective threshold voltage of the mixer switches. This makes the switchthreshold dependent on the input signal level, and also dierent forpositive and negative paths.

42

N_ LO+ N_LO-

IN+

IN-

OUT+

OUT-

Figure 5.10: Implementation sketch for NMOS charge injection can-celling mixer

Table 5.1: Eects of charge injection cancellation on voltage-modepassive mixers, fLO = 4GHz and f1,2 = 4.6GHz, 4.60314GHz. Mixeroperated at 250mV Vcm.

Mixer GC [dB] OIP2 [dBm] OIP3 [dBm]With charge injectioncancellation

−2.2 35.8 19.3

Without chargeinjection cancellation

−4.0 6.1 17.3

43

5.2 Linearised baseband ampliers

This section details the design and performance of linearised basebandampliers. In the designed ampliers all transistors are operated withtheir substrate tied to ground or supply for NMOS and PMOS devices,respectively. For the amplier designed in this section the bandwidthpresented is the non compensated −3 dB bandwidth. This bandwidthshould be expected to drop slightly after frequency compensation butas single stage ampliers are inherently more stable than multi stageampliers, the reduction is expected to be small.

5.2.1 Derivative superposition using common mode

voltage shift

As an initial proof of concept approach to linearisation of BB amp-liers, a simplied approach is used. This approach uses ideal voltagesources for generating the DC-shift required to set the transistor op-erating points where the main transistor g′′m is nulled by the additionof the auxiliary transistor. However, as argued in Chapter 4 thisapproach is not feasible in an actual implementation. For implement-ation friendly approaches to derivative superposition ampliers referto Sections 5.2.2 through 5.2.4.

Fig. 4.1 a) illustrates the simulated derivative superposition amplier.The amplier is designed using the procedure outlined in 4.1.1, ex-ploiting the symmetry of g′′m around 180− 200mV as seen in Fig. 2.4.Initially the drain source voltage is set by a voltage source which fur-ther simplies the design. In this conguration transistor sizes of17 × 2/0.14 µm and 8 × 2/0.14 µm, for the primary and auxiliary tran-sistor respectively gives an area around 200 mV where g′′m is close tozero.

In a more realistic amplier conguration the drain source voltage isgenerated by a cascode transistor with current supplied from a res-istive load, as is illustrated in Fig. 4.1. In this conguration, the gmderivatives of Fig. 5.11 are obtained. Note that the move from a zeroohm load, as the voltage source used previously presents, to a nonzero ohm load requires some changes in the circuit. This change ismainly to increase the size of the auxiliary transistor to 55× 2/0.14 µmin order to achieve zero g′′m. The dierence is remarkable but none

44

0,0

5,0

10,0

15,0

20,0

25,0

-10 -5 0 5 10

gm

[m

A/V

]

ΔVin [mV]

gm

NMOS primary

NMOS auxiliary

Cascode

-0,20

-0,15

-0,10

-0,05

0,00

0,05

0,10

0,15

0,20

-10 -5 0 5 10ΔI [m

A] ΔVin [mV]

ΔI

NMOS primary

NMOS auxiliary

Cascode

-15

-10

-5

0

5

10

15

-10 -5 0 5 10

gm

' [m

A/V

2]

ΔVin [mV]

gm'

NMOS primaryNMOS auxiliaryCascode -2000

-1500

-1000

-500

0

500

1000

1500

-10 -5 0 5 10

gm

'' [

mA

/V3]

ΔVin [mV]

gm''

NMOS primaryNMOS auxilaryCascode

Figure 5.11: Output current and dierential transconductance withderivatives for the NMOS derivative superposition amplier using idealDC shift.

the less fulls the requirement of zero g′′m and consequently third or-der distortion cancellation. As this circuit is intended primarily as ademonstration of the linearity improvement achievable by the derivat-ive superposition, no amount of eort has been put in optimisation ofgain with respect to linearity as well as linearity of the output stage.With regards to the output stage, the source follower causes a severedegradation in amplier linearity which is discussed in greater detailin Section 5.2.5.

With the linearity problems stemming from the source follower outputstage, Table 5.2 presents a comparison between the derivative super-position amplier for both at the internal amplication node as wellas the source follower output node. The comparison shows the down-side of using a source follower output stage. The source follower maycause output nonlinearity to be independent of linearity in the internalnodes.

45

Table 5.2: Performance of the derivative superposition amplier withand without linearising cross coupled dierential pair. Linearity andgain measured at 10MHz with −60 dBV input signal.

Amplier AV [dB] OIP3 [dBV] f-3 dB [GHz]

With auxiliarytransistor, atinternal node

20.5 18.0 0.7

With auxiliarytransistor, at outputnode

18.6 5.4 0.7

Without auxiliarytransistor, atinternal node

19.4 14.0 0.7

Without auxiliarytransistor, at outputnode

17.7 8.3 0.7

5.2.2 Derivative superposition using cross coupled

dierential pair

Recognising that the DC-shift utilised in the previous section is dif-cult to accomplish for single ended ampliers operating at frequen-cies down to DC an approach utilising a dierential pair to achievelinearisation is proposed here. Intuitively the eects of biasing thetransistors using a current source should be identical to that of a shiftin eective VGS as used in the previous section to set operating pointsfor the transistors. However, this is not accurate as is explained in thefollowing section.

5.2.2.1 Implications of dierential pair DC characteristics

Unfortunately, while the dierential pair should, for small signals, be-have equivalently to a pseudo dierential amplier with the same qui-escent current, the large signal behaviour is very dierent. Further-more, the large signal behaviour is unfortunately the foundation of thederivative superposition method. In the pseudo dierential case, thetransconductances of the auxiliary transistors do not interact allowingthe dierential current to show an input voltage dependence similar

46

a) -40

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'' [

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gm''

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Mx

Mc

Figure 5.12: a) Dierential output current from a pseudo dierentialpair in weak inversion, detail from Fig. 5.11. b) Detail from Fig. 4.3.

to that of Fig. 5.12 a) if placed in the correct bias point for third or-der intermodulation cancellation to occur. The dierential transcon-ductance increases for high dierential input voltage, or equivalently,large input signals suer from expansion rather than compression. InFig. 5.12 a) the eect is subtle but noticeable.

In contrast the true dierential pair looses transconductance for largedierential input voltages. This comes from that the maximum currentcarried by a single transistor is double its quiescent current. This doesessentially mean that the dierential current follows a similar curveto that of Fig. 5.12 a) but saturates at 2 × Iq which means that thetransconductance drops to zero for large dierential input voltages anddoes not increase like for the pseudo dierential pair.

Looking back at the dierential transconductance curve of Fig. 4.3,here reprised in Fig. 5.12 b), it is obvious that the auxiliary tran-sistor, Mx, transconductance characteristic must be a concave in or-der to compensate the convex curvature of the main transistor, Ma,transconductance. This cannot be accomplished by a dierential pairunless the signal currents are cross coupled as per the explanation inthe previous paragraph.

5.2.2.2 Simulation data

With the results from previous section in mind a derivative superpos-ition amplier using a cross coupled dierential pair as the linearisingelement is designed. The main and auxiliary transistors are sized33× 2/0.14 µm and 17× 2/0.14 µm respectively, based on the DC-analysis

47

using the dierential transconductance derivatives as described in Sec-tion 4.1.1. The bias current for the main transistors is 2.2mA and theauxiliary transistors are biased at 84 µA. The bias current of the aux-iliary transistor is very small, about 1/26:th, compared to that of themain transistor. This allows for a comparison where the auxiliarytransistors are simply removed to determine the eciency of this lin-earisation scheme. The results of such a test is given in Table 5.3where IP3 improves by 4 dB which shows the linearising eect.

Table 5.3: Performance of the derivative superposition amplier withand without linearising cross coupled dierential pair. Linearity andgain measured at 10MHz with −60 dBVpeak input signal.

Amplier AV [dB] OIP3 [dBV] f-3 dB [GHz]

With cross coupledlineariser

16.0 13.1 1.3

Without crosscoupled lineariser

16.8 9.0 1.3

By tuning the size ratio between the main and auxiliary transistors andusing harmonic balance analysis, the third order intercept point can beimproved further. However, optimal size for the auxiliary transistor asdetermined by harmonic balance analysis is signal level dependent. Foreach input signal level there is a sweet spot where perfect cancellationof intermodulation currents occur. The input level dependence of thissweet spot solution is presumably due to moving the input dierentialvoltages where g′′m crosses zero as opposed to the DC-analysis basedsolution where g′′m only reaches zero close to Vindi = 0.

By decreasing the input level signicantly, the optimal size of the aux-iliary transistor does indeed approach the 17× 2/0.14 µm , as suggestedby DC analysis. However, at such small input levels, the upper andlower IM3 harmonics diverge in amplitude due to simulator character-istics indicating that the results are invalid. The full schematic withsizes and bias currents for all transistors is given in Appendix B. Forthe simulations performed later in this section the size derived fromDC-analysis is used. This is done to verify the accuracy of the DCsolution.

48

5.2.3 Derivative superposition using PMOS auxil-

iary transistor

As illustrated in Fig. 4.1 b), it is possible to implement a derivative su-perposition amplier using a PMOS transistor as the auxiliary deviceinstead of an NMOS, such as suggested in [3] and [1]. By sizing theauxiliary device and setting the input common mode voltage appro-priately, the PMOS can operate in the weak inversion region. In thisregion of operation both g′m and g′′m are of opposite sign compared tothe NMOS primary amplication transistor [3]. However, achievingthis bias point requires a precise relationship between the thresholdvoltages of the two devices. Furthermore, for the PMOS transistor tooperate in weak inversion while the NMOS transistor is not driven intothe triode region of operation, both devices need to be high thresholdvoltage varieties and the input common mode level must be close tohalf supply. Within the context of this thesis this implies unfavour-able operating conditions for the passive mixer if implemented usingNMOS transistors.

Regardless of the diculties outlined above an amplier using thislinearisation technique is studied here. By using standard thresholdvoltage devices, the highest threshold devices available in the 65 nmRF CMOS design kit for which PSP models are available, and oper-ating at an input common mode level of 725mV, an amplier utiliz-ing this linearisation technique is constructed. The NMOS primaryamplication transistor is sized 16 × 2/0.14 µm and the PMOS auxili-ary transistor 85 × 2/0.14 µm. The bias currents are 1.62mA for theNMOS and 373 µA for the PMOS device. The corresponding dieren-tial transconductance and derivatives are given in Fig. 5.13.

The results presented in Fig. 5.13 indicates that the amplier cong-uration should be more linear than just the NMOS transistor. Moreso, the amplier should have increased transconductance compared tothat of the NMOS transistor. This is in contrast to the derivativesuperposition amplier using a cross coupled dierential pair wheretransconductance is decreased by the linearisation. In this amplieran appreciable amount of the bias current for the NMOS transistor issupplied by the PMOS auxiliary transistor. Therefore, simply remov-ing this transistor for the purpose of comparing the linearised and nonlinearised case would upset the bias point for the amplier. This wouldnot allow for a fair comparison between the linearised and non linear-ised case. By connecting the PMOS transistor to the input common

49

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Figure 5.13: Dierential output current and transconductance withderivatives for the derivative superposition amplier using a PMOSauxiliary transistor.

mode voltage instead of removing it, the bias point can be conserved.This method is used to determine amplier characteristics for com-parisons with the non linearised case. However, doing so decreasesthe input capacitive load to just 16% of the linearised amplier whichwill also aect amplier properties, and of course the performance ofthe passive mixer core. The performance metrics of the derivativesuperposition amplier using a PMOS auxiliary transistor is given inTable 5.4. The full schematic of the linearised amplier is given inFig. 5.14.

Another method for estimating the eect of the auxiliary transistoron linearity is to measure the output current harmonics of the threedevices in the circuit, the main amplier, auxiliary transistor andcascode transistor. Using this approach it is seen that the third orderintermodulation current is reduced by 20 dB compared to what is gen-erated by the main amplication transistor. This would correspondto a 10 dB improvement in third order intercept point provided thatthe load and cascode are linear.

50

MC1

Rload

VbiasC

MA1

MX1

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MX2

Rload

MSF1,2

VbiasC

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biasSN VbiasSN

IN+ IN-

OUT - +

Figure 5.14: Schematic for the derivative superposition amplier usinga PMOS auxiliary transistor

Table 5.4: Performance metrics of the derivative superposition ampli-er using a PMOS auxiliary transistor.

Amplier AV [dB] OIP3 [dBV] f-3 dB [GHz]

Linearised 14.3 19.4 1.1Non linearised 10.0 11.6 1.1

It is apparent that the use of the additional transistor serves both toincrease the amount of gain as well as amplication. Though noneof the ampliers have large amounts of amplication. To increase theamount of amplication, the load resistor could be replaced with a res-istor/current source combination as in Fig. 4.2. However, in this case,doing so caused load impedance nonlinearity to dominate amplierlinearity which makes linearisation of the transconductor pointless.

5.2.4 Post distortion using folded PMOS common

gate amplier

In [32] a linearisation technique for CMOS LNAs is proposed whichuses a PMOS common gate amplier to post distort the current fromthe main amplication transistor. By selecting the proper gate voltageand size ratio between the tree transistors, MA, MX andMC , in thecascode conguration of Fig. 4.4 the linearity of the resulting voltageto current converter can be improved. However, when the PMOS

51

device is placed in the correct operating point for IM3 cancellation,a signicant amount of signal current is sunk by the auxiliary device,eectively limiting the gain of the amplier, as can be seen in Table 5.5.

Sizing the amplier so that the main amplication transistor is 33 ×2/0.14 µm and the PMOS IM3 sinker 41×2/0.14 µm and with bias currents1mA and 128 µA, respectively, the amplier performs according toTable 5.5. In Table 5.5 the performance of the post distortion amplieris compared to the same amplier with the PMOS post distortiondevice replaced by an ideal current source to maintain the correctbias point for the amplier. Note that linearity does not improvesignicantly. However, the IM3 current produced by the linearisedtransconductance stage is considerably lower than than in the nonlinearised amplier. This indicates that the cascode device and/orload impedance dominates nonlinearity in this amplier.

Table 5.5: Performance metrics of the linearised amplier using foldedPMOS IM3 post distorter, or IM3 sinker as described in [32].

Amplier AV [dB] OIP3 [dBV] f-3 dB [GHz]

With post distortion 15.7 −1.0 0.7Without post distortion 18.0 −1.8 0.7

5.2.5 Output stage nonlinearity and matching char-

acteristics

All of the ampliers discussed in the previous sections use a simplesource follower type output stage. The source follower has a num-ber of problems. The achievable gain is much less than unity, for lowimpedance loads below −6 dB, and the circuit is very nonlinear incertain operating points. Testing the source follower using a NMOSimplementation biased by a NMOS current source show that the thirdorder intercept point for the follower can vary as much as 10 dB. Theamount of distortion depends on the chosen operating point. In par-ticular if VDS is small in comparison to VOV = VGS − VTH , so thatthe source follower is barely in saturation, the amount of distortion ismaximised.

Considering the amplier of Section 5.2.1 and the concept of dominantsource of nonlinearity, as discussed in Section 2.4, the IIP3 of thesource follower, measured outside the circuit, is −5 dBV when seen

52

from the input of the amplier. The linearised amplier on the otherhand has an IIP3 of 11 dBV showing that the source follower is in factthe dominant source of nonlinearity in that circuit. This means thatpossible amplier linearity is decreased by adding the source followerstage. Hence, the amplier is presumably less linear in a feedbackarrangement using a source follower output stage than if it is used asan open loop amplier without the source follower stage, contrary towhat might be expected.

Another note is that obtaining the proper bias point for the amplierspresented in this chapter is critical in order to achieve the best possiblelinearity. Regarding this, the source follower poses another problem.This is understood by considering how the amplier bias point is gen-erated in the closed loop and open loop congurations. In the openloop case, the amplier bias point is generated via a current mirrorwhich for DC is connected to the gate of the amplier transistors. Thisallows for a well dened quiescent current as it can be derived from acurrent reference. In the feedback conguration the quiescent currentis determined by the threshold voltage of the source follower and thevoltage drop across the load resistance. Thus, the operating point ofthe amplier relies on several parameters which ought to increase pro-cess induced bias spread. Furthermore, most of these circuits operatewith a common mode input level close to ground and a common modevoltage at the internal amplication node that is close to supply. Thismeans that the source follower must have a VGS close to the full sup-ply voltage. Hence the source follower is preferably a high Vth devicewhich will induce further mismatch between the follower and the amp-lication transistor as their diering threshold voltages are adjustedin separate steps [34]1.

5.3 LO driver circuit used in simulations

To avoid any eects appearing in the simulations due to using anideal pulse wave voltage source as the LO, a cascade of inverters (fourinverters to be exact) type LO driver is used for the complete mixersimulations. The LO driver uses low threshold voltage devices sized

1Note that the method proposed in [34] is but one way to manufacture multithreshold CMOS. None the less the process described in [34] shows that thresholdadjustment requires extra process steps compared to standard CMOS technology.

53

according to Table. 5.6. The rise and fall times at the output of theLO driver is roughly 25 ps when driving the switch transistors.

Table 5.6: Sizes for the four stage LO driver/buerStage 1 2 3 4

WN [µm] 0.5 0.5 1 2.5WP [µm] 1.5 1.5 3 7.5

The eects of using the non ideal LO driver compared to a voltagesource based ideal LO driver with various rise times are given inTable 5.7. In Table 5.7 it is seen that the switch to a non ideal LOdriver has a small eect on the overall linearity of the mixer circuit.The IP3 for similar rise times is improved by less than 2 dB whenusing an ideal LO-driver. However, the rise time of the LO aectsthe linearity of the mixer, and optimal linearity is achieved for rise-times around 25 ps. The tests are performed using the same mixerconguration in Section 5.1.2.

Table 5.7: Performance of current-mode passive mixer with ideal andnon ideal LO-drive circuitry

Conguration RC [dB] LO trise [ps] OIP3 [dBm]

Ideal LO drive 65 1 28.0Ideal LO drive 64.5 25 29.4Ideal LO drive 64 50 26.8

Non ideal LO drive 64 ≈ 25 27.7

5.4 Complete mixer circuit

This section summarises the performance of passive mixers using thelinearised BB ampliers from the previous sections. For the mixer us-ing the derivative superposition amplier with PMOS auxiliary tran-sistor, which operates close to half supply, results are presented bothusing an NMOS based mixer core and using a mixer core with trans-mission gates. This is to give an estimate of achievable circuit per-formance when using the most favourable mixer conguration. Inthese simulations 25% LO duty cycle is used which is responsible forthe slightly higher RC/GC than what is presented for similar mixercongurations in Fig. 5.8.

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5.4.1 Current-mode mixers using linearised BB amp-

liers

As the linearised ampliers designed in Section 5.2 have varying levelsof gain their input impedance when connected as transimpedance amp-liers will not be equal. This eectively means that the linearity ofthe passive mixer core is dierent for all of the ampliers. This will in-uence the comparison between the dierent linearisation techniques.The CMOS derivative superposition amplier using a PMOS auxili-ary transistor, in particular, operates so close to half supply that usingcomplementary mixer switches is desirable making comparisons evenmore dicult.

Therefore in an eort to see how close to the achievable performancethe mixer circuits are, a test arrangement using ideal ampliers isused. The test performed for each mixer implementation consists ofthe mixer with rst: the linearised amplier, second: the non lin-earised amplier and nally an ideal amplier with the same gain asthe linearised amplier, and 50 fF of input capacitance as used in thesimulations of the passive mixer core. This testing scheme shouldshow the eects of the proposed linearisation technique and allow forfair comparisons between the mixer circuits, provided that the inputcapacitance of the amplier stage is close to 50 fF.

All tests in this section are done using the basic circuit of Fig. 5.3but for the CMOS derivative superposition amplier using a PMOSauxiliary transistor, the test are performed both with a transmissiongate based mixer and with a NMOS mixer. The values for the feedbackcomponents in the tested circuits are the same as in Section 5.1.4. TheLO-driver used is the one described in Section 5.3.

Results from the tests are presented in Table 5.8 and 5.9 where theconversion transimpedance RC is dened as the ratio between theoutput voltage and input current. In Table 5.8, a NMOS passivemixer core is used whereas in Table 5.9 a transmission gate version isused. In Tables 5.8 through 5.10 the mixer circuits are labelled as:

1. Using the derivative superposition amplier with cross coupleddierential pair operating at 248mV input common mode

2. Using the NMOS derivative superposition amplier with DC-shift operating at 200mV input common mode

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Table 5.8: Performance of dierent current-mode passive mixer con-gurations, tests performed with LO at 4GHz and two RF tones at4.6GHz and 4.60314GHz respectively.Amplier RC

[dB]OIP2

[dBm]OIP3

[dBm]Amplier powerdissipation [mW]

1 Linearised 61.8 32.6 21.2 7.41 Non Linearised 62.0 33.8 18.8 7.41 Equivalent gain 62.0 34.1 25.8 N/A2 Linearised 62.5 31.2 15.6 4.12 Non Linearised 61.8 33.1 15.8 4.02 Equivalent gain 61.8 37.5 25.4 N/A3 Linearised 51.7 −19.0 −10.1 4.63 Non Linearised 44.0 −23.0 −13.0 4.63 Equivalent gain 63.0 −2.0 1.3 N/A4 Linearised 59.0 18.0 9.7 5.14 Non Linearised 58.6 20.6 9.5 5.14 Equivalent gain 59.0 50.0 28.5 N/A

3. Using the CMOS derivative superposition amplier with PMOSauxiliary transistor operating at 724mV input common mode

4. Using the post distortion amplier using with PMOS foldedcommon gate post distorter operating at 206mV input commonmode

The data presented in Table 5.8 shows that the linearity of the baseband amplier has a noticeable impact on the linearity of the completemixer circuit. In particular, the cross coupled derivative superpositionshows this eect even though the non linearised amplier has highergain. The cross coupled pair gives a 2.4 dB improvement of thirdorder intercept point. This eect is also seen for the CMOS derivat-ive superposition amplier although the unfavourable operating pointcauses the total circuit nonlinearity to be greater than in the othercircuits.

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Table 5.9: Performance of the CMOS derivative superposition ampli-er with PMOS auxiliary transistor with a transmission gate mixer.LO at 4GHz and two RF tones at 4.6GHz and 4.60314GHz respect-ively.Amplier RC

[dB]OIP2

[dBm]OIP3

[dBm]Amplier powerdissipation [mW]

3 Linearised 58.3 11.0 3.7 4.63 Non Linearised 51.0 7.0 2.4 4.63 Equivalent gain 59.0 12.0 6.8 N/A

5.4.2 Voltage-mode mixers using linearised BB amp-

liers

Even though current-mode architectures are popular for short chan-nel CMOS implementations [12], and the available supply voltage islimited, voltage-mode architectures should not be considered obsolete.Furthermore, voltage-mode architectures allow for the BB amplier tobe operated in an open loop conguration. Hence the BB-amplierstage can be designed for optimum linearity rather than achieving therequired input common mode voltage. Furthermore there is no needto drive a resistive feedback network. This makes it possible to omitthe source follower output stage which allows for even greater BB-amplier linearity. Considering, that it is likely that the base bandamplier dominates system nonlinearity, the relative increase in sys-tem linearity might be greater for voltage-mode circuits.

As shown in Table 5.10 it is indeed the case that the impact of im-proved BB linearity is greater in voltage-mode mixers. Note that incontrast to Table 5.8 the gures for amplier 3 are given when com-bined with a transmission gate mixer. The results in Table 5.10 arefor ampliers using a source follower output stage. This is done toensure that all ampliers are in the same conguration as what wasused to generate their open loop performance metrics as presented inprevious sections. When measuring before the source follower outputstage of amplier 1, as per the previous section, the output third orderintercept point is 2 dB higher than at the output node. Therefore, ifthe next stage presents a load that can be driven by a high imped-ance source then the linearity can be further improved by omittingthe source follower output stage.

57

Table 5.10: Performance of dierent voltage-mode passive mixer con-gurations, tests performed with LO at 4GHz and two RF tones at4.6GHz and 4.60314GHz respectively.Amplier GC

[dB]OIP2

[dBm]OIP3

[dBm]Amplier powerdissipation [mW]

1 Linearised 14.6 22.6 23.8 7.41 Non Linearised 13.9 18.7 18.3 7.41 Equivalent gain 15.1 43.0 30.5 N/A2 Linearised 14.3 9.7 18.1 4.12 Non Linearised 13.4 10.0 18.3 4.02 Equivalent gain 15.0 52.6 28.6 N/A3 Linearised 0.0 11.6 2.9 4.63 Non Linearised 5.2 24.4 20.4 4.63 Equivalent gain 10.9 30.9 22.7 N/A4 Linearised 10.7 −9.1 0.3 5.1of4 Non Linearised 12.5 −9.0 0.5 5.14 Equivalent gain 16.6 47.0 42.0 N/A

Looking at the linearity gures for the ideal ampliers, it is evidentthat BB amplier characteristics, both amplication and input imped-ance, has a big impact on amplier performance. The absolute valuesof OIP3,2 are also similar to the current-mode case when the amplieris perfectly linear. This combined with the larger relative improve-ment of system linearity when using linearised BB ampliers showsthat voltage-mode circuits are a viable alternative to current-modearchitectures.

A nal note regarding the gures presented for amplier 3 in Table5.10, is that the conversion gain for the linearised amplier is verylow. The reason for the low conversion gain is that the test tone of600MHz, demodulated, is outside the mixer bandwidth when loadedby the large capacitance presented by the PMOS auxiliary device.If testing at a lower frequency, such as 200MHz, then the gain andlinearity gures approach those of the non linearised amplier.

58

Chapter 6

Final results

6.1 Linearity of the passive mixer core

The data presented in the previous chapter show that the passivemixer core is very sensitive to operating conditions. This is made es-pecially clear by looking at Figures 5.5 and 5.6 where the capacitiveload on the mixer causes a radical change in the linearity versus com-mon mode voltage characteristics, in particular for transmission gatebased mixers. Another interesting feature of the voltage-mode mixersin those gures is the gain increase for high common mode voltages.This can, as stated in Section 5.1.3, be connected to the mixer movingcloser to impulse sampling which in theory should allow for a conver-sion loss of 0 dB [10]. This eect is not as pronounced in the case ofcurrent-mode mixers. Presumably, this is due to the input impedanceincreasing as the eective overdrive voltage for the switch transistorsis reduced and eective LO duty cycle decreases.

The use of complementary switch networks as proposed in [13] and [15]has a linearising eect both on the switch on-state conductance asshown in Section 5.1.1 and on the linearity of the passive mixer core asshown in Figures 5.5 through 5.7. However, the linearising propertiesof the transmission gate appears only at common mode voltages closeto half supply for identical size transistors. This is if the LO is DC-coupled to gates of the transistors so that switch VGS is dependent oncommon mode voltage. Note that depending on the implementationchosen for the BB-open loop amplier following the passive mixer, acommon mode voltage close to half supply may be desirable. In thiscase, a mixer using complementary switches will provide an advantage

59

over a non complementary mixer implementation as demonstrated inSection 5.4.1.

Charge injection cancellation, as studied briey in Section 5.1.7, showspromise as an eective way of limiting the amount of even order dis-tortion generated in the voltage-mode passive mixer. As mentionedin Section 5.1.7, this is likely to be due to the charge injection modu-lating the turn on threshold for the mixer switches. The eectivenessof this technique in the presence of capacitive loading from the nextstage is not studied. It is probably the case that capacitive loadingdecreases the eects of charge injection. This is as the channel chargeis small in comparison to the charge stored in the successive stage'sinput capacitance.

6.2 Techniques for improving amplier lin-

earity

As demonstrated in the previous chapter, there are several DC-compatibletechniques for improving the linearity of single stage ampliers. Outof the studied linearised ampliers, the derivative superposition amp-lier using a cross coupled dierential pair presented in Section 5.2.2is particularly interesting. While this amplier suers from gain lossdue to the out of phase signal current from the cross coupled dier-ential pair the amount of gain reduction is small in comparison to thelinearity improvement. Furthermore the use of only NMOS transist-ors in the transconductance part of the amplier is advantageous withregards to matching over process corners.

Unfortunately, whilst it is possible to improve the linearity of thetransconductance stage of the BB-amplier other sources of nonlin-earity such as that of the source follower or load impedance greatlyaect circuit performance. This complicates the design of linearisedampliers and shows that amplier linearisation techniques need toall sources of nonlinearity. This is particularly important in shortchannel CMOS technologies where transconductance nonlinearity nolonger the only dominant cause of circuit nonlinearity [22, 1].

Considering the other ampliers, such as the derivative superposi-tion amplier using a PMOS auxiliary transistor and the amplierwith PMOS post distorter. These show comparable and sometimesgreater relative improvements in linearity compared to the derivative

60

superposition amplier using a cross coupled dierential pair. Unfor-tunately the matching of NMOS and PMOS transistors over processvariations is likely to be poor. Note that the demonstration ideal DCshift NMOS derivative superposition amplier is omitted here as it isincluded in the thesis for demonstration purposes only.

6.3 Complete circuit considerations

Considering the mixers using linearised ampliers, circuit linearitydoes not improve to the same degree as would be expected fromsimulating the ampliers in isolation. This is to be expected as theBB-amplier is not necessarily the dominant source of nonlinearity.Moreover, the two stages, mixer and base band amplier, are likely tointeract due to eects such as the lack of isolation between RF andBB in passive mixers [10, 12]. None the less, the derivative super-position amplier using a cross coupled dierential pair shows thatlinearisation of the BB-amplier will improve mixer linearity.

The derivative superposition amplier using a PMOS auxiliary tran-sistor shows an appreciable degree of linearity improvement. How-ever, the eects are not as strong as for the cross coupled derivativesuperposition amplier. In the case of this amplier, the eects ofusing a transmission gate based mixer are presented in Figures 5.8and 5.9. There it is seen that the third order intercept point improveswith around 14 dB by using a transmission gate mixer instead of theNMOS mixer. This conrms the results of the simulations of the pass-ive mixer core. However, this is only valid for common mode levelsclose to half supply, when using a direct coupled LO. None the less,linearity can be improved considerably by using transmission gates inthe switch network under these conditions.

For voltage-mode mixers, the eects of using linearised BB ampliers issimilar to the current-mode case. Unfortunately,only the mixer usingthe derivative superposition amplier with a cross coupled dierentialpair shows a linearity improvement. The cause of the limited improve-ment in linearity for the voltage-mode passive mixers is possibly thatthe mixer-core dominates circuit nonlinearity. This, as discussed inSection 2.4, will prevent the amplier from improving circuit linearity.However, considering the comparisons with ideal voltage ampliers inTable 5.10 the achievable linearity does not seem to be dominated by

61

the mixer but rather in some way by the BB amplier, be it due tononlinear input capacitance or simply due to amplier nonlinearity.

62

Chapter 7

Conclusions and future work

This thesis studies the linearity performance of passive mixer circuitsfor homodyne receivers. The thesis covers the mixer core as well asBB-ampliers with focus on linearity performance and linearisationtechniques. Several DC-compatible amplier linearisation techniquesare studied and the impact of base band linearity on mixer linearityis demonstrated. Results presented in Chapter 5 show that base bandlinearity has a noticeable impact on mixer linearity.

7.1 Conclusions

The results presented in this thesis show that passive mixer linearity issensitive to operating conditions, such as common mode voltage leveland load impedance as previously discussed by [12]. The passive mixercore's sensitivity to operating conditions is important to consider whendesigning receivers using passive mixers. In particular, as an NMOSbased mixer core provides superior performance to both the PMOSand complementary implementations when operating close to negativesupply, the BB-amplier should be designed with an input commonmode voltage close to negative supply.

The desirability of operating close to negative supply puts constraintson the BB-amplier. Operating close to negative supply requires thatthe BB-amplier has either a NMOS pseudo dierential input pair op-erating with small VGS, presumably low threshold devices, or a PMOSdierential pair operating with a large VGS. Furthermore, if using asingle stage NMOS input amplier with a non folded gain stage, the

63

output common mode level of the amplier is close to positive sup-ply, forcing the output buer stage to shift the signal down close toone supply voltage. This in turn will require the designer to use highthreshold voltage devices or large quiescent currents in the output buf-fer, which either complicate matching, as the forward voltage of theoutput stage needs to be matched to the VGS of the input stage, orincrease power consumption, due to large currents, both of which areundesirable circuit features. This could possibly be solved to somedegree by using common mode feedback, a topic not approached inthis thesis.

With regards to the linearisation of BB-ampliers, the three demon-strated circuits, excluding the demonstration amplier using the idealDC-shift, show dierent degrees of linearity improvement and suitab-ility for use in passive mixer circuits. The NMOS derivative super-position amplier using a cross coupled dierential pair looks like themost promising approach as the linearity improvement is consistentboth for the open loop amplier as well as for the complete mixercircuit. Furthermore, the amplier relies only on matching NMOStransistors. This is an advantage compared to the derivative super-position amplier using a PMOS auxiliary transistor [3, 1] or the postdistortion amplier using a PMOS common gate post distorter [32, 1].Both of these rely on matching between PMOS and NMOS devices.Maintaining matching between PMOS and NMOS devices over processvariations should be considered highly unlikely as the device paramet-ers are dependent on dierent processing steps. This ties on to thepreviously discussed matching issue between transistors of dieringthreshold voltages as the threshold adjustment is done in a separateprocess step, such as modication of channel dopant level [34] or gateoxide thickness, and therefore correlation between the two thresholdvoltages will be weak at best.

Disregarding the issue of matching devices with dierent thresholdvoltages, the use of a cross coupled dierential pair to improve thelinearity of pseudo dierential ampliers is shown to be an eectiveand DC-compatible technique. The technique also shows promise inimproving the linearity of the passive mixer based receiver.

As the power consumption of the linearising dierential pair is verysmall, this technique can be applied to existing amplier designs withoutrequiring extensive redesign of the circuit and without a penalty inpower consumption. However, the linearity degradation due to amp-lier load impedance nonlinearity or output stage nonlinearity may in

64

practice limit the eectiveness of the BB amplier linearisation tech-niques presented in this thesis.

In conclusion, this thesis shows that the passive mixer while it is verylinear is highly dependent on surrounding circuit properties. Thus,studying passive mixer circuits is preferably done at a level whereboth the preceding and succeeding stages as well as the LO driver isincorporated or at the very least modelled accurately. Furthermore,while the linearisation techniques presented are eective at nominalprocess parameters this thesis is greatly lacking in not having studiedthe eectiveness of these techniques when exposed to process vari-ations. This is a glaring weak-point and is something that will requirefurther study if any of the ampliers presented or mixer circuits inthis thesis will be manufactured.

A closing note is that while voltage mode and current mode circuitshave been presented in this thesis, not much eort has been put oncomparisons. This stems from the issue of comparing quantities withdiering units. It is possible to dene input power derived from thecurrent sourced to the passive mixer as well as the voltage appearingat the input nodes of the passive mixer. This is commonly done forvoltage quantities where the voltage is assumed to be applied over a50 Ω load giving a power measurement. Similarly, the current couldbe assumed to pass through a 50 Ω load which yet again gives power.Comparing the two power quantities will none the less risk being non-sensical which is why no such attempts are done.

7.2 Suggestions for future work

Research considering low power homodyne receivers is of great interestas the use of wireless communications is rapidly increasing. Further-more, the importance of limiting energy usage is acknowledged bothfor stationary and mobile devices. With this in mind there are severalareas where further research if warranted and a complete list is out ofthe scope of this thesis, probably a suitable topic for a thesis in it self.However, this section will list a number of areas which are related tothe topics in this thesis.

The use of complementary switch networks in passive mixers is notlimited to using transmission gates as switch devices. Another pos-sible implementation would use two independent mixers operating at

65

dierent common mode levels and combined through current summa-tion could possibly provide similar linearity improvement without therequirement of operation close to half supply. Such an approach wasbriey studied in the work preceding this thesis but not to such anextent as to give any presentable results.

Applying the DC-compatible linearisation techniques presented in thisthesis to existing ampliers and mixer circuits would also be an inter-esting topic of study particularly if focus is put on manufacturabilityand performance in relation to wireless standards.

Further optimisation of the linearised ampliers presented here is alsosubject worth investigating. The fact that all ampliers presented inthis thesis uses only the nominal 1.2V supply means that there isdenitely room for improvement by simply using outside-rail tech-niques [35, 36].

A nal area of interest is to study the linearity characteristics of dier-ent untuned amplier loads and output stages. The studied amplierlinearisation techniques are primarily derived from low noise amplierapplications where high gain is not a primary requirement. Therefore,load linearity is not of great concern as resistive loads can be used. Insome narrow band cases it is even possible to use tuned loads whichallows for a high impedance load even at high quiescent currents. Thisarea is of particular importance as linearised ampliers presented inthis thesis in some cases suered from load nonlinearity.

66

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[2] D. Na and T. W. Kim, A 1.2 v, 0.87 - 3.7 GHz Wideband low-noise mixer using a current mirror for multiband application, Mi-crowave and Wireless Components Letters, IEEE, vol. 22, no. 2,pp. 9193, 2012.

[3] M. Parvizi and A. Nabavi, Low-power highly linear UWB CMOSmixer with simultaneous second- and third-order distortion can-cellation, Microelectronics Journal, vol. 41, no. 1, pp. 1 8, 2010.

[4] D. Raychaudhuri and N. Mandayam, Frontiers of wireless andmobile communications, Proceedings of the IEEE, vol. 100,pp. 824 840, april 2012.

[5] A. Goldsmith, Wireless Communications. Cambridge UniversityPress, aug. 2005.

[6] S. Seely, Electron-tube Circuits. McGraw-Hill, 2nd ed., 1958.

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[8] L. Yao, M. Steyaert, and W. M. Sansen, Low-Power Low-VoltageSigma-Delta Modulators in Nanometer CMOS (The SpringerInternational Series in Engineering and Computer Science).Springer, 2006 ed., dec. 2006.

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[10] B. Razavi, RF Microelectronics. Pearson Educacion, internationaled. of 2nd revised ed., dec. 2011.

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[12] H. Khatri, P. Gudem, and L. Larson, Distortion in currentcommutating passive CMOS downconversion mixers, MicrowaveTheory and Techniques, IEEE Transactions on, vol. 57, pp. 26712681, nov. 2009.

[13] T.-T. Liu and J. Rabaey, Linearity analysis of CMOS passivemixer, in Circuits and Systems (ISCAS), 2011 IEEE Interna-tional Symposium on, pp. 2833 2836, may 2011.

[14] M. Voltti, T. Koivi, and E. Tiiliharju, Comparison of active andpassive mixers, in Circuit Theory and Design, 2007. ECCTD2007. 18th European Conference on, pp. 890893, 2007.

[15] S. Zhou and M.-C. Chang, A CMOS passive mixer with lowicker noise for low-power direct-conversion receiver, Solid-StateCircuits, IEEE Journal of, vol. 40, no. 5, pp. 10841093, 2005.

[16] F. Tillman and H. Sjoland, A bootstrapping technique to im-prove the linearity of CMOS passive mixers, in VLSI Circuits,2003. Digest of Technical Papers. 2003 Symposium on, pp. 221222, 2003.

[17] N. Kim, V. Aparin, and L. Larson, A resistively degeneratedwideband passive mixer with low noise gure and high IIP2, Mi-crowave Theory and Techniques, IEEE Transactions on, vol. 58,no. 4, pp. 820830, 2010.

[18] A. Mercha, W. Jeamsaksiri, J. Ramos, S. Jenei, S. Decoutere,D. Linten, and P. Wambacq, Impact of scaling on analog/RFCMOS performance, in Solid-State and Integrated CircuitsTechnology, 2004. Proceedings. 7th International Conference on,vol. 1, pp. 147152 vol.1, 2004.

[19] T. Zhang, V. Subramanian, and M. Haase, Comparison of pspand bsim4 mosfet model across various parameters, in GermanMicrowave Conference, 2010, pp. 3235, 2010.

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[20] B. P. Lathi, Linear Systems and Signals (The Oxford Series inElectrical and Computer Engineering). Oxford University Press,USA, 2nd ed., jul. 2004.

[21] D. Webster, J. Scott, and D. Haigh, Control of circuit distor-tion by the derivative superposition method [MMIC amplier],Microwave and Guided Wave Letters, IEEE, vol. 6, no. 3, pp. 123125, 1996.

[22] W. Cheng, A.-J. Annema, G. J. M. Wienk, and B. Nauta, Awideband IM3 cancellation technique using negative impedancefor LNAs with cascode topology, in Radio Frequency IntegratedCircuits Symposium (RFIC), 2012 IEEE, pp. 1316, 2012.

[23] S. Rodriguez, S. Tao, and A. Rusu, An IIP2 digital calibrationtechnique for passive CMOS down-converters, in Circuits andSystems (ISCAS), Proceedings of 2010 IEEE International Sym-posium on, pp. 825828, 2010.

[24] K. Lundberg, Survey of noise sources in bulk CMOS. On-line: http://web.mit.edu/klund/www/papers/ retrieved 2013-04-16, 2002.

[25] C. Andrews and A. Molnar, A passive-mixer-rst receiver withbaseband-controlled RF impedance matching, 6dB NF, and 27dBm wideband IIP3, in Solid-State Circuits ConferenceDigest of Technical Papers (ISSCC), 2010 IEEE International,pp. 4647, 2010.

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[29] Y. Tang and R. Geiger, Eects of open-loop nonlinearity on lin-earity of feedback ampliers, in Circuits and Systems, 2002. IS-CAS 2002. IEEE International Symposium on, vol. 2, pp. II141II144 vol.2, 2002.

[30] B. Toole, C. Plett, and M. Cloutier, RF circuit implications ofmoderate inversion enhanced linear region in MOSFETs, Cir-cuits and Systems I: Regular Papers, IEEE Transactions on,vol. 51, no. 2, pp. 319328, 2004.

[31] D. Webster, D. Haigh, J. Scott, and A. Parker, Derivativesuperposition-a linearisation technique for ultra broadband sys-tems, inWideband Circuits, Modelling and Techniques, IEE Col-loquium, pp. 3/1314, 1996.

[32] T.-S. Kim and B.-S. Kim, Post-linearization of cascode CMOSlow noise amplier using folded PMOS IMD sinker, Microwaveand Wireless Components Letters, IEEE, vol. 16, no. 4, pp. 182184, 2006.

[33] X. Li, W. Wu, A. Jha, G. Gildenblat, R. Van Langevelde, G. D. J.Smit, A. Scholten, D. B. M. Klaassen, C. McAndrew, J. Watts,M. Olsen, G. Coram, S. Chaudhry, and J. Victory, Benchmarkingthe PSP compact model for MOS transistors, in MicroelectronicTest Structures, 2007. ICMTS '07. IEEE International Confer-ence on, pp. 259264, 2007.

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[35] K. Ishida, A. Tamtrakarn, T. Sakurai, and H. Ishikuro, Anoutside-rail opamp design targeting for future scaled transistors,in Asian Solid-State Circuits Conference, 2005, pp. 7376, 2005.

[36] P.-I. Mak and R. Martins, High-/mixed-voltage RF and analogCMOS circuits come of age, Circuits and Systems Magazine,IEEE, vol. 10, no. 4, pp. 2739, 2010.

[37] R. L. S. Pierre Jr, R. Acoustics, D. J. Maguire, and C. S. Au-tomotive, The impact of a-weighting sound pressure level mea-surements during the evaluation of noise exposure, in ConferenceNOISE-CON, pp. 1214, 2004.

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Appendix A

Source impedance model

As the passive mixer is very sensitive to variations in source and loadimpedance, a model for the output impedance of the amplier stagepreceding the mixer was developed. The model is not intended toreplicate a specic amplier but rather serve as a better than noneapproximation of the output impedance of a high bandwidth amplierstage.

Considering the ampliers developed within the context of this thesisand the characteristics of the transistors available, in the 65 nm RF/analgoueprocess used, a output capacitance of 50 fF was chosen as a reason-able estimate of the drain source capacitance. The actual value for a33× 2/0.06 µm transistor, a size frequently used in this thesis, is 39 fF.The −3 dB bandwidth of the cascode ampliers implemented in thisthesis is in the range of 2 GHz. As a carrier frequency of 4 GHz wasused frequently in the simulations, a −3 dB bandwidth of 10 GHz waschosen for the output impedance model. The model is illustrated inFig. A.1. For voltage mode circuits the model was replaced by itsThevenin equivalent.

Ro

Isource

Co

Ro= 330 Ω

Co= 50 fF

Figure A.1: Output impedance model used in passive mixer simula-tions

71

Appendix B

Complete schematics for

studied circuits

This appendix contains the complete schematics for the tested BB-ampliers. The schematics contain sizes, bias currents and bias voltagesfor all devices in the circuit as well as their types. This appendix isprovided as a quick reference for verifying the results of this thesis andby no means are these circuits to be considered as optimised examplesof the studied techniques.

72

B.1 NMOS derivative superposition amp-

lier using DC shift

MA1

MX1

MC1

IA

IC I

X

Vshift

Rload

VbiasC

IN+

IX=44 µA

IA=752 µA

IC=796 µA

ISP

=450 µAIF=210 µA

Vshift

=190 mV VbiasC

VbiasSN

IN-

OUT- +

MX2 M

A2

MC2

Rload

MSP1 M

SP2

MSN2

MSN1

VbiasSP V

biasSP

ISP

MSF1

MSF2

Vshift

17X2/0.14 µm

66X2/0.36 µm

55X2/0.14 µm

20X2/0.14 µm

20X4/0.36 µm

40X2/0.36 µm

Figure B.1: Schematic for the NMOS derivative superposition ampli-er using ideal DC shift

73

B.2 NMOS derivative superposition amp-

lier using cross coupled dierential

pair

33X2/0.14 µm

33X2/0.14 µm

33X2/0.14 µm

50X6/0.36 µm

500 Ω500 Ω

30X2/0.36 µm

33X2/0.14 µm

IX

IA

IX=85 µA

IA=2.3 mA

IF= 700 µA

ISP

=1.52 mATo source follower not illustrated here

IF

20X2/0.06 µm

30X4/0.36 µm

VbiasC

MC1

Vin+

Vout

+

Vin-

MC2

MA1

MA2M

X1M

X2

MSP1,2

VbiasSP50X6/0.36 µm

MSF

MSN

VbiasC

MSD

VbiasSD

VbiasSN

ISP

Figure B.2: Schematic for the NMOS derivative superposition ampli-er using a cross coupled dierential pair

74

B.3 CMOS derivative superposition amp-

lier using PMOS auxiliary transistor

IA

IX=373 µA

IA=1.64 mA

IC=1.26 mA

IF=300 µA

16X2/0.14 µm

330 Ω

IX I

C IF

Illustration of half of diff amplifier where other half is identical

30X4/0.36 µm

70X4/0.14 µm

100X2/0.36 µm

85X2/0.14 µm

MC

MX

MA M

SN

MSF

VbiasC

VbiasSN

Vout

-

Vin+

Figure B.3: Schematic for CMOS derivative superposition amplierusing a PMOS auxiliary transistor

75

B.4 Post distortion amplier using folded

PMOS common gate post distorter

VbiasX

VbiasC

MA

MX

MC

4kΩVbiasSP

Vin+

33X1/0.14 µm 28X1/0.14 µm

33X1/0.14 µm

100X2/0.36 µm

IX

60X1/0.36 µm

10X3/0.09 µm

IA

ISP

IF

IX=189 µA

IA=905 µA

IF=500 µA

ISP

=1 mA

Illustration of ½ of amplifier where other half is identical

MSP

MSF

MSN

VbiasSN

Vout

-

Figure B.4: Schematic for the post distortion amplier using PMOScommon gate post distorter

76

Appendix C

Possible denition of input and

output power

RF engineering commonly describes input and output levels in terms ofpower or dBm. Using dBm as a measurement unit makes perfect sensein systems having well dened source and load impedances. However,for the circuits studied in this thesis this is not the case as the circuitshave either very low impedance, corresponding to current-mode, orvery high impedance, corresponding to voltage-mode. Thus, the actualinput and output power is zero for all circuits. However, in order topresent the measured data in a familiar format, a system for movingbetween current/voltage measurements and power is used throughoutthe thesis. This system is commonly employed, at least in terms ofvoltage to power conversion, in publications on RF circuits.

With regards to interpreting voltage in terms of power, the conversionis done thorugh assuming that the voltage is applied across a 50 Ωload. This is the equivalent of having a super buer connected tothe measured node that drives a 50 Ω load and measuring the resultingpower. This conversion is illustrated by Fig. C.1.

Ro

Isource

Co

Iin

Fictonal load

50Ω

Ro

Vsource

Co V

in

Fictonal load

50Ω

Figure C.1: Voltage to power conversion

77

Ro

Isource

Co

Iin

Fictonal load

50Ω

Ro

Vsource

Co V

in

Fictonal load

50Ω

Figure C.2: Current to power conversion

With regards to current-mode, the conversion consists of an imaginarycurrent buer. Essentially the case is the same as for voltage-modecircuits. The input current is converted to power by passing it througha 50 Ω load, as illustrated in Fig. C.2. Assuming that peak quantitiesare measured, the conversions are given by:

Current to power: 10 · log10

((10

Iin/20√2

)2

· 500.001

)= Iin + 44 dBm

(C.1)

Voltage to power: 10 · log10

((10

V in/20√2

)2

· 150·0.001

)= Vin + 10 dBm .

(C.2)

If RMS quantities are measured the same gures are +47 dBm forcurrent and +13 dBm for voltage.

Whether or not this makes sense is the readers decision. In the thesisthe only conversion used is that of voltage to power. The opinion ofthe author of this thesis is that the use of these conversions are atbest questionable as without a well dened impedance any denitionof power is completely ctional. Thus for integrated circuits it wouldbe more appropriate to measure quantities in dBV or the equivalentunit for current dB-Ampere or dBA (not to be confused with the A-weighted sound pressure measurement of dBA [37]).

78

Appendix D

Low frequency distortion

current in MOS switches

The test used to determine the nonlinear characteristics of MOS switchesin the linear region is the Gummel symmetry test commonly used tocheck the behaviour of MOSFET models with a VDS close to zero [33].The test setup is illustrated in Fig. D.1. However, another use for thistest is to study the nonlinear behaviour of the on state conductancewhen a sinusoidal waveform is applied across the switches, correspond-ing roughly to a mixer where the LO frequency is much lower thanthe RF carrier frequency. While this is not the case in homodynereceivers, switch nonlinearity will aect the signal in a similar way.

To study the nonlinearity of a MOS switch, a 1 kHz sinusoidal wavewith 10mV peak voltage is applied across the switch as per Fig. D.1.The switch devices are sized 7× 1/0.06 µm both NMOS and PMOS andthe test is performed with a common mode voltage of 600 mV. Thegates of the NMOS and PMOS transistors are connected to 1.2V and0V respectively. Fig. D.2 show the resultant current waveform as well

Vcm+0.5V

DS

VgateN

Vcm-0.5V

DS

VgateP

Figure D.1: Setup for the Gummel symmetry test

79

-100

-50

0

50

100

0 0,25 0,5 0,75 1Ids [

µA

]

Time [ms]

Tgate current-0,15

-0,10

-0,05

0,00

0,05

0,10

0,15

0 0,25 0,5 0,75 1

ΔId

s

[µA

]

Time [ms]

Resistor current -NMOS current

Resistor current -PMOS current

-2,0

-1,5

-1,0

-0,5

0,0

0,5

1,0

1,5

2,0

0 0,25 0,5 0,75 1

ΔId

s [

nA

]

Time [ms]

Resistor current -Tgate current

Figure D.2: Current waveforms for the symmetry tested switch

as the dierence in switch current compared to a resistor tted at 0Vacross the switch. The equivalent resistors are sized 318.4 Ω for theNMOS, 984.1 Ω for the PMOS and 240.6 Ω for the transmission gate.In Fig. D.2 it is shown that the dierence current in the transmis-sion gate is reduced by approximately 100 times by the transmissiongate connection. This corresponds to a 40 dB reduction in distortioncurrent which was also conrmed by steady state analysis.

80

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