A T-Type Isolated Zero Voltage Switching DC-DC Converter ...€¦ · Abstract—A novel isolated dc-dc converter is proposed, using the T-Type topology with zero voltage switching

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2016.2600654, IEEETransactions on Power Electronics

A T-Type Isolated Zero Voltage Switching DC-DCConverter With Capacitive Output

Delvanei Gomes Bandeira Jr., Member, IEEE, and Ivo Barbi, Fellow, IEEE.

Abstract—A novel isolated dc-dc converter is proposed, usingthe T-Type topology with zero voltage switching and pulse widthmodulated(TT-ZVS-PWM) with a capacitive output filter. It usesfour switches, two of which are subjected to the input voltage,and the other two to half the input voltage. All switches com-mutate under zero-voltage over a wide load range. The proposedconverter has the following features: (a) symmetrical operationof the isolation transformer, (b) modulation by pulse width withconstant frequency, (c) zero voltage switching, and (d) three-level voltage applied to the primary winding of the transformer.Theoretical analysis, design example, and experimental data fora 2 kW, 400 VDC input, 400 VDC output, and 50 kHz switchingfrequency laboratory prototype, working in two operating pointsare included in the paper. The measured efficiency was 95% at950W.

Index Terms—Zero voltage switching, power supplies, T-type,DC-DC converter.

NOMENCLATURED Duty cyclefs Switching frequencyiLr Resonant inductor currentIo Load currentIo Normalized load currentIomin Normalized minimal load current for ZVS switchingn Transformer turns ratioNp Number of turns in the transformer primary coilNs Number of turns in the transformer secondary coilLd Transformer leakage inductanceq Static gainTs Switching periodtd Dead timeVo Converter output voltageV

′o Converter output voltage reflected to the transformer

primary windingV1 Converter input voltage

I. INTRODUCTION

ISOLATED dc-dc converters with capacitive output filtersare widely used in applications to meet the requirements

of galvanic isolation and voltage conversion ratio, such ashybrid electric vehicles, solar, telecom, automotive, eolic,

This work was supported by CAPES – Brazilian Federal Agency for Sup-port and Evaluation of Graduate Education within the Ministry of Educationof Brazil, Federal University of Santa Catarina and Power Electronics Institute(INEP)

D. G. Bandeira Jr. is with the Power Electronics Institute(INEP), De-partment of Electrical Engineering, Federal University of Santa Catarina,Florianopolis 88040970, Brazil (e-mail: [email protected]).

I. Barbi is with the Department of Automation and Systems, FederalUniversity of Santa Catarina, Florianopolis 88040970, Brazil (e-mail: [email protected])

ultracapacitor system, uninterruptible power system, batteryenergy storage system and others [1]–[7].

The full-bridge zero voltage switching modulated by pulsewidth with phase shift dc-dc converter(FB-ZVS-PWM-PS)is suitable for such applications due to the following fea-tures: high power density, zero voltage switching, bidirectionalpower transfer capability, modular, symmetric structure, andhigh-frequency galvanic isolation [8]–[14].

The three-level zero voltage switching modulated with pulsewidth dc-dc converter(TL-ZVS-PWM) is used for high powerand high input voltages because it enables the use of lowvoltage rated semiconductor devices that has small on-stateresistance, small parasitic capacitance, reduced reverse recov-ery of the intrinsic diode of MOSFETs, when compared tohigher voltage rated devices [15]–[20].

It can be seen that both FB-ZVS-PWM-PS and TL-ZVS-PWM share similar features, but the rated DC-bus voltagedefines which one should be used. These features lead tohigh efficiency power conversion and generation of many othertopologies, starting from these two cells and improving someissues, such as ZVS over a restrict load range, reactive powercirculation and others.

Considering two level dc-dc converters, the isolated asym-metrical half-bridge zero voltage switching modulated by pulsewidth(HB-ZVS-PWM) is a low cost solution, since it hasfewer components when compared to other solutions [21]–[24]. However, due to asymmetrical operation, this topologyworks with restricted duty cycle range in order to avoid satu-ration of the transformer, also the rectifier voltage stresses aredifferent and load dependent. In addition, the filter capacitorvoltages changes with the control duty cycle [25].

In order to overcome the issues of the HB-ZVS-PWM andimprove the primary winding voltage to a three level one, theT-type structure, recently proposed and successfully tested insingle and three-phase inverters, can be used [26], [27].

The aim of this work is to investigate the utilization of theT-type structure in the design of isolated dc-dc converters. Itwill be demonstrated that the proposed converter has featuressimilar to the FB-ZVS-PWM-PS and TL-ZVS-PWM convert-ers, such as: operation at constant switching frequency, softswitching(ZVS) and symmetrical operation of the isolationtransformer. However, while the voltages across two powerswitches are equal to the DC bus voltage, two other switchesare subjected to half the input voltage, which allows theutilization of lower voltage switches. To improve the ZVSload range of the circuit, a small inductance is added in orderto improve the load range to a full range, improving theefficiency. Moreover, to overcome the reverse recovery issuein the secondary winding rectifier diodes, a capacitive filter



Fig. 1. Power stage diagram of the proposed TT-ZVS-PWM converter.

clamps its voltages, also it imposes a linear rate of change inthe primary inductor currents. The commutation of the rectifierdiodes occurs with zero current, thus improving the efficiencyof the converter.In Section II the operation of the proposed converter isdescribed, theoretical analysis is presented in Section III.Section IV deals with the commutation analysis, Section Vproposes a design procedure and experimental results takenfrom a laboratory prototype are presented in Section VI.

II. THE T-TYPE DC-DC CONVERTER

The proposed TT-ZVS-PWM dc-dc converter is depictedin Fig.1. It consists of two capacitors Cb1 and Cb2, wherevoltages are equal to half the input voltage, two main switches,namely S1 and S2, a bi-directional switch Sb, where (b) and (c)presents different configurations for switches implementation.The commutation capacitors (Cr1...Cr3) include the intrinsicparasitic capacitors of the switches. Lr represents the resonantinductance, which includes transformer leakage and parasiticinductances along the circuit. La represents an auxiliary induc-tance that improves the soft switching load range. The outputfilter is composed by the capacitors Co1 and Co2 which areconnected to the secondary winding of the transformer via avoltage doubler rectifier formed by diodes Dr1 and Dr2. Thecircuit of Fig.1 can be represented by the equivalent circuit ofFig.2 (a)-(f) provided the following assumptions are made, asfollows:

• Each capacitor of the output filter is represented by adirect voltage source with Vo/2 volts and reflected to thetransformer primary side(V

′

o/2 );• The transformer turns ratio is n = Ns/Np and both the

magnetizing inductance and La are neglected along theanalysis;

• Capacitors Cb1 and Cb2 are represented by direct voltagesource with half of the input voltage;

• All components, including the power semiconductors areideal.

The proposed converter has three different operationschemes, namely Continuous Conduction Mode(CCM),Boundary Conduction Mode(BCM) and Discontinuous Con-duction Mode(DCM). The operation in CCM will be dis-cussed, since the operation in BCM and DCM are similar.Considering CCM, there are six operating modes within each

half of the commutation cycle. They are presented as follows,with the converter main waveforms of voltages and currentsdepicted in Fig.3, for operation in (a)CCM and (b)DCM.

A. t1 ≤ t ≤ t2 [Fig.2 (a)]

At the instant t = t1, switch S1 begins to conduct andvoltage across the transformer secondary winding becomesequal to Vo/2. The current through the resonant inductanceiLr increases linearly, thus the diode Dr1 begins to conductand power is transferred to the load.

B. t2 ≤ t ≤ t3 [ Fig.2 (b)]

At the instant t = t2, iLr(t2) = I1 and S1 is turned off.The current iLr starts flowing through S3 and D4 , the voltageacross the resonant inductance is the negative of V

′

o/2, thusthe current iLr begins to decrease linearly. The next operatingstage starts at the instant t = t3, where S3 is turned off.

C. t3 ≤ t ≤ t4 [Fig.2 (c)]

At the instant t = t3 , iLr(t3) = I2 when S3 is turned off.The current iLr flows through the diode D2. The voltage vabbecomes negative. The current iLr decays linearly to zero,eventually reaching zero at the instant t = t4, where thediode Dr1 current reduces to zero, and the reverse recovery iseliminated. During this time interval, the switch S2 is gatedon.

D. t4 ≤ t ≤ t5 [Fig.2 (d)]

At the instant t = t4, iLr becomes negative and startsflowing through the switch S2, the diode Dr2 begins toconduct, and the voltage across the transformer secondarywinding becomes equal to −Vo/2. This stage ends at theinstant t = t5, when the switch S2 is turned off. The converteroperation over the time interval Ts/2 ≤ t ≤ Ts is similar, withthe topological stages illustrated in Fig.2 (d)(e)(f)(a).

III. THEORETICAL ANALYSIS

A. Voltage Gain at CCM

The converter duty cycle D is defined by (1), consideringa switching period of Ts, both presented in Fig.3(a). Thevoltage across the inductance Lr, depicted in Fig.3(a) has anull average value, this means that (3) can be used with (1)and (2) to determine the time instants ∆tk, k = 1..3.

∆t1 + ∆t2 =DTs

2(1)

∆t3 =(1 −D)Ts

2(2)

(V1/2−V′

o/2)∆t1−(V1/2+V′

o/2)∆t2−V′

o/2)∆t3 = 0 (3)

The peak currents during each interval are calculated with (4)and (5). The rectifier diode current io waveform is illustratedin Fig.3(a), which is used to obtain the average of the outputcurrent, calculated by (6). The converter static gain q is definedby (7).



Fig. 2. Topological stages of the proposed TT-ZVS-PWM converter.

Fig. 3. Typical theoretical waveforms of the proposed TT-ZVS-PWM converter for operation in (a) CCM; (b) DCM.



Fig. 4. Static voltage gain of the TT-ZVS-PWM converter as function of thenormalized load current, for different duty cycles.

I1 = Lr

V1/2 − V′

o

/2

∆t1(4)

I2 = Lr

V1/2 + V′

o

/2

∆t2(5)

Io =I1∆t1

2+I2∆t2

2+

(I1 − I2) ∆t32

(6)

q =V

′

o

V1(7)

With (1)-(7) the static gain q can be obtained as a function ofthe converter parameters, show in (8), were the output currentis normalized with (9).

q =

√D (2 −D) − 8Io (8)

Io =4LrfsIonV1

(9)

The static gain versus the normalized load current, is rep-resented in Fig.4. Identical behavior is found in the classicFB-ZVS-PWM [18], [28]–[31].

B. VOLTAGE GAIN AT DCM

Fig.3(b) shows key waveforms for operation in DCM mode.The converter operates in DCM mode when I2 = 0, becausetheres not enough energy stored in the Lr inductance. Thus,the current reaches null value during ∆t3 time interval. Byevaluating the same equations in CCM for I2 = 0, the staticgain is obtained as

q =D2

D2 + 4Io. (10)

C. Boundary Between CCM and DCM

In the boundary condition, current reaches the null valueright at the time instant equivalent to half of the switchingperiod. This leads to the following consideration:

Lr

V1/2 + V′

o

/2

∆t2= 0, (11)

thereforeD = q. (12)

Fig. 5. Commutation schemes for the primary side switches and auxiliarycommutation inductance configuration.

By replacing the duty cycle in (8), it returns the equationthat shows the boundary between CCM and DCM modes,depicted in (13).

Dcrit =1 ±

√1 − 16Io2

(13)

IV. COMMUTATION ANALYSIS

Refering to the topological stages of Fig.2, there are twocommutations for primary side switches along half of theswitching period, both depends on the Lr stored energy.One commutation starts with iLr(t) = I1, the other withiLr(t) = I2. As previously demonstrated, I2 = 0 in DCMmode. Hence, the ZVS load range is inside the CCM areadelimited in Fig.4. The same limitation is found in the classicFB-ZVS-PWM. The commutations are described as follows,and a solution to overcome the limited ZVS load range isintroduced.

A. Main Switches Commutation Analysis

Before S1 is turned off, vCr1

(t−2)

= 0 ,vCr2

(t−2)

= V1, vCr3

(t−2)

= 0, vCr4

(t−2)

= V1/2 and iLr

(t−2)

= I1. Theload current, reflected to the transformer primary side, flowsthrough S1 and Lr. At the instant t = t2, S1 is turned offand its current starts flowing through the switches parasiticcapacitors as shown in Fig. 5.(a), vCr1 rises linearly from zeroto V1/2 , vCr4 decays linearly from V1/2 to zero and vCr3

remains equal to zero. Switch S3 remains gated on during thistime interval. The behavior of the voltage across the equivalentcapacitor is represented by (14), from which the commutationtime, given by (15) is obtained.

CrdvCr

dt=I13

(14)

tc1 =3CrV1

2I1(15)

B. Auxiliary Switches Commutation Analysis

Prior to this commutation, the current flows through Lr, S3

and D4, according to Fig.2(c), with value iLr

(t−3)

= I2. Atthe instant t = t3, switch S3 is turned off. The capacitor Cr3

begins to charge linearly in parallel with capacitors Cr1 andCr2. The corresponding topological stage is show in Fig.5(b).This stages finishes when vCr2 = 0, vCr1 = V1 and vCr3 =



Fig. 6. Auxiliary inductance impact on currents waveforms: (a) CCM; (b) DCM.

V1/2. The switch S2 is gated on while diode D2 is conductingto ensure commutation with zero voltage. Equation (16) canbe derived to this commutation, from which the time intervaltc2 can be evaluated, resulting in (17).

Cr∆vCr

∆t=I23

(16)

tc2 =3CrV1

2I2(17)

From equations (15) and (17) the commutations interval can beobtained. As the load decreases, the time interval calculatedin (17) tends to increase more than the time interval from(15). Therefore, this time interval is the reference for the deadtime (td) necessary to achieve zero voltage switching on mainswitches, thus

td > tc2. (18)

C. Commutation in DCM

Considering the operation in DCM mode, it is verified atwaveforms of Fig.3(b) that iLr current reaches null valuebefore the auxiliary switches turns off. At this point, noenergy is available in the resonant inductor to perform thecharge/discharge in parasitics capacitors of switches, thus thevoltage across switches S1 and S2 before this commutationwill be different from zero, and hard switching is obtained.The auxiliary switches commutations depends on the Lr storedenergy, this means that soft switching will be lost when theconverter operates at the DCM mode. In fact, this behavior

is found in the traditional full bridge converter with phaseshift [29], [30]. A proper solution for this scheme is to usean auxiliary inductance (La) in parallel with switches S3 andS4, has shown in Fig.5(c). The design of this inductance mustensure a current source behavior during the auxiliary switchescommutation in DCM. The peak value of the current flowingthrough La (ILa) can be evaluated as follows:

ILa =V1 (DminTs + tc2)

8La. (19)

Replacing I2 by ILa in (16) and solving for La it returns

La =DminTstc2

12Cr(20)

By choosing a minimal load to obtain ZVS, calculating theduty cycle for this load ( Dmin) and substituting into (20), itreturns the inductance value to achieve soft switching duringDCM mode. A modification in the circuit current distributiondue the auxiliary inductance is verified in Fig.6. The iLa

current flows through the primary side switches and passiveelements, but does not affect the converter mechanisms.

V. DESIGN PROCEDURE

Given the specifications set listed in Table I, an operationpoint must be chosen, which leads to the static gain q and thenormalized output current Io. In order to validate the auxiliaryinductance behavior, the operation point where q = 0.5, D =0.7 and Io = 0.123 is adopted, this leads to a small load rangeof soft switching. Using these specification values and (7), thetransformer turns ratio is evaluated by



TABLE IT-TYPE ISOLATED DC-DC CONVERTER SPECIFICATIONS

Symbol Quantity Value(Unit)Po Output power 2kWV1 Input voltage 400VVo Output voltage 400Vfs Switching frequency 50kHz– Soft switching load range 20-100%

n =400

400×0.5= 2. (21)

The resonant inductance value can be obtained from (9).The external parasitic capacitance to achieve ZVS in CCMmode is evaluated with (16). Performing these calculations, itresults:

Lr =0.0828×400

4×50000×2×5= 16.51µH (22)

At this operation point, the available load range for ZVSswitching can be derived from (13) and (6), where the loadnecessary to enter in the BCM mode is the lower limit, inwhich Io = 0.062 for q = 0.5. This leads to a small load rangeof soft switching (75%-100%), by choosing the lower limit as78%, the normalized current at this load can be evaluated by(9).

Iomin =4×16.51×10−6×50000×2

400× 2000 × 0.785

400= 0.065

(23)For Iomin = 0.065 and q = 0.5 the curves in Fig.4 returns

D = 0.51, the peak current I2 for this condition can beevaluated employing eq. (5). The dead time required for softswitching is then evaluated using (16). Choosing 3% of theswitching period as the dead time, the commutation capacitorrequired is obtained, as follows.

Cr =20×10−6×0.036×2×1.846

3 × 400≈ 2.2nF (24)

In order to improve the load range from 75%-100% to20%-100% despite the chosen operating point, the auxiliaryinductance is employed. The normalized current at 20% ofload is evaluated with (9) as Io = 0.017, the duty cycle Dmin

is evaluated at q = 0.5, substituting in (20), returns:

La =0.261×20×10−6×250×10−9

12 × 2.2 × 10−9≈ 45µH (25)

VI. EXPERIMENTAL RESULTS

In order to validate the analysis results, a 2 kW proto-type was designed, built and tested. Table I summarize theprototype specifications, Table II shows passive componentsbased on results of section V with semiconductors employedin the prototype construction, which is depicted in Fig.7. Theparameters have been combined to ensure soft-commutation(ZVS)for 20 to 100 % of load range, thus an external induc-tance of 45 uH was added in parallel with the primary winding

Fig. 7. Prototype of the proposed TT-ZVS-PWM converter.

TABLE IICOMPONENTS USED IN PROTOTYPE

Symbol Quantity Value(Technology)Cr1, ..., Cr4 Commutation capacitor 2.2nF(polyphropilene)Cb1, Cb2 DC link capacitor 2x20µF(polyphropilene)Co1, Co2 Output filter capacitor 200µF(polyphropilene)La External auxiliary inductance 45µH-gap = 1mm

N87-E50(epcos)LITZ wire (487x32 AWG)

Lr External resonant inductance 15.47µH-gap = 1mmN87-E40(epcos)LITZ wire (487x32 AWG)

Tr High frequency transformer Np=4, Ns=8, Ld=0.3µHN87-E60(epcos)LITZ wire (487x32 AWG)

S1, S2 Main switches IPW60R041C6 (Infineon)S3, S4 Auxiliary switches IRFP4332PBF (IR)

of the transformer. An external inductance of 15.65 uH wasadded in series with the leakage inductance of the transformerto provide the desired resonant inductance.

The waveforms presented in Fig.8(a)-(f) illustrates the op-eration in DCM of the proposed converter. The voltage acrossthe auxiliary switches depicted in (a) have half the input volt-age, without significant overshoot due to ZVS commutation,obtained even with iLr reaching the null value during theconverter operation. In Fig.8(b) the auxiliary inductor current(iLa) is show with the voltage across one main switch and oneauxiliary switch, both with ZVS commutation. A scaled viewof Fig.8(b) illustrated in Fig.8(c) shows the critical commuta-tion in DCM, performed by the peak value of iLa, which waspredicted in section IV-C. In Fig.8(d) ZVS commutation of themain switch S1 is verified by the gate signal of main switchS1(vg1) changing level right after the voltage across switch S1

reaches null value, as predicted in sections IV-B and IV-C. InFig.8(e) ZVS commutation of switch S3 is verified by the gatesignals of switches S3(vg3), S2(vg2) and the voltage across theswitch S3(vS3), since vS3 reaches the null value a half periodbefore switch S3 turns on, as predicted in section IV-A.

Considering the operation in BCM and CCM, the resultsare presented in Fig.9 (a) and Fig.9 (b)-(f) respectively. Thevoltage across the auxiliary switches and iLr are presented inFig.9(a) for the operation in BCM. The waveforms presentedin Fig.9(b) show the current flowing through the resonant in-ductor and the voltage across the transformer primary winding



Fig. 8. Experimental results for DCM operation (Po = 400 W): (a) Auxiliary switches drain source voltages (100V/div) and resonant inductor currentiLr (10A/div); (b) Main switch drain source voltage vS1 (100V/div), auxiliary switch drain source voltage vS3(100V/div) and auxiliary inductor currentiLa(5A/div), where (c) details the commutation; (d) Gate source voltage vg1 (20V/div), main switch drain source voltage vS1 (100V/div) and gate sourcevoltage vg4 (20V/div); (e) Gate source voltage vg2 (20V/div), auxiliary switch drain source voltage vS3 (100V/div) and gate source voltage vg3 (20V/div).

with the three levels, corresponding to the expected theoreticalwaveforms in CCM. Fig 9(c) shows ZVS commutation ofthe main switch S1 and Fig 9(d) shows ZVS commutationof the auxiliary switch S3, with same mechanism describedearlier. Fig.9(e) show the capacitor DC link voltages, bothstable with and equal to half of the input voltage, due to thesymmetrical behavior of the converter in open loop operation.Fig.9(f) shows the output voltage and current for nominal loadconditions.

The converter efficiency was measured employing Yoko-gawa WT300 power analyzer and is shown in Fig. 9(g).For q = 0.5 the maximum value, equal to 94.2% occurs at41% of the rated load power, while at the rated power, themeasured efficiency is 92.6%. Several efficiency tests for thesame specifications and a different operation point (definedby q = 0.65, D = 0.9 and Io = 0.07084) are plotted,

with efficiency equivalent to 95%. A further investigationin efficiency reveals that conduction losses increases whenoperating with La, as demonstrated by Fig.9(h) and (i). Animprovement in conduction losses also is achieved in thesecond operation point, demonstrated by Fig.9(i). Therefore,a proper parameter combination can lead to high efficiency.

VII. CONCLUSION

A new four-switch power-circuit topology, for realizationof isolated dc-dc converters with capacitive output filter wasproposed, analyzed, designed, and tested in the laboratory.From the theoretical and experimental results presented inthis paper, the proposed topology is well-suited to economicalrealization of high power density and high efficiency powersupplies.



Fig. 9. Experimental results for BCM and CCM operation (Po = 1.3 kW and Po = 2 kW): (a) Auxiliary switches drain source voltages (50V/div)and resonant inductor current iLr (20A/div) for BCM operation; (b) Primary winding transformer voltage vab (100V/div) and resonant inductor currentiLr(20A/div); (c) Auxiliary switch gate source voltage vg4 (20V/div), main switch gate source voltage vg1(20V/div) and drain source voltage vS1 (90V/div);(d) gate source voltage vg2 (20V/div), auxiliary switch drain source voltage vS3 (50V/div) and gate source voltage vg3 (20V/div); (e) DC bus capacitancevoltages vcb1 and vcb2 (100V/div); (f) Output voltage Vo (100V/div) and output current Io (5 A/div); (g) Measured efficiency versus the load power of theproposed TT-ZVS-PWM, for different static gains; (h) Conduction losses on the transformer primary side elements; (i) Conduction losses for two operationpoints.



ACKNOWLEDGMENT

The authors would like to thank A. L. S. Pacheco and L.M. Coelho for the support during the prototype assembly andCAPES for the financial support.

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Delvanei Gomes Bandeira Junior was born inPelotas, Rio Grande do Sul, Brazil, in 1986. Hereceived the B.S. degree from the Catholic Uni-versity of Pelotas-UCPel, Pelotas, Brazil, in 2010,and the M.S. degree from the Federal University ofSanta Catarina, Florianopolis, Brazil, in 2014, bothin electrical engineering. He is currently workingtoward the Ph.D. degree in electrical engineering atthe Power Electronics Institute, Federal Universityof Santa Catarina. His research interests includesoft switching, switched capacitors, and high voltage

power supplies.

Ivo Barbi(F’ 11) was born in Gaspar, Santa Cata-rina, Brazil, in 1949. He received the B.S. and M.S.degrees in electrical engineering from the FederalUniversity of Santa Catarina, Florianopolis, Brazil,in 1973 and 1976, respectively, and the Dr. Ing.degree from the Institut National Polytechnique deToulouse, Toulouse, France, in 1979. He founded theBrazilian Power Electronics Society (SOBRAEP)and the Brazilian Power Electronics Conference(COBEP) in 1990, and the Brazilian Power Elec-tronics and Renewable Energy Institute (IBEPE) in

2016. Prof. Barbi is an Associate Editor of the IEEE TRANSACTIONS ONPOWER ELECTRONICS and the IET ELECTRONICS LETTERS, Presidentof the Brazilian Power Electronics and Renewable Energy Institute (IBEPE),researcher at the Solar Energy Research Center and Professor of ElectricalEngineering at Federal University of Santa Catarina (Brazil).

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A T-Type Isolated Zero Voltage Switching DC-DC Converter ...€¦ · Abstract—A novel isolated dc-dc converter is proposed, using the T-Type topology with zero voltage switching