acer1670

A

B

C

D

E

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the waterma

LA-24111

1

2

Compal confidentialSchematics Document DT TRANSPORT or Prescott uFCPGA with ATI-RC300M+SB200 core logic2004-06-28REV:0.3

2

3

3

4

4

Compal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D

Cover SheetSize Date: Document Number

LA-2411PT C , 07, 2004E

Rev 0.1 Sheet 1 of 65

A

B

C

D

E


Compal confidentialFile Name :LA2411 Fan Controlpage 7

Intel Northwood/Prescott Processor uFCBGA-479/uFCPGA-478 CPUpage 4,5,6

Thermal Sensor ADM1032ARpage 7

CLOCK GENERATOR ICS951402AGT1

1

CRT & TV-OUT Conn.page 25 H_A#(3..31) 800MHz

page 24

PSB

H_D#(0..63)

LCD ConnW/EXT VGA CHIP W/EXT VGA CHIP

page 25

W/O EXT VGA CHIP W/O EXT VGA CHIP

ATI-RC300MVGA M9 Embeded 868 pin u-BGApage 8,9,10,11,12,13

Memory BUS(DDR) DDR-SO-DIMM X2BANK 0, 1, 2, 3page 14,15,162.5V DDR- 200/266 USB1.1

ATI-M9+X/M10Cpage 17,18,19,20,21

AGP BUS

BTUSB2.0

page 42

USB conn x4page 35

VGA DDR x2 CHBpage 23

VGA DDR x2 CHApage 22

A-Link

2

Audio Codec ALC 250

AMP & Audio Jackpage 37

2

page 36

MDC & BT Conn3.3V 33 MHzIDSEL:AD19 (PIRQD#,GNT#1,REQ#1)

RJ11 CONNpage 42

PCI BUSIDSEL:AD20 (PIRQA,B#,GNT#2,REQ#2)

page 42

ATI-SB200BGA 457 pinpage 26,27,28,29

AC-LINK

Mini-PCI soltpage 41

CardBus Controller IEEE 1394 Mini PCI LAN ENE 714/1410 TI-TSB43AB22 socket 41 RTL 81000CL page 33 page 34 page page 31IDSEL:AD16 IDSEL:AD18 (PIRQA#,GNT#0,REQ#0)(PIRQC#,GNT#3,REQ#3)

Primary IDE ATA-100

HDD Connectorpage 30

RJ45 CONN RTC CKT.page 26

3

page 33

Slot 0

page 32

Card slotpage 32

Secondary IDE ATA-100

CDROM Connector page

30

3

LPC BUSCABLE CONN.

Power OK CKT.page 46

ENE910page 44

SUPER I/O SMC 207page 38

page 41

Power On/Off CKT.page 46

Touch Pad

page 40

Int.KBD BIOS

page 43

FIRpage 45

page 43

*RJ45 CONN *LINE IN JACK *DC JACK *COM PORT *USB CONN x1 *SPDIF *5V INPUT *VOLUME ADJUSTMENT +TV-OUT PORT

KEY

EC I/O Buffer DC/DC Interface CKT.page 47

page 45

4

4

Power Circuit DC/DCpage 50,51,52,53,54,55,56,57THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D

Compal Electronics, Inc.Title

Block DiagramSize Date: Document Number

LA-2411PT C , 07, 2004E


A


Voltage RailsPower Plane VIN B+ +VCC_CORE +VCCVID +1.25VS +1.2VS_VGA +1.5VS +1.8VS +2.5VALW +2.5V +2.5VS +3VALW +3V +3VS +5VALW +5V +5VS +12VALW RTCVCC Description Adapter power supply (19V) AC or battery power rail for power circuit. Core voltage for CPU The voltage for Processor VID select 1.25V switched power rail for DDR Vtt 1.2V I/O power rail for ATI-VGA M9+X/M10P. 1.5V I/O power rail for ATI-RS300M/RC300M NB AGP. 1.8V switched power rail for ATI-RS300M/RC300M NB. 2.5V always on power rail 2.5V system power rail for DDR 2.5V switched power rail 3.3V always on power rail 3.3V system power rail for SB,LAN,CardReader and HUB. 3.3V switched power rail 5V always on power rail 5V system power rail . 5V switched power rail 12V always on power rail RTC power S0-S1 N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A O FF O FF O FF O FF O FF O FF ON ON O FF ON ON O FF ON ON O FF ON ON S5 N/A N/A O FF O FF O FF O FF O FF O FF ON* O FF O FF ON* O FF O FF ON* O FF O FF ON* ON

Symbol Note :: means Digital Ground

: means Analog Ground @ : means just reserve , no build NAGP@ : means just build when no external AGP VGA chip build in (UMA). M10@ : means build VGA M10 M9@ : means build VGA M9+X M9-M10@ : means build VGA M9 or M10 1520@ : means build Cardbus PCI1520 1620@ : means build Cardbus PCI1620 ATI@ : means build ATI SB USB2.0 related to turn on the function . NEC@ : means build NEC USB2.0 related to turn on the function .

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Board ID Table for AD channel External PCI DevicesDEVICENB Internal VGA AGP BUS SOUTHBRIDGE USB AC97 ATA 100 ETH ERNET 1394 L AN CARD BUS

Vcc RaREQ/GNT #N /A N /A N /A N /A N /A N /A N /A 0 1 2 3

1

IDSEL #N /A AGP_DEVSEL AD31 (INT.) AD30 (INT.) AD31 (INT.) AD31 (INT.) AD24(INT.) AD16 AD19 AD20

PIRQA A N /A D B A C A D A .B C

Board ID

0 1 2 3 4 5 6 7

3.3V +/- 5% 100K +/- 5% Rb 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC

V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V

V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V

V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V

1

Wireless LAN(MINI PCI) AD18

I2C / SMBUS ADDRESSINGDEVICEDDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)

HEXA0 A2 D2

ADDRESS1010000X 1010001X 1101001X

Board ID 0 1 2 3 4 5 6 7

PCB Revision 0.1


Notes ListTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A

Size Date:

Document Number

LA-2411PT C , 07, 2004 Sheet 3 of 65

Rev 0.1

5

4

3

2

1


+VCC_CORE

JP8A

H_A#[3..31]

VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73

A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10

D

D

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31

C

K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 V3 W2 Y1 AB1 J1 K5 J4 J3 H3 G1 AC1 V5 AA3 AC3 H6 D2 G2 G4

A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 ADS# AP#0 AP#1 BINIT# IERR# BR0# BPRI# BNR# LOCK# BCLK0 BCLK1

Prescott

H_REQ#[0..4]

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADS#

+VCC_CORE +VCC_CORE R231

R230 51_0402_5% 1 2 1 2 H_BR0# H_BPRI# H_BNR# H_LOCK#

H_ IERR# 51_0402_5%

CK_BCLK CK_BCLK#

CK_BCLK CK_BCLK#

AF22 AF23

BOOTSELECT

H_HIT# H_HITM# H_DEFER#

F3 E3 E2

HIT# HITM# DEFER# VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55

VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74

D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63

B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24

H _D#0 H _D#1 H _D#2 H _D#3 H _D#4 H _D#5 H _D#6 H _D#7 H _D#8 H _D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_D#[0..63]

C

+5VS 1

+5VS 1

H1 H4 H23 H26 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD10 AD12 AD14 AD16 AD18 AD21 AD23 AD4 AD8

B

AD1

F13 F15 F17 F19 F9 F11 E8 E20 E18 E16 E14 E12

R1099 AMP_3-1565030-1_Prescott 47K_0402_5% 2 2

R1100 47K_0402_5% H_BOOTSELECT

B

+VCC_CORE 1

C

1

B

2

1

MMBT3904_SOT23 R900 100K_0402_5%

Pin number Northwood Pin name A6 B6 TESTHI11 FERR#

Commend

Prescott Pin name TESTHI11

Commend Pull-up 62ohm to +VCC_CORE

Northwood MT Pin name GHI FERR#

Commend Connect to PLD CPUPREF through 0ohm Pull-up 62ohm to +VCC_CORE

Northwood

Prescott

Northwood MT2

Pull-up 200ohm to +VCC_CORE Pull-up 62ohm to +VCC_CORE

Pop Pop

Pop Pop

Pop Pop

FERR#/PBE# Pull-up 62ohm to +VCC_CORE TESTHI6 TESTHI7 VIDPWRGD VID5 Pull-up 62ohm to +VCC_CORE Pull-up 62ohm to +VCC_CORE Pull-up 2.43K ohm to +VCCVID Pull-up1Kohm to +3VRUN & connect to PWRIC Connect to +VCCVID Connect to CPU Filter Connect to CPU Filter

AA20 AB22

ITPCLKOUT0 Pull-up56ohm to +VCC_CORE ITPCLKOUT1 Pull-up 56ohm to +VCC_CORE NC NC float float

ITPCLKOUT0 ITPCLKOUT1 NC NC

Pull-up56ohm to +VCC_CORE Pull-up 56ohm to +VCC_CORE float

Pop Pop Depop

Pop Pop Pop Pop Pop

Pop Pop Depop DepopA

AD2 AD3

float Depop

A

AF3 AE23

NC VCCA VCCIOPLL VSS VSS

float Connect to CPU Filter Connect to CPU Filter Connect to GND Connect to GND Pull-up 200ohm to +VCC_CORE5

VCCVIDLB VCCIOPLL VCCA

NC VCCA VCCIOPLL VSS VSS

float Connect to CPU Filter Connect to CPU Filter Connect to GND Connect to GND

Depop

Depop

AD20

AD1 AE26

BOOTSELECT CPU determine OPTIMIZED/ float COMPAT# TESTHI12 Pull-up 62ohm to +VCC_CORE

Pop Pop

Depop Depop Pop

PopTitle

3

Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5

3

E

Reference Intel document Desktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0

R899 1

2 22K_0402_5%

2 Q107

Q106 2SC2411K_SC59

Compal Electronics, Inc.Prescott Processor in uFCPGA478THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

PopSize Date:

AD25

TESTHI12

DPSLP4

Connect to PLD through 0ohm

Document Number

Pop

Pop

LA-2411PT C, 07, 20041


5

4

3

2

1

+VCC_CORE


Place near SB200 (U6) R513 1 R515 1 56_0402_5% 2 H_F ERR# AE11 AE13 AE15 AE17 AE19 AE22 AE24 AE7 AE9 AF1 AF10 AF12 AF14 AF16 AF18 AF20 AF6 AF8 B10 B12 B14 B16 B18 B20 B23 B26 B4 B8 C11 C13 C15 C17 C19 C2 C22 C25 C5 C7 C9 D10 D12 D14 D16 D18 D20 D21 D24 D3 D6 D8 E1 E11 E13 E15 E17 E19 E23 E26 E4 E7 E9 F10 F12 F14 F16 F18 F2 F22 F25 F5 56_0402_5% 2 H_THERMTRIP# JP8B AF26 R514 1 2

@0_0402_5%

D

R517 1 R518 1 R519 1

130_0402_5% 2 H_PROCHOT# 300_0402_5% 2 H _PWRGOOD 56_0402_5% 2 H_RESET#

Place near CPU

H_RS#[0..2]

H_RS#0 H_RS#1 H_RS#2

H_TRDY#

F1 G5 F4 AB2 J6

SKTOCC#

VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128

RS#0 RS#1 RS#2 RSP# TRDY#

DP#0 DP#1 DP#2 DP#3 GTLREF0 GTLREF1 GTLREF2 GTLREF3

J26 K25 K26 L25 AA21 AA6 F20 F6 AE26 AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3 A6 AD25 R520 1

D

+CPU_GTLREF

H_A20M# H_FERR# H_IGNNE# H_SMI# H_PWRGOOD H_STPCLK# H_INTR H_NMI H_INIT# H_RESET# H_DBSY# H_DRDY# BSEL0 BSEL1 H_THERMDA H_THERMDC +VCC_CORE H_THERMTRIP# R529 R530 1 1 1 2 3 4 2 56_0402_5% 2 56_0402_5% 8 7 6 5

H_F ERR# H _PWRGOOD

C6 B6 B2 B5 AB23 Y4 D1 E5 W5 AB25 H5 H2 AD6 AD5

Pop: Northwood Depop: Prescott@0_0402_5% 2 +VCC_CORE

A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK# LINT0 LINT1 INIT# RESET# DBSY# DRDY# BSEL0 BSEL1 THERMDA THERMDC THERMTRIP# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 TCK TDI TDO TMS TRST# VCCIOPLL VCCA VCCSENSE VSSSENSE VCCVIDLB VSSA ITP_CLK0 ITP_CLK1 VIDPWRGD COMP0 COMP1 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VID0 VID1 VID2 VID3 VID4 VID5

OPTIMIZED/COMPAT# TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9 TESTHI10 TESTHI11 TESTHI12

H_TESTHI0_1 H_TESTHI2_7

R521 R522 RP136

1 1 1 2 3 4 1 1

2 56_0402_5% 2 56_0402_5% 56_0804_8P4R_5% 8 7 6 5 2 300_0402_5% 2 56_0402_5% CPU_GHI# CPU_STP#

H_RESET#

H_TESTHI8 H_TESTHI9 H_TESTHI10 H_TESTHI11 H_DPSLP# H_TESTHI12

R990 R527

H_THERMDA H_THERMDC H_THERMTRIP# ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5 ITP_TCK ITP_TDI ITP_TDO ITP_TMS ITP_TRST#

B3 C4 A2 AC6 AB5 AC4 Y6 AA5 AB4 D4 C1 D5 F7 E6 AD20 AE23 A5 A4 AF3 AD22

Prescott

DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 ADSTB#0 ADSTB#1 DBI#0 DBI#1 DBI#2 DBI#3 DBR# PROCHOT# MCERR# SLP# NC1 NC2 NC3 NC4 NC5 VCCVID

E22 K22 R22 W22 F21 J23 P23 W23 L5 R5 E21 G25 P26 V21 AE25 C3 V6 AB26 A22 A7 AF25 AF24 AE21 ITP_DBRESET# H_PROCHOT#

H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3

for mobile CPU

C

C

RP137 56_0804_8P4R_5% +VCC_CORE

Note: Please change to 10uH, DC current of 100mA parts and close to cap

H_ADSTB#0 H_ADSTB#1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3

L36 1

LQG21F4R7N00_0805 2

33U_D2_8M_R35 H _VCCA 1 C544 + 2 1 + C854 VCCSENSE VSSSENSE +VCCVID H_VSSA CK_ITP CK_ITP# COMP0 COMP1 1 1

W/O ITPH_PROCHOT# H_CPUSLP#

R1017

1 L37

2 LQG21F4R7N00_0805

2 33U_D2_8M_R35

1 2 0_0402_5%

PLL Layout note :1.Place cap within 600 mils of the VCCA and VSSA pins.

R1017-> Pop: Prescott Depop: Northwood

CK_ITP CK_ITP#

AC26 AD26 L24 P1

2.H_VCCIOPLL,HVCCA,HVSSA trace wide 12 mil s(min)

width= 10milR540 61.9_0603_1%

R539 61.9_0603_1% 2 2

F8 G21 G24 G3 G6 J2 J22 J25 J5 K21 K24 K3 K6 L1 L23 L26 L4 M2 M22 M25 M5 N21 N24 N3 N6 P2 P22 P25 P5 R1 R23 R26 R4 T21 T24 T3 T6 U2 U22 U25 U5 V1 V23 V26 V4 W21 W24 W3 W6 Y2 Y22 Y25 Y5

AE5 AE4 AE3 AE2 AE1 AD3

51.1 Ohm for Northwood, 61.9 Ohm for Prescott

AD2

AF4

AMP_3-1565030-1_Prescott

1

+VCCVID C932 0.1U_0402_10V6K

B

+VCC_CORE +3VS R546 @54.9_0603_1% ITP_TDO 1 2

V ID0 V ID1 V ID2 V ID3 V ID4 V ID5

2

R_ER541 680_0603_5% 1 2 H_ VID_PWRGD

RE Pop: Prescott Depop: Northwood+VCCVID

B

R545 4.7K_0402_5%

+3VALW 14 H_ VID_PWRGD 1 D Q45 3 7 S 2N7002 1N_SOT23

R547 @54.9_0603_1% ITP_DBRESET# 1 2

VID_PWRGD

1 U32A

P

If CPU is P4 , Change the resistor R 546 va lue to 75_0603_1%

I G

O

2

2 G

SN74LVC14APWLE_TSSOP14

Close to the ITP

+3VS

1

2

R550 1K_0402_5% 2 1 R552 1

R993 4.7K_0402_5% CPU_STP# ITP_TMS 1 +VCC_CORE Q95 MMBT3904_SOT23 3 1

GTL Reference VoltageLayout note :1. +CPU_GTLREF Trace wide 12mils(min),Space 15mils 2. Place R_A and R_B near CPU. 3. Place decoupling cap 220PF near CPU.R553 100_0402_1% 2 +CPU_GTLREF VID5 VID4 VID3 VID2 VID1 VID0 +3VS V ID5 V ID4 V ID3 V ID2 V ID1 V ID0 RP94 R542 R543 1 1 5 6 7 8 2 2 4 3 2 1 1K_1206_8P4R_5%A

1K_0402_5% 1K_0402_5%

CPUCLK_STP#

1

R1125 2

1

1K_0402_5% ITP_TDI 2 2

2

A

2 R556

ITP_TCK 1 1K_0402_5%

3

12K_0402_5%

Q96 MMBT3904_SOT23

R_A

1

R558

2

C546 1U_0603_10V4Z

1

C547 220P_0402_25V8K

Close to the CPUR559 1K_0402_5% 1 2

R_B2

169_0402_1%

1

2

ITP_TRST# Title

Compal Electronics, Inc.Prescott Processor in uFCPGA478THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Between the CPU and ITPSize Date:

Document Number

LA-2411PT C, 07, 20041


5

4

3

2

5

4

3

2

1


Place 11 North of Socket(Stuff 6)+VCC_CORE

1 C131 22U_1206_16V4Z

1 C132 22U_1206_16V4Z

1 C133 22U_1206_16V4Z

1 C134 22U_1206_16V4Z

1 C135 22U_1206_16V4Z

1 C136 22U_1206_16V4Z

1 C137 22U_1206_16V4Z

1 C138 22U_1206_16V4Z

1 C139 22U_1206_16V4Z

1 C140 22U_1206_16V4Z

1 C141 22U_1206_16V4Z

2

2

2

2

2

2

2

2

2

2

2

D

D

Place 12 Inside Socket(Stuff all)+VCC_CORE

1 C142 22U_1206_16V4Z

1 C143 22U_1206_16V4Z

1 C144 22U_1206_16V4Z

1 C145 22U_1206_16V4Z

1 C146 22U_1206_16V4Z

1 C147 22U_1206_16V4Z

1 C148 22U_1206_16V4Z

1 C149 22U_1206_16V4Z

1 C150 22U_1206_16V4Z

1 C151 22U_1206_16V4Z

2

2

2

2

2

2

2

2

2

2

+VCC_CORE

1 C152 22U_1206_16V4Z

1 C153 22U_1206_16V4Z

2

2

C

C

Place 9 South of Socket(Unstuff all)+VCC_CORE

1 C154 22U_1206_16V4Z

1 C155 22U_1206_16V4Z

1 C156 22U_1206_16V4Z

1 C157 22U_1206_16V4Z

1 C158 22U_1206_16V4Z

1 C159 22U_1206_16V4Z

1 C160 22U_1206_16V4Z

1 C161 22U_1206_16V4Z

1 C162 22U_1206_16V4Z

2

2

2

2

2

2

2

2

2

B

B

SANYO OS-CON 820uF H:13*3 (C163,C164,C165)+VCC_CORE

SANYO OS-CON 820uF H:9*2 (C166,C167)

Place Inside Socket around the edge1 + C167 2 820U_E9_2_5V_M_R7 1 C168 0.22U_0603_10V7K 1 C169 0.22U_0603_10V7K 1 C170 0.22U_0603_10V7K 1 C171 0.22U_0603_10V7K 1 C172 0.22U_0603_10V7K 1 C173 0.22U_0603_10V7K +VCC_CORE

1 + C163 2 820U_E9_2_5V_M_R7

1 + C164 2 820U_E9_2_5V_M_R7

1 + C165 2 820U_E9_2_5V_M_R7

1 + C166 2 820U_E9_2_5V_M_R7

2

2

2

2

2

2

+VCC_CORE

1 + 2

C174 470U_D2_2.5VM

1 + 2

C175 470U_D2_2.5VM

1 + 2

C176 @470U_D2_2.5VM

1 + 2

C177 @470U_D2_2.5VM

1 + 2

C178 @470U_D2_2.5VM

+VCC_CORE

A

A

1 + 2

C179 470U_D2_2.5VM

1 + 2

C180 470U_D2_2.5VM

1 + 2

C181 470U_D2_2.5VM

1 + 2

C182 470U_D2_2.5VM

1 + 2

C183 @470U_D2_2.5VM


CPU DecouplingTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C, 07, 20041


5

4

3

2

1

Thermal Sensor ADM1032AR+3VALW H_THERMDA W= 15mil 2 C251 H_THERMDC H_THERMDA H_THERMDC


1

1 0.1U_0402_10V6K R283 U8 @10K_0402_5% C253 2200P_0402_25V7K 1 1 H_THERMDA H_THERMDC 2 3 4 VDD D+ DTHERM# SCLK SDATA ALERT# GND 8 7 6 5 EC_SMC_2 EC_SMD_2 D

D

2

2

ADM1032AR_SOP8

Address:1001_100X

+VCC_CORE

R286 2

1 300_0402_5%

C256 2

1 @1U_0603_10V6K

2

B C 1 MAINPWON

H_THERMTRIP#

H_THERMTRIP#

3

E

Q17 2SC2411K_SC59

C

C

FAN CONN.1+12VALW 8 U10A P EN_FAN1 2 EN_FAN1 1 3 2 +IN OUT -IN G 4 LM358A_SO8 1 R913 1 2 100_0402_5% 2 C840 1 2 B

+5VS

FAN CONN. 21SS355_SOD323 1 1 U10B C838 10U_0805_16V4Z EN_FAN2 2 2 FA N1 EN_FAN2 1 5 6 +IN OUT -IN 7 R914 1 2 100_0402_5% 2 C841 1 1 R918 2 8.2K_0402_5% 2 B FMMT619_SOT23 Q90 D67 2

+5VS

1 1 C FMMT619_SOT23 Q91 3 E FA N2 1 C266 10U_0805_10V4Z 2 1 D68 2

C

1

C839 10U_0805_16V4Z

R915 10K_0402_5%

3

E

LM358A_SO8

0.1U_0402_10V6K 1 D25

R916 10K_0402_5% C855 1 JP10 1 2 3 ACES_85205-0300 1000P_0402_16V7K

1SS355_SOD323 JP11 C856 1 2 3 ACES_85205-0300 1000P_0402_16V7K

0.1U_0402_10V6K D26 1N4148_SOD80 2

C265 10U_0805_10V4Z

1

1

1

1 R917

2 8.2K_0402_5%

1N4148_SOD80 2

2

2

2

2

+3VS

R919 1

2 10K_0402_5%

+3VS 1

R920 1

2 10K_0402_5%

FANSPEED1 C907 1000P_0402_16V7K

FANSPEED2 1 C908 1000P_0402_16V7KB

B

2

2

A

A


CPU Thermal Sensor&FAN CTRLTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C, 07, 20041


5

4

3

2

1


H_A#[3..31] H_REQ#[0..4] H_D#[ 0..63] U27APART 1 OF 6

H_A#[3..31] H_REQ#[0..4] H_D#[0..63]

D

H_ADSTB#0

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADSTB#0 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_ADSTB#1 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRD Y# H_DBSY# H_BR0# H_LOCK# H_RESET# H_RS#2 H_RS#1 H_RS#0 H_TRDY# H_HIT# H_HITM#

M28 P25 M25 N29 N30 M26 N28 P29 P26 R29 P30 P28 N26 N27 M29 N25 R26 L28 L29 R27 U30 T30 R28 R25 U25 T28 V29 T26 U29 U26 V26 T25 V25 U27 U28 T29 L27 K25 H26 J27 L26 G27 F25 K26 A17 G25 G26 J25 F26 J26 H25 A9 AH5 AG5 C7 V28 W29 H23 J23 W28 Y29 Y28 B17

CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADSTB0# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_ADSTB1# CPU_ADS# CPU_BNR# CPU_BPRI# CPU_DEFER# CPU_DRDY# CPU_DBSY# CPU_BR0# CPU_LOCK#

CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_DBI0# CPU_DSTBN0# CPU_DSTBP0# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_DBI1# CPU_DSTBN1# CPU_DSTBP1# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_DBI2# CPU_DSTBN2# CPU_DSTBP2# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63# CPU_DBI3# CPU_DSTBN3# CPU_DSTBP3#

L30 K29 J29 H28 K28 K30 H29 J28 F28 H30 E30 D29 G28 E29 D30 F29 E28 G30 G29 B26 C30 A27 B29 C28 C29 B28 D28 D26 B27 C26 E25 E26 A26 B25 C25 A28 D27 E27 F24 D24 E23 E24 F23 C24 B24 A24 F21 A23 B23 C22 B22 C21 E21 D22 D23 E22 F22 B21 F20 A21 C20 E20 D20 A20 D19 C18 B20 E18 B19 D18 B18 C17 A18 F19 E19 F18

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DINV#0 H_DSTBN#0 H_DSTBP#0 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DINV#1 H_DSTBN#1 H_DSTBP#1 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DINV#2 H_DSTBN#2 H_DSTBP#2 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DINV#3 H_DSTBN#3 H_DSTBP#3

D

ADDR. GROUP 0

DATA GROUP 0

H_DINV#0 H_DSTBN#0 H_DSTBP#0

C

PENTIUM AGTL+ I/F IV

ADDR. GROUP 1

DATA GROUP 1

C

H_ADSTB#1 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR0# H_LOCK# H_RESET# H_RS#2 H_RS#1 H_RS#0 H_TRDY# H_HIT# H_HITM#


0.1U_0402_10V6K C974 2 1 --> 412_0402_1% R380 1

CPU_TRDY# CPU_HIT# CPU_HITM# CPU_RSET# SUS_STAT# SYSRESET# POWERGOOD CPU_COMP_N CPU_COMP_P

2 330_0402_5% NB_SUS_STAT# NB_RST# NB_PWRGD R381 1 2 24.9_0402_1% COMP_N

CONTROL

CPU_CPURSET# CPU_RS2# CPU_RS1# CPU_RS0#

DATA GROUP 2


L

Note: PLACE CLOSE TO RC300M, USE 10/10 WIDTH/SPACE+VCC_CORE

+VCC_CORE

B

CPVSS CPU_VREF MISC.

R383 100_0402_1% 1

NB_GTLREF 1 C362 1U_0603_10V6K 1 C363 220P_0402_25V8K 1 R385

THERMALDIODE_N THERMALDIODE_P TESTMODE

R384 169_0402_1% 2

1

DATA GROUP 3

PLACE CLOSE TO U27 Ball W28, USE 20/20 WIDTH/SPACE

+1.8VS

R382 1 2 49.9_0402_1% COMP_P L34 CPVDD 1 2 @1U_0603_10V6K HB-1M2012-121JT03_0805 1 2CPVSS C361 1 2 10U_0805_10V4Z C996

B

CPVDD

2

2

2


C363 CLOSE TO Ball W28

4.7K_0402_5% 216RC300M_BGA_718 2

+VCC_CORE 0.1U_0402_10V6K C364 22U_1206_16V4Z_V1 1 C365 1 C366 1 C367 1 0.1U_0402_10V6K C368 1 C369 1 0.1U_0402_10V6K C370 1 C371 1 1 C372 0.1U_0402_10V6KA

2

A

2 2 0.1U_0402_10V6K

2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K

2

2 2 0.1U_0402_10V6K


ATI RC300M-AGTL+THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

1


RP27 RP28 U27B DDRA_ADD0 DDRA_ADD1 DDRA_ADD2 DDRA_ADD3 DDRA_ADD4 DDRA_ADD5 DDRA_ADD6 DDRA_ADD7 DDRA_ADD8 DDRA_ADD9 DDRA_ADD10 DDRA_ADD11 DDRA_ADD12 DDRA_ADD13 DDRA_ADD14 DDRA_ADD15 DDRA_DM0 DDRA_DM1 DDRA_DM2 DDRA_DM3 DDRA_DM4 DDRA_DM5 DDRA_DM6 DDRA_DM7 DDRA_RAS# DDRA_CAS# DDRA_WE# DDRA_RAS# DDRA_CAS# DDRA_WE# DDRA_DQS0 DDRA_DQS1 DDRA_DQS2 DDRA_DQS3 DDRA_DQS4 DDRA_DQS5 DDRA_DQS6 DDRA_DQS7 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# AH19 AJ17 AK17 AH16 AK16 AF17 AE18 AF16 AE17 AE16 AJ20 AG15 AF15 AE23 AH20 AE25 AH7 AF10 AJ14 AF21 AH23 AK28 AD29 AB26 AF24 AF25 AE24 AJ8 AF9 AH13 AE21 AJ23 AJ27 AC28 AA25 AK10 AH10 AH18 AJ19 AG30 AG29 DDRA_CLK3 DDRA_CLK3# DDRA_CLK4 DDRA_CLK4# DDRA_CLK3 DDRA_CLK3# DDRA_CLK4 DDRA_CLK4# AK11 AJ11 AH17 AJ18 AF28 AG28 +1.8VS DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CS#0 DDRA_CS#1 DDRA_CS#2 DDRA_CS#3 DDRA_CKE_R0 DDRA_CKE_R1 DDRA_CKE_R2 DDRA_CKE_R3 DDRA_CS#0 DDRA_CS#1 DDRA_CS#2 DDRA_CS#3 MPVDD C375 1 2MPVSS 2.2U_0805_10V4Z 216RC300M_BGA_718 +2.5V +2.5V 1 DDRA_DQ25 DDRA_DQ29 R408 1K_0603_1% 2 DDR_VREF 1 C377 0.1U_0402_10V6K 2 R409 1K_0603_1% DDRA_DQS3 2 R412 DDRA_DM3 2 R415 +2.5V 0.1U_0402_10V6K C857 1 C858 1 C859 1 C860 1 1 C861 C378 2 2 @0.1U_0402_10V6K 2 2 @0.1U_0402_10V6K 2 @0.1U_0402_10V6K 150U_D2_6.3VM 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 2 2 0.1U_0402_10V6K 1 + C379 1 C380 1 C381 1 C382 1 C383 1 C384 1 C385 1 C386 1 C387 1 C388 1 C389 1 C390 1 1 C391 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6KA

DDRA_DQ8 DDRA_DQ12PART 2 OF 6

1 2

4 3

DDRA_SDQ8 DDRA_SDQ12

DDRA_DQ36 DDRA_DQ32

1 2

4 3


D

MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_DM0 MEM_DM1 MEM_DM2 MEM_DM3 MEM_DM4 MEM_DM5 MEM_DM6 MEM_DM7

MEM_RAS# MEM_CAS# MEM_WE# MEM_DQS0 MEM_DQS1 MEM_DQS2 MEM_DQS3 MEM_DQS4 MEM_DQS5 MEM_DQS6 MEM_DQS7 MEM_CK0 MEM_CK0# MEM_CK1 MEM_CK1# MEM_CK2 MEM_CK2# MEM_CK3 MEM_CK3# MEM_CK4 MEM_CK4# MEM_CK5 MEM_CK5# MEM_CKE0 MEM_CKE1 MEM_CKE2 MEM_CKE3 MEM_CS#0 MEM_CS#1 MEM_CS#2 MEM_CS#3 MPVDD

C

DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1#

AF13 AE13 AG14 AF14 AH26 AH27 AF26 AG27 AC18

MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15 MEM_DQ16 MEM_DQ17 MEM_DQ18 MEM_DQ19 MEM_DQ20 MEM_DQ21 MEM_DQ22 MEM_DQ23 MEM_DQ24 MEM_DQ25 MEM_DQ26 MEM_DQ27 MEM_DQ28 MEM_DQ29 MEM_DQ30 MEM_DQ31 MEM_DQ32 MEM_DQ33 MEM_DQ34 MEM_DQ35 MEM_DQ36 MEM_DQ37 MEM_DQ38 MEM_DQ39 MEM_DQ40 MEM_DQ41 MEM_DQ42 MEM_DQ43 MEM_DQ44 MEM_DQ45 MEM_DQ46 MEM_DQ47 MEM_DQ48 MEM_DQ49 MEM_DQ50 MEM_DQ51 MEM_DQ52 MEM_DQ53 MEM_DQ54 MEM_DQ55 MEM_DQ56 MEM_DQ57 MEM_DQ58 MEM_DQ59 MEM_DQ60 MEM_DQ61 MEM_DQ62 MEM_DQ63 MEM_CAP1 MEM_CAP2 MEM_COMP

AG6 AJ7 AJ9 AJ10 AJ6 AH6 AH8 AH9 AE7 AE8 AE12 AF12 AF7 AF8 AE11 AF11 AJ12 AH12 AH14 AH15 AH11 AJ13 AJ15 AJ16 AF18 AG20 AG21 AF22 AF19 AF20 AE22 AF23 AJ21 AJ22 AJ24 AK25 AH21 AH22 AH24 AJ25 AK26 AK27 AJ28 AH29 AH25 AJ26 AJ29 AH30 AF29 AE29 AB28 AA28 AE28 AD28 AC29 AB29 AC26 AB25 Y26 W26 AE26 AD26 AA26 Y27 AF6 AA29 AK19

DDRA_DQ0 DDRA_DQ1 DDRA_DQ2 DDRA_DQ3 DDRA_DQ4 DDRA_DQ5 DDRA_DQ6 DDRA_DQ7 DDRA_DQ8 DDRA_DQ9 DDRA_DQ10 DDRA_DQ11 DDRA_DQ12 DDRA_DQ13 DDRA_DQ14 DDRA_DQ15 DDRA_DQ16 DDRA_DQ17 DDRA_DQ18 DDRA_DQ19 DDRA_DQ20 DDRA_DQ21 DDRA_DQ22 DDRA_DQ23 DDRA_DQ24 DDRA_DQ25 DDRA_DQ26 DDRA_DQ27 DDRA_DQ28 DDRA_DQ29 DDRA_DQ30 DDRA_DQ31 DDRA_DQ32 DDRA_DQ33 DDRA_DQ34 DDRA_DQ35 DDRA_DQ36 DDRA_DQ37 DDRA_DQ38 DDRA_DQ39 DDRA_DQ40 DDRA_DQ41 DDRA_DQ42 DDRA_DQ43 DDRA_DQ44 DDRA_DQ45 DDRA_DQ46 DDRA_DQ47 DDRA_DQ48 DDRA_DQ49 DDRA_DQ50 DDRA_DQ51 DDRA_DQ52 DDRA_DQ53 DDRA_DQ54 DDRA_DQ55 DDRA_DQ56 DDRA_DQ57 DDRA_DQ58 DDRA_DQ59 DDRA_DQ60 DDRA_DQ61 DDRA_DQ62 DDRA_DQ63 C373 1 C374 1 2 2

DDRA_DQ9 DDRA_DQ13

1 2

0_0404_4P2R_5% RP31 DDRA_SDQ9 4 DDRA_SDQ13 3

DDRA_DQ37 DDRA_DQ33

1 2

0_0404_4P2R_5% RP30 DDRA_SDQ37 4 DDRA_SDQ33 3 0_0404_4P2R_5% RP33 DDRA_SDQ38 4 DDRA_SDQ34 3 0_0404_4P2R_5% RP36 DDRA_SDQ39 4 DDRA_SDQ35 3 0_0404_4P2R_5% DDRA_SDQS4 1 0_0402_5% DDRA_SDM4 1 0_0402_5% RP41 DDRA_SDQ44 DDRA_SDQ40

DDRA_DQ10 DDRA_DQ14

0_0404_4P2R_5% RP34 DDRA_SDQ10 1 4 DDRA_SDQ14 2 3 0_0404_4P2R_5% RP37 DDRA_SDQ11 1 4 DDRA_SDQ15 2 3 0_0404_4P2R_5% DDRA_SDQS1 1 0_0402_5% DDRA_SDM1 1 0_0402_5% RP40 DDRA_SDQ0 DDRA_SDQ4

DDRA_DQ38 DDRA_DQ34

1 2

D

DDRA_DQ11 DDRA_DQ15

DDRA_DQ39 DDRA_DQ35

1 2

DDRA_DQS1 2 R387 DDRA_DM1 2 R388 DDRA_DQ0 DDRA_DQ4


1 2

4 3

1 2

4 3

DDRA_DQ1 DDRA_DQ5

0_0404_4P2R_5% RP43 DDRA_SDQ1 1 4 DDRA_SDQ5 2 3 0_0404_4P2R_5% RP45 DDRA_SDQ3 1 4 DDRA_SDQ7 2 3 0_0404_4P2R_5% RP47 DDRA_SDQ2 4 DDRA_SDQ6 3 0_0404_4P2R_5% DDRA_SDQS0 1 0_0402_5% DDRA_SDM0 1 0_0402_5% RP49 4 3 DDRA_SDQ20 DDRA_SDQ16

DDRA_DQ45 DDRA_DQ41

0_0404_4P2R_5% RP44 DDRA_SDQ45 1 4 DDRA_SDQ41 2 3 0_0404_4P2R_5% RP46 DDRA_SDQ46 4 DDRA_SDQ42 3 0_0404_4P2R_5% RP48 DDRA_SDQ47 4 DDRA_SDQ43 3 0_0404_4P2R_5% DDRA_SDQS5 1 0_0402_5% DDRA_SDM5 1 0_0402_5% RP50 DDRA_SDQ60 DDRA_SDQ56

MEM I/F

DDRA_DQ3 DDRA_DQ7

DDRA_DQ46 DDRA_DQ42

1 2

DDRA_DQ2 DDRA_DQ6

1 2

DDRA_DQ47 DDRA_DQ43

1 2

C

DDRA_DQS0 2 R394 DDRA_DM0 2 R397 DDRA_DQ20 DDRA_DQ16 1 2


DDRA_DQ21 DDRA_DQ17

0_0404_4P2R_5% RP51 DDRA_SDQ21 1 4 DDRA_SDQ17 2 3 0_0404_4P2R_5% RP53

1 2

4 3

DDRA_DQ61 DDRA_DQ57

1 2

0_0404_4P2R_5% RP52 DDRA_SDQ61 4 DDRA_SDQ57 3 0_0404_4P2R_5% RP54 DDRA_SDQ62 4 DDRA_SDQ58 3 0_0404_4P2R_5% RP56 DDRA_SDQ63 4 DDRA_SDQ59 3 0_0404_4P2R_5% DDRA_SDQS7 1 0_0402_5% DDRA_SDM7 1 0_0402_5% RP58 DDRA_SDQ52 DDRA_SDQ48

DDRA_DQ18 DDRA_DQ22

1 2

4 3


DDRA_DQ62 DDRA_DQ58

1 2

Group 6 sweep Group 7DDRA_DQ19 DDRA_DQ23 0.47U_0603_16V7K 0.47U_0603_16V7K 2 49.9_0402_1% 1 2

0_0404_4P2R_5% RP55 DDRA_SDQ19 4 DDRA_SDQ23 3 0_0404_4P2R_5% DDRA_SDM2 1 0_0402_5% DDRA_SDQS2 1 0_0402_5% RP57 DDRA_SDQ24 DDRA_SDQ28

DDRA_DQ63 DDRA_DQ59

1 2

DDRA_SDM[0..7] DDRA_SDQ[0..63] DDRA_SDQS[0..7] DDRA_ADD[0..15]

DDRA_SDM[0..7] DDRA_SDQ[0..63] B

DDRA_DM2 2 R403 DDRA_DQS2 2 R406 DDRA_DQ24 DDRA_DQ28


B

L35 1 2 HB-1M2012-121JT03_0805

MEN_COMP R405 1

DDRA_SDQS[0..7] DDRA_ADD[0..15]

AD18

MPVSS

MEM_DDRVREF

AK20

1 2

4 3

1 2

4 3

0_0404_4P2R_5% RP59 DDRA_SDQ25 1 4 DDRA_SDQ29 2 3 0_0404_4P2R_5% RP61 DDRA_SDQ26 1 4 DDRA_SDQ30 2 3 0_0404_4P2R_5% RP63 DDRA_SDQ27 4 DDRA_SDQ31 3 0_0404_4P2R_5% DDRA_SDQS3 1 0_0402_5% DDRA_SDM3 1 0_0402_5%

DDRA_DQ53 DDRA_DQ49

0_0404_4P2R_5% RP60 DDRA_SDQ53 1 4 DDRA_SDQ49 2 3 0_0404_4P2R_5% RP62 DDRA_SDQ50 1 4 DDRA_SDQ54 2 3 0_0404_4P2R_5% RP64 DDRA_SDQ51 4 DDRA_SDQ55 3 0_0404_4P2R_5% DDRA_SDQS6 1 0_0402_5% DDRA_SDM6 1 0_0402_5%

Layout note Place these resistor closely DIMM0, all trace length Max=0.75"

C376 0.1U_0402_10V6K

2

1

DDRA_DQ26 DDRA_DQ30

DDRA_DQ50 DDRA_DQ54

DDR_VREF

DDRA_DQ27 DDRA_DQ31

1 2

DDRA_DQ51 DDRA_DQ55

1 2

1 2

DDRA_DQS6 2 R413 DDRA_DM6 2 R416

+2.5V

[email protected]_0402_10V6K

DDR_VREF trace width of 20mils and space 20mils(min)

A

0.1U_0402_10V6K


ATI RC300M-DDR I/FTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

1

A_AD[0..31] A_CBE#[0..3]

A_AD[0..31] A_CBE#[0..3] U27C A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31 A_CBE#0 A_CBE#1 A_CBE#2 A_CBE#3 AK5 AJ5 AJ4 AH4 AJ3 AJ2 AH2 AH1 AG2 AG1 AG3 AF3 AF1 AF2 AF4 AE3 AE4 AE5 AE6 AC2 AC4 AB3 AB2 AB5 AB6 AA2 AA4 AA5 AA6 Y3 Y5 Y6 AG4 AE2 AC3 AA3 AD5 AC6 AC5 AD2 W4 AD3 AD6 W5 W6 V5 V6 ALINK_AD0 ALINK_AD1 ALINK_AD2 ALINK_AD3 ALINK_AD4 ALINK_AD5 ALINK_AD6 ALINK_AD7 ALINK_AD8 ALINK_AD9 ALINK_AD10 ALINK_AD11 ALINK_AD12 ALINK_AD13 ALINK_AD14 ALINK_AD15 ALINK_AD16 ALINK_AD17 ALINK_AD18 ALINK_AD19 ALINK_AD20 ALINK_AD21 ALINK_AD22 ALINK_AD23 ALINK_AD24 ALINK_AD25 ALINK_AD26 ALINK_AD27 ALINK_AD28 ALINK_AD29 ALINK_AD30 ALINK_AD31 ALINK_CBE#0 ALINK_CBE#1 ALINK_CBE#2 ALINK_CBE#3 PCI_PAR/ALINK_NC PCI_FRAME#/ALINK_STROBE# PCI_IRDY#/ALINK_ACAT# PCI_TRDY#/ALINK_END# INTA# ALINK_DEVSEL# PCI_STOP#/ALINK_OFF# ALINK_SBREQ# ALINK_SBGNT# PCI_REQ#0/ALINK_NC PCI_GNT#0/ALINK_NCPART 3 OF 6


PCI BUS 1 / AGP Bus (GPIO , TMDS , ZVPort)

D

PCI Bus 0 / A-Link I/F

AGP_AD0/TMD2_HSYNC AGP_AD1/TMD2_VSYNC AGP_AD2/TMD2_D1 AGP_AD3/TMD2_D0 AGP_AD4/TMD2_D3 AGP_AD5/TMD2_D2 AGP_AD6/TMD2_D5 AGP_AD7/TMD2_D4 AGP_AD8/TMD2_D6 AGP_AD9/TMD2_D9 AGP_AD10/TMD2_D8 AGP_AD11/TMD2_D11 AGP_AD12/TMD2_D10 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16/TMD1_VSYNC AGP_AD17/TMD1_HSYNC AGP_AD18/TMD1_DE AGP_AD19/TMD1_D0 AGP_AD20/TMD1_D1 AGP_AD21/TMD1_D2 AGP_AD22/TMD1_D3 AGP_AD23/TMD1_D4 AGP_AD24/TMD1_D7 AGP_AD25/TMD1_D6 AGP_AD26/TMD1_D9 AGP_AD27/TMD1_D8 AGP_AD28/TMD1_D11 AGP_AD29/TMD1_D10 AGP_AD30/TMDS_HPD AGP_AD31 AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK# AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK# AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK

Y2 W3 W2 V3 V2 V1 U1 U3 T2 R2 P3 P2 N3 N2 M3 M2 L1 L2 K3 K2 J3 J2 J1 H3 F3 G2 F2 F1 E2 E1 D2 D1 E5 E6 T3 U2 G3 H2

AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1# AGP_SBSTB AGP_SBSTB# AGP_ADSTB0 AGP_ADSTB0# AGP_ADSTB1 AGP_ADSTB1#

AGPAND LVDS MUXED SIGNALS

AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA1 AGP_SBA0

R560 R561 R562 R563 R994 R995

1 1 1 1 1 1

2 NAPG@0_0402_5% 2 NAPG@0_0402_5% 2 NAPG@0_0402_5% 2 NAPG@0_0402_5% 2 NAPG@0_0402_5% 2 NAPG@0_0402_5%

ENBKL# ENAVDD AGP_STP# AGP_BUSY# DDC_DAT DDC_CLK DDC_DAT DDC_CLK D

Pop for internal AGP Depop for M11PAGP_AD[0..31] AGP_SBA[0..7] AGP_CBE#[0..3] AGP_ST[0..2] AGP_AD[0..31] AGP_SBA[0..7] AGP_CBE#[0..3] AGP_ST[0..2]

C

A_PAR A_STROBE# A_ACAT# A_END# R1005 1 PCI_PIRQA# A_DEVSEL# A_OFF# A_SBREQ# A_SBGNT# +3VS

A_PAR A_STROBE# A_ACAT# A_END# 2 0_0402_5% A_DEVSEL# A_OFF# A_SBREQ# A_SBGNT# 1 2 R570 8.2K_0402_5%

C

AGP2_CBE#0/AGP3_CBE0/TMD2_D7 AGP2_CBE#1/AGP3_CBE1/TMD2_DE AGP2_CBE#2/AGP3_CBE2 AGP2_CBE#3/AGP3_CBE3/TMD1_D5 AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA AGP_PAR AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA AGP2_PIPE#/AGP3_DBI_HI AGP2_NC/AGP3_DBI_LO AGP2_RBF#/AGP3_RBF AGP2_WBF#/AGP3_WBF AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0 AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1 AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON# AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP# AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY# AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN AGP_ST0 AGP_ST1 AGP_ST2

R3 M1 L3 H1 P5 R6 T6 T5 P6 R5 C1 D3 N6 N5 C3 C2 D4 E4 F6 F5 G6 G5 L6 M6 L5

AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI/PIPE# AGP_DBI_LO AGP_RBF# AGP_WBF# AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2 AGP_IRDY# AGP_TRDY# AGP_STOP# AGP_PAR AGP_FRAME# AGP_DEVSEL# AGP_DBI_HI/PIPE# AGP_DBI_LO AGP_RBF# AGP_WBF#

+3VS

2 +3VS 1 R568 2 R567 NAGP@10K_0402_5%

AGP_GNT# AGP_REQ# AGP8X_DET# VREF_8X_IN

AGP_GNT# AGP_REQ# AGP8X_DET# AGPREF_8X C550 1 2

K5 K6 M5 J6

AGP2_GNT#/AGP3_GNT AGP2_REQ#/AGP3_REQ AGP8X_DET# AGP_VREF/TMDS_VREF

R569 1 1 D 2 ENBKL NAGP@0_0402_5% Q2 3 S NAGP@2N7002_SOT23

NAPG@10K_0402_5% 1

?

2 G 1 3 ENBKL# NAGP@2N7002_SOT23 NB_PWRGD 2 G S D Q1

+1.5VS

+1.5VS R575 1

0.1U_0402_10V6K

Ra

2

AGP_COMP

J5

AGP_COMP

2

169_0402_1% R576

B

Rb1 2

B

324_0402_1% AGPREF_8X R577

+3VS

216RC300M_BGA_718

Pop for internal AGP

8X(M9+M10@)PLACE CLOSE TO CONNECTORR945 NAGP@47K_0402 AGP8X_DET# 1

4X(NAGP@)Depop 1K_0402_1% 1K_0402_1%

Depop for M11P

Rc1

100_0402_1%

Ra Rb Rc

169_0402_1% 324_0402_1% 100_0402_1%

2

ATI request+3VS +1.5VS 0.1U_0402_10V6K 1 C563 1 C564 1 0.1U_0402_10V6K C565 1 C566 1 0.1U_0402_10V6K C567 1 C568 1 0.1U_0402_10V6K 1 C569 C947 0.01U_0402_16V7Z 1 C948 1 C864 1 0.01U_0402_16V7Z C949 1 C950 1 0.01U_0402_16V7Z 0.01U_0402_16V7Z C935 1 C936 1 C933 1 C934 1 0.01U_0402_16V7Z 1 C951 0.1U_0402_10V6K 1 C556 1 C557 1 0.1U_0402_10V6K C558 1 C559 1 0.1U_0402_10V6K C560 1 1 C561 10U_0805_10V4Z C632 1 C562

+1.5VS 0.1U_0402_10V6K 1 C551 47U_B_6.3VM + 2 C553 1 C554 1 C555

2 0.1U_0402_10V6K

2

2 0.1U_0402_10V6K

2

2 0.1U_0402_10V6K

2

2 0.1U_0402_10V6K +1.5VS

2

2 0.1U_0402_10V6K

2

2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K

2

2 2 0.1U_0402_10V6K

2 2 0.1U_0402_10V6K

2 2 2 2 2 2 2 2 2 2 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z 0.01U_0402_16V7Z

+1.5VS 0.1U_0402_10V6K 1 C552 47U_B_6.3VM + 2 C570 1 C571 1 C572 1 1 C573 0.1U_0402_10V6K

0.1U_0402_10V6K C574 0.1U_0402_10V6K 1 C575 1 C576 1 C577 1

0.1U_0402_10V6K C578 1 C937 1

0.1U_0402_10V6K C938 1 C939 1

0.1U_0402_10V6K C940 1 C941 1

0.1U_0402_10V6K C942 1 C943 1

0.1U_0402_10V6K C944 1 C945 1

0.1U_0402_10V6K C946 1A

A

2 0.1U_0402_10V6K

2

2 2 0.1U_0402_10V6K

2

2 2 0.1U_0402_10V6K

2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K

2

2 2 0.1U_0402_10V6K

2 2 0.1U_0402_10V6K

2 2 0.1U_0402_10V6K

2 2 0.1U_0402_10V6K

L

Note: PLACE CLOSE TO U27 (NB RC300M)Title

Compal Electronics, Inc.ATI RC300M-AGP, ALINK BUSSize Date: Document Number

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

LA-2411PT C , 07, 20041


5

4

3

2

1


D

D

L58 +2.5VS 1 1 2 FBM-11-160808-121-T_0603

+3VS

1

C586 0.1U_0402_10V6K

L59 KC FBM-L11-201209-221LMAT_0805 2 U27D G9 H9 C587 0.1U_0402_10V6K A14 B13 +1.8VS_AVDDDI B14 C13 +1.8VS_AVDDQ C590 A15 B15 PLLVDD_18 H11 G11 VDDR3 VDDR3 AVDD_25 AVSSN AVDDDI_18 AVSSDI AVDDQ AVSSQ PLLVDD_18 PLLVSS

2

1

PART 4 OF 6

+1.8VS

KC FBM-L11-201209-221LMAT_0805 L60 1 2 1 C588 0.1U_0402_10V6K +1.8VS 2 1

2

TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXCLK_UN TXCLK_UP TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXCLK_LN TXCLK_LP LPVDD_18 LPVSS

D12 E12 F11 F12 D13 D14 E13 F13 E10 D10 B9 C9 D11 E11 B10 C10 A12 A11 B12 C12 B11 C11

TXB0-_NB TXB0+_NB TXB1-_NB TXB1+_NB TXB2-_NB TXB2+_NB TXBCLK-_NB TXBCLK+_NB TXA0-_NB TXA0+_NB TXA1-_NB TXA1+_NB TXA2-_NB TXA2+_NB TXACLK-_NB TXACLK+_NB +1.8VS_LPVDD C594 +1.8VS_LVDDR 1 KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K 1 2 L63 1 1 C595 C596 2 10U_0805_16V4Z

L61 1 2 KC FBM-L11-201209-221LMAT_08051 C589

+1.8VS

LVDS

C

0.1U_0402_10V6K 0.1U_0402_10V6K 2 2 L62 1 2 KC FBM-L11-201209-221LMAT_0805 1 1 1 C591 C592 C593 10U_0805_16V4Z 2 2 2 0.1U_0402_10V6K

+1.8VSC

0.1U_0402_10V6K RED_R GREEN_R BLUE_R HSYNC_R VSYNC_R F14 F15 E14 C8 D9 C14 A4 B4 A5 B5 B6 A6 RED GREEN BLUE DACHSYNC DACVSYNC RSET XTALIN XTALOUT HCLKIN HCLKIN# SYS_FBCLKOUT SYS_FBCLKOUT# ALINK_CLK

CRT

LVDDR_18 LVDDR_18 LVSSR LVSSR

2 2 0.1U_0402_10V6K

R584 1 R585 0_0402_5% 1 2

2 715 _0402_1% NB_RSET RC300M_X1 RC300M_X2

REFCLK1_NB CLK_AGP_66M 1

R587 R588 56_0402_5% 2 @10_0402_5%

CLK_NB_BCLK CLK_NB_BCLK#

SVID

CLK_NB_BCLK CLK_NB_BCLK#

C_R Y_G COMP_B DACSCL DACSDA

E15 C15 D15 D6 C6

CRMA_R LUMA_R COMPS_R DDCCLK_R DDCDATA_R D 1

+1.8VS KC FBM-L11-201209-221LMAT_0805 0.1U_0402_10V6K 1 2 L64 1 1 1 C598 C599 C600 2 0.1U_0402_10V6K 2 2 10U_0805_16V4Z

2

1

C601 @15P_0402_50V8J CLK_AGP_66M CLK_MEM_66M 1 R591 @10_0402_5% 2 C603 @15P_0402_50V8J CLK_MEM_66M CLK_AGP_66M CLK_MEM_66M

D8 B2 B3 A3 D7 B7 C5

Q97 @2N7002 1N_SOT23 3 CPUCLK_STP# S CPUCLK_STP#

AGPCLKOUT AGPCLKIN CPUSTOP# EXT_MEM_CLK SYSCLK USBCLK REF27 OSC 216RC300M_BGA_718 A8 B8 R590 R589 D5

2 G

PCI_RST# B

B

+3VS

R592

10K_0402_5%

CLK. GEN.

SYSCLK#

@0_0402_5% 1K_0402_5% +3VS

L LNote: PLACE CLOSE TO U27 (NB CHIP)CRMA_R LUMA_R COMPS_R R597 1 R598 1 R599 1 2 NAPG@0_0402_5%TV_CRMA 2 NAPG@0_0402_5%TV_LUMA 2 NAPG@0_0402_5%TV_COMPS TV_CRMA TV_LUMA TV_COMPS

Note: PLACE CLOSE TO U27 (NB CHIP)C604 RC300M_X1 1 1 2 R593 @1M_0402_1% RC300M_X2 2 @18P_0402_50V8K Y4 @14.31818MHZ_20P_6X1430004201 C605 @18P_0402_50V8K

L CRT_R CRT_G CRT_B

Note: PLACE CLOSE TO U6 (VGA CHIP)CRT_R R594 1 CRT_G R595 1 CRT_B R596 1 RP103 2 NAPG@0_0402_5%RED_R 2 NAPG@0_0402_5%GREEN_R 2 NAPG@0_0402_5%BLUE_R

A

CRT_HSYNC CRT_VSYNC

CRT_HSYNC 1 CRT_VSYNC 2

4 3

HSYNC_R VSYNC_R

A

NAGP@0_4P2R_0402_5% RP104 DDCCLK_R DDCDATA_R 4 3 1 2 3VDDCCL 3VDDCDA 3VDDCCL 3VDDCDA Title

Compal Electronics, Inc.ATI RC300M-VIDEO I/FTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NAGP@0_4P2R_0402_5%

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

5

4

3

2

1


+1.5VS U27EPART 5 OF 6

+2.5V U27F VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM VDDR_MEM AA23 AA27 AB30 AC10 AC12 AC13 AC15 AC17 AC19 AC21 AC23 AC24 AC25 AC27 AD10 AD12 AD13 AD15 AD17 AD19 AD21 AD23 AD24 AD25 AD27 AE10 AE14 AE15 AE19 AE20 AE30 AE9 AF27 AG11 AG12 AG17 AG18 AG23 AG24 AG26 AG8 AG9 AJ30 AK14 AK23 AK8 V23 W23 W24 W25 Y25 +1.5VS A29 AB23 AB24 AB27 AB4 AB8 AC1 AC11 AC14 AC16 AC20 AC30 AD11 AD14 AD16 AD20 AD4 AE27 AF30 AF5 AG10 AG13 AG16 AG19 AG22 AG25 AG7 AH28 AH3 AJ1 AK13 AK2 AK22 AK29 AK4 AK7 B1 B16 B30 C19 C23 C27 C4 D21 D25 E3 E8 E9 F27 F4 F8 G14 G15 G18 G20 H14 H15 H18 H20 H27 H4 H8 J7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSPART 6 OF 6

D

C

POWER

F10 F9 G12 H12 H13 M12 M13 M14 M17 M18 M19 N12 N13 N14 N17 N18 N19 P12 P13 P14 P17 P18 P19 U12 U13 U14 U17 U18 U19 V12 V13 V14 V17 V18 V19 W12 W13 W14 W17 W18 W19 +VCC_CORE C16 D16 D17 E16 E17 F16 F17 G17 G21 G23 G24 H16 H17 H19 H21 H24 K23 K24 M23 P23 P24 T23 T24 U23 U24 W30 +3VS AA1 AA7 AA8 AC7 AC8 AD1 AD7 AD8 AK3 W8

VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE

GND

VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU VDDR2_CPU

B

VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP VDDP_AGP

A2 G4 H5 H6 H7 J4 K8 L4 M7 M8 N4 P1 P7 P8 R4 T8 U4 U5 U6

AGP PWR

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

R23 R7 R8 T12 T13 T14 T15 T16 T17 T18 T19 T27 T4 U15 U16 U7 U8 V15 V16 V27 V4 V7 V8 W15 W16 W27 Y1 Y23 Y24 Y30 Y4 Y7 Y8 R19 R18 R17 R16 R15 R14 R13 R12 R1 P4 P27 P16 P15 N8 N24 N23 N16 N15 M4 M27 M16 M15 L8 L7 L25 L24 L23 K4 K27 J8

D

CORE PWR

MEM I/F PWR

C

CPU I/F PWR

216RC300M_BGA_718

M9-M10@0_0603_5% R418 1 R419 1 +1.8VS 2 +1.5VS

Pop for M11P Depop for internal AGP

B

VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK VDDL_ALINK

ALINK PWR

VDDP_AGP/VDDP33 VDDP_AGP/VDDP33 VDDP_AGP/VDDP33

E7 F7 G8

NAGP@0_0603_5% 2 +3VS

VDD_18 VDD_18 VDD_18 VDD_18

AC22 AC9 H10 H22

Pop for internal AGP Depop for M11P

216RC300M_BGA_718

+1.8VS 0.1U_0402_10V6K C579 10U_0805_10V4Z 1 C580 1 C581 1 C582 1 1 C583 0.1U_0402_10V6K

2

2 0.1U_0402_10V6K

2

2 0.1U_0402_10V6K

2

A

A


ATI RC300M-POWERTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

1

A_AD[0..31] A_CBE#[0..3]

A_AD[0..31] A_CBE#[0..3]


R420 1 A_AD31 R422

2 10K_0402_5%

+3VS BSEL1 +3VS BSEL0

A_AD[31..30] : FSB CLK SPEED

R421 A_AD18 R423

@4.7K_0402_5% 4.7K_0402_5%

4.7K_0402_5% 2 1 D85 RB751V_SOD323 R424 1 10K_0402_5% 2 4.7K_0402_5% 2 1 D86 RB751V_SOD323 2 10K_0402_5% @4.7K_0402_5% +3VS

DEFAULT: 0100: 100 MHZ 01: 133 MHZ 10: 200MHZ 11:166 MHZ

+3VS

A_AD18 : ENABLE PHASE CALIBRATION DEFAULT: 0 0: DISABLE 1:ENABLE

D

A_AD30

R425

D

R426 R427 1 A_AD29 R429

@4.7K_0402_5% 4.7K_0402_5%

A_AD29: STRAP CONFIGURATION

+3VS

A_AD25/A_AD17 : CPU VOLTAGE[1..0] DEFAULT: 0 00: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V

A_AD17

R428

DEFAULT:10: REDUCEDE SET 1: FULL SET

R430 1 A_AD28 R431

2 @10K_0402_5% 4.7K_0402_5%

+3VS

A_AD28: SPREAD SPECTRUM ENABLE

DEFAULT:00: DISABLE 1: ENABLE A_PAR A_PAR R463 R460 @4.7K_0402_5% 4.7K_0402_5% +3VS

PAR: EXTENDED DEBUG MODE DEFAULT : 1 0: DEBUG MODE 1: NORMAL

R434 1 A_AD27 R435

2 10K_0402_5% @4.7K_0402_5%

+3VS

A_AD27: FrcShortReset#

DEFAULT: 10: TEST MODE 1: NORMAL MODE

R438 1 A_AD26 R440

2 10K_0402_5% @4.7K_0402_5%

+3VS

A_AD26 : ENABLE IOQ

DEFAULT: 10: IOQ=1 1: IOQ=12C

C

R443 1 A_AD25 R444

2 10K_0402_5% @4.7K_0402_5%

+3VS

A_AD25/A_AD17 : CPU VOLTAGE[1..0]

DEFAULT: 1000: 1.05V 01: 1.35V 11: 1.75V 10: 1.45V

AD25=1 DESTOP CPU AD25=0 MOBILE CPU AD17--DON'T CARE

A_AD24

R448 1

2 10K_0402_5%

+3VS

A_AD24 : MOBILE CPU SELECT

DEFAULT: 10: BANIAS CPU 1: OTHER CPUR452 1 A_AD23 R454 2 10K_0402_5% @4.7K_0402_5%

+3VS

A_AD23 : CLOCK BYPASS DISABLE

DEFAULT: 10: TEST MODE 1: NORMAL+3VS

B

R1309 1 A_AD22 R457

2 10K_0402_5% @4.7K_0402_5%

B

A_AD22 : OSC PAD OUTPUT PCICLK

DEFAULT : 10:PCICLK OUT 1: OSC CLK OUTR461 1 A_AD21 R462 2 10K_0402_5% @4.7K_0402_5%

+3VS

A_AD21 : AUTO_CAL ENABLE

DEFAULT : 10: DISABLE 1: ENABLE

R464 A_AD20 R465

@4.7K_0402_5% 4.7K_0402_5%

+3VS

A_AD20 : INTERNAL CLK GEN ENABLE

DEFAULT : 00: DISABLE 1: ENABLE

R466 A_CBE#3 R467

@4.7K_0402_5% @4.7K_0402_5%

+3VS

A_CBE#3: NOT USED

A

A

R468 A_CBE#0 R469

@4.7K_0402_5% @4.7K_0402_5%

+3VS

A_CBE#0 :NO USED


ATI RC300M-SYSTEM STRAPTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

1

+2.5V +2.5V

+2.5V

+2.5V 1


JP24 DDRA_SDQ[0..63] DDRA_SDQS[0..7] DDRA_ADD[0..15] DDRA_SDM[0..7] DDRA_SDQ[0..63] DDRA_SDQS[0..7] D DRA_ADD[0..15] DDRA_SDM[0..7] DDRA_SDQS1 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQS0 DDRA_SDQ2 DDRA_SDQ3 DDRA_CLK0 DDRA_CLK0# DDRA_SDQ8 DDRA_SDQ9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID AMP_1565918-1 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDM1 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDM0 DDRA_SDQ6 DDRA_SDQ7

2

1

R472 C411 0.1U_0402_10V6K 1K_0603_1% D DRA_VREF 2 2 1

2

1

R473 C412 0.1U_0402_10V6K 1K_0603_1%

D

Group 0 sweep Group 1

D

L

DDRA_VREF trace width of 20mils and space 20mils(min)

Group 0 sweep Group 1DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDM3 DDRA_SDQ30 DDRA_SDQ31

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQS3 DDRA_SDQ26 DDRA_SDQ27

C

DDRA_CKE_R1

DDRA_CKE_R1 D DRA_ADD12 DD RA_ADD9 DD RA_ADD7 DD RA_ADD5 DD RA_ADD3 DD RA_ADD1 D DRA_ADD10 D DRA_ADD13 DD RA_WE# DDRA_CS#0 D DRA_ADD15 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQS5 DDRA_SDQ42 DDRA_SDQ43

DDRA_CKE_R0 D DRA_ADD11 DD RA_ADD8 DD RA_ADD6 DD RA_ADD4 DD RA_ADD2 DD RA_ADD0 D DRA_ADD14 DDRA_RAS# DDRA_CAS# DDRA_CS#1 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDM4 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDM5 DDRA_SDQ46 DDRA_SDQ47

DDRA_CKE_R0

C

DDRA_WE# DDRA_CS#0

DDRA_RAS# DDRA_CAS# DDRA_CS#1

DDRA_CLK1# DDRA_CLK1 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDM7 DDRA_SDQ62 DDRA_SDQ63 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQS7 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ48

B

B



DDRA_SDQ49 DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51

SMB_CK_DAT2 SMB_CK_CLK2 +3VS

DIMM0 REVERSE+2.5V

System Memory Decoupling capsC413 0.1U_0402_10V6K 1 C414 0.1U_0402_10V6K 1 C415 0.1U_0402_10V6K 1 C416 0.1U_0402_10V6K 1 C417 0.1U_0402_10V6K 1 C418 0.1U_0402_10V6K 1 C419 0.1U_0402_10V6K 1 C420 0.1U_0402_10V6K 1 C421 0.1U_0402_10V6K 1 C422 0.1U_0402_10V6K 1 C423 0.1U_0402_10V6K 1 C424 0.1U_0402_10V6K 1 C425 10U_0805_6.3V6M

1

2

2

2

2

2

2

2

2

2

2

2

2

2

+2.5VA

A

1

C426 0.1U_0402_10V6K

1

C427 0.1U_0402_10V6K

1

C428 0.1U_0402_10V6K

1

C429 0.1U_0402_10V6K

1

C430 0.1U_0402_10V6K

1

C431 0.1U_0402_10V6K

1

C432 0.1U_0402_10V6K

1

C433 0.1U_0402_10V6K

1

C434 0.1U_0402_10V6K

1

C435 0.1U_0402_10V6K

1

C436 0.1U_0402_10V6K

1

C437 0.1U_0402_10V6K

1

C438 10U_0805_6.3V6M

2

2

2

2

2

2

2

2

2

2

2

2

2

Compal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

DDR-SODIMM SLOT1Size Date: Document Number

LA-2411PT C, 07, 20041


5

4

3

2

1

DDRA_SDQ[0..63] DDRA_SDQS[0..7] DDRA_ADD[0..15] DDRA_SDM[0..7]

DDRA_SDQ[0..63] +2.5V DDRA_SDQS[0..7] D DRA_ADD[0..15] DDRA_SDM[0..7] DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQS1 DDRA_SDQ10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 JP23 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2# VDD CKE1 DU/A13 A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE# S0# DU VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDD_SPD VDD_ID AMP_1565917-1 VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 DU/RESET# VSS VSS VDD VDD CKE0 DU/BA2 A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# S1# DU VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDM1 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDM0 DDRA_SDQ6 DDRA_SDQ7 +2.5V

+2.5V

+2.5V 1


2

1

R470 C392 0.1U_0402_10V6K 1K_0603_1% D DRB_VREF 2 2 1

2


DDRA_SDQ11 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQS0 DDRA_SDQ2 DDRA_SDQ3

1

R471 C393 0.1U_0402_10V6K 1K_0603_1%D

D

L

DDRB_VREF trace width of 20mils and space 20mils(min)

DDRA_CLK3 DDRA_CLK3#

Group 0 sweep Group 1DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDM3 DDRA_SDQ30 DDRA_SDQ31 DDRA_CKE_R3 DDRA_CKE_R3 2 R1122 RP26 DDRA_SMA9 1 DDRA_SMA12 2 4 3 DD RA_ADD9 D DRA_ADD12 DD RA_ADD8 1 D DRA_ADD11 2 1 DDRA_CKE3 10_0402_5% DDRA_CKE_R2 DDRA_CKE_R2 2 R1121 RP29 4 3 DDRA_SMA8 DDRA_SMA11 1 DDRA_CKE2 10_0402_5%

DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQS3 DDRA_SDQ26 DDRA_SDQ27

DDRA_SMA5 DDRA_SMA7 DDRA_CKE2 DDRA_SMA11 DDRA_SMA8 DDRA_SMA6 DDRA_SMA4 DDRA_SMA2 DDRA_SMA0 DDRA_SMA14 DDRA_SRAS# DDRA_SCAS# DDRA_SCS#3 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDM4 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDM5 DDRA_SDQ46 DDRA_SDQ47 DDRA_CLK4# DDRA_CLK4 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDM7 DDRA_SDQ62 DDRA_SDQ63 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55 +3VS DDRA_SMA1 DDRA_SMA3

10_0404_4P2R_5% RP32 1 4 DD RA_ADD5 2 3 DD RA_ADD7 10_0404_4P2R_5% RP38 4 DD RA_ADD1 3 DD RA_ADD3 10_0404_4P2R_5% RP42 4 D DRA_ADD13 3 D DRA_ADD10 DDRA_RAS# DDRA_CAS# DDRA_CS#3

10_0404_4P2R_5% RP35 DD RA_ADD4 1 DDRA_SMA4 4 DD RA_ADD6 2 DDRA_SMA6 3C

C

DDRA_CKE3 DDRA_SMA12 DDRA_SMA9 DDRA_SMA7 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1 DDRA_SMA10 DDRA_SMA13 DDRA_SWE# DDRA_SCS#2 DDRA_SMA15 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQS5 DDRA_SDQ42 DDRA_SDQ43

1 2

DD RA_ADD0 1 DD RA_ADD2 2

10_0404_4P2R_5% RP39 DDRA_SMA0 4 DDRA_SMA2 3 10_0404_4P2R_5%

DDRA_SMA13 1 DDRA_SMA10 2

D DRA_ADD14 2 R390 DDRA_RAS# DDRA_CAS# DDRA_CS#3 2 R396 2 R393 2 R402

DDRA_SMA14 1 10_0402_5% 1 DDRA_SRAS# 10_0402_5% 1 DDRA_SCAS# 10_0402_5% 1 DDRA_SCS#3 10_0402_5%

DDRA_WE# DDRA_CS#2

10_0404_4P2R_5% DD RA_WE# 2 1 DDRA_SWE# R392 10_0402_5% DDRA_CS#2 2 1 DDRA_SCS#2 R401 10_0402_5% DDRA_SMA15 2 1 D DRA_ADD15 R391 10_0402_5%

DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQS7 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 SMB_CK_DAT2 SMB_CK_CLK2 +3VS

B

B


DIMM1 STANDARD

System Memory Decoupling caps+2.5V 150U_D2_6.3VM 1 C1118 + 2 22U_1206_10V4Z 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 0.1U_0402_10V6K 2 10U_0805_6.3V6M 2 10U_0805_6.3V6M 2

1

A

C394

1

C395

1

C396

1

C397

1

C398

1

C399

1

C400

1

C401

1

C402

1 C1119 + 2

150U_D2_6.3VM

A

+2.5V 0.1U_0402_10V6K 1 C410 2 2 150U_D2_6.3VM 2THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

1

C403 0.1U_0402_10V6K

1

C404 0.1U_0402_10V6K

1

C405 0.1U_0402_10V6K

1

C406 0.1U_0402_10V6K

1

C407 0.1U_0402_10V6K

1

C408 0.1U_0402_10V6K

1

C409

1 C1120 +

1 C1121 + 150U_D2_6.3VM Title

Compal Electronics, Inc.DDR-SODIMM SLOT2Size Date: Document Number

2

2

2

2

2

2

2

0.1U_0402_10V6K

LA-2411PT C, 07, 20041


5

4

5

4

3

2

1


DDR Termination resistors & Decoupling caps+1.25VS +1.25VS

RP65 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ12 DDRA_SDQ13 1 2 3 4 8 7 6 5 56 _0804_8P4R_5% RP68 8 7 6 5 56 _0804_8P4R_5% RP71 8 7 6 5 56 _0804_8P4R_5% RP74 8 7 6 5 56 _0804_8P4R_5% RP77 8 7 6 5 56 _0804_8P4R_5% RP80 8 7 6 5 56 _0804_8P4R_5% RP83 8 7 6 5 56 _0804_8P4R_5% RP86 8 7 6 5 56 _0804_8P4R_5% RP90 8 7 6 5 56 _0804_8P4R_5% 8 7 6 5

RP66 1 2 3 4 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ26 DDRA_SDQ27 8 7 6 5

RP67 1 2 3 4 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ36 DDRA_SDQ37D

D

DDRA_SDQS1 DDRA_SDQ10 DDRA_SDM1 DDRA_SDQ14

1 2 3 4

4 3

56 _0804_8P4R_5% RP69 DDRA_CKE_R0 1 DDRA_CKE_R1 2 33_0404_4P2R_5% PIR RP75 DD RA_ADD9 1 DD RA_ADD3 2 DD RA_ADD7 3 DD RA_ADD5 4

DDRA_CKE_R0 DDRA_CKE_R1

BOM & Layout 93.1.9R1180 2 @100_0402_5%

8 7 6 5

56 _0804_8P4R_5% RP70 DDRA_SDQS4 1 DDRA_SDQ34 2 DDRA_SDM4 3 DDRA_SDQ38 4 56 _0804_8P4R_5% RP73 DDRA_SDQ35 1 DDRA_SDQ39 2 DDRA_SDQ44 3 DDRA_SDQ40 4 56 _0804_8P4R_5% RP76 DDRA_SDQ46 1 DDRA_SDQ47 2 DDRA_SDQ42 3 DDRA_SDQ43 4 56 _0804_8P4R_5% RP79 DDRA_SDQ45 1 DDRA_SDM5 2 DDRA_SDQ41 3 DDRA_SDQS5 4 56 _0804_8P4R_5% RP82 DDRA_SDQ60 1 DDRA_SDQ61 2 DDRA_SDQ56 3 DDRA_SDQ57 4 56 _0804_8P4R_5% RP85 DDRA_SDM7 1 DDRA_SDQ62 2 DDRA_SDQS7 3 DDRA_SDQ58 4 56 _0804_8P4R_5% RP88 DDRA_SDQ63 1 DDRA_SDQ52 2 DDRA_SDQ59 3 DDRA_SDQ48 4 56 _0804_8P4R_5% RP91 DDRA_SDQ53 1 DDRA_SDM6 2 DDRA_SDQ49 3 DDRA_SDQS6 4 56 _0804_8P4R_5% RP93 DDRA_SDQ54 1 DDRA_SDQ55 2 DDRA_SDQ51 3 DDRA_SDQ50 4 56 _0804_8P4R_5%

+2.5V

DDRA_SDQ11 DDRA_SDQ15 DDRA_SDQ4 DDRA_SDQ0

1 2 3 4

8 7 6 5

1

1

DDRA_SDQ5 DDRA_SDM0 DDRA_SDQ1 DDRA_SDQS0

1 2 3 4

33_0804_8P4R_5% RP78 DD RA_ADD1 8 1 D DRA_ADD10 7 2 D DRA_ADD13 6 3 D DRA_ADD15 5 4 33_0804_8P4R_5% RP81 DD RA_ADD8 1 DD RA_ADD6 2 DD RA_ADD4 3 DD RA_ADD2 4 33_0804_8P4R_5% RP84 DD RA_ADD0 1 D DRA_ADD14 2 DDRA_RAS# 3 DDRA_CAS# 4 33_0804_8P4R_5% RP87 DD RA_WE# 1 D DRA_ADD11 2

8 7 6 5

C475 0.1U_0402_10V6K

1

C476 0.1U_0402_10V6K

1

C477 0.1U_0402_10V6K

1

C478 0.1U_0402_10V6K

1

C479 0.1U_0402_10V6K

1

C480 0.1U_0402_10V6K

1

C481 0.1U_0402_10V6K

1

C482 0.1U_0402_10V6K

2

2

2

2

2

2

2

2

+1.25VS +2.5V

8 7 6 5

1


1 2 3 4

8 7 6 5

C493 0.1U_0402_10V6K

1

C494 0.1U_0402_10V6K

1

C495 0.1U_0402_10V6K

1

C496 0.1U_0402_10V6K

1

C497 4.7U_0805_16V6K

8 7 6 5

2

2

2

2

2


1 2 3 4

8 7 6 5

+1.25VS

DDRA_RAS# DDRA_CAS#

8 7 6 5

C

DDRA_SDQS2 DDRA_SDQ18 DDRA_SDM2 DDRA_SDQ22

4 3

DDRA_WE# 8 7 6 5

1 2 3 4

33_0404_4P2R_5% RP89 DDRA_CS#0 4 1 DDRA_CS#3 3 2 R474 2 33_0404_4P2R_5% D DRA_ADD12 1

C

DDRA_CS#0 DDRA_CS#3


1 2 3 4

33_0402_5% RP72 DDRA_CKE_R3 4 1 DDRA_CKE_R2 3 2 33_0404_4P2R_5% RP92 DDRA_CS#1 4 1 DDRA_CS#2 3 2 33_0404_4P2R_5%

8 7 6 5 DDRA_CKE_R3 DDRA_CKE_R2 8 7 6 5

DDRA_SDQ29 1 DDRA_SDM3 2 DDRA_SDQ25 3 DDRA_SDQS3 4

DDRA_CS#1 DDRA_CS#2

8 7 6 5 DDRA_SDQ[0..63] DDRA_SDQS[0..7] D DRA_ADD[0..15] DDRA_SDM[0..7]

DDRA_SDQ[0..63] DDRA_SDQS[0..7] DDRA_ADD[0..15] DDRA_SDM[0..7]

B

+2.5V

B

1

C451 0.1U_0402_10V6K

1

C452 0.1U_0402_10V6K

1

C453 0.1U_0402_10V6K

1

C454 0.1U_0402_10V6K

1

C455 0.1U_0402_10V6K

1

C456 0.1U_0402_10V6K

1

C457 0.1U_0402_10V6K

1

C458 0.1U_0402_10V6K +1.25VS

2

2

2

2

2

2

2

2

+1.25VS

1

C459 0.1U_0402_10V6K

1

C460 0.1U_0402_10V6K

1

C461 0.1U_0402_10V6K

1

C462 0.1U_0402_10V6K

1

C463 0.1U_0402_10V6K

1

C464 0.1U_0402_10V6K

1

C465 0.1U_0402_10V6K

1

C466 0.1U_0402_10V6K

2

2

2

2

2

2

2

2

+1.25VS

1

C467 0.1U_0402_10V6K

1

C468 0.1U_0402_10V6K

1

C469 0.1U_0402_10V6K

1

C470 0.1U_0402_10V6K

1

C471 0.1U_0402_10V6K

1

C472 0.1U_0402_10V6K

1

C473 0.1U_0402_10V6K

1

C474 0.1U_0402_10V6K

2

2

2

2

2

2

2

2

+1.25VS

1

C483 0.1U_0402_10V6K

1

C484 0.1U_0402_10V6K

1

C485 0.1U_0402_10V6K

1

C486 0.1U_0402_10V6K

1

C487 0.1U_0402_10V6K

1

C488 0.1U_0402_10V6K

1

C489 4.7U_0805_16V6K

1

C490 4.7U_0805_16V6K

1 + C491

1 + C492A

A

2

2

2

2

2

2

2

2

2

@100U_D2_10M_R45 100U_D2_10M_R45 2

Compal Electronics, Inc.TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

DDR Termination ResistorsSize Date: Document Number

LA-2411PT C, 07, 20041


5

4

3

2

1

U6A AGP_AD[0..31] AGP_AD[0..31] AGP_SBA[0..7] AGP_CBE#[0..3] AGP_ST[0..2] AGP_AD0 AGP_AD1 AGP_AD2 AGP_AD3 AGP_AD4 AGP_AD5 AGP_AD6 AGP_AD7 AGP_AD8 AGP_AD9 AGP_AD10 AGP_AD11 AGP_AD12 AGP_AD13 AGP_AD14 AGP_AD15 AGP_AD16 AGP_AD17 AGP_AD18 AGP_AD19 AGP_AD20 AGP_AD21 AGP_AD22 AGP_AD23 AGP_AD24 AGP_AD25 AGP_AD26 AGP_AD27 AGP_AD28 AGP_AD29 AGP_AD30 AGP_AD31 AGP_CBE#0 AGP_CBE#1 AGP_CBE#2 AGP_CBE#3 CLK_AGP_EXT_66M NB_RST_R# AGP_REQ# AGP_GNT# AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# H29 H28 J29 J28 K29 K28 L29 L28 N28 P29 P28 R29 R28 T29 T28 U29 N25 R26 P25 R27 R25 T25 T26 U25 V27 W26 W25 Y26 Y25 AA26 AA25 AA27 N29 U28 P26 U26 AG30 AG28 AF28 AD26 M25 N26 V29 V28 W29 W28 AE26 AC26 AGP_STP# AH30 AGP_BUSY# AH29 AGP_RBF# AE29 AGP_ADSTB0 M28 AGP_ADSTB1 V25 AGP_ADSTB0# M29 AGP_ADSTB1# V26 AGP_SBA0 AGP_SBA1 AGP_SBA2 AGP_SBA3 AGP_SBA4 AGP_SBA5 AGP_SBA6 AGP_SBA7 AGP_ST0 AGP_ST1 AGP_ST2 AGP_SBSTB AGP_SBSTB# (25mil) R264 1 1 R1316 2 (15mil) 47_0603_1% @47_0603_1% 2 AGP_DBI_HI/PIPE# AGP_DBI_LO AD28 AD29 AC28 AC29 AA28 AA29 Y28 Y29 AF29 AD27 AE28 AB29 AB28 M26 M27 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE#0 C/BE#1 C/BE#2 C/BE#3 PCICLK RST# REQ# GNT# PAR STOP# DEVSEL# TRDY# IRDY# FRAME# INTA# WBF# STP_AGP# AGP_BUSY# RBF# AD_STBF_0 AD_STBF_1 AD_STBS_0 AD_STBS_1 SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 ST0 ST1 ST2 SB_STBF SB_STBS AGPREF AGPTEST DBI_HI DBI_LO AGP8X_DET# DMINUS DPLUS

+3VS

M10-P/(M9+X) (1/6)

AGP_SBA[0..7]

AGP_CBE#[0..3] AGP_ST[0..2]

ZV PORT / EXT TMDS / GPIO / ROM

D

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16

VREFG/(NC) ROMCS# ZV_LCDDATA0 ZV_LCDDATA1 ZV_LCDDATA2 ZV_LCDDATA3 ZV_LCDDATA4 ZV_LCDDATA5 ZV_LCDDATA6 ZV_LCDDATA7 ZV_LCDDATA8 ZV_LCDDATA9 ZV_LCDDATA10 ZV_LCDDATA11 ZV_LCDDATA12 ZV_LCDDATA13 ZV_LCDDATA14 ZV_LCDDATA15 ZV_LCDDATA16 ZV_LCDDATA17 ZV_LCDDATA18 ZV_LCDDATA19 ZV_LCDDATA20 ZV_LCDDATA21 ZV_LCDDATA22 ZV_LCDDATA23 ZV_LCDCNTL0 ZV_LCDCNTL1 ZV_LCDCNTL2 ZV_LCDCNTL3 DVOMODE

STRAP_G AJ5 STRAP_H AH5 STRAP_J AJ4 STRAP_K AK4 STRAP_D AH4 STRAP_E AF4 STRAP_F DRAM128M AJ3 +3VS STRAP_B AK3 STRAP_A AH3 STRAP_O AJ2 DRAM128M AH2 STRAP_L R955 AH1 @10K_0402_5% STRAP_M AG3 STRAP_N AG1 AG2 R235 1 AF3 2 @1K_0402_5% AF2 MCLK_SPREADR237 1 2 XTALIN_SS 0_0402_5% VREFG (25 mil) AG4 1 2 AF5 AH6 AJ6 AK6 AH7 AK7 AJ7 AH8 AJ8 AH9 AJ9 AK9 AH10 AE6 AG6 AF6 AE7 AF7 AE8 AG8 AF8 AE9 AF9 AG10 AF10 AJ10 AK10 AJ11 AH11 AE10 DVOMODE 1 R258 TXA0TXA0+ TXA1TXA1+ TXA2TXA2+ TXACLKTXACLK+ TXB0TXB0+ TXB1TXB1+ TXB2TXB2+ TXBCLKTXBCLK+ ENAVDD 1 R829 1 R830 2 2 0_0402_5% STRAP_R STRAP_S

R1149 @10K_0402_5% 2

AGP, DAC & LVDS INTERFACE+3VS


1

For 8Mx32 VGA DRAM onlyID_Disable GPIO8STRAP_A R232 R233 R236 R238 R240 R241 R242 R243 R244 R245 R246 R247 R248 R250 R252 R254 R255 R256 R1255 R257 R1256 R259 R260 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 M10@10K_0402_5% 1 @10K_0402_5% 1 M10@10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5% 1 10K_0402_5% 1 @10K_0402_5% 1 10K_0402_5% 1 @10K_0402_5% 1 @10K_0402_5%

+3VS

VGA_Disable GPIO7STRAP_BD

1 R234 M10@1K_0603_1% 2

GPIO4STRAP_D

GPIO5STRAP_E

1

GPIO6R239 M10@1K_0603_1% STRAP_F

GPIO0STRAP_G

2

GPIO1STRAP_H

GPIO2STRAP_J

C184 @10P_0402_50V8K 1 2 1 R249

GPIO3STRAP_K

2 @10_0402_5% D69 1

GPIO9STRAP_O

CLK_AGP_EXT_66M @RB751V_SOD323 2

GPIO11STRAP_L STRAP_T DDC_DAT DDC_CLK

NB_RST#

C

PCI/AGP

NB_RST# 1 2 R6 AGP_REQ# 0_0603_5% AGP_GNT# AGP_PAR AGP_STOP# AGP_DEVSEL# AGP_TRDY# AGP_IRDY# AGP_FRAME# PCI_PIRQA# AGP_WBF# AGP_STP# AGP_BUSY# AGP_RBF# AGP_ADSTB0 AGP_ADSTB1 AGP_ADSTB0# AGP_ADSTB1#

GPIO12STRAP_M

GPIO13STRAP_NC

Vedio Memory Config.STRAP_R

R

S0 1 0 1

Size4Mx32 4Mx32 8Mx32 8Mx32 M9+X

VendorSamsung Hynix Samsung Hynix M10-P+3VS STRAP_T STRAP_S

*

0 0 1 1

VREF_8X_IN

1

+3VS

1 R261 10K_0402_5%

C185 0.1U_0402_10V6K

2

(Closed to M26) AGP_SBSTB AGP_SBSTB#

TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP TXOUT_U0N TXOUT_U0P TXOUT_U1N TXOUT_U1P TXOUT_U2N TXOUT_U2P TXOUT_U3N TXOUT_U3P TXCLK_UN TXCLK_UP DIGON BLON/(BLON#) TX0M TX0P TX1M TX1P TX2M TX2P TXCM TXCP DDC2CLK DDC2DATA HPD1

1

AK16 AH16 AH17 AJ16 AH18 AJ17 AK19 AH19 AK18 AJ18 AG16 AF16 AG17 AF17 AF18 AE18 AH20 AG20 AF19 AG19 AE12 AG12 AJ13 AH14 AJ14 AH15 AJ15 AK15 AH13 AK13 AE13 AE14 AF12

AGP8X

LVDS

TXA0TXA0+ TXA1TXA1+ TXA2TXA2+

RaTXACLK- TXACLK+ TXB0- TXB0+ TXB1- TXB1+ TXB2- TXB2+ TXBCLK- TXBCLK+ ENAVDD M9@0_0402_5% ENBKL 2 G 3 S

180_0603_5% 261_0603_1% 150_0402_5% 150_0402_5%

Rb

Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out1.5V OSC out for M9+X 1.2V OSC out for M10-P1 2 261_0603_1% R263 150_0402_5% XTALIN

3.3V OSC out for W180OUT GND 3 2 FREQOUT 1 R262

2

2

M9@10K_0402_5% R1297 ENBKL D 2 Q30 M9@2N7002_SOT23 1

X1 4 1 VDD OE

Ra

B

+1.5VS

If M10+P POP 47_0603_1% If M9+P POP 137_0603_1%

AGP_DBI_HI/PIPE# AB25 AGP_DBI_LO AB26 AC25 AE11 AF11

ENBKL 2 M10@0_0402_5%

R265 1 2 M9+M10@0_0402_5%

AGP8X_DET# Low: AGP8X_DET# AGP3.0

For VGA DDR

spread sprum1 0.1U_0402_10V6K 1 1 C188 C189 L13 1 C190 1 2 2.2U_0603_6.3V4Z C191 FCM2012C-800_0805

2

27MHZ_15P C186 0.1U_0402_10V6K

C187B

1

Rb

@15P_0402_50V8J

+3VS

TV_CRMA TV_LUMA TV_COMPS

SSC DAC2

AJ23 AJ22 AK22 AJ24 AK24 AG23 AG24

C_R Y_G COMP_B H2SYNC V2SYNC DDC3CLK DDC3DATA SSIN SSOUT

R267

100K_0402_5%

U7

VDD

Selection Table For W180AK27 AJ27 AJ26 AG25 AH25 AH26 AF25 AF24 AF26 B6 E8 AE25 AG29 1 R276 2 1K_0603_5%THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2

6

(15mil) R266

715_0603_1% TV_CRMA TV_LUMA TV_COMPS

AK21

R2SET

TMDS

THRM

2 2 0.1U_0402_10V6K

2 2 0.1U_0402_10V6K 22_0402_5% 2 2 R271 2 1

R G B HSYNC VSYNC RSET

CRT_R CRT_G CRT_B CRT_HSYNC CRT_VSYNC

CRT_R CRT_G CRT_B CRT_HSYNC CRT_VSYNC

SS% 0 1

Spread % Setting for Freq. Range Fin>Fout>Fin-1.25% Fin>Fout>Fin-3.75%

+3VS 2 R269 2 R270

FREQOUT

1

X1/CLK FS1

CLKOUT X2 GND SS%

5 R268 1 R1 1 2 4

XTALIN_SS @0_0402_5% +3VS 1 @10K_0402_5% XTALIN_SS 2 R2 @22_0402_5%

DAC1

R574

10K_0402_5%

SSOUT

2 R273 10K_0402_5% 1

R936

10K_0402_5%

SSIN

AK25 AJ25

DDC1DATA DDC1CLK AUXWIN TEST_MCLK/(NC) TEST_YCLK/(NC)

(15mil) AGP_RSET 1 2 R272 499_0402_1% 3VDDCDA 3VDDCDA 3VDDCCL 3VDDCCL 1 R274 2 10K_0402_5% +3VS

7 1 10K_0402_5% 8 1 10K_0402_5%

FS2

SS%

XTALIN XTALOUT

AJ29

CLK

A

XTALIN

AH28

2 R16

1 0_0402_5%

3

W180-01GT_SO8A

L

Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)

R275 1 AGP_SUS_STAT# R253 1

2 1K_0603_5% 2 SUSSTAT#

AH27 AG26

TESTEN SUS_STAT# SA002160E00(0301021300)

PLLTEST/(NC) RSTB_MSK/(NC)


0_0402_5% Size Date:

ATI M10-P & M9+X (AGP BUS)Document Number

LA-2411PT C , 07, 20041


5

4

5

4

3

2

1


D

NMDA[0..63] NMAA[0..13] NDQMA[0..7] NDQSA[0..7]

NMDA[0..63] NMAA[0..13] NDQMA[0..7] NDQSA[0..7]

MEMORY INTERFACE A

D

U6B NMDA0 NMDA1 NMDA2 NMDA3 NMDA4 NMDA5 NMDA6 NMDA7 NMDA8 NMDA9 NMDA10 NMDA11 NMDA12 NMDA13 NMDA14 NMDA15 NMDA16 NMDA17 NMDA18 NMDA19 NMDA20 NMDA21 NMDA22 NMDA23 NMDA24 NMDA25 NMDA26 NMDA27 NMDA28 NMDA29 NMDA30 NMDA31 NMDA32 NMDA33 NMDA34 NMDA35 NMDA36 NMDA37 NMDA38 NMDA39 NMDA40 NMDA41 NMDA42 NMDA43 NMDA44 NMDA45 NMDA46 NMDA47 NMDA48 NMDA49 NMDA50 NMDA51 NMDA52 NMDA53 NMDA54 NMDA55 NMDA56 NMDA57 NMDA58 NMDA59 NMDA60 NMDA61 NMDA62 NMDA63 L25 L26 K25 K26 J26 H25 H26 G26 G30 D29 D28 E28 E29 G29 G28 F28 G25 F26 E26 F25 E24 F23 E23 D22 B29 C29 C25 C27 B28 B25 C26 B26 F17 E17 D16 F16 E15 F14 E14 F13 C17 B18 B17 B15 C13 B14 C14 C16 A13 A12 C12 B12 C10 C9 B9 B10 E13 E12 E10 F12 F11 E9 F9 F8 DQA0 DQA1 DQA2 DQA3 DQA4 DQA5 DQA6 DQA7 DQA8 DQA9 DQA10 DQA11 DQA12 DQA13 DQA14 DQA15 DQA16 DQA17 DQA18 DQA19 DQA20 DQA21 DQA22 DQA23 DQA24 DQA25 DQA26 DQA27 DQA28 DQA29 DQA30 DQA31 DQA32 DQA33 DQA34 DQA35 DQA36 DQA37 DQA38 DQA39 DQA40 DQA41 DQA42 DQA43 DQA44 DQA45 DQA46 DQA47 DQA48 DQA49 DQA50 DQA51 DQA52 DQA53 DQA54 DQA55 DQA56 DQA57 DQA58 DQA59 DQA60 DQA61 DQA62 DQA63

M10-P/(M9+X) AA0 (2/6) AA1AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12/(AA13) AA13/(AA12) AA14/(NC) DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7

C

E22 B22 B23 B24 C23 C22 F22 F21 C21 A24 C24 A25 E21 B20 C19 J25 F29 E25 A27 F15 C15 C11 E11 J27 F30 F24 B27 E16 B16 B11 F10

NMAA0 NMAA1 NMAA2 NMAA3 NMAA4 NMAA5 NMAA6 NMAA7 NMAA8 NMAA9 NMAA10 NMAA11 NMAA12 NMAA13 NDQMA0 NDQMA1 NDQMA2 NDQMA3 NDQMA4 NDQMA5 NDQMA6 NDQMA7 NDQSA0 NDQSA1 NDQSA2 NDQSA3 NDQSA4 NDQSA5 NDQSA6 NDQSA7

C

MEMORY INTERFACE A

+2.5VS 1 R475 1K_0402_1% NMRASA# NMCASA# NMWEA# NMCSA0# NMCSA1# NMCKEA NMCLKA0 NMCLKA0# NMCLKA1 NMCLKA1# NMRASA# NMCASA# NMWEA# NMCSA0# NMCSA1# NMCKEA NMCLKA0 NMCLKA0# NMCLKA1 NMCLKA1# 2 +2.5VS 1 MVREFD C498 0.1U_0402_10V6K 1 (25 mil) 1 R478 1K_0402_1% 2B

RASA# CASA# WEA# CSA0# CSA1# CKEA CLKA0 CLKA0# CLKA1 CLKA1# DIMA0 DIMA1 MVREFD MVREFS/(NC)

A19 E18 E19 E20 F20 B19 B21 C20 C18 A18 D30 B13 B7 B8 MVREFD

B

2

2 R486 M10@1K_0402_1% 1 R487 M10@1K_0402_1% 2

MVREFS C503 MVREFS [email protected]_0402_16V4Z 2 1

(25 mil)

SA002160E00(0301021300)

Poped for M10-P Depoped for M9+X

A

A


ATI M10-P/M9+X DDR-ATHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Document Number

LA-2411PT C , 07, 20041


5

4

3

2

1


D

D

MEMORY INTERFACE B NMDB[0..63] NMAB[0..13] NDQMB[0..7] NDQSB[0..7] NMDB[0..63] NMAB[0..13] NDQMB[0..7] NDQSB[0..7]

U6C NMDB0 NMDB1 NMDB2 NMDB3 NMDB4 NMDB5 NMDB6 NMDB7 NMDB8 NMDB9 NMDB10 NMDB11 NMDB12 NMDB13 NMDB14 NMDB15 NMDB16 NMDB17 NMDB18 NMDB19 NMDB20 NMDB21 NMDB22 NMDB23 NMDB24 NMDB25 NMDB26 NMDB27 NMDB28 NMDB29 NMDB30 NMDB31 NMDB32 NMDB33 NMDB34 NMDB35 NMDB36 NMDB37 NMDB38 NMDB39 NMDB40 NMDB41 NMDB42 NMDB43 NMDB44 NMDB45 NMDB46 NMDB47 NMDB48 NMDB49 NMDB50 NMDB51 NMDB52 NMDB53 NMDB54 NMDB55 NMDB56 NMDB57 NMDB58 NMDB59 NMDB60 NMDB61 NMDB62 NMDB63 D7 F7 E7 G6 G5 F5 E5 C4 B5 C5 A4 B4 C2 D3 D1 D2 G4 H6 H5 J6 K5 K4 L6 L5 G2 F3 H2 E2 F2 J3 F1 H3 U6 U5 U3 V6 W5 W4 Y6 Y5 U2 V2 V1 V3 W3 Y2 Y3 AA2 AA6 AA5 AB6 AB5 AD6 AD5 AE5 AE4 AB2 AB3 AC2 AC3 AD3 AE1 AE2 AE3 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQB9 DQB10 DQB11 DQB12 DQB13 DQB14 DQB15 DQB16 DQB17 DQB18 DQB19 DQB20 DQB21 DQB22 DQB23 DQB24 DQB25 DQB26 DQB27 DQB28 DQB29 DQB30 DQB31 DQB32 DQB33 DQB34 DQB35 DQB36 DQB37 DQB38 DQB39 DQB40 DQB41 DQB42 DQB43 DQB44 DQB45 DQB46 DQB47 DQB48 DQB49 DQB50 DQB51 DQB52 DQB53 DQB54 DQB55 DQB56 DQB57 DQB58 DQB59 DQB60 DQB61 DQB62 DQB63

M10-P/(M9+X) (3/6)

C

AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12/(AB13) AB13/(AB12) AB14/(NC) DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 RASB# CASB# WEB# CSB0# CSB1# CKEB CLKB0 CLKB0# CLKB1 CLKB1#

N5 M1 M3 L3 L2 M2 M5 P6 N3 K2 K3 J2 P5 P3 P2 E6 B2 J5 G3 W6 W2 AC6 AD2 F6 B3 K6 G1 V5 W1 AC5 AD1 R2 T5 T6 R5 R6 R3 N1 N2 T2 T3

NMAB0 NMAB1 NMAB2 NMAB3 NMAB4 NMAB5 NMAB6 NMAB7 NMAB8 NMAB9 NMAB10 NMAB11 NMAB12 NMAB13 NDQMB0 NDQMB1 NDQMB2 NDQMB3 NDQMB4 NDQMB5 NDQMB6 NDQMB7 NDQSB0 NDQSB1 NDQSB2 NDQSB3 NDQSB4 NDQSB5 NDQSB6 NDQSB7 NMRASB# NMCASB# NMWEB# NMCSB0# NMCSB1# NMCKEB NMCLKB0 NMCLKB0# NMCLKB1 NMCLKB1# NMRASB# NMCASB# NMWEB# NMCSB0# NMCSB1# NMCKEB NMCLKB0 NMCLKB0# NMCLKB1 NMCLKB1# +1.8VS

C

B

MEMORY INTERFACE B

B

MEMVMODE0 MEMVMODE1 DIMB0 DIMB1 MEMTEST

C6 C7 E3 AA3 C8

R509 1 R510 1

2 4.7K_0402_5% 2 4.7K_0402_5%

R511 1

2 47_0603_1% (15mil)

SA002160E00(0301021300)

A

A


ATI M10-P/M9+X DDR-BTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2

Size Date:

Documen

Documents

acer1670