Achieving End-to-End QoS - MemCon 2016 · Achieving End-to-End QoS Poonacha Kongetira ([email protected]) MemCon 2014 October 15 th, 2014

Achieving E nd- to- E nd QoS Poonacha K ongetira ([email protected])

MemCon 2014 October 15th, 2014

Poonacha Kongetira, MemCon 2014 | © Copyr ight 2014 NetSpeed Systems | 2

AGE NDA

Problem Statement

NetSpeed Platfor m Over view

QoS Pr imer

Achieving E nd- to- end QoS

E xample: B uilding R apid Vir tual SoC Platfor ms

Summar y


AGE NDA

Problem Statement


QoS Pr imer



Summar y


Problems Faced in Moder n Day SoCs Changing Abstraction Levels

CUSTOM

Sea of transistors

1980s

ASIC

Sea of Cells

1990s

S OC

Sea of B locks

2000s Now

NE XT- GE N SOCS

Sea of IPs

Time- to- Mar ket Pressure

Per for mance Analys is from Day # 1

Create Differentiated Platfor ms


Time- to- mar ket Pressure Decreas ing TTM even with exploding complexity

Sophisticated Functionality Increas ing Design Complexity

Source: Qualcomm Snapdragon SoC

190

165

65 nm

38

90 nm

16

+135%

28 nm

81

+113%

14 nm (E st)

22 nm (E st)

E ver Increas ing Number of IP B locks in an SoC

Source: IB S report, 2012


Creating Differentiated Platfor ms Core Architecture and Der ivative Products

CPU: 32, 64, DUAL, QUAD, OCTA ?

MIPI SPI I2C

LPDDR3

NAN

D

GPU

L3 CACHE

VIDEO DECODER

DSP

DISP

LAY

AUD

PCIe I2C

SATA

USB HDMI

CPU CPU

VIDEO ENCODER

1 2 3 4

6 7 8

9 10

11 12 13

14 15 16 17

19 20 21

22 23 24

ME MOR Y: DDR , LPDDR , 2, 3,4 ?

OTHE R IP B LOCK S: WHAT, WHO, HOW ?

IMPACT ON PPA, TTM ?

COHE R E NCY: WHAT L E VE L ?

Source: Google Project AR A


Per for mance Analys is Multiple Agents Contending for Memor y

Multiple tr affic profiles with sophisticated B andwidth, QoS requirements

SoC Interconnect

CPU Cluster

L1/L2 GPU Display USB

Memor y Controller

Video E ncode /Decode

SoC Interconnect

CPU Cluster


Memor y Controller


SoC Interconnect

CPU Cluster


Memor y Controller


SoC Interconnect

CPU Cluster


Memor y Controller


SoC Interconnect

CPU Cluster


Memor y Controller


Heavy Traffic

L ight Traffic

Medium Traffic


AGE NDA

Problem Statement


QoS Pr imer



Summar y


Next- Gen Platfor m to help B uild Faster , E fficient SoCs

Redef ining SoC Design

SoC Architecture Synthesis Platform


B R INGING THE P OWE R OF SYNTHE SIS TO SOC DE SIGN

HIGH P E R FOR MANCE, COR R E CT- B Y- CONSTR UCTION IP

S CALAB LE, COHE R E NT NOC P LATFOR M

NetSpeed Platfor m SoC Architecture Synthes is

P E R FOR MANCE, P OWE R, AR E A

SYSTE M- L E VE L USE CASE S

IP B LOCK S

NE TS PE E D P LATFOR M SOC AR CHITE CTUR E SYNTHE SIS

NE TS PE E D SYSTE MS IP

ON- CHIP INTE R CONNE CT

CACHE COHE R E NCY


NetSpeed Technology B reakthrough Innovation

Sophisticated Algor ithms

Scalable Cache Management

Networ king Concepts

50+ Patents filed

100+ Patentable Ideas


Design Flow

• Components , Connectivity • PPA, QoS R equirements • SoC Level Use Cases

Step 1: Specify

• R apid Architecture E xploration • R eal- time Customization • Power E stimation & Optimization

Step 2: Customize

• Customized SoC Interconnect IP

Synthesizable R TL

Ver ification IP

C++ Functional Models

PPA Statistics

IPXACT, Custom R eference Manual

Step 3: Generate


K ey Components of the NetSpeed Solution E ssential Toolkit for SoC Architecture

SoC Architecture Synthes is Platfor m

Per for mance Analys is

Sophisticated Power Management

E nd- to- end R obust QoS

Application- level Deadlock Avoidance

Multi- Layered Secur ity

F lexible, Scalable Coherency

Complete Phys ical Awareness


AGE NDA

Problem Statement


QoS Pr imer



Summar y


NetSpeed’s QoS Approach Automated, User - Controlled QoS

Automated, User - controlled QoS implementation – QoS implementation par t of des ign flow

Str ict pr ior ity & weighted bandwidth allocation schemes

NetSpeed F low

SoC R equirements

NocStudio Fully automated flow

Advanced algor ithms to achieve QoS specifications

Optimal allocation of Vir tual channels


NetSpeed NoC QoS Details

SoC Interconnect

CPU Cluster


Memor y Controller


QOS - 1 QOS - 2 QOS - 3

NoC QoS – 4 F ixed Pr ior ity levels ; higher pr ior ity wins – Weighted B W allocation within a pr ior ity level

• Weights are configurable at r un time

– QoS set up dur ing Noc Constr uction • QoS value for each transaction, applies to all hops • Amba QoS optionally mapped to Noc QoS

SoC Interconnect

CPU Cluster


Memor y Controller


SoC Interconnect

CPU Cluster


Memor y Controller


SoC Interconnect

CPU Cluster


Memor y Controller


add_traffic_b qos 1 profile video cpu/m.ar bw 0.1 peak 0.2 mem/s .ar /

add_traffic_b qos 1 profile video cpu/m.aww bw 0.1 peak 0.2 mem/s

add_traffic_b qos 2 profile video vid/m.ar bw 0.5 peak 1 mem/s .ar /s .r …

add_traffic_b qos 2 profile video vid/m.ar bw 0.5 peak 1 mem/s .aww…

add_traffic_b qos 2 profile video cse/m.ar bw 1 peak 2 mem/s .ar /s .r …

add_traffic_b qos 2 profile video cse/m.ar bw 1 peak 2 mem/s .aww…

add_traffic_b amba_qos { 0 1} qos 2 profile video disp/m.ar bw 2 peak 4

add_traffic_b amba_qos { 4 5} qos 3 profile video disp/m.ar bw 2 peak 4

…


Providing E nd- to- end QoS Match Gear R atios For Optimal R esults

NoC QoS K nobs 4 Fixed Pr ior ity levels • Higher pr ior ity wins

Weighted B W allocation within a pr ior ity level • Configurable at r un time

DDR QoS K nobs Por t Ar bitration • F ixed Pr ior ity among por ts • B W allocation by rate limiting

Command Ar bitration • Commands from a higher

pr ior ity executed fir st

Match Gear r atios for Optimal E nd to E nd QoS


AGE NDA

Problem Statement


QoS Pr imer



Summar y


Achieving E nd- to- end QoS Unifor m Weights


Achieving E nd- to- end QoS Different Weights


Achieving E nd- to- end QoS Memor y Conser vation


AGE NDA

Problem Statement


QoS Pr imer



Summar y


E xample Use Case: B uilding R apid Vir tual SoCs A Phased Approach

Phased approach in enabling vir tual chip

Phase 1: E xercis ing the memor y controller

Phase 2: E xercis ing controller IP , MC and NoC

Phase 3: Taking frames from CPU to memor y

Phase 4: Frames from CPU to Mem to on- screen display

Pha

se 1

MC + NoC + NS Transactors E xercise the mem controller

Pha

se 2

Controller IP , MC + NoC Take frames from agent to memor y

Pha

se 3

CPU, MC + NoC Take frames from CPU to memor y

Pha

se 4

CPU, MC, DSP, Display + NoC Frames from CPU to Mem to on- screen display


E xample Platfor m: Mobile SoC Subsystem

SoC Subsystem

64- B it Inter connect - NetSpeed NoC

High- speed IOs

SR AM0 AR M CPU Subsystem

A9 CPU R TL

CSI2 DSI

SR AM Controller

APB B ridge

SR AM1

SR AM Controller

SoC IP

PIC Timer

B asic IOs

GPIO UAR T

PHY

LPDDR Controller

USB 2

R TL0 Shell

R TL1 Shell

CSI2 I2C

Cadence Palladium Platfor m

Testbench Interconnect

AR M Cortex M3 Testbench

CPU I2C

AVIP

UAR T AVIP

GPIO AVIP

Display Controller

R GB TB A

USB 2 AVIP

EVOS

I2C AVIP

DSI AVIP

CSI2 AVIP

CSI2 AVIP

C Tests

EVOS

RST

CLK

UART TBA

UART TBA

Bare-metal SW test environment with pre-built basic IP integration tests

Automatically generated Accelerated Embedded

Testbench

Supports SoC integration tests to use cases and peripheral modeling


AGE NDA

Problem Statement


QoS Pr imer



Summar y


Summar y


Problems Faced in Modern Day SoCsChanging Abstraction Levels

CUSTOM

Sea of transistors

1980s

ASIC

Sea of Cel ls

1990s

SOC

Sea of Blocks

2000s Now

NEXT-GENSOCS

Sea of IPs

Time-to-Market Pressure

Performance Analysis from Day #1

Create Differentiated Platforms


BRINGING THE POWER OF SYNTHESISTO SOC DESIGN

HIGH PERFORMANCE, CORRECT-BY-CONSTRUCTION IP

SCALABLE, COHERENTNOC PLATFORM

NetSpeed PlatformSoC Architecture Synthesis

PERFORMANCE, POWER, AREA

SYSTEM-LEVELUSE CASES

IPBLOCKS

NETSPEED PLATFORMSOC ARCHITECTURE SYNTHESIS

NETSPEED SYSTEMS IP

ON-CHIPINTERCONNECT

CACHECOHERENCY


Achieving End-to-end QoSMemory Conservation

Documents

Achieving End-to-End QoS - MemCon 2016 · Achieving End-to-End QoS Poonacha Kongetira ([email protected]) MemCon 2014 October 15 th, 2014