Achieving System Certification with DSP, Power ... · ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, ... Glenn Beck Segment Marketing June

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,

ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,

Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of

Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,

CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and

Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

.

Glenn Beck

Segment Marketing

June 2012

Mark Griglock

VP of Engineering – Green Hills

TM 2

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,

mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All

other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

• Challenges in 21st Aerospace and Defense

• Freescale

Freescale Portfolio for A&D

Power Architecture Roadmap

• What’s new?

• T-series features

• E6500 Core/power management

• Altivec

• Trust Architecture

− Its more than a product.

• Green Hills – the path to certification

3 TM






• Dramatic increase networking traffic:

voice, data and video in all systems.

• Unmanned Vehicles demanding higher

control and signal processing in more

stringent SWaP environments.

• Secure systems are becoming as

important as the performance

requirements of the mission.

• Certification of SOC multicore devices in

commercial and defense applications.

4 TM






Inc

rea

sin

g P

erf

orm

an

ce

Power Sensitive

Applications

5W

Value Priced

for Power/Performance

Applications

10W

Performance at

Reasonable Power

15 W

High-Performance

Control and Data

Plane Processing

PowerQUICC I

PowerQUICC II

PowerQUICC II Pro

PowerQUICC III

e600 +Soc

De

cre

as

ing

Po

we

r

QorIQ – P2 P2020/P2010

P2040/P2041

QorIQ – P3 P3041

QorIQ – P4 P4080

P4040

QorIQ – P5

P5040 P5020

P5010

Up to 6 cores

Up to 6 MB of L2 cache

High-Performance

Control Plane

Processing

QorIQ – P1 P1010/P1014

P1020/P1011/P1024/P1015

P1021/P1012/P1025/P1016

P1022/P1013

P1023/P1017

AltiVec technology

AltiVec technology

AltiVec technology

AMP – T5

AMP – T4

T4240

AMP – T3

AMP – T2

AMP – T1

NEW

Increasing Performance

Up to 12 cores

Up to 6 MB of L2 cache

5 TM






16-Lane 10 GHz SerDes

64-bit

DDR2/3

Memory

Controller

CoreNet Coherency Fabric

PAMU PAMU PAMU

Peripheral Access

Mgmt Unit

Security Fuse

Processor

Security Monitor

2x USB 2.0 w/PHY

IFC

Power Management

SD/MMC

2x DUART

2x I2C

SPI, GPIO

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory Controller

64-bit

DDR3

Memory Controller

512KB

CoreNet

Platform Cache

512KB

CoreNet

Platform Cache

PAMU

Queue

Mgr.

Buffer

Mgr.

Pattern

Match

Engine

2.0

Security 5.0

64-bit

DDR2/3

Memory

Controller

64-bit

DDR3

Memory Controller

512KB

CoreNet

Platform Cache

RMAN

DCE

1.0

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G

Parse, Classify,

Distribute

1/ 10G

1/ 10G

1G

1G

1G

1G

FMan

1G

1G


HiGig DCB HiGig DCB

Pre

-fe

tch

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2MB Banked L2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power ™

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

2 MB Banked L2

Power Architecture®

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Power Architecture

e6500

D-Cache I-Cache

32 KB 32 KB

T1 T2

Watchpoint Cross

Trigger

Perf Monitor

CoreNet Trace

Aurora

Real Time Debug

Inte

rlaken L

A

SA

TA

2

.0

SA

TA

2.0

PC

Ie

PC

Ie

2xDMA

sR

IO

sR

IO

PC

Ie

PC

Ie

6 TM






High-Performance

− Industry’s highest CoreMark score

− 64-bit core built on Power Architecture®

technology

− Dual strong threads provide 1.7 times the performance of a single thread

Clustered L2 cache allowing strict allocation or full sharing

− 128b AltiVec SIMD unit

192 GFLOP aggregate

Large Memory Space

− 40-bit real address

− Terabyte physical address

Increase Productivity

− Core virtualization

Hypervisor

Logical to real address translation

Energy Efficiency

1.4 to 3 times more power efficient than the nearest competition

− Drowsy: core, cluster, AltiVec

CoreNet Interface 40-bit Address Bus 256-bit Rd & Wr Data Busses

CoreNet Double Data Processor Port

T T

32K

AltiVec

e6500

32K

PM

C T T

32K

AltiVec

e6500

32K

PM

C T T

32K

AltiVec

e6500

32K

PM

C T T

32K

AltiVec

e6500

32K

PM

C

2MB 16-way Shared L2 Cache, 4 Banks

*Source: www.coremark.org CoreMark / Watt

Dual 6 core (12

thread) server

processors

@ 2.266 GHz *

32 core

processor

@ 1.5 GHz*

12 core

(24 thread)

T4240

@ 1.8 GHz

1.4x 3x

Industry’s

Highest

CoreMark

Score

Core Performance: CoreMark™ / Watt Benchmark

7 TM






Tie

red

AP

M H

iera

rch

y

• Run, Nap

• Dynamic frequency scaling

• Drowsy cluster

• Dynamic clock gating

• SoC sleep with state retention

• Cascading power management

• Drowsy DDR/ self refresh


• Energy Efficient Ethernet (EEE)

So

C

Clu

ste

r C

ore

• Run, Doze, Nap

• Wait

• AltiVec drowsy

• Core drowsy (state retention)


Cascading Power Management

TMU

T4240

Die temp

sensor

Die temp

sensor

Die temp

sensor

Thermal Management Unit

T T

32K

AltiVec

e6500

32K P

MC

2048KB Banked L2

PM

C

PMC

DPAA

Cache

DD

R

CoreNet

QMAN FMAN

8 TM






>Assured Computing without comprising

performance

Protection Against

Theft Increase Security –

Lower Cost

QorIQ Assured

Computing

• Theft of Functionality – loss of control of the system’s functionality

• Theft of Data – where a data protection policy exists, loss of data to an unauthorized party

• Theft of Uniqueness – loss of product differentiation through reverse engineering, duplication, and unapproved inter-operability.

• Elimination of multiple devices – TPM, FPGA’s, custom devices

• Fewer exposed buses that are vulnerable to snooping

• COTs devices are lower cost than custom ASICs or high cost FPGAs

• Secure Boot – start from Trusted Code base or don’t start at all

• Domain Separation – Isolation of cores from each other

• Threat Detection – both physical and network attacks

• Secure Debug – debug and update software code in a trust environment remotely

SWAaP Assured

9 TM






AltiVec across the full T-series product –

More performance and Power choices

AltiVec on T4240 T4240 with AltiVec QorIQ AMP with

AltiVec

• 128-bit SIMD engine

• Executes on every clock cycle

• Improved load /store to ease bit alignment

• New instructions for video analytics

• Royalty Free library

• 12 AltiVec units

• Algorithms and data protected by trust architecture

• 192 GFLOPS of performance

(1/5 of a TFLOPS)

• Every e6500 core has an AltiVec unit

• Increase in performance with multithreading - no wasted cycles waiting on instructions

• Implemented across the QorIQ AMP family T1 – T5

10 TM






• Compilers − GCC, Green Hills® Multi®, Wind River®

Diab®

− AltiVec intrinsics for in-line optimizations

• Conversion tools − SSE to AltiVec header file

• Low-level libraries − Mentor Embedded Performance Library

for AltiVec Technologies

− Mercury SAL Library

• Open algorithmic libraries − OpenSAL, VSIPL, OpenCV, OpenGLes

• Multicore/multi-threading

libraries − VSIPL++, multicore SAL

www.freescale.com/AltiVec

Market Specific Applications

Video

RTOS Linux® OS

Wireless Enterprise

Market/Application Algorithmic Libraries

Custom

Video

Graphics

Enterprise

Printing

Wireless

Algorithmic Libraries

VSIPL++ OpenSAL SAL OpenCV Other Libs

Mentor Embedded Performance Library for AltiVec Technology

QorIQ AMP Series

To

ols

Com

pile

rs, C

onverte

rs, ID

Es

11 TM






• Close working relationship with ecosystem − OS and SBC Market Leaders

• Multicore for Avionics – MCFA Working Group

− Assist the industry with the certification of Multicore SOC processors in commercial and defense aviation

− Members include BAE Systems, BARCO, Boeing, EADS, ELBIT, GE Aviation, Hamilton Sundstrand, Honeywell, Raytheon, Rockwell Collins, Thales and Freescale Semiconductor. .

• Trust Architecture Users Group

− Assist the industry with the certification of Multicore SOC processors in commercial and defense aviation

− Membership is 18+ companies ranging from OEM’s to Ecosystem

• A&D data packet - what is it you need?

− SER Data

− Benchmarks – Control and Signal Processing

− Early access to new product information

12 TM






• Mercury Computer and its announcement of a

OpenVPX solution based on the latest QorIQ

T4240 AMP series processor built on Power

Architecture technology – 380 GFLOPS

• BAE announces adoption of Freescale QorIQ IP for

development of next generation of RAD Hard

processors for space.

• Extreme Engineering offers XPedite5205

ruggedize router with Power Architecture and

Cisco IOS

13 TM






TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,

ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,

Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of

Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,

CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,

Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and

Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service

names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.

.

15 TM






• Independent subsystems

• Shared resources

shared system resources

Core 1 Core 2

Sub-

System

Core 3 Core 4 Core 5 Core 6 Core 7 Core 8

Sub-

System Sub-System Sub-System

• Different Criticality Levels

• Load Balance

16 TM






• Independent subsystems

• Shared resources


Core 1 Core 2

Sub-System


Sub-System

• Different Criticality Levels

• Load Balance

17 TM






• Shutting down cores

− Always or periodically

• Lengthening Time Allocation

• Pure SMP

− Legacy difficult to port

• Single Level simultaneously

− Works well for Security

• Only simultaneously Partition I/O or Servers

18 TM






• Hardware Design Assurance

− MCFA Working Group

• Robust Space partitioning

− Data Integrity

− Confidentiality (Security)

• Robust Time partitioning

− Loss of Function

• Next Generation Scheduler

• Software Design Assurance

19 TM






2x DMA

PCIe


PCIe SRIO PCIe

CoreNet

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

SRIO

Watchpoint Cross Trigger

Perf Monitor

CoreNet Trace

Aurora

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

Coherency Fabric Peripheral

Access Mgmt Unit

eOpenPIC

Power Mgmt

2x USB 2.0/ULPI

SD/MMC

Clocks/Reset

2x DUART

4x I 2 C

SPI

GPIO

Pre Boot Loader

Security Monitor

Internal BootROM

Security 4.0

Pattern

Match

Engine

2.0

Queue

Mgr.

Buffer

Mgr.

eLBC

Test

Port/

SAP

CCSR


e500-mc Core

D-Cache I-Cache

128KB

Backside

L2 Cache 32KB 32KB

Frame Manager

Parse, Classify, Distribute

Buffer

1GE 1GE

1GE 1GE 10GE

Frame Manager


Buffer

1GE 1GE

1GE 1GE 10GE

Real Time Debug

External

Tamper

Detect

RapidIO

Message

Unit (RMU)

20 TM






2x DMA

PCIe


PCIe SRIO PCIe

CoreNet

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

SRIO


Perf Monitor

CoreNet Trace

Aurora

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

PAMU

Coherency Fabric PAMU PAMU PAMU PAMU

Peripheral

Access Mgmt Unit

eOpenPIC

Power Mgmt

2x USB 2.0/ULPI

SD/MMC

Clocks/Reset

2x DUART

4x I 2 C

SPI

GPIO

Pre Boot Loader

Security Monitor

Internal BootROM

Security 4.0

Pattern

Match

Engine

2.0

Queue

Mgr.

Buffer

Mgr.

eLBC

Test

Port/

SAP

CCSR


e500-mc Core

D-Cache I-Cache

128KB

Backside

L2 Cache 32KB 32KB

Frame Manager


Buffer

1GE 1GE

1GE 1GE 10GE

Frame Manager


Buffer

1GE 1GE

1GE 1GE 10GE

Real Time Debug

External

Tamper

Detect

HV MMU

RapidIO

Message

Unit (RMU)

21 TM






2x DMA

PCIe


PCIe SRIO PCIe

CoreNet

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

SRIO


Perf Monitor

CoreNet Trace

Aurora

1024KB

Frontside

L3 Cache

64-bit

DDR-2 / 3

Memory Controller

PAMU

Coherency Fabric PAMU PAMU PAMU PAMU

Peripheral

Access Mgmt Unit

eOpenPIC

Power Mgmt

2x USB 2.0/ULPI

SD/MMC

Clocks/Reset

2x DUART

4x I 2 C

SPI

GPIO

Pre Boot Loader

Security Monitor

Internal BootROM

Security 4.0

Pattern

Match

Engine

2.0

Queue

Mgr.

Buffer

Mgr.

eLBC

Test

Port/

SAP

CCSR

Frame Manager


Buffer

1GE 1GE

1GE 1GE 10GE

Frame Manager


Buffer

1GE 1GE

1GE 1GE 10GE

Real Time Debug

External

Tamper

Detect

RapidIO

Message

Unit (RMU)

Per-Core:

- Timers

- Cache

CSD allocation

Other*

DDR allocation

Other*


e500-mc Core

D-Cache I-Cache

128KB

Backside

L2 Cache 32KB 32KB

HV MMU

Way Allocation

22 TM






• Separate, independent monolith images

• Cores locked to specific subsystems

• Each subsystem is one of traditional models (AMP/SMP)

• No OS-enabled communication between subsystems


Core 1 Core 2

AMP

OS


AMP

AS

AMP

AS

SMP

AS

SMP

AS

AMP

OS

SMP OS SMP OS

SMP

AS

SMP

AS

23 TM







Core 1 Core 2 Core 3 Core 4 Core 5 Core 6 Core 7 Core 8

AMP

AS

AMP

AS

SMP

AS

SMP

AS

SMP

AS

SMP

AS

• Single OS Load Image

• Cores locked to subsystems

• OS resource sharing

• Blocking terms only exist when system architect “shares” something (e.g. Connection, Link)

UMP OS

24 TM







Core 1 Core 2 Core 3 Core 4 Core 1 Core 2 Core 3 Core 4

AMP

AS

AMP

AS

SMP

AS

SMP

AS

SMP

AS

SMP

AS

tuMP OS

Time Window

• Single OS Load Image

• Affinity Groups scheduled on a temporal basis

• Blocking terms only exist when system architect “shares” something (e.g. Connection, Link)

• Can be configured to support pure AMP/SMP scenarios

• Eliminates load-balancing constraints of UMP

tuMP OS

Time Window

25 TM






• INTEGRITY-178B compliant to DO-178B Level A

− First approval in 2002

− First commercial partitioning-supporting RTOS to obtain DO-178B compliance approval

• INTEGRITY-178B certified as complying to Separation Kernel Protection Profile to High-Robustness / EAL 6+

− First certificate issued in 2008

− First and only RTOS to be issued SKPP compliance certificate

• One operating system that satisfies both DO-178B Level A and High-Robustness / EAL 6+ requirements

− No program risk or compromise

26 TM






• INTEGRITY-178B Pedigree

− 60+ Certification Packages delivered to date

30+ Different Microprocessors

4 Major RTOS versions

• Broadly scrutinized

− FAA/EASA/NSA/customer audits and reviews

− Formally mathematically modeled and proven in support of SKPP certification

27 TM






• Changes isolated to Scheduler

− Legacy interfaces remain constant

− Minimal impact to application developer

• Reduce dependencies on novel hardware features

− Hypervisor only required for Low Criticality Guest OSes

TM 28






Tweeting? Please use hashtag

#FTF2012

Facebook.com/Freescale Tag yourself in photos

and upload your own!

Session materials will be posted @ www.freescale.com/FTF Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter

• Thank you

http://www.freescale.com/FTF

TM

Documents

Achieving System Certification with DSP, Power ... · ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, ... Glenn Beck Segment Marketing June