Agilent U1083A-005Acqiris SVM3500 High-Speed 6U

VME/VXS Digitizer

12-bit, 4 ch, 500 MS/s

12-bit, 2 ch, 1 GS/s

12-bit, 1 ch, 2 GS/s

2

Main Features

• 6U single slot VME/VXS (VITA 41) module

• Quad-channel 12-bit 500 MS/s ADC

• Dual 12-bit 1GS/s and single 12-bit 2GS/s

configuration possibilities

• External clock distributed by an in-house developed low

jitter chipset

• One Xilinx® Virtex-5 FPGA providing on board FIR for

interleaving mismatch correction

• Lookup table providing data correction

• Two Xilinx Virtex-4 FPGAs for real-time signal

processing and data flow control

• Two on-board DDR2 SDRAM banks, 32 Mwords, each

64-bit wide, for a total of 512 MB processing memory

• Tundra TSI148 VME bus interface, VME64x and

2eSST compliant

• VXS VITA 41.0 compliant, 8x 3.125 Gbps serial I/O links

on P0 connector

• Two front panel SFP slots for up to 3.125 Gbps fiber or

copper transceivers

• Auxiliary I/O mezzanine with multipurpose 12-bit

65 MS/s ADC, 12-bit 130 MS/s DAC, and 14 digital

front-panel I/O ports

• External trigger input

• High-speed digital I/O on P0 and P2 user-defined I/O

• Firmware Development Kit containing FPGA interface

cores, software, and reference design

• FPGA-based VXS and optical data link interfaces for

easier adaptation to different protocols

• Local FLASH memory to store multiple FPGA bitstreams

for complex, multimode applications

• Device drivers for Windows®, VxWorks®, and Linux®

3

The Agilent Acqiris SVM3500 is based on a modular VME/

VXS platform common to all U1083A family products and

features a quad-channel 12-bit 500 MS/s ADC coupled with

a processing engine capable of up to 300 GigaMAC/s.

The U1083A board family features two Xilinx Virtex-4

FPGAs, one SX55 targeted at digital signal processing, and

one FX100 for data flow control. The embedded 128 MB

FLASH memory allows the platform to be easily reconfig-

ured to perform user defined applications.

This architecture makes the new platform ideal for wide-

band, high-dynamic-range, demanding applications such

as electronic warfare (EW), radar digital receiver, telecom-

munications, and semiconductor testing, where high reso-

lution, high sample rate, high data-processing capabilities,

and high throughput are mandatory.

The SVM3500 module provides an analog mezzanine, based

on four single-channel, 12-bit, 500 MS/s state-of-the-art

Texas Instruments ADS5463 ADCs, and supports its full

capabilities and performance. To allow channel interleaving

and get dual-channel, 1 GS/s or single-channel, 2 GS/s

acquisition modes, the MCK, a clock distribution chipset,

is able to distribute four clock signals throughout the

mezzanine either in phase, in anti-phase, or in quadrature

with very low added jitter. Thanks to an externally acces-

sible Lookup Table (LUT) correcting static offset and gain

errors for each channel, and an implemented Finite Impulse

Response (FIR) filter providing frequency dependent ADCs

gain and delay mismatch correction, outstanding inter-

leaved analog performance can be reached from 10 MHz to

1 GHz input signal1.

The board supports eight 3.125 Gbps serial links on the VXS

backplane and two optical links on the front panel supporting

up to 3.125 Gbps, providing a substantial aggregate data band-

width of more than 3.5 GB/s. It also includes a fully compliant

VME64x interface supporting the 2eSST protocol.

A comprehensive Firmware Development Kit (FDK), soft-

ware drivers, and application examples make it easier to

develop your applications.

1) Requires the use of adequate external splitter. Please contact factory for more information.

High-Resolution, High-Sample-Rate Data Conversion with Real-Time Processing

Distributed clock mode Maximum sampling rate Number of channels Module configurationIn phase 500 MS/s 4 Standard

In anti-phase 1 GS/s 2 With external splitter

In quadrature 2 GS/s 1 With external splitter

Figure 1 : Block diagram showing the use of an external splitter in the case of the

quadrature mode, resulting in a single-channel, 12-bit, 2 GS/s digitizer.

Extended Functionality

4

Trigger

The external trigger circuitry includes a switchable 50 Ω/1 M Ω front end coupled with a very high-speed comparator chip and a 12-bit DAC for threshold adjustment.

Processing clock distribution

The COS201, a sophisticated proprietary clock distribution circuit, is used to synchronize all internal resources and allows fine control of processing and I/O synchronization.

Analog mezzanines

The SVM3500 features a four channel 12-bit, 500 MS/s ADC mezzanine based on four Texas Instruments ADS5463 ADCs with an AC-coupled analog front end.

Clock distribution

An external clock input provides direct access to the MCK, a proprietary clock distribution circuit with very low added jitter. The MCK is able to generate four clocks, either in phase (4 channels at 500 MHz), in anti-phase (equivalent to 2 channels at 1 GS/s), or in quadrature (equivalent to 1 channel at 2 GS/s)2.

Data correction fi lter

The mezzanine also includes a Finite Impulse Response (FIR) filter

implemented on a Xilinx Virtex-5 SX50T FPGA. This filter is used in interleaved mode (anti-phase or quadrature clock) to correct frequency-dependant phase and amplitude mismatches between ADCs.

JTAG

The SVM3500 features a JTAG connector that can be used for on board firmware debug using a ChipScope probe (requires option U1091A-CB1).

Auxiliary I/O mezzanine

The SVM3500 features an auxiliary I/O mezzanine to support control and command functions. It includes one 12-bit 65 MS/s ADC, one 12-bit 130 MS/s DAC, and 14 digital I/Os.

On-board processing FPGA

The SVM3500 offers on-board, high-performance, real-time data processing by means of two very large FPGAs, one Xilinx Virtex-4 SX55 and one Xilinx Virtex-4 FX100. The SX55 FPGA is capable of executing 512 multiplications/accumulations (18x18) at up to 450 MHz, leading to an impressive processing power of 230 GigaMAC/s, while offering more than 55,000 logic cells and up to 5 Mbits of on-chip RAM.

Optical data links

Two SFP front-panel optical transceivers provide for data transfer at rates of up to 3.125 Gbps per link. The link layer implemented by the provided firmware is based on Xilinx Aurora Protocol.

VME 2eSST interface The SVM3500 is fully VME64x and 2eSST compliant. Designed

to benefit from fast data interfaces, it can be integrated with

other state-of-the-art VME boards.

Fast data throughput with large memories The MAC200 memory and acquisition controller is a digital

CMOS integrated circuit. A high-speed data multiplexer/

demultiplexer with on-board memory, it is designed for the

capture and memorization of 10-bit or 20-bit digital data,

at speeds of up to 2 GS/s or the generation of 20-bit data

streams at up to 1.2 GS/s.

VXS VITA 41 interface The VXS VITA 41.0 standard gives the SVM3500 the very-

high-data-throughput capability needed in EW, Radar, or ATE

equipment. The eight serial links available on the P0 connector

support up to 3.125 Gbps each, for an aggregate throughput of

up to 2.5 GBytes/s. Protocols such as RapidIO, PCI-EXPRESS®,

Infiniband, or Gigabit Ethernet, as defined in the VITA 41

dot-standards, can be supported through off-the-shelf FPGA

IP cores.

On-board communication controller FPGA

The Xilinx Virtex-4 FX100 FPGA is capable of executing up to

160 multiplications/accumulation (18x18) at up to 450 MHz,

leading to an impressive processing power of 70 GigaMAC/s

while offering more than 94,000 logic cells and up to 6.7 Mbits

of on-chip RAM. Moreover, the FX100 includes two PPC cores

and four 10/100/1000 Ethernet MAC blocks. The on-board

FPGA-based Signal Processing Unit allows the platforms to be

easily reconfigured to perform user-defined, on-board, realtime

signal processing

Large memory

The Xilinx Virtex-4 FX100 interfaces to two banks of DDR2-533

SDRAM, 32 MWords, each 64-bit wide, for a total of 512 MB.

5

2) Please contact factory for more information.

Figure 2 : Agilent SVM3500 quad-channel digitizer.

6

The VME/VXS board family has been designed to optimize

both internal and external data throughput.

Associated with other members of the family, the SVM3500

allows the construction of complete systems with fewer

resources.

The SVM3500 digitizer’s analog mezzanine implements

four 12-bit, 500 MS/s Texas Instruments ADS5463 ADCs.

The presence of the MCK, distributing the external clock

throughout the mezzanine either in phase, in anti-phase, or

in quadrature with very low added jitter and the implemen-

tation of a dynamic data correction filter (FIR) in a Xilinx

Virtex-5 SX50T FPGA provide sensational performance.

Coupled with the use of an external splitter, they allow

channel interleaving to get a dual-channel, 12-bit, 1 GS/s

or a single-channel, 12-bit, 2 GS/s acquisition mode, while

maintaining outstanding analog operation.

Data-Flow-Optimized Architecture

High-Resolution, High-Sample-Rate Data Acquisition Mezzanine

Figure 3 : SVM3500 architecture.

Figure 4 : Analog mezzanine architecture.

COS201

FPGASX50T

Analog Mezzanine

PCI InterfaceFPGA + FLASH

MAC200

ProcessingFPGASX55

CommunicationFPGAFX100

MAC200

CLK

ADC12-bits

500 MS/s

ADC12-bits

500 MS/s

ADC12-bits

500 MS/s

ADC12-bits

500 MS/s

ExtTrig

MCK

Auxiliary I/O Std: (ADC/DAC/Digital)

Optical Data Links 2 x SFPStandard [LNK]: 3.125 Gbit/s

[L25 Option]: 2.5 Gbit/s

Data MuxFIR Correction

CLR

SC SC

A

B D D1

D2

AuxIO

Hsb

us

1 to

4

Hsb

us

1 to

4Y

C

C C C SerDes

DDR2 SDRAM32MW64-bit

DDR2 SDRAM32MW64-bit

SerDes

IO

A

B D

Y

C

TSI148

VME 2eSST VXS P0 P0/P2 I/O

In 4

In 3

In 2

In 1

Ext Clk

ADC12-bits

500 MS/s

Flash XilinxXCF32P

66 MHz

ADC12-bits

500 MS/s

ADC12-bits

500 MS/s

ADC12-bits

500 MS/s

AC-CoupledInput

DAC

DAC

DAC

MCKSX50TFPGA

DAC

AC-CoupledInput

AC-CoupledInput

AC-CoupledInput

AC-CoupledInput

Analog Mezzanine

D0

SelectMap

B0PORT

FE0_SPI

B1PORT

C0SCLK

FE1_SPI

D1

D2

D3

MCK

7

Figure 5 : Firmware development kit architecture.

Firmware development kit

The U1083A board family is available with an optional

Firmware Development Kit (FDK) to make application

development easier on the SX55 and FX100 FPGAs. The

FDK includes a set of cores to easily interface to the under-

lying hardware, a base design for each family member to

provide very simple, ready-to-use designs, and a test-bench

environment for design and simulation.

An embedded FLASH memory can store up to seven bit-

streams for each FPGA for complex, multimode

applications.

The SVM3500, is supplied with MicroDriver, a C standard

compliant software driver. It runs on standard operating

systems, as well as on Real-Time operating systems:

MicroDriver supports VxWorks (Pentium® and PowerPC),

Linux (Pentium and PowerPC), and Windows® (Pentium).

MicroDriver is provided as full source code and gives

direct access to the module registers, as well as main

components, including FLASH and DDR2 memories, FPGAs,

and back-plane and front-panel links. MicroDriver works in

conjunction with the PCI to VME bridge device driver of the

host to provide VME burst transfers (including 2eSST) and

interrupts.

MicroDriver has been specially designed for the U1083A

family products so that every single line of code is useful,

implying a very low footprint driver, that can even be

reduced further to include only the needed SVM3500

module functionalities.

Easy Custom Application Development

MicroDriver Software

SX55

Auxiliary I/OResources

D Port InterfaceA

User DefinedProcessing Block

Local Bus Interface

User Reg. Sys Reg.

Local Bus Interface

User Defined Communications Block

DDR2 SDRAMcontroller A

DigitalI/OUser Reg. Sys Reg.

WRBuffer

RDBuffer

DDR2 SDRAMcontroller A

WRBuffer

LinkController Aurora

Controller

RX

FIFO

MG

T

TX FIFO

RX

FIFO

MG

T

TX FIFO

Data

Link In

terface

RDBuffer

High S

peed Bus 1 to 4

High S

peed Bus 1 to 4

D Port InterfaceB

FX100

C BusC Bus

O B

us 1O

Bus 2

Optical Data Links

DD

R2 S

DR

AM

bank AD

DR

2 SD

RA

M bank B

VXSLinks

8

Agilent know-how in digitizer development combined with

extensive use of application specific technologies provides

high-fidelity measurement over the full input bandwidth.

Innovative design, careful circuit layout and custom ICs are

all used to optimize analog performance.

High-Fidelity Frequency-Related Measurements

Dynamic range in standard configuration

85

80

75

70

SFD

R [

dBc]

FIN

[MHz]

65

60

55

500 100 200 300 400 500 600 700 800 900 1000

Harmonic distortion in standard configuration

-50

-55

-60

-65

-70

-75

-80

-85

TH

D [

dBc]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Effective bits in standard configuration12

11

10

9

8

7

6

5

4

3

2

1

0

EN

OB

[LS

B]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Figure 6 : Typical SFDR for each channel at 500 MS/s SR and

-1 dBFS input signal as a function of frequency.

Figure 8 : Typical SNR for each channel at 500 MS/s SR and

-1 dBFS input signal as a function of frequency.

Figure 7 : Typical harmonic distortion for each channel at

500 MS/s SR and -1 dBFS input signal as a function of

frequency.

Figure 10 : Typical analog input bandwidth.

Figure 9 : Typical ENOB for each channel at 500 MS/s SR and

-1 dBFS input signal as a function of frequency.

Noise in standard configuration

70

65

60

55

50

SN

R [

dBc]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Frequency response2.00

1.00

0.00

-1.00

-2.00

-3.00

-4.00

-5.00

-6.00

-7.00

-8.00

-9.00

-10.00

Gai

n [

dB]

FIN

[MHz]

1 10 100 1000 10000

9

Figure 11 : Typical SFDR in interleaved mode at 2 GS/s SR and

-1 dBFS input signal as a function of frequency. The

action of the FIR is remarkable.

Figure 12 : Typical harmonic distortion in interleaved mode at

2 GS/s SR and -1 dBFS input signal as a function of

frequency.

Figure 13 : Typical SNR in interleaved mode at 2 GS/s SR and

-1 dBFS input signal as a function of frequency.

Figure 14 : Typical ENOB in interleaved mode at 2 GS/s SR and

-1 dBFS input signal as a function of frequency. The

action of the FIR is remarkable.

Dynamic range in interleaved configuration

75

70

65

60

55

50

45

40

SFD

R [

dBc]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Harmonic distortion in interleaved configuration

-50

-55

-60

-65

-70

-75

-80

-85

TH

D [

dBc]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Noise in interleaved configuration

70

65

60

55

50

SN

R [

dBc]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Effective bits in interleaved configuration

12

11

10

9

8

7

6

5

4

3

2

1

0

EN

OB

[LS

B]

FIN

[MHz]

0 100 200 300 400 500 600 700 800 900 1000

Signal input

Bandwidth (-3 dB)

1 MHz to >2 GHz

Input voltage

± 1.1 V DC (10.83 dBm)

Coupling

AC (1 MHz LF limit)

VSWR (typ.)

< 1.5 DC to 3 GHz

Impedance

50 Ω ± 1% at 10 MHz

Connectors

SMA, gold-plated

Digital conversion

Sample rate

External clock only:

500 MHz to 2 GHz

Acquisition modes

- In phase:

Sampling Rate = ¼ external clock

- In anti-phase:

Sampling Rate = ½ external clock

- In quadrature:

Sampling Rate = external clock

Channels

Four

Two (with external splitter)

One (with external splitrer)

Resolution

12 bits (1:4096)

System performance

All values for signal input frequencies

from 10 MHz to 925 MHz

In-phase mode (max. 500 MS/s)

SFDR (typ.)

>56 dBc

THD (typ.)

>56 dB

SNR (typ.)

>61 dBc

ENOB (typ.)

>10 for fin = 10 MHz to 500 MHz

>8.7 for fin = 500 MHz to 925 MHz

Anti-phase mode3 (max.1 GS/s)

SFDR (typ.)

>56 dBc

THD (typ.)

>56 dB

SNR (typ.)

>59 dBc

ENOB (typ.)

>9.6 for fin = 10 MHz to 500 MHz

>8.6 for fin = 500 MHz to 925 MHz

Quadrature mode3 (max.2 GS/s)

SFDR (typ.)

>56 dBc

THD (typ.)

>56 dB

SNR (typ.)

>59 dBc

ENOB (typ.)

>9.6 for fin = 10 MHz to 500 MHz

>8.6 for fin = 500 MHz to 925 MHz

External clock input

Input amplitude

> 500 mV pk-pk into 50 Ω

Maximum input voltage

±2 V DC

Ext. clock frequency

from 500 MHz to 2 GHz

Connector

SMA, nickel-plated

Time base

Acquisition modes

Continuous / software triggered

Trigger (external)

Sensitivity

Sensitivity > 5% Full Scale

DC to 1 GHz at 50 Ω

DC to 300 MHz at 1 MΩ

Impedance

50 Ω ±1%, 1 MΩ at DC

Connector

SMA, gold-plated

Full scale

±5 V

Modes

Edge, positive and negative

Acqiris High-Speed VME/VXS Data Converters

Model SVM3500Quad-channel, 12-bit, 500 MS/s digitizer

10

3) Performances in interleaved modes require an

external calibration process and are measured at

calibrated temperature.

11

Auxiliary I/O

Digital signals

14 I/O configurable as 7 LVDS pairs

μDB15 connector

One digital I/O LVTTL 3.3V,

5V tolerant, MMCX,

gold-plated connector (I/O P1)

Analog input

12-bit 65 MS/s ADC

± 1 V DC 50 Ω input

MMCX, gold-plated connector

Analog output

12-bit 130 MS/s DAC

± 1 V DC into 50 Ω

MMCX, gold-plated connector

On board memory

FLASH

128 MB

SDRAM

2 x 256 MB DDR2 533

Optical data links

Transceiver

2 x Small Form Pluggable

Multimode 850 nm

Connector

LC Duplex

Throughput

3.125 Gbps/link

Option 2.5 Gbps/link

Host interface

VME

Full VME64x and 2eSST compliance

VXS

8 x serial links on P0

3.125 Gbps/link

Aggregate: up to 25 Gbps

Option 2.5 Gbps/link

Digital IO

12 LVDS pairs on P0

20 LVDS pairs on P2

One SPI interface on P2

Supported host and OS 4

Single board computers

Kontron :

PowerNode3, PowerEngine

(Linux, VxWorks)

PentXM, PentXM2 (Linux)

Concurent Technologies:

VP337 (Linux)

VP426 (WinXP)

GE Fanuc:

V7812 (WinXP)

Interfaces

GE Fanuc Bus Adapter 810 (WinXP)

General and physical

Power consumption

< 80 W typ.

Dimensions

6U VME standard

233.35 mm x 160 mm x 20.02 mm

Front panel complies with IEEE1101.10

Certification and Compliance

Current requirements (typ.)5

+12 V 0.8 A

+5 V 7.1 A

+3.3 V 8.4 A

-12 V 0.005 A

EMC

Complies with European EMC

directive 2004/108/EC

- IEC/EN 61326-2-1

- CISPR Pub 11 Group 1, class A

- AS/NZS CISPR 11

- ICES/NMB-001 This ISM device complies with

Canadian ICES-001.

Cet appareil ISM est conforme à la

norme NMB-001 du Canada.

Warranty

1 year

Environmental6

Operating temperature

0° to 60°C

Non operating temperature

-40° to 85°C

Required airfl ow

>2 m/s at sea level

Altitude

-1,000 to 15,000 ft

Shock/Vibration

- Operating random vibration - type

tested at 5 to 2000 Hz, 7.6 g RMS

(VITA 47 Class V2)

- Survival random vibration - type

tested at 5 to 500 Hz, 2.09 g RMS

- Functional shock - type tested,

halfsine, 30 g, 11 ms

Humidity

Relative Humidity type-tested at

95%, +40°C (non-condensing)

4) For other configurations, please contact factory.

5) SVM3500 sampling at 500 MS/s, FPGA with base

design. Depending on FPGA customer usage.

6) Samples of this product have been type tested

in accordance with the Agilent Environmental Test

Manual and verified to be robust against the envi-

ronmental stresses of Storage, Transportation and

End-use; those stresses include but are not limited to

temperature, humidity, shock, vibration, altitude and

power line conditions. Test Methods are aligned with

IEC 60068-2 and levels are similar to MIL-PRF-28800F

Class 3.

Model Description

U1083A-005 Quad-channel, 12-bit 500 MS/s SVM3500

digitizer module

U1083A-FDK Firmware development kit for VME-VXS

platform

Options

U1083A-LNK Standard data link

U1083A-L25 2.5 Gbps VXS and front panel links

Accessories

U1092A-CB1 MMCX to BNC, 1 m cable

U1091A-CB1 Chipscope cable and connector

Ordering Information

For more information on Acqiris product line, sales

or services, see our website at:

www.agilent.com/find/acqiris

For more information on Agilent, go to:

www.agilent.com

Windows is a U.S. registered trademark of Microsoft

Corporation.

Pentium is a U.S. registered trademark of Intel Corporation.

PCI Express and PCIe are registered trademarks of PCI-SIG.

Product specifications and descriptions in this document

subject to change without notice.

© Agilent Technologies, Inc. 2009

Printed in USA, August 14, 2009

5990-4151EN

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Revised: July 2, 2009