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Allegro

PCB Editor User Guide:Routing the Design

Series XL and GXL

Product Version 16.0

June 2007


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Allegro PCB Editor User Guide: Routing the Design

June 2007 3 Product Version 16.0

1

Overview of the Routing Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2

Component Fanout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Controlling Fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Overriding Line Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin - Via Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Specifying Vias and Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Creating Via Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Copying Fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

Interactive Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19General Routing Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Dynamic Etch Editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Setting Visibility During Interactive Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Highlighting Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Viewing Ratsnests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Etch Edit Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Highlighting Segments Over Voids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

About Bubble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Hug and Shove-Preferred Modes When Adding Clines . . . . . . . . . . . . . . . . . . . . . . . 26

Handling DRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Obeying Line Angle Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Odd Angle Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

45-Degree Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Constraint Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Contents


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Via Shoving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Using the slide Command in Bubble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Using the add_connect Command in Bubble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Adding Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Interactive Routing with Layer-set Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Defining Line Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Cornering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Adding Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Editing Connections and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Moving or Sliding Connect Lines and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Custom Smoothing of Connect Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Deleting Connections and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Changing the Layer of a Connect Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Creating or Moving Vertices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Deleting Vertices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Spreading Between Voids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Routing High Speed Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Routing Rat Ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Displaying Timing Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Displaying Timing Feedback With Constraint Manager . . . . . . . . . . . . . . . . . . . . . . . 55

Displaying Etch Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Generating a Delay Information Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Delay Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Elongation Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Interactive Routing for Differential Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Single Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Setup and Editing Differential Pairs Using the Etch Edit Tools . . . . . . . . . . . . . . . . . . . . 65

Line Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Cornering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Grid Snapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Route Necking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Single Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Gathering and Splitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Slide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73


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Interactive Group Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Routing Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Control Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Cornering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Snapping and Hugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Routing in Single Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Routing with Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Generating Reports on Interactive Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

About Power and Ground Ratsnest Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Setting POWER_AND_GROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4

Prerequisites for Allegro PCB Router Automatic Routing. . . . 85General Routing Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Grids and Automatic Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Defining Routing Grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Via Grids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Controlling How Vias Are Used During Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Defining Vias for Use During Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Controlling Via Staggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Allowing Via Placement on Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Controlling the Distance Between Buried Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Controlling the Number of Vias on a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Scheduling Nets Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Constraints That Affect Automatic Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Net Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Component Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Optimizing Tpoint Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5Cleaning Up a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Setting Properties to Prevent Net Changes During Glossing . . . . . . . . . . . . . . . . . . 100

Adding No-Gloss Polygons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Defining the Area to be Glossed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Setting Glossing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102


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Glossing Designs Interactively or in Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Glossing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Pad and T Connection Fillet Glossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Preparing the Design for Filleting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Changing a Filleted Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Error Reporting for Pad and T Connection Filleting . . . . . . . . . . . . . . . . . . . . . . . . . 105

Error Reporting for Dielectric Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6

Using the Allegro PCB Router Translator . . . . . . . . . . . . . . . . . . . . . 107

Translator Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108Prerequisites to Running the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Restrictions and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Running the Pre-Route Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Running the Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Mapping Allegro PCB Editor Properties, Assignment Tables, Rule Sets, and Constraints .113

Allegro PCB EditorProperties to Allegro PCB Router . . . . . . . . . . . . . . . . . . . . . . . 113

Allegro PCB EditorAssignment Tables to Allegro PCB Router . . . . . . . . . . . . . . . . 124

Allegro PCB EditorRule Sets to Allegro PCB Router . . . . . . . . . . . . . . . . . . . . . . . . 125Allegro PCB Edtior Constraints to Allegro PCB Router Rules . . . . . . . . . . . . . . . . . 129

Troubleshooting Translation Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

7

Automatic Routing with Allegro PCB Router . . . . . . . . . . . . . . . . . 135Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

File Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Autorouting Task Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Mainstream Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

High-speed Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

High-speed Power User Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Autorouting Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Setting Parameters in the Mainstream Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Setting Parameters in the High-speed or High-speed Power User Flows . . . . . . . . 144


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File Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Sample Rules File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Sample Forget File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148


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1

Overview of the Routing Process

Allegro PCB Editor provides tools that help you perform the following when routing designs:

Interactive routing

Automatic routing with Allegro PCB Router

Glossing to improve the appearance and manufacturability of a design

The following list describes a flowchart of the basic Allegro PCB Editor routing process. Thebasic routing flowassuming automatic routingis:

1. Prepare for routing:

Check layers to see that layer types and photo film types are correct.

Create internal shapes on planes.

Create blind and buried vias.

Set routing controls (routing areas, constraints and properties, grids, nets, and soon).

2. Manually route critical nets.

3. Define routing parameters in Allegro PCB Router to control how automatic routingfunctions.

4. Run Allegro PCB Router.

5. Review routing results.

6. Interactively finish or correct etch.

7. Gloss the design.

8. Optionally analyze the design for signal integrity or EMI.

Perform routing anytime after placement in a design flow as shown in Figure 1-1.


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Allegro PCB Editor User Guide: Routing the DesignOverview of the Routing Process


Figure 1-1 Interactive Routing in a Design Flow

LIBRARY DEVELOPMENT

Create custom pad shapes

Define library padstacks

LIBRARY DEVELOPMENT Create custom pad shapes

Define library padstacks

Define unique packages

Define mechanical elements

LOGIC DATA TRANSFER

Create design database

Associate Design Entry HDL orSystem Connectivity Managerschematic or create and enter third-

LAYOUT PREPARATION

Define design rules (properties andconstraints)

Define layers (cross section)

Create mechanical elements(outline, keepins, keepouts)

DESIGN LAYOUT

Placement (automatic/interactive)

Routing (automatic/interactive)

DESIGN COMPLETION

Rename reference designators

Backannotate

Add power and ground planes

Run Design Rule Checking (DRC)

MANUFACTURING OUTPUT

Generate pen plots

Create artwork

Generate numerical control output

DESIGN ANALYSIS

Signal integrity analysis

EMI Compliance


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2

Component Fanout

Allegro PCB Editor offers several interactive and automatic controls for component fanout, aprocess sometimes referred to as pin escaping. You can use Route Fanout By Pick(fanout_by_pickcommand) to invoke the Allegro PCB Router and work with .dofiles,route interactively within Allegro PCB Editor, build fanouts into your library symbols, or use

the suite of interactive fanout commands located in the Route menu. The interactive suiteincludes four commands to create, copy, define via structures, and convert cline/viaextensions to fanouts.

Fanouts created with the interactive suite are automatically associated to the symbolinstance. This is beneficial when moving a component; fanouts not associated remain inplace when a component is moved. Route Convert Fanout Mark(mark fanoutcommand) can be used to associate fanouts that may have originated from the Allegro PCBRouter or ones routed manually.

Route Create Fanout(create_fanout command) is applied to a single packagesymbol. There are several control options available to customize the style and physicalcharacteristics of the resulting fanout pattern. Unlike Route Fanout By Pick, Route Create Fanoutis not DRC aware and may result in via to element conflicts. Runningadditional passes with parameter adjustments may be required to reach final intent.

Complexvia structures are typicallyused on designs utilizingHigh Density Interconnect (HDI)rules. If required for fanout, they can be defined using Route Define Via Structure(define via structure command) and then applied to a symbol with Route CreateFanout. Via structures are uniquely named and are stored in the database.

Route Copy Fanout(copy_fanoutcommand) is used to replicate an existing fanoutpattern to all other packages or devices of the same name on the same layer. There are no

restrictions on the origin fanout; it can be auto generated or user defined.

Controlling Fanouts

Route Create Fanoutworks with the Optionstab of the Control Panel where severalparameters exist to control the physical spacing and style of the fanout pattern. Available
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Allegro PCB Editor User Guide: Routing the DesignComponent Fanout


elements for selection are symbols and pins. Generating a fanout automatically replaces anyexisting fanout on the chosen elements. If pins connect to a different component, existingfanouts are preserved. The command does not create:

shared vias

multiple vias for voltage pins

fanouts for thru-hole pins

fanouts for pins whose padstack name contains FID, assumed to be fiducials

If multiple via padstacks are associated with a net, then fanout does not occur, and a warningmessage displays. In this case, you must select a specific via padstack from the via dropdownmenu.

Route Create Fanoutand Route Copy Fanoutare not DRC aware. DRC errors mayresult after each operation. Parameter adjustments or interactive editing may be required tocomply with DRC rules.

Figure 2-1 Options tab for Route Create Fanout

The use of the Unassigned Pinsoption results in the fanout of all pins on a component. Pinsnot assigned a logical connection are considered unassigned, as shown in Figure 2-2.


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Figure 2-2 Fanout of Unassigned Pins

Overriding Line Width

By default, Route Create Fanoutuses the line width specified in the respective nets cset.

Use of the Override Line Widthparameter overrides the inherited value and applies to allpins.

Selective override at the net level can be accomplished by enabling the Include all SameNet Pinsoption. For example, you may want all logical nets to be 6 mils, but DC nets to be10 mils. After using Route Create Fanoutwith override line width set to 6 mils, changethe override line with to 10 mils, enable the same pin option, set the Find Filter to pins, thenselect a DC pin to fanout all pins on that net.

Pin - Via Space

Distance between the edge of the pin-pad and the edge of the via-pad may be regulated withthe Pin to Via Spaceparameter. Zero or negative numbers are valid entries.


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Figure 2-3 Pin to Via Spacing (top: negative clearance value; bottom: positive value)

Specifying Vias and Orientation

You can choose the type of via from a list of those stored in the database that span specifiedsubclasses. The combination of the start-end layers produces the list of applicable via typesfor that range. There are 13 direction types to consider pending the type of package symbolwith which you are working. The direction of the fanout via is relative to the pin location.Distance between the edge of the pin-pad and the edge of the via-pad may be regulated withthe Pin to Via Spaceparameter. Zero or negative numbers are valid entries


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Figure 2-4 Via Direction Parameters

Via in Padcenters a via at the pin origin with no cline between the via and the pad.

Figure 2-5 Via in Pad

BGA Quadrantis the default style in which vias are created for each pin in the direction awayfrom the symbol center. Two unused channels remain (one vertical, one horizontal) that passthrough the symbol center. BGAs by default fan out using 45 degree angles.


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Figure 2-6 BGA Quadrant Style

North, South, East, Westspecify compass-point directions.

NE(northeast), NW(northwest), SE, (southeast), and SW(southwest) control 45degree angles.

Inward, Outward, and In/Outare useful for SOICs and other non-BGA components.

Inwardallows vias underneath the component.

Outwardallows vias outside the component.

In/Outallows fanouts to alternate between Inwardand Outwardorientation.

The Min Channel Spaceparameter is used to maintain a minimum space between adjacentfanout vias. The distance spans the edge of a via-pad to the edge of a via-pad on thediagonal, and as the distance increases, so does the stagger effect, as shown in Figure 2-7.The value defaults from the via-to-via space in the default constraint set and is available whenyou set Via Directionto Inward, Outward,or In/Out.


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Figure 2-7 Minimum Channel Space Between Vias

To create fanout clines with two segments and an arc either clockwise (cw) or counter-clockwise (ccw), a Curveoption is available when used in conjunction with a Via Directionof BGA Quadrant Style, NE, NW, SE, orSW. A graphic depiction of the Curveoptionseffects is available by pressing the ? on the Optionstab.

Figure 2-8 Curved Cline Segments

Creating Via Structures

A via structure is a series of vias and clines used primarily on HDI designs to transition asignal from the surface into the HDI or core layers. The Route Define Via Structure(define via structurecommand) can be used to define a single via structure that
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comprises a single via and connect line, or a multiple combination of these elementsspanning many layers. Chosen vias and clines must all be connected to each other andbelong to the same net. They may be connected to only one pin, whose location becomes the

symbol origin. Duplicate symbol names are not created. A via structure must start and endon the subclasses specified in the create fanout commands Startand Endsubclassesfields when used in creating fanouts.

When more than one type of via structure is required for a component fanout, such as forpower or ground fanouts that terminate on different end layers, you can define additional viastructures, then use Route Create Fanoutin combination with the Include all Same NetPinsoption to disperse the new via structures across all same net pins across the symbol.

Copying Fanouts

Route Copy Fanout(copy_fanout command) replicates instantiated fanouts across allcommon package names or device types. Replication is limited to the same side of the boardwhere the origin component is placed. For symbols on the opposite side, you can create afanout for one instance using Route Create Fanout, and then copy it to the remainingsymbols on that subclass.

Copyinga fanout automatically replacesany existing fanout on the chosen component unlessthe FIXED property has been assigned, or the fanout is routed to a different component. Acopy occurs even if you have modified a symbol pin's padstack on one instance, as long asthe pin location remains unchanged.

Copied fanouts replicate the origin symbol attributes such as line width, via type, direction orvia structure. DRC errors may occur after the command is completed; for example, the copiedfanout via may conflict with an adjacent pad or may not meet minimum line widthrequirements.

Figure 2-9 Copied Fanouts
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3

Interactive Routing

Allegro PCB Editor provides several interactive routing options for producing manufacturableresults on the following types of designs:

Analog

Digital

Surface-mount

Through-hole

High-speed

Multichip module

Hybrid

Interactive routing lets you do the following:

Connect two points, with and without vias

Start a connection from a Rat T point

Edit vertices

Insert blind, buried, and through-hole vias

Shove vias when adding clines

Add, slide, or delete connections and vias

Begin a connection, then run automatic routing to finish the etch for that pin-pair Route timing-sensitive circuits

Route with layer-set constraints


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Allegro PCB Editor User Guide: Routing the DesignInteractive Routing


Interactive routing features complement automatic routing features. You can use interactiverouting to:

Complete critical nets before automatic routing. Finish disconnects left after automatic routing.

General Routing Prerequisites

Table 3-1shows general prerequisites, recommendations, and optional considerations forinteractive routing. The table also provides links to the areas of the user guide that detail eachprocess.

Table 3-1 Prerequisites for Interactive Routing

Prerequisite Interactive Routing For Details, See...

Define nets in netlist Required unless routing in apackage symbol

Writing an Allegro PCBEditor Netlist in theAllegro PCB Editor UserGuide: TransferringLogic Design Data.

Schedule nets in netlist If needed Scheduling a Netin theAllegro PCB Editor User

Guide: TransferringLogic Design DataandScheduling NetsInteractively

Load netlist Partial netlist for intelligentconductor optional, but notrequired

Creating a Databaseinthe Allegro PCB EditorUser Guide: TransferringLogic Design Data

Place components Partial placement, reflectingnetlist, required

Chapter 3, PlacingElements Manually,in the

Allegro PCB Editor UserGuide: Placing theElements

Define etch subclasses As needed How Etch Shapes AffectRoutingin the AllegroPCB Editor User Guide:Preparing the Layout
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Dynamic Etch Editing

When you route connections interactively, you get immediate, real-time feedback by way ofdynamic WYSIWYG etch editing. You can see the results of any changes you make whenadding or editing etch. Components of dynamic etch editing are integrated in theRoute

Define etch width Required Defining Line Width

Define route grid As needed Specifying Gridsin theAllegro PCB Editor UserGuide: Getting Startedwith Physical Design

Verify layer information Recommended Working with CrossSection Layersin theAllegro PCB Editor UserGuide: Preparing for

LayoutDefine blind and buried vias As needed Defining Blind and Buried

Vias

Define route and via keepouts As needed Keepin and KeepoutAreas in the Allegro PCBEditor User Guide:Preparing for Layout

Define spacing and physicalconstraint sets for design rulechecking

As needed Chapter 3, Working withConstraints, in the AllegroPCB Editor User Guide:

Creating Design Rules

Define electrical constraint sets As needed Chapter 3, Working withConstraints, in the AllegroPCB Editor User Guide:Creating Design Rules

Define via padstacks As needed Chapter 3, LayoutPadstacks, Vias, and EtchShapesin the AllegroPCB Editor User Guide:Preparing for Layout

Table 3-1 Prerequisites for Interactive Routing

Prerequisite Interactive Routing For Details, See...
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Connect(add connect command), Route Slide(slide command), andEdit Vertex(vertex command) menu items. They include:

Bubbling in hug- or shove-preferred modes Smoothing connect lines

In-compliance or out-of-compliance feedback on timing constraints

Dynamic DRC

Full visibility of elements on dimmed or invisible layers during etch editing operations

All these features let you complete interactive routing tasks quickly and successfully.

The menu items and console commands used in dynamic etch editing are described in the

Allegro PCB and Package Physical Layout Command Reference.

The following issues are related to some components of dynamic etch editing:

Bubble functionality may not perform optimally on arc segments or line segments thatneed to bubble arcs.

Dynamic DRC does not support electrical DRC violations.

In some instances, use of smoothing in bubble mode could result in one cline causinganother to bubble.

Full smoothing on long non-orthogonal segments may result in slower performancewhen in vertexmode.

Based on your hardware, performance degradation may occur on very dense designs asa result of WYSIWYG functionality.

Setting Visibility During Interactive Routing

You can set the visibility (highlighting, dimming, and so on) of elements and layers to assistyou while manually editing etch and other design elements. You can set these functions

statically using commands for highlighting nets and viewing ratsnests or dynamically throughthe use of Shadow modein the Color dialog box, and a user preference.

Highlighting Nets

You can highlight nets that you want to route so that they are more visible. To chooseelements for display in the permanent highlight color, choose Display Highlight
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(hilight command). To turn off the highlighting, choose Display Dehilight(dehilightcommand).

Viewing Ratsnests

To display all rats or only those for a component or a net, choose Show Rats All(ratsall command), Show Rats Components (rats componentcommand), or Show Rats Nets (rats net command).

To blank out rats or remove them from display, choose the Blank Rats All (unrats allcommand), Blank Rats Components(unrats component command), or Blank Rats Nets(unrats netcommand) menu items.

Etch Edit Visibility

Normally, as you edit etch using the Route Connect(add connect command), Route Slide(slide command), or Edit Vertex(vertex command) menu items, if the editactivity moves or affects an element or a cline on a non-visible layer, that layer becomestemporarily visible. This happens whether or not a DRC violation occurs.

To control the visibility of layers that are not active, use the following:

Shadow modein the Displayfolder of the Color dialog box

Shadow modeshows the active etch layer in full color and dims all other visible layers,that is, layers that are selected in the Visibilitytab. Other layers are temporarilyhighlighted only if a DRC violation occurs.

To set shadow mode, choose Display Color/Visibility(shadowor color192commands).

The bubble_no_display_invisibleenvironment variable affects how invisibleelements are dynamically displayed when bubbled

If an invisible element is modified by shove in a way that causes a DRC violation, theelement, via or segment, is displayed in the highlighted color. If an invisible element is

modified by shove and there is no DRC violation, it is displayed only if you have not setthe bubble_no_display_invisibleenvironment variable.

To set environment variables, choose Setup User Preferences(envedcommand).

If you enable Shadow modeand you set the bubble_no_display_invisibleenvironment variable, the following occurs:

The active etch layer appears in full color.
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Other visible layers are dimmed.

All other layers do not appear.

If a DRC violation occurs on a layer that is visible but not active, the elements on thatlayer appear in the temporary highlight color.

If a DRC violation occurs on a layer that is not visible, the element with the DRC markerappears.

Highlighting Segments Over Voids

Critical signal traces must travel over an uninterrupted copper plane to insure a continuousloop of return path current. Even traces that overlap pin voids can be subject to signal

disruption. Identifying and locating all of these void overlaps is crucial to assuring the integrityof the signals in question.

The Highlight Segments Over Voids feature (highlight sovcommand) locates andhighlights the segments of nets where signals overlap voids. The pin where the overlapoccurs is also highlighted. This feature streamlines your ability to eliminate potential signalintegrity problems during the clean-up phase of your design.

Typically, you use this feature near the end of the design process, after the routing hasbeencompleted and all other constraints have been met.

How Highlight Segments Over Voids Works

All segments of the selected nets that overlap voids are highlighted, as well as the offendingvoid. Only adjacent voltage planes are considered. The Highlight Segments Over Voidsfeature works across the entire board.

Note: In the case of cross-hatched planes, the Highlight Segments Over Voids featurehighlights only those clines that cross the boundaries of the planes. Such violations forcross-hatched planes appear in the report file under the section Segments with partialor missing plane coverage.

Highlight Segments Over Voids checks all nets except those with the VOLTAGE property. Youcan limit the check to particular nets by assigning the SOV_CHECK property to one or morenets. If a net is assigned both the SOV_CHECK property and the VOLTAGE property, theVOLTAGE property takes precedence and the net is not checked.

A report file containing the violations is generated. The report file appears in the Viewlogdialog box, which allows you to click on the X,Y coordinates of a violation and center thedesign window on that object.


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The report file shows the spacing of the overlap for each violation. You can scan the listquickly, looking at the spacing values, and determine if there is a common number that wouldbe considered acceptable (for example, 0.2 mils). You can then set the sov_spacing value

to offset that (sov_spacing = -0.2) and rerun highlight sov to see where the really significantoverlaps occur. This process eliminates many false violations and helps you choose areasonable value for sov_spacing without a lot of guesswork. By repeating this processincrementally, you can arrive at the smallest acceptable value based on what you havedesigned.

Setting the User Preference Variables

You can set the following user preference variables to control how Highlight Segments OverVoids operates:

sov_spacing Allows you to specify the minimum space that must existbetween void and a cline segment. This will suppress


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highlighting anything less than or equal to that value if it isacceptable to have a small part of a cline exposed by an antipadbut the majority covered. You can use this variable to eliminate

any false failures and highlight only the most troublesomeconditions. The value for sov_spacingis expressed in thesame units that the design uses (mils, mm, inch, micron). Thedefault value is 0. A positive value means there must be spacebetween the void and the cline segment. A negative value meansthe segment is allowed to overlap the void by that amount. Avalue of 0 allows the segment to touch a void withoutoverlapping.

sov_active If enabled, only the active layer is checked. If you disablesov_active, the Highlight Segments Over Voids checks all

conductive layers that have at least one adjacent plane.

You set these variables in the User Preferences Editor(from the Setupmenu, chooseUser Preferences), under the category Display_SOV.

About Bubble Mode

You can choose hug- or shove-preferred bubble modes to avoid spacing DRC errors whenadding new etch using Route Connect(add connect command) or modifying etch usingRoute Slide(slide command), or Edit Vertex(vertex command) during interactiverouting.

When Allegro PCB Editor, in hug-preferred mode, encounters an obstacle, it tries tomaintain the geometry of the existing etch to avoid spacing violations. If it cannotsuccessfully hug existing etch with hug-preferred mode enabled, then it tries to shoveclines to avoid spacing violations.

When Allegro PCB Editor, in shove-preferred mode, encounters an obstacle, it tries tomaintain the geometry of the new etch. If it cannot successfully shove existing etch dueto obstacles with shove-preferred mode enabled, then it tries to hug obstacles to avoidspacing violations.

For additional information, see Obeying Line Angle Controls.

Hug and Shove-Preferred Modes When Adding Clines

Figure 3-1shows the differences between hug- and shove-preferred bubble modes whenadding clines.
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Figure 3-1 Hug and Shove-Preferred Modes

Off Hug Shove

Off:Shows the original path of the new etch without bubble mode enabled. The new etchruns on top of the bottom cline, causing DRC errors.

Hug-preferred bubble mode:New etch hugs the bottom cline. The bottom cline retainsits original position.

Shove-preferred bubble mode:New etch moves the bottom cline.

Handling DRC Errors

Using Route Connect(add connect command) andRoute Slide(slide command)you can dynamically bubble to fix spacing violations when in hug- or shove-preferred bubblemode. If Allegro PCB Editor, in the mode, cannot fix some violation(s), it changes the cursor

to the DRC marker shape and highlights segments that have spacing violations as you movethe mouse. Allegro PCB Editor dynamically highlights cline segments affected by DRC errorsusing the temporary highlight color you defined in the Color dialog box, accessed usingDisplay Color/Visibility(color192command).

If Allegro PCB Editor, in bubble mode, fails to fix DRC errors, takes undesired paths to fixthem, or requires too much time to arrive at a solution, you can make intermediate picks toguide more specifically through obstacles. If you disable Allow DRCsin the Optionstabwhen using Route Slide(slide command), the extent of the slide is limited to preventyou from creating spacing violations.

Shove- and hug-preferred bubble modes conform to spacing checks and may consequentlycause electrical constraint-set DRC errors, which are not reported until you make the nextpick.
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Obeying Line Angle Controls

The initial path for new etch follows the Line lockangle you specified. However, when you

enable bubble mode, new or existing etch hugs or shoves other clines to avoid DRC errors,even if it violates the specified angle.

Odd Angle Lines

If the original design contains odd angle lines, bubbling may create more odd angle lines, asshown in Figure 3-2, even if the Line lockvalue is 90.

Figure 3-2 Odd Angle Lines

90/off 45/off Hug preferred/45 and 90

(Left) A line with a Line locksetting of 90and bubble disabled

(Center) A line with a Line locksetting of 45and bubble disabled

(Right) Hug-preferredbubble mode enabled, hugging an oddangle line, regardless of the45- or 90-degree angle setting

45-Degree Lines

If theoriginal designcontains45-degree angle lines, Allegro PCB Editor, in bubble mode, maycreate more 45-degree angle lines (Figure 3-3) even if you set the angle to 90 degrees.

Hugging the outside of a 45-degree turn may result in 45-degree segments that exceed thespecified value in the Max 45 length field, as shown in Figure 3-3.


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Figure 3-3 45-Degree Angle With and Without Hug-Preferred Mode

(Left) The specified maximum 45 length obeyed.

(Right) If the shortest cline was added at the maximum 45-degree length, Allegro PCBEditor, in hug-preferred mode, adds other segments at greater than maximum 45 length.

Pads

With hug- and shove-preferred bubble mode, circular objects such as pads do not producecircular etch, as shown in Figure 3-4.

Figure 3-4 Handling Pads

(Left) When the Line lockangle is 90 degrees, orthogonal routeshandlecircular objects.

(Right) When the Line lockangle is 45 degrees or off, Allegro PCB Editor uses 45-degree lines to bubble around circular objects.

Arcs

You cannot add arcs while in shove- or hug-preferred mode. Allegro PCB Editor does notsupport hugging or shoving of existing arcs. Consequently, specifying a value of Arcin theLine lockfield disables bubble mode. Conversely, enabling bubble mode to either hug- orshove-preferred sets the Line lockvalue to Line.


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Constraint Areas

If a line crosses a constraint-area boundary, more than one line-to-line spacing rule may

apply to the cline. This could result in bubble using the wrong spacing rule for the line. Toavoid this issue, pick just inside the constraint area and then continue routing.

Via Shoving

When you are in bubble mode, you can shove vias when adding or sliding connections orediting vertices. This functionality lets you complete a connection without DRC violations.

You set via shoving in the Options tab when you choose Route Connect(add connectcommand), Route Sl ide(slide command), or Edit Vertex(vertex command), as

shown in Figure 3-5. Note that in each case, Shove viasis disabled when Bubblemode isinactive.

Figure 3-5 Shove Via Settings in Options Tab

add connectconfiguration vertexconfigurationslideconfiguration
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You can set via shoving to operate in three modes. Table 3-2shows how the Shove viasmodes work with the Bubblemodes.

Table 3-2 Shove Via Modes

Regardless of the Shove viamode you choose, the behavior of vias when you shove themis identical. A shoved via moves the minimum distance from an element acting upon it. Toaccommodate this behavior, a via may sometimes hop over a connect line to ensure the leastamount of disruption to the overall design. This behavior is shown in Figure 3-6.

BubbleShove Vias

Minimal Full

Hug-PreferredMode

Clines hug the vias unless there isno room, then shoving occurs.


Hug-OnlyClines hug the vias. Other etchremains the same.

Clines hug the vias. Other etchremains the same.

Shove-PreferredMode


Vias are shoved. If a via cannotbe shoved, Allegro PCB Editorgoes around it.
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Figure 3-6 Via Hopping

Display Configurations for Via Shoving

Like all other aspects of etch editing, via shoving appears in WYSIWYG mode. Because viastypically exist on many layers of a design, elements on layers other than the active (visible)layer become visible when acted upon by a shoved via. Figure 3-7shows how a design innon-shadow mode displays etch when acted upon by a shoved via.

Figure 3-7 Shoved Via Display Characteristics

Original configuration Via hopping over clineHorizontal cline moving toward via
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In the left design no vias have been shoved. The design displays the vias and connect lineson the active layer. The right design shows when the via at the center of the picture has beenshoved upward by the addition of a newly added connect line. All the affected traces on the

hitherto invisible layer become visible.

Figure 3-7 shows the default display behavior. You can modify the display of this informationby configuring which layer is active and which layers are visible and by setting shadow modeand the bubble_no_display_invisibleenvironment variable. See Setting VisibilityDuring Interactive Routingfor details on these visibility options.

Using the slide Command in Bubble Mode

When you modify existing etch during interactive routing, you can use the two bubble mode

optionshug- or shove-preferredto assist you in avoiding DRC errors. Use hug-preferredmode when you want to model the etch you are sliding to other etch. Use shove-preferredmode when you want the etch you are sliding to move other etch out of its path.

Using the add_connect Command in Bubble Mode

When you add new etch during interactive routing, you can use hug- or shove-preferred orhug-only bubble mode to avoid creating DRC errors. Use hug-preferred mode to place routesas closely as possible to existing routes. Use hug-only mode to contour without changingother etch objects Use shove-preferred mode to route through a path blocked by other clines.

To ensure that existing critical clines meeting your requirements remain unchanged, chooseEdit Properties(property edit command) or use the toolbar icon to attach the FIXEDproperty to these clines after you complete the route.

Guidelines

Hug and shove-preferred bubble modes are not auto-routing modes. When in these modes,Allegro PCB Editor does not always locate the optimal path from one point to another. It startswith the line lock-based segments that go from the last pick to the cursor. It then attempts tocorrect any spacing violations by hugging or shoving etch. Consequently, as you use the

shove-preferred and hug modes, the Line Lockand toggle settings are critical. You canaccess the toggle options from the pop-up menu.

Note that setting the Line Lockfield to Arcdisables bubble mode. Conversely, enablingbubble mode (to either hug-preferred or shove-preferred mode) sets the Line Lockfield to
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Lineto prevent adding arcs while in shove/hug mode. Shoving or hugging existing arcs is notsupported.

During hug or shove-preferred routing, excessive delays typically indicate the result may beundesirable. To maximize performance when you use bubble modes during etch editing:

Avoid particularly dense or complicated or both types of regions.

Do not shove many traces simultaneously.

Minimize distances between selections to preclude crossing constraint-area boundaries.

If you do not like the result, you can try again by adding smaller amounts of etch with eachpick.

Adding Connections

ChooseRoute Connect(add connect command) to add connections to a designinteractively. You can add etch interactively before or after automatic routing. Before addingconnections, you may want to familiarize yourself with some aspects of interactive routing:



About Bubble Mode

For information related to time-sensitive connections, see Routing High Speed Circuits.
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When you add connections using Route Connect(add connect command),Allegro PCB Editor displays the following tabs.

The Optionstab lets you choose various routing controls.

The Find Filter lets you identify and choose pins, vias, and etch segments for routing.

The Visibilitytab controls visibility of those elements as well as selection of visibility

settings.

For instructions on how to add a connect line, see the Route Connect(add connectcommand) section in the Allegro PCB and Package Physical Layout CommandReference.
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Interactive Routing with Layer-set Constraints

The add connect command lets you route nets that have layer-set constraints.

Note: You can place layer-set constraints on nets, XNets, differential pairs, buses, or ECSets.

The Optionstab helps you to route with layer-set constrained nets in the following ways:

Displays the legal routing layer-set layers (also referred to as subclasses) in bold-facedtype.

Automatically sets the Act(active) and Alt(alternate) drop-down list boxes to layers thatare in the applicable layer sets.

Tip

Uncheck the Planesbox in the Visibilitytab to reduce the number of layers thatappear in the drop-down list boxes of the Optionstab.

Allegro PCB Editor defaults to the layer closest to the initial active subclass setting. When youstart routing on a net, the layer-set constraint and the existing clines determine the layer setthat applies to the current route. In cases where the layer-set constraint contains more thanone layer set, the pre-existing clines determine the legal layers for both the active andalternate subclasses. If no clines exist, all layers in all layer sets of the layer-set constraint arelegal for the active and alternate subclasses. If you choose a layer-set subclass in the Actdrop-down list box, Allegro PCB Editor displays the applicable alternate subclass in the Altdrop-down list box.


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For example, in Figure 3-8, a 64-bit bus has a layer-set constraint that allows LS3-4(layerset 3-4) and LS6-7as legal routing layer sets. When you choose the first element, the fourlayers contained in the two layer sets appear in bold-faced type in the Actand Altsubclass

drop-down list boxes. For example, LS3-4consists of layers Sig_3Hand Sig_4V. LS6-7includes layers Sig_6H and Sig_7V. The Actsubclass defaults to Sig_3H, as a result ofthe previous setting of Top, and the Altsubclass becomes Sig_4V. After you pick the firstelement and the Actsubclass was previously set to Bottom, the default Actsubclass isSig_7V and the Altsubclass becomes Sig6-H. If you want, you can change the activelayer to a layer from the second layer set (LS6-7) at the point of the initial pick.

Figure 3-8 Picking the First Element

LS3-4

LS6-7
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When you add the first cline, Allegro PCB Editor locks the routing on the LS3-4 setcontaining routing layersSig_3H and Sig_4V. SubclassesSig_6H and Sig_7V revert backto normal font in the Optionstab, as shown in Figure 3-9.

Figure 3-9 Committing to a Layer Set

If a layer set does not include top and bottom etch layers, then surface-mount pins associatedwith the layer set require pin escaping to access the legal routing layers. In this case, DRCignores the etch from the surface-mount pin to the via. The accumulated amount of etchlength on non-layer set subclasses appears in the Lengthcolumn of the Electrical ConstraintSpreadsheet.

Caution

Allegro PCB Editor does not prevent routing on an illegal layer; however,

DRC reports an error.

For additional information on layer-set constraints, see Layer Sets in the Allegro PCB EditorUser Guide: Creating Design Rules.
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Defining Line Width

To determine the line width of the etch you add to the design, Allegro PCB Editor uses several

locations to determine the width of each line segment (lines and arcs). An impedance rulecan control width, and as with minimum line width, it can come from the constraint set (exceptwhen it is electrical) or from a property (IMPEDANCE_RULE) on the net. The net propertyoverrides the constraint set impedance rule.

The precedence is as follows:

If you type in a new line width in the Optionstab during operation, it takes precedenceover values at any other locations. See Overriding the Minimum Line Width Setting.

If the route is constrained by an impedance rule, a line width based on that impedancerule is used as long as that line width is greater than the minimum line width defined inthe physical rule set. Line width, subclass, board materials, and cross-section affectimpedance.

If the route is constrained by an impedance rule and a neck width greater than zero thatallows the cline to meet the target impedance, necking is used and automatically adjuststo meet the target impedance. If the minimum neck width is zero, necking is not used, sothe neck width is not considered for automatic width generation. Instead the minimumline width is the constraint limit to meet the target impedance. If the target impedance isnot met, a DRC error occurs.

If no impedance rule exists, or if the width based on impedance is less than the minimum

line width, the minimum line width is used.

Note: Line widths that are derived from an impedance rule are rounded to the databaseaccuracy. If databaseaccuracy is greater than one decimal place, the resulting line width maynot be an integer multiple of the base design unit; for example, 1 mil or 1 micron.

Overriding the Minimum Line Width Setting

By entering a new value in theLine widthfield of the Optionstab, you can override theminimum line width determined by an impedance rule on a property or by a constraint setting.

If you are adding etch to an existing cline segment whose line width differs from that of theconstraint/property setting, the new etch uses the width of the existing segment. This appliesto new routes that extend a dangling cline or which tee into a cline.

Unless you specify a width override in the Optionstab and you connect from an existingsegment, Allegro PCB Editor automatically uses the width of the existing segment. Table 3-3shows behaviors that apply to minimum line width settings and manual overrides when youare connecting from existing segments.


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Note: The override value remains in effect until you complete the connection task or clickResetin the Optionstab.

Reverting to Constraint-Set Minimum Line Width

You can revert a manually overridden minimum line width to constraint/property settings. Thethe drop-down menu associated with the Line Widthfield shows previous values that wereset. If the current value in the field is not the default value (the minimum line width) the drop-down menu shows an item called Default. Choosing this item resets the line width so thatAllegro PCB Editor uses the minimum line width from the applicable physical constraint set.This feature replaces the Resetbutton.

When you use this function, the following conditions occur:

The constraint/property-based minimum line width takes effect immediatelyand under allthe conditions described above.

The Line widthfield in the Optionstab displays the constraint/property-based setting.

Table 3-3 Line Width Behavior When Connecting from Existing Segments

If... Then Allegro PCB Editor...You override the line width for an existingsegment

Uses the line value specified as an override forthe connection.

You begin a new route or route from anexisting segment that does not have anoverride value

Uses the line width setting defined in theconstraint/property.

You connect from other element types,such as pins, vias, or shapes

Uses the minimum line width specified by theconstraint/rule. This behavior, however, ispartially dependent on the type of elementselected and the element types selected in the

Visibilitytab.

You add a via while a minimum line widthoverride is in effect

Reverts to its property constraint setting.

The line width of an existing segment isless than the constraint-based line width

Uses the constraint-based line width.


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Cornering

During interactive routing, you now have more control in cornering with arcs and 45-degree

angles.

If you set the Line lockoption as Arcwith 45 or 90 degrees, the radius controls appear.These controls let you specify a minimum or fixed radius.

If you set the Line lockoption as Linewith a 45-degree angle, the miter controls appear.These controls allow you to specify a minimum or fixed miter size. Miter means that AllegroPCB Editor cuts a corner with a 45-degree angle.

See Route Connect(add connectcommand) in the Allegro PCB and PackagePhysical Layout Command Referencefor additional information.

Adding Vias

There are two types of vias: through-hole and blind/buried. You can add either type as part ofa connection or as a stand-alone via. A stand-alone via is either a through-hole or a blind/buried via that is not added to a particular connection.

Through-hole Via

A through-hole via penetrates all layers and allows a connection to travel between the top andbottom etch layers.

To add a through-hole via, choose Route Connect(add connect command). The addconnectcommand in the Allegro PCB and Package Physical Layout CommandReferencedescribes the procedure.

Through-hole via
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Blind Via

A blind via travels between an outer layer and an inner layer.

Buried Via

A buried via travels between two internal layers.

Defining Blind and Buried Vias

Before you can add blind or buried vias to a design, first create a blind or buried padstack.You can do this automatically by choosing Setup Vias Auto Define B/B Via(autodefine bbviacommand) or manually by choosing Setup Vias DefineB/B(define bbviacommand). You can also define a via in the Padstack Designer bychoosing Tools Padstack Modify Design Padstack(padeditdbcommand).

To assign vias that you are going to use on a net for routing, choose Setup Constraints Physical, then in the Physical worksheet of Constraint Manager, click in the cell under the

Viascolumn for the net and select the vias from the Edit Via List dialog box.

These menu items and commands are described in the Allegro PCB and PackagePhysical Layout Command Reference.

Blind via

Buried via
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Editing Connections and Vias

You can use menu items or routing commands described in the Allegro PCB and PackagePhysical Layout Command Referenceto perform the tasks listed in this section.

Moving or Sliding Connect Lines and Vias

In menu-driven editing mode, choose Route Slide(slide command) to interactively moveor edit connect lines, segments, or vias while maintaining their connectivity. You choose theelement to move, then its destination. If you chooseTemp Groupfrom the pop-up menu, youcan move multiple segments. If you choose Cut, you can move only a portion of a segment.

Custom Smoothing of Connect Lines

Choose Route Custom Smooth(custom smooth command) to optimize selected clinesor cline segments according to parameters set in the Optionstab. Smoothing the angles ofclines or cline segments can minimize the distance to pad connections.

Before you start, note that custom smoothing cannot be performed on clines or segments thatcontain DRC errors. You may need to perform a DRC update and appropriate cleanup beforeusing this feature.

Deleting Connections and Vias

Choose Edit Delete(delete command) to remove a connect line or segment or cut outa piece of etch and discard it. The original connection remains on the design with twodangling ends. You also use these methods to remove vias.

Changing the Layer of a Connect Line

ChooseEdit Change(changecommand) to change the layer of a connect line.

Creating or Moving Vertices

Choose Edit Vertex(vertexcommand) to edit etch by creating a vertex or moving anexisting one. While doing so, Allegro PCB Editor can dynamically correct DRC errors throughthe use of bubble capability similar to that which exists when you choose Route Connect(add connectcommand) and Route Slide(slide command). When you choose
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Edit Vertex(vertexcommand), bubble is active only when you are editing cline or etchline segments.

Deleting Vertices

Unlike other aspects of etch editing, you cannot view the results of deleting a vertex until thechange has been made. To undo a deletion, click the right mouse button, and choose Oopsfrom the pop-up menu.

To avoid creating DRC errors when deleting vertices, deselect the Allow DRCscheck box inthe Optionstab. Doing so prohibits you from removing any vertex that would generate DRCerrors, and displays an error message at the console window prompt.

To delete a vertex, choose Edit Delete Vertex(delete vertexcommand).

Spreading Between Voids

The Spread Between Voids feature spreads out the clines in a routing channel you specify.You can use this feature to correct return path issues that occur when clines overlap pad voidson adjacent layers. Typically, you apply the spreading function at the end of the designprocess after you complete routing, meet all other design constraints, and execute thehighlight sov command to highlight any problems.

You choose two objects (a combination of two pins, two vias, or one of each) that define arouting channel. The clines within the channel are pushed toward voids found on adjacentplanes. The spacing between routes is the largest minimum spacing for the group of clines inthat channel. If the clines cannot space evenly, based on the spacing rule applied forspreading, then no spreading occurs. The following examples illustrate what happens to theclines using different void clearances.
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Figure 3-10 Before Spreading Between Voids

Figure 3-11 Spreading Between Voids with Zero Clearance


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Figure 3-12 Spreading Between Voids with 10 mil Clearance

Routing High Speed Circuits

Adding connections to high speed circuits in a design may make it necessary for you to userat Ts and delay rules that are not present in other nets.

Routing Rat Ts

Rat Ts are logical database (not physical) objects that you can use to insert a branch in a netschedule at a point other than at a component pin. A rat Ts physical location is typically anapproximate location for a T or a via in the nets interconnect. However, once located in thedesign, you can use the optimize_tscommand to further optimize the location of rat Tsautomatically. See the net schedulecommand for further details on working with rat Ts.

To route rate Ts, chooseRoute Connect(add connectcommand), described in theAllegro PCB and Package Physical Layout Command Reference.

Displaying Timing Feedback

High-speed circuits often require timing constraints to ensure successful routing. Delay rulesare timing constraint variations that you can attach to timing-sensitive nets. Allegro PCBEditor provides you with dynamic timing feedback on nets, extended nets (Xnets), buses,differential pairs, and pin pairs that have properties such as the following attached:
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PROPAGATION_DELAY

RELATIVE_PROPAGATION_DELAY

TOTAL_ETCH_LENGTH

See the Allegro Platform Properties Referencefor the syntax of these properties.

Dynamic timing feedback, a type of heads-up display, lets you determine if connections youare adding or modifying are within the acceptable timing parameters of the properties. Thedisplay updates as you route using the following commands:

add connect

delay tune

slide

vertex

The feedback displayed shows you whether the etch you are adding or changing is within theacceptable range, determined by the values of the attached timing properties and the overallproposed etch of the interconnect. Proposed etch, as the add connectexample shows inFigure 3-13, is the total of all interconnect between start and end points. It includes:

Existing etch (shown as old and new etch in Figure 3-13)

Dynamic etch (the rubberband display that appears as you move the cursor)

Expected etch (represented as a ratsnest line)
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Figure 3-13 Components of Proposed Etch

Note: Proposed etch must provide at least some of the connection between pin pairsspecified in attached timingconstraints. For timing constraints on Xnets, pin pairs do not haveto be part of the current net.

In addition to the components of proposed etch described above, timing displays also take

into account unrouted portions of a net (or other supported object). The calculation ofunrouted portions of a proposed etch assumes routing at manhattan length with current linewidth on the current subclass. Timing constraints for pin pairs that are not connected (fullyrouted) have the following conditions:

Reference pin pairs of a RELATIVE_PROPAGATION_DELAY constraint are assumed tobe routed at manhattan length and are assigned the default propagation velocity, whichis defined on Interconnect Modelstab of the Analysis Preferences dialog box,accessed by choosing Analyze SI/EMI Sim Preferences(signal prefscommand).

Unreferenced pin pairs are ignored; no timing feedback is displayed.

The Timing Feedback Window

The dynamic timing feedback window is an Allegro PCB Editor heads-up display that providesfeedback on how well you satisfy timing constraints when editing an electrically-constrainednet. These constraints include properties such as PROPAGATION_DELAY, RELATIVEPROPAGATION_DELAY, TOTAL_ETCH_LENGTH, and so on.
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Figure 3-14shows the basic components of the timing feedback window, and the sectionsbelow the figure describe the components.

Figure 3-14 Dynamic Timing Feedback Window

Color Indicator

The frame of the window and the slide bar show a color representing one of the followingconditions. Allegro PCB Editor uses the length of the current etch plus the estimatedmanhattan distance of the unrouted segment when determining these conditions.

Numeric Output

The top of the window shows text representing the timing constraint and the numeric outputof the timing margin. The display changes as you add, subtract, or move dynamic etch (theinterconnect that changes as you move the cursor). The numeric output display has thefollowing characteristics:

The displayed value of the timing margin is in length user units of the design (mils,inches, and so on).

Color Description

Green Indicates that the current etch is within the minimum/maximum constraintrange.

Red Indicates that the current etch is not within the minimum/maximumconstraint range.

Yellow Indicates that you have a violation, but possibly, it can be corrected by adifferent as yet unrouted connection.

Property name and numeric output

Sliding meter bar

RDly +14

Color indicator

Minimum and maximumconstraints
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The margin is relative to either the minimum or maximum timing constraint, dependingon which makes a smaller value. In Figure 3-14, the margin value (+14) is relative to theminimum timing constraint, so it appears on the left side of the display. When the margin

is relative to the maximum timing constraint, the value appears on the right side.

The margin value displays a decimal accuracy based on the accuracy settings in theDesigntab of the Design Parameter Editor, available by choosing Setup DesignParameters(prmed command). The maximum number of digits after the decimal pointin the display is the same as the value in the Designtab of the Design Parameter Editor.However, trailing zeros to the right of the decimal point are suppressed.

Sliding Meter Bar

The bottom of the window has a meter bar that slides to the right as you increase theproposed etch length. The meter bar has these characteristics:

Vertical lines represent the minimum and maximum timing constraint values. If either aminimum or maximum timing constraint is not set, then only one line, representing theconstraint that is set, appears.

The meter reaches its maximum extent to the left or right if the proposed etch extendstoo far outside the acceptable range. Beyond that point, you must read the numericoutput for valid data.

Figures 3-15and 3-16show the timing display for conditions when there is only a minimum

value set for the constraint setting.
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Figure 3-15 Red Condition Delay Less Than Minimum Value

Figure 3-16 Green Condition Delay Satisfies the Minimum Value

Figures 3-17 and 3-18 show the timing display for conditions when there is only a maximumvalue set for the constraint setting.
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Figure 3-17 Red Condition Delay Exceeds Maximum Value

Figure 3-18 Green Condition Delay Satisfies the Maximum Value

Figures 3-19 through 3-21 show the timing display for conditions when both minimum and

maximum values are set for the constraint setting.
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Figure 3-19 Red Condition Delay is Less than Minimum Value

Figure 3-20 Red Condition Delay Exceeds Maximum Value


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Figure 3-21 Green Condition Delay Is in Acceptable Range for Both Min/Max Values

Target Net Identified in Matched Groups

If you create a matched group using relative conditions, for example, delta:tolerance,the word Target is assigned to the member with the longest manhattan length. The letterThas been added to the heads-up display (see below) to indicate that the net being editing isthe target net of a relative matched group.

Note: To obtain this feedback, you must dock the heads-up display.

Docking the Heads-Up Display in the Options Tab

To dock the heads-up display, chooseSetup User Preferencesfrom the Allegro PCBEditor menu bar, then choose Etchand enable the allegro_dynam_timing_fixedposenvironment variable.

When you dock the heads-up display in the Optionstab in newer versions of Allegro PCBEditor, each length or timing constraint margin displays its own meter. Figure 3-22 shows thetuning of a differential pair with phase control, relative delay and propagation delay rules. Themultiple heads-up display shows that only relative delay conditions are in violation.
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Figure 3-22 Multiple Heads-Up Display Meters

Turning Off the Timing Feedback Window

If you do not want to automatically display feedback on timing-sensitive circuits, set theallegro_dynam_timingenvironment variable, located in the Etchcategory in the UserPreferencesEditor, to off. Choose Setup User Preferences(enved command) to accessthe User Preferences Editor. If you are viewing etch length feedback on circuits that do nothave timing constraints attached, using Route Connect(add connect command)displays only that information until you unset the variable. For additional information, seeDisplaying Etch Length.

Displaying Timing Feedback With Constraint Manager

If you areworking with Allegro PCB Editor supporting simulation, you can view detailed timingfeedback using Constraint Manager. This may be required in instances when complicatedtiming situations make it difficult for you to route a net using only a worst case feedbackdisplay.

Note: This section describes only the procedure for viewing timing feedback in ConstraintManager. For complete information on Constraint Manager, see the Constraint Managerdocumentation.

To display timing information in Constraint Manager:
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1. Choose Setup Constraints Electrical(cmgr_eleccommand) to open theElectrical worksheet of Constraint Manager.

2. In the tree view, expand the Netfolder and

Documents

Al Gro Route