Alaram Clock Dld

DigitalLogicDesignandAnalysis

8.

A

DesignExample:

DigitalAlarm

Clock

PorasT.Balsara

and

Kamlesh

Rath

DepartmentofElectricalEngineering

TheUniversityofTexasatDallas

A

Design

Example:

DigitalAlarm

Clock

8.1

c

August1998

ptb,kr

DigitalAlarm

ClockDesign

�

GeneraldesignMethodology

�

Speci�cationsandusage

�

Overallarchitecture

�

Designdetails

�

Simulationresults

A

Design

Example:

DigitalAlarm

Clock

8.2

c

August1998

ptb,kr

GeneralDesignMethodology

�

Top-downvsBottom-updesignmethodology.

�

Proceedinatop-downfashionstartingwithahighlevelspeci�cationof

thesystemtobedesigned.

�

Developatoplevelarchitectureblockdiagram.

�

Determinespeci�cationsofbuildingblocksandinterfaceamongdi�erent

blocks.

�

Designbuildingblocksbygoingdownthehierarchytillyoureachthe

mostprimitiveblocks,i.e.,combinationallogicgatesand ip- opsinthis

designenvironment.

�

Designandthoroughlysimulatethemostbasicblocksusingthe

primitivecomponents.

�

Buildnext(higher)levelblocksusingtheabovebasicblocks,simulating

thoroughlyateachlevel{Bottom-updesignprocess.

A

Design

Example:

DigitalAlarm

Clock

8.3

c

August1998

ptb,kr

Speci�cations and Usage

� Digital clock with alarm.

� Displays hours and minutes in 12 hour mode with AM/PM and

Alarm ON LED indicators.

� Push button switches to set time of day and alarm time.

� Push button switches to set hours and minutes.

� Push button switch that toggles alarm on or o� and a speaker to provide

an audible tone when alarm goes o�.Set_Time

Set_AlarmSpeaker

Alarm on/offMinutes

Hours

AM/PM

Alarm on/off LED

A Design Example: Digital Alarm Clock 8.4 c August 1998 ptb,kr

�

Tosettimeofday:

{

PressSetTimepushbuttonswitchand

{

PushHoursswitchtomodifyHoursdisplayorMinutesswitchtomodify

Minutesdisplay.

{

ReleaseSetTimeswitchtocontinuenormaloperation.

{

EachpushofHoursorMinutesswitchwillincrementthecorresponding

displaybyone.

{

HoursandMinutesswitchesshouldnotbeoperatedatthesametime.

�

Tosetalarm

time:

{

PressSetAlarmandswitchanduseHoursandMinutesswitchesas

mentionedabovetosetalarmtime.

{

ReleaseSetAlarmswitch.

{

Inordertoturn-onthealarmpushtheAlarmon/o�switchonce.

Pushingitagainwillturn-o�thealarm.

{

Oncethealarmgoeso�itcanbeshutonlybypushingthe

Alarmon/o�switch.

A

Design

Example:

DigitalAlarm

Clock

8.5

c

August1998

ptb,kr

OverallArchitecture

�

Therearetwodistinctcomponentsinthisdesigna:

(a)clocktimecircuit,and(b)alarmtimecircuit.

�

Theseblocksgeneratedataforhours,minutesandAM/PMdisplays.

�

Thereisnoneedtodisplayalarmtimeallthetime.Itshouldbe

displayedonlywhenalarmtimeisbeingset.Atallothertimesclock

timeisdisplayed.Thisisachievedbymultiplexingthedataoutputsfrom

theclocktimeandalarmtimecircuitsusingSetAlarmascontrolinput.

�

Sincethedisplaydevicesare7-SegmentLEDdisplaysthereisaneedfor

eitherabinary-to-7-segmentoraBCD-to-7-segmentconverter.

�

Amagnitudecomparatorisneededtocomparetheclockandalarm

timesandtogenerateasignalwhichcanturnonanalarmringerifthe

alarmwasturnedonearlier.

a

Partsofthisdesignarefrom

theSynopsysVSSFamilyTutorials,ver3.3

A

Design

Example:

DigitalAlarm

Clock

8.6

c

August1998

ptb,kr

7 7 7

Alarm Time Block

Tone Generator & Ringer ControlComparator

2

AM/PM

2 7 7 7

Multiplexer

Hrs. Mins.

MH

Clock Time Block

=Speaker

Alarm_on

BCD-7 Segment Converter

5 7

1313Set Alarm Set Time Hrs. Mins.

CLK

Display Drivers

Alarm_on/off


Clock Time Block

7

5chrs

cam_pm

cmins

CLK

CLOCK TIME

BLOCKmins

hrs

set_time

TIMECOUNTER

inc_h

inc_m

inc_s

TIME

STATE MACHINE

hrsmins

set_time

CLK

chrscmins

cam_pm

5

7


Time State Machine:

� Based on the status of set time input it generates input signals for the

time counter. If set time is active it generates pulses on inc h or inc m

line each time hrs. or mins. switch is pushed.

� In the normal mode, it sets inc s high so that the time counter counts

the pulse on CLK input which has a frequency of 1 Hz.

set_time hrs mins inc_h inc_m inc_s

conditionsall other

SET_MINS

SET_HRS

110 10

COUNTTIME

101 010101 000

0110 000

001all other conditions 000

all other conditions 000

00

01

10


.

TIME-SM

clk

inc_s

inc_m

inc_h

Q1

Q0set_time

min

hrs

Schematic diagram of Time State Machine


Tim

e

Counter:

�

Inputtothecounterhasafrequencyof1Hz.

�

Togenerateminutesoutputthisinputhastobedividedby60.Thiscan

bedonebyusingamod-60counterorbyusingamod-10andamod-6

counterwitharipplecarrybetweenthem.

�

Togeneratehoursoutputtheminutesoutputhastobedividedby60.

�

Hourscounterisamod-13counterwhoseoutputcanbeusedtogenerate

theAM/PMsignal.

�

Themod-6andmod-10countersgenerateBCDoutput,whereasthe

mod-13countergeneratesbinaryoutputwhichisconvertedtotwoBCD

digits.

�

AM/PMsignalisturnedonoro�eachtimehourscountreaches12.

�

Duringthesettimemodetheminutesandhourscountersaredetached

fromtheirnormalripplecarryinputsandareincrementedbypulseson

theincmandinchinputs.

A

Design

Example:

DigitalAlarm

Clock

8.11

c

August1998

ptb,kr

.

.. 10.. 6 .. 10.. 6

MUXMUX

..

Minutes SecondsHoursam_pm(not displayed)

1 4 3 4 3 4

inc_h inc_m inc_s

CLK

set_time

1 pulse/hour 1 pulse/minute 1 pulse/second

13Block diagram of Time Counter


.

clkMOD-6

carry-out

Q2 Q1 Q0

Schematic diagram of Mod-6 Counter


.

MO

D-10

carry-outclk

Q3

Q2

Q1

Q0

Schematicdiagram

ofMod-10Counter

A

Design

Example:

DigitalAlarm

Clock

8.14

c

August1998

ptb,kr

.

MO

D-13 (B

CD

)

clk

carry-out

Qt0

Q3

Q2

Q1

Q0

Schematicdiagram

ofMod-13Counter

A

Design

Example:

DigitalAlarm

Clock

8.15

c

August1998

ptb,kr

.

mod-13 mod-6 mod-10 mod-6 mod-10

TIME-CTR

cam_pm

csecs

set_time

cminschrs

clk

inc_s

inc_m

inc_h

Schematic diagram of Time Counter


Alarm Time Block

mins

ALARM TIME

BLOCK

ahrs

amins

aam_pm

CLK

ahrsaminsaam_pmSTATE MACHINE

ALARM

COUNTER

ALARMinc_h

inc_m

mins

hrs

set_alarm5

7

5

7 hrs

set_alarm

CLK


Alarm State Machine:

� This state machine is similar to the time state machine described earlier,

except that it does not generate an inc s signal and that it is active only

during the set alarm mode.

IDLE

set_alarm hrs mins inc_h inc_m

101 01

110 10

conditionsall other

101 00SET_MINS

SET_HRS 110 00



00

01

10


.

ALARM_SM

clk

inc_m

inc_h

Q1

Q0set_alarm

min

hrs

Schematic diagram of Alarm State Machine


Alarm Counter:

� Alarm time counter circuit is a subset of the time counter circuit

described earlier. It has a mod-60 minutes counter and a mod-13 hours

counter. These counters receive their counting pulses from inc m and

inc h inputs.

.. 10.. 6..

MinutesHoursam_pm

1 4 3 4

13

inc_h

inc_m


.

mod-13 mod-6 mod-10

ALARM_CTR

aam_pm aminsahrs

inc_m

inc_h

Schematic diagram of Alarm Counter


ClockandAlarm

TimeMultiplexer

AM

/PMM

inutesH

ours

MU

X

set_alarm

clock_time

alarm_tim

e

A

Design

Example:

DigitalAlarm

Clock

8.22

c

August1998

ptb,kr

BCD-to-7-SegmentConverterandDisplayDriver

DISPL

AY

DR

IVE

RS

BC

D-to-7-SE

GM

EN

T D

EC

OD

ER

gfe

d

c b

a

gf

ed

cb

a

D (1)

C (2)

B (4)

A (8)

A

Design

Example:

DigitalAlarm

Clock

8.23

c

August1998

ptb,kr

Alarm and Clock Time Comparator

clock timealarm time

COMPARATOR equal


Ringer State Machine

� This machine determines when the alarm ringer (audible output for the

speaker) turns on.

� Ringer turns on when alarm is turned on AND the clock time matches

the alarm time. Once the ringer is on, it can only be turned o� by

turning o� the alarm on/o� switch.IDLE WAKEUP

alarm_on equal ring

0

00,01,100

11 1

OSCILLATOR

ring

Speaker Output

0 1

0

1 1


.

RIN

GE

R-SM

alarm_on/off

clk

osc

equal

ring

speaker

Schematicdiagram

ofRingerStateMachine

A

Design

Example:

DigitalAlarm

Clock

8.26

c

August1998

ptb,kr

DigitalAlarm

ClockCircuit

.

alarm-sm

alarm-ctr

ringer-sm

time-ctr

time-sm

alarm_on/off

mins hrs

speaker

alarm_on/off

clk

set time

set alarm

cam_pm

"time-blk"

"alarm-blk"

osc_in alarm_on/off

equal

MU

X

set_alarm

clock_time

alarm_tim

e

A

Design

Example:

DigitalAlarm

Clock

8.27

c

August1998

ptb,kr

SomeSimulationResults

SimulationresultsoftheMod-6counter

A

Design

Example:

DigitalAlarm

Clock

8.28

c

August1998

ptb,kr

SimulationresultsoftheMod-13BCDcounter

A

Design

Example:

DigitalAlarm

Clock

8.29

c

August1998

ptb,kr

.

SimulationresultsoftheAlarm

StateMachine

A

Design

Example:

DigitalAlarm

Clock

8.30

c

August1998

ptb,kr

SimulationresultsoftheRingerStateMachine

A

Design

Example:

DigitalAlarm

Clock

8.31

c

August1998

ptb,kr

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Alaram Clock Dld