AM26C32 Quadruple Differential Line Receiver datasheet

4Y

3Y

2Y

1Y

4B

4A

3B

3A

2B

2A

1B

1A

G

G4

12

2

1

6

7

10

9

14

15

3

5

11

13

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

AM26C32SLLS104L –DECEMBER 1990–REVISED OCTOBER 2018

AM26C32 Quadruple Differential Line Receiver

1

1 Features1• Meets or Exceeds the Requirements of ANSI

TIA/EIA-422-B, TIA/EIA-423-B, and ITURecommendation V.10 and V.11

• Low Power, ICC = 10 mA Typical• ±7-V Common-Mode Range With ±200-mV

Sensitivity• Input Hysteresis: 60 mV Typical• tpd = 17 ns Typical• Operates From a Single 5-V Supply• 3-State Outputs• Input Fail-Safe Circuitry• Improved Replacements for AM26LS32 Device• Available in Q-Temp Automotive

2 Applications• High-Reliability Automotive Applications• Factory Automation• ATM and Cash Counters• Smart Grid• AC and Servo Motor Drives

3 DescriptionThe AM26C32 device is a quadruple differentialline receiver for balanced or unbalanced digitaldata transmission. The enable function iscommon to all four receivers and offers a choiceof active-high or active-low input. The 3-stateoutputs permit connection directly to a bus-organized system. Fail-safe design specifies thatif the inputs are open, the outputs always arehigh. The AM26C32 devices are manufacturedusing a BiCMOS process, which is a combinationof bipolar and CMOS transistors. This processprovides the high voltage and current of bipolarwith the low power of CMOS to reduce the powerconsumption to about one-fifth that of thestandard AM26LS32, while maintaining AC andDC performance.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)AM26C32N PDIP (16) 19.30 mm × 6.35 mmAM26C32NS SO (16) 10.20 mm × 5.30 mmAM26C32D SOIC (16) 9.90 mm × 3.90 mmAM26C32PW TSSOP (16) 5.00 mm × 4.40 mmAM26C32J CDIP (16) 21.34 mm × 6.92 mmAM26C32W CFP (16) 10.16 mm × 6.73 mmAM26C32FK LCCC (20) 8.90 mm × 8.90 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Simplified Schematic

http://www.ti.com/product/am26c32?qgpn=am26c32

http://www.ti.com/product/AM26C32?dcmp=dsproject&hqs=pf

http://www.ti.com/product/AM26C32?dcmp=dsproject&hqs=sandbuy&#samplebuy

http://www.ti.com/product/AM26C32?dcmp=dsproject&hqs=td&#doctype2

http://www.ti.com/product/AM26C32?dcmp=dsproject&hqs=sw&#desKit

http://www.ti.com/product/AM26C32?dcmp=dsproject&hqs=support&#community

2

AM26C32SLLS104L –DECEMBER 1990–REVISED OCTOBER 2018 www.ti.com

Product Folder Links: AM26C32

Submit Documentation Feedback Copyright © 1990–2018, Texas Instruments Incorporated

Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions....................... 46.4 Thermal Information ................................................. 46.5 Electrical Characteristics........................................... 56.6 Switching Characteristics .......................................... 56.7 Typical Characteristics .............................................. 6

7 Parameter Measurement Information .................. 78 Detailed Description .............................................. 8

8.1 Overview ................................................................... 88.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 88.4 Device Functional Modes.......................................... 9

9 Application and Implementation ........................ 109.1 Application Information............................................ 109.2 Typical Application ................................................. 10

10 Power Supply Recommendations ..................... 1211 Layout................................................................... 12

11.1 Layout Guidelines ................................................. 1211.2 Layout Example .................................................... 12

12 Device and Documentation Support ................. 1312.1 Receiving Notification of Documentation Updates 1312.2 Community Resources.......................................... 1312.3 Trademarks ........................................................... 1312.4 Electrostatic Discharge Caution............................ 1312.5 Glossary ................................................................ 13

13 Mechanical, Packaging, and OrderableInformation ........................................................... 13

4 Revision History

Changes from Revision K (June 2015) to Revision L Page

• Changed II unit value From: µA To: mA in the Electrical Characteristics table...................................................................... 5

Changes from Revision J (February 2014) to Revision K Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1

Changes from Revision I (September 2004) to Revision J Page

• Updated document to new TI data sheet format - no specification changes ......................................................................... 1• Deleted Ordering Information table. ....................................................................................................................................... 1• Updated Features ................................................................................................................................................................... 1• Added ESD Warning .............................................................................................................................................................. 3


http://www.ti.com


http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=SLLS104L&partnum=AM26C32

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

4A

4Y

NC

G

3Y

1Y

G

NC

2Y

2A

1A

1B

NC

3B

3A

4B

2B

GN

D

NC

CC

V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1B

1A

1Y

G

2Y

2A

2B

GND

VCC

4B

4A

4Y

G

3Y

3A

3B

3

AM26C32www.ti.com SLLS104L –DECEMBER 1990–REVISED OCTOBER 2018


Submit Documentation FeedbackCopyright © 1990–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

D, N, NS, PW, J or W Package16-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP

Top ViewFK Package20-Pin LCCC

Top View

(1) NC – no internal connection.

Pin FunctionsPIN

I/O DESCRIPTIONNAME LCCC SOIC, PDIP, SO,

TSSOP, CFP, or CDIP1A 3 2 I RS422/RS485 differential input (noninverting)1B 2 1 I RS422/RS485 differential input (inverting)1Y 4 3 O Logic level output2A 8 6 I RS422/RS485 differential input (noninverting)2B 9 7 I RS422/RS485 differential input (inverting)2Y 7 5 O Logic level output3A 13 10 I RS422/RS485 differential input (noninverting)3B 12 9 I RS422/RS485 differential input (inverting)3Y 14 11 O Logic level output4A 18 14 I RS422/RS485 differential input (noninverting)4B 19 15 I RS422/RS485 differential input (inverting)4Y 17 13 O Logic level outputG 5 4 I Active-high selectG 15 12 I Active-low selectGND 10 8 — Ground

NC (1)

1

— — Do not connect61116

VCC 20 16 — Power Supply


http://www.ti.com



4




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to the network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVCC Supply voltage (2) 7 V

VI Input voltageA or B inputs –11 14

VG or G inputs –0.5 VCC + 0.5

VID Differential input voltage –14 14 VVO Output voltage –0.5 VCC + 0.5 VIO Output current ±25 mATstg Storage temperature -65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVCC Supply voltage 4.5 5 5.5 VVIH High-level input voltage 2 Vcc VVIL Low-level input voltage 0 0.8 VVIC Common-mode input voltage -7 +7 VIOH High-level output current –6 mAIOL Low-level output current 6 mA

TA Operating free-air temperature

AM26C32C 0 70

°CAM26C32I –40 85AM26C32Q –40 125AM26C32M –55 125

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1)AM26C32

UNITD (SOIC) N (PDIP) NS (SO) PW (TSSOP)16 PINS 16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 73 67 64 108 °C/W


http://www.ti.com



http://www.ti.com/lit/pdf/spra953

5




(1) All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.(2) The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-

mode input voltage.

6.5 Electrical Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT

VIT+Differential input high-thresholdvoltage

VO = VOH(min), IOH = –440µA

VIC = –7 V to 7 V 0.2V

VIC = 0 V to 5.5 V 0.1

VIT–Differential input low-thresholdvoltage VO = 0.45 V, IOL = 8 mA

VIC = –7 V to 7 V –0.2 (2)V

VIC = 0 V to 5.5 V –0.1 (2)

Vhys Hysteresis voltage (VIT+ – VIT−) 60 mVVIK Enable input clamp voltage VCC = 4.5 V, II = –18 mA –1.5 VVOH High-level output voltage VID = 200 mV, IOH = –6 mA 3.8 VVOL Low-level output voltage VID = –200 mV, IOL = 6 mA 0.2 0.3 V

IOZOFF-state (high-impedance state)output current VO = VCC or GND ±0.5 ±5 µA

II Line input currentVI = 10 V, Other input at 0 V 1.5 mAVI = –10 V, Other input at 0 V –2.5 mA

IIH High-level enable current VI = 2.7 V 20 μAIIL Low-level enable current VI = 0.4 V –100 μAri Input resistance One input to ground 12 17 kΩICC Quiescent supply current VCC = 5.5 V 10 15 mA

(1) All typical values are at VCC = 5 V, TA = 25°C.

6.6 Switching Characteristicsover operating free-air temperature range, CL = 50 pF (unless otherwise noted)

PARAMETER TEST CONDITIONSAM26C32CAM26C32I

AM26C32QAM26C32M UNIT

MIN TYP (1) MAX MIN TYP (1) MAXtPLH Propagation delay time,

low- to high-leveloutput

See Figure 2

9 17 27 9 17 27 ns

tPHL Propagation delay time,high- to low-leveloutput

9 17 27 9 17 27 ns

tTLH Output transition time,low- to high-leveloutput

See Figure 2

4 9 4 10 ns

tTHL Output transition time,high- to low-leveloutput

4 9 4 9 ns

tPZH Output enable time tohigh-level

See Figure 3

13 22 13 22 ns

tPZL Output enable time tolow-level

13 22 13 22 ns

tPHZ Output disable timefrom high-level

See Figure 3

13 22 13 26 ns

tPLZ Output disable timefrom low-level

13 22 13 25 ns


http://www.ti.com



±1

0

1

2

3

4

5

6

0 10 20 30 40 50

Out

put

Vol

tage

- V

Logic Input Current - mA

HIGHLOW

C001

6




6.7 Typical Characteristics

Figure 1. Output Voltage vs Input Current


http://www.ti.com



TEST CIRCUIT

Device

Under

Test

G Input

G Input

VCCS1

RL = 1 kΩ

CL = 50 pF

(see Note A)

VID = ±2.5 V

VOLTAGE WAVEFORMS

tPZL, tPLZ Measurement: S1 to VCC

tPZH, tPHZ Measurement: S1 to GND

1.3 VG

G

(see Note B)

Output

(with VID = 2.5 V)

Output

(with VID = −2.5 V)

tPZH tPHZ tPZH tPHZ

tPZL tPLZ tPZL tPLZ

VOH −0.5 V

VOL + 0.5 V

VOH −0.5 V

VOL + 0.5 V

3 V

0 V

3 V

0 V

VOH

VOL

VOH

VOL

1.3 V

50%

50%

A Input

B Input

TEST CIRCUIT VOLTAGE WAVEFORMS

0 V

Output

VOH

VOL10%

90%90%

10%

tTLH tTHL

tPLHtPHL

2.5 V

−2.5 V

50%

Input

Device

Under

Test

A

B

VCC

CL = 50 pF

(see Note A)Input

7




7 Parameter Measurement Information

A. CL includes probe and jig capacitance.

Figure 2. Switching Test Circuit and Voltage Waveforms

A. CL includes probe and jig capacitance.B. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf

= 6 ns.

Figure 3. Enable/Disable Time Test Circuit and Output Voltage Waveforms


http://www.ti.com



Input

VCC

EQUIVALENT OF A OR B INPUT TYPICAL OF ALL OUTPUTS

Output

VCCVCC

1.7 kΩ

NOM

GND GND

1.7 kΩ

NOM17 kΩ

NOM

288 kΩ

NOM

VCC (A inputs)

or

GND (B inputs)

Input

GND

EQUIVALENT OF G OR G INPUT

8




8 Detailed Description

8.1 OverviewThe AM26C32 is a quadruple differential line receiver that meets the necessary requirements for NSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or low voltageMCU to interface with heavy machinery, subsystems and other devices through long wires of up to 1000m, givingany design a reliable and easy to use connection. As any RS422 interface, the AM26C32 works in a differentialvoltage range, which enables very good signal integrity.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 ±7-V Common-Mode Range With ±200-mV SensitivityFor a common-mode voltage varying from -7V to 7V, the input voltage is acceptable in low ranges greater than200 mV as a standard.

8.3.2 Input Fail-Safe CircuitryRS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is notdefined and can randomly assume high or low. Removing the uncertainty of random output states, moderntransceiver designs include internal biasing circuits that put the receiver output into a defined state (typically high)in the absence of a valid input signal.

A loss of input signal can be caused by an pen circuit caused by a wire break or the unintentional disconnectionof a transceiver from the bus. The AM26C32 has an internal circuit that ensures functionality during an idle bus.

8.3.3 Active-High and Active-LowThe device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enablesactive low operation. These are simply a way to configure the logic to match that of the receiving or transmittingcontroller or microprocessor.

8.3.4 Operates from a Single 5-V SupplyBoth the logic and receivers operate from a single 5-V rail, making designs much more simple. The line driversand receivers can operate off the same rail as the host controller or a similar low voltage supply, thus simplifyingpower structure.


http://www.ti.com



9




8.4 Device Functional Modes

8.4.1 Enable and DisableThe receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled ordisabled. This allows users to ignore or filter out transmissions as desired.

Table 1. Function Table (Each Receiver)DIFFERENTIA

L INPUT ENABLES OUTPUT

A/B G G Y

VID ≥ VIT+H X HX L H

VIT < VID <VIT+

H X ?X L ?

VID ≤ VIT-H X LX L L

X L H Z


http://www.ti.com



DIND

AM26C31

(One Driver)

D

RT

AM26C32

(One Receiver)

ROUT

10




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationWhen designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,proper cable termination is essential for highly reliable applications with reduced reflections in the transmissionline. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end of thecable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors toconsider when determining the type of termination usually are performance requirements of the application andthe ever-present factor, cost. The different types of termination techniques discussed are unterminated lines,parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each terminationtechnique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly, RS-485). Similar results can be obtained if 485-compliant devices and termination techniques are used. Forlaboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver andreceiver, TI AM26C31C and AM26C32C, respectively, were tested at room temperature with a 5-V supplyvoltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and thebottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections, thefirst plot shows output waveforms from the driver at the start of the cable; the second plot shows input waveformsto the receiver at the far end of the cable.

9.2 Typical Application

Figure 4. Differential Terminated Configuration

9.2.1 Design RequirementsResistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary fromsystem to system. For example, the termination resistor, RT, must be within 20% of the characteristic impedance,Zo , of the cable and can vary from about 80 Ω to 120 Ω.

9.2.2 Detailed Design ProcedureFigure 4 shows a configuration with no termination. Although reflections are present at the receiver inputs at adata signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the inputdifferential voltage and produces a clean signal at the output.


http://www.ti.com



±3

±2

±1

0

1

2

3

4

5

0 0.1 0.2 0.3 0.4 0.5

Vol

tage

(V

)

Time (s)

Y A/B

C001

11




Typical Application (continued)9.2.3 Application Curve

Figure 5. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)


http://www.ti.com



AM26C32

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1B

1A

1Y

G

2Y

2A

2B

GND

VCC

4B

4A

4Y

G

3Y

3A

3B

0.1µF

VDD

Termination Resistor

Reduce logic signal trace

when possible

12




10 Power Supply RecommendationsPlace 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies.

11 Layout

11.1 Layout GuidelinesFor best operational performance of the device, use good PCB layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the

operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedancepower sources local to the analog circuitry.– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effectivemethods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digitaland analog grounds, paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. Ifit is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular asopposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the invertinginput minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 6. Trace Layout on PCB and Recommendations


http://www.ti.com



13




12 Device and Documentation Support

12.1 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

12.2 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.3 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


http://www.ti.com



http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://e2e.ti.com

http://support.ti.com/

http://www.ti.com/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 26-Mar-2022

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

5962-9164001Q2A ACTIVE LCCC FK 20 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001Q2AAM26C32MFKB

5962-9164001QEA ACTIVE CDIP J 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QEAAM26C32MJB

5962-9164001QFA ACTIVE CFP W 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QFAAM26C32MWB

AM26C32CD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 26C32

AM26C32CDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 AM26C32C

AM26C32CN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN

AM26C32CNE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 AM26C32CN

AM26C32CNSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C32

AM26C32CNSRG4 ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 26C32

AM26C32ID ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDE4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

http://www.ti.com/product/AM26C32M?CMP=conv-poasamples#samplebuy



http://www.ti.com/product/AM26C32?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/AM26C32C?CMP=conv-poasamples#samplebuy















Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

AM26C32IDRG4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AM26C32I

AM26C32IN ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 AM26C32IN

AM26C32INSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32IPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 26C32I

AM26C32MFKB ACTIVE LCCC FK 20 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001Q2AAM26C32MFKB

AM26C32MJB ACTIVE CDIP J 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QEAAM26C32MJB

AM26C32MWB ACTIVE CFP W 16 1 Non-RoHS& Green

SNPB N / A for Pkg Type -55 to 125 5962-9164001QFAAM26C32MWB

AM26C32QD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q

AM26C32QDG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 26C32Q

AM26C32QDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AM26C32Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
















Addendum-Page 3

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AM26C32, AM26C32M :

• Catalog : AM26C32

• Enhanced Product : AM26C32-EP, AM26C32-EP

• Military : AM26C32M

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

http://focus.ti.com/docs/prod/folders/print/am26c32.html

http://focus.ti.com/docs/prod/folders/print/am26c32-ep.html

http://focus.ti.com/docs/prod/folders/print/am26c32-ep.html

http://focus.ti.com/docs/prod/folders/print/am26c32m.html



Addendum-Page 4

• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

AM26C32CDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

AM26C32CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

AM26C32CNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

AM26C32IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

AM26C32INSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

AM26C32IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

AM26C32QDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

AM26C32CDBR SSOP DB 16 2000 853.0 449.0 35.0

AM26C32CDR SOIC D 16 2500 340.5 336.1 32.0

AM26C32CNSR SO NS 16 2000 853.0 449.0 35.0

AM26C32IDR SOIC D 16 2500 340.5 336.1 32.0

AM26C32INSR SO NS 16 2000 367.0 367.0 38.0

AM26C32IPWR TSSOP PW 16 2000 367.0 367.0 35.0

AM26C32QDR SOIC D 16 2500 350.0 350.0 43.0




TUBE


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)

5962-9164001Q2A FK LCCC 20 1 506.98 12.06 2030 NA

5962-9164001QFA W CFP 16 1 506.98 26.16 6220 NA

AM26C32CD D SOIC 16 40 507 8 3940 4.32

AM26C32CDE4 D SOIC 16 40 507 8 3940 4.32

AM26C32CN N PDIP 16 25 506 13.97 11230 4.32

AM26C32CN N PDIP 16 25 506 13.97 11230 4.32

AM26C32CNE4 N PDIP 16 25 506 13.97 11230 4.32

AM26C32CNE4 N PDIP 16 25 506 13.97 11230 4.32

AM26C32ID D SOIC 16 40 507 8 3940 4.32

AM26C32IDE4 D SOIC 16 40 507 8 3940 4.32

AM26C32IDG4 D SOIC 16 40 507 8 3940 4.32

AM26C32IN N PDIP 16 25 506 13.97 11230 4.32

AM26C32IPW PW TSSOP 16 90 530 10.2 3600 3.5

AM26C32IPWG4 PW TSSOP 16 90 530 10.2 3600 3.5

AM26C32MFKB FK LCCC 20 1 506.98 12.06 2030 NA

AM26C32MWB W CFP 16 1 506.98 26.16 6220 NA

AM26C32QD D SOIC 16 40 505.46 6.76 3810 4

AM26C32QDG4 D SOIC 16 40 505.46 6.76 3810 4




www.ti.com

PACKAGE OUTLINE

C

8.27.4 TYP

14X 1.27

16X 0.510.35

2X8.89

0.15 TYP

0 - 10

0.30.1

2.00 MAX

(1.25)

0.25GAGE PLANE

1.050.55

A

10.410.0

NOTE 3

B 5.45.2

NOTE 4

4220735/A 12/2021

SOP - 2.00 mm max heightNS0016ASOP

NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

1 16

0.25 C A B

98

PIN 1 IDAREA

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 1.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAXALL AROUND

0.07 MINALL AROUND

14X (1.27)

(R0.05) TYP

(7)

16X (1.85)

16X (0.6)

4220735/A 12/2021


NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

OPENINGSOLDER MASK METAL

SOLDER MASKDEFINED

LAND PATTERN EXAMPLESCALE:7X

SYMM

1

8 9

16

SEEDETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

(7)(R0.05) TYP

16X (1.85)

16X (0.6)

14X (1.27)

4220735/A 12/2021


NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:7X

SYMM

SYMM

1

8 9

16

www.ti.com

PACKAGE OUTLINE

C

14X 0.65

2X4.55

16X 0.300.19

TYP6.66.2

1.2 MAX

0.150.05

0.25GAGE PLANE

-80

BNOTE 4

4.54.3

A

NOTE 3

5.14.9

0.750.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016ASMALL OUTLINE PACKAGE

4220204/A 02/2017

1

89

16

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153.

SEATINGPLANE

A 20DETAIL ATYPICAL

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAXALL AROUND

0.05 MINALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 10X

SYMM

SYMM

1

8 9

16

15.000

METALSOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSED METALEXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP


4220204/A 02/2017

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

SYMM

1

8 9

16

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

0°–8°

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements.These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2022, Texas Instruments Incorporated

https://www.ti.com/legal/termsofsale.html

https://www.ti.com