AMIE Study Material & Admission Packages AMIE(I) Study ... · Construct the FSM model for!, = xn-r+ xn (r) Design aMOD-5 synchronouscounterusing Tflip-flops. (c) Derive the characteristic

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S'16: 5 AN: CP 4O5/EC 422 (14501

PULSE AND DIGITAL CIRCUITS

Time : Three hours

Maximum Marlcs: 100

Ansu,er plvp, auestions. takins ANYTwo r?orn Groun A.ANy rwo/o m Groip B a;d e* froinGroup C

All parts of a questiqn ( a, b, _etc. \ skauld beanswered at one place-

Answer should be brief and to-the-point and be supple-mented with neat slcctches. Unnecessary long answei may

result in loss of marl<s.

Any missing or.yrong datu lnay-pe assumed suitablygiv in g p roper j us tiJi c at ion.

Figures on the righthand side margin indicatefull marks"

Group A

1. (a) Define (i) Product-of-Sums (PoS) form and (ir)Sum-of-Products (SoP) form. 3 + 3

(6) SimplifythefollowingBoolean frrnctiontominimumnumberofliterals: 5

eEc+enc

(c) Minimize the following switchingfirnctionsusingKamaughmap: I

p =l(2,t,8, 14,1 5) + f a(0,:,ro)

2. (c) Conveft (n:+),u todecimaf octalandbinaryforms. 6

(Tumtur)


33

(4 Whyure NAND andNOR gates called universalgates ? Irrplernent Ex-OR gate with minimumntnnber ofNA}{D gdes only.

(4 Devetrop SoP expression for Fl " F2 and F3 in the

table$ovrnbelow:Ou@ts

lrnplelinent the following expression using a single4:l multiplexer:

r:(/, B, ci)--frr{Ul4,G,7\ ICI

Implenrurt afirll rxldercircuit using PLA having[m:e.inputs"eigfutpnoduciternnsaudtu'o outputs" l0

What is FROIvn ? Draw the block diagram of aPR0il{anddescribeitsfirnctions. 3

@ Simplifi the following Booleanfrurction r:sing Iabu-larrnethod: 10

Y (A, B,c, D) = Z * (1,2,3,5,9,12,1 4, I 5) +

a(+,t,tt)Group B

5. ta) What do you mean by finite-state machine (FSM)model ? Construct the FSM model for

!, = xn-r+ xn

(r) Design aMOD-5 synchronouscounterusing Tflip-flops.

(c) Derive the characteristic equation

Q,*t=Srnr * R^rQ.

forS-Rflip-flop.

Design a serial binary adder using D-flip-flop.

Design a circuit to generate the sequence (usingJ-Kflip-flop) 0-+ 2-+5-+4-+ 7 repeatedly.

Design an asynchronous sequential circuit with trvoinputs I, and I, rmd one output, z. lnitially bothinputsareequallo0. When i, changesfrom0to l,z becomes 1" When I, changes from tl ta 1, zbecomes 0, otherwise 2 is 0. Realize the circuituingJ-Kt}pflop.

7. Construct a transition graph that recognizes the set (i)1(00)'r.0 and (il) (o+o1t+00)'1). 10 + 10

8. (a) Draw the state transition graph for the sequentialmachine with binary inputx and binary output z . _

dehned in the table belovr' : 10

Inputtrz000.001010

-0 I It 00l0tI t0't I I

FI

0

0

I

I

I

0

1

I

FZ F3

0l11rll000t01l0l

6

83" (a)

4" (4

6. (a)

(b)

(&)(c)

(.&) Defrrrc tlre tenri 'prirne irnplicants' and 'essentialpirneirnplicant'"Holvdottrc-vaff,irtdigital dcsign ? 3

(s) Describe some popular fault diagnosis and testingtedniqnesf,ordigitalcfucuits. 4

5'16 : 5 AN : CP{&iiBC42? (l{50} ( ? ) l(ontiaucd)

S'tr6 : 5AN : CP405/EC 422 (1450) ( 3 ) (Turnb'er)


34

x=0 x=lC,O D,IC,O A, IA,1 B,OB,O C,1

(u) Thecharrcteristicequ*ionofaTflipflopisgivenby

ABCD

(a) Q. =78+rA

(c) Q. =TQ

(a) 20MHz

1i1 s ltuz

stable statres :

(c4 t

(c) o

5"16 : 5 AN : CP405/8C422 (1450)

(b) g =rQ+N

(q Q. =rA

(b) Realizethemachinebyaschematicdiagr'anL l0

Group C

9. Choosethe correctalrswetforthefollowing: l0 x 2

(, Which one ofthe following uses the least power :

(D)ECL

(d)Alluse samepower.

(vr) A 4-bit MOD- 16 ripple counter uses a J-K flip-flop. If the pnrpagation delay of eaoh fl ipflop is50 mq the maxirnum clock frequenry is equal to

(a) TTL

(c) CMoS

(D) l0 Mrtu

(d)4M*Iz

{b)2

(dlAllthethreeabove.

(ir) The minimum nu4gber o;!NA}{D gates required toimplement a + aB + agC is equal to

(r'ii) How many flipflops are required for dividing thefrequencybyd4 ?

(a) 4 (b,5 (c) 6 (dls

(vriil) An r-stnge ripple counter can count r,ry to

(a| 2" (D) 2" -l (c) n (d) 2*'

(r.r) 'Ilre durationnf the output pulse ofa monostablemtiltivibrdor is given by

(a) r'=0.693RC

@) r:0"693(4 +ZR IC(r) Morxx;tablernr.rltivibratorhasfollowingnmoberof

(a) o (D)1 (c)4 (47

(iir) Which one ofthe following circuit is a parallel-to-' serialconverter?

(a) Digitalcounter (b)Decoder

(c) Denrultiplexer (@Mulliplexer

(iv) An R-S latch is a

(a) combinationalcircuit.

(b) synchronous sequential circuit.

(c) one-bitmemorycircuit.

(d1 one clock delaY element.

S'16 : 5 AN : CP 405/EC 422 (1450) ( 4 ) (Continued)

{ s } AG-no0


35

W'1 6; 5 AN: CP 405lEt: 11,22 (1450)

PULSE AND DIGtrTAI, CIRCT}ITS

Thne : Threc ltours

Iulaximunt lulcirhq : l0A

Artsv,er FIVE quesliorts, takingnNY Two Jiom Group A,r\NY rwafronz Group B and. tLL fi'ont Group C,

A t t p ar r s { :.?:lzi.!,ri'i,(,?;,u; fl f ;)

s h o u t d b e

Ans **er should be brief and to-the-point and be supple-mented with neat ',1:';#;,Yx":ir;;rx tons an$ryer mov

Any missing olyrong data lnqy ^be a.ssumed suitably

SNtn g proper J us t u tc ot rcn.

Figures on the right-hand side margin indicate full marlu.

Group A

l. (a) State andproofdistibutive law. 6

(b) Prove the follorving Boolean theorem :

AB +ZC - (A+q(Z+ B) 6

(c) Simplifythe Boolean expression using K-map

Y (A, B,c, D) =\m(0,1, 2,3,4,5, 6, I l) 8

2. (a) hnplement the follor,ving combinational logiccircuitsusingmultiplexer: 6 + 6

(,) Half-adder

(i,) Half-subtractor

(Turn Over)

f


36

(b) lmplement the following expression using a single4: I multipler<er:

Y (A, B,c)- I * (0,1, 4,6,7)

3. (a) A combinational circuit is defined by the functions :

n(A,B,c)- X(3,s, 6,7)

F,(A,B,c)- I (a,2,4,7)

Implement the circuit rvith a PLA having rlrreeinputs, four product terms and two outputs.

(b) What is the difference between canonical lbnrr iur<lstandard form ofany Boolean cxprcssion ? Explainwithexarnple.

1. (a) What is ROM ? Drarvthe Iogic constnrction of a32 x 4 ROM and explain. 4 +-8

(b) Describe quad logic and also explainthe diffcrcncc:between hazard and hazard-fiee designs. 8

Group B i

5. (a) What is the difference between truth tablc arrdexcitationtable ? 4

(A) Design and irnplbment a MOD-5 synchronouscounter using J-K flip-flbp. 12

(c) What are the asynchronous input of a flip-flopand its output at diflerent inputs ? , 4

6. (a) Design a clocked sequential circuit using J-Kflip-flop for the state diagrarn shown below : 14

0/0

(1r) Write the charactcristic cquation of S-R, .I-K, D\"'" *Af-niP-flop. 6

7. (a\ Design an asyltcfirolous circuit with trvo i.nputs

i, *? I, a.clbpc otttput, z. Initially both the inputs

ui" "qui,l

to z.cro. Wltenl, 9t I, becotnes 1, zULto*"- 1. Wlr,:n tttc second inilut goes 1o i' the

oirtput clt:tttgcs 1l'o;1 I to 0. The oytput stays at 0

"irtif t6o cir'-cuit goes back to (0,0)- Realize the

circt,it using D-flif-floP. 12

Define state table and state diaEam and explain' 8

What is static and dynamic Hazard's ? 6

Draw ancl explain the pulse rnode sequential circuit. 6

I-tow to retnove the essential hazard? Explain ' 6

@ What is the difference between combinationalcircuit;J;;qiiliill circuit? 2

GrouP C

g. Clroose the correcl answer for the following : 1 0 x 2

(r) Which ofthe following logic is the fastest ?

(a) TTL (b) ECL (c) CMoS (d) LSI

14

(b)

8. (a)

(b)

(')

W'16:5AI.i : CP405/EC422 (1450) (2, (Continued) W'16 : 5 AN : CI' 405/EC 422 045A) ( 3 ) (Ttu'nOver)


37

(rr) The logic expressiori I/ = A -r tln is r:cluivalclit to

(a) Y=AB

(c) Y=A+ti @)V,=A+B

(rO Which of the following cirq:uit is a parallel toserial converter ?

(a) digtal counter (2,) dccodcr

(c) demultiplexer (C)n:ultiplexer

(iv) The number of flip-tlops required to truild aMOD-15 counter is

(a) 4 (b) 5

(v) FIou'rnuury flip-flop are required for dividing thefrequency by 64 ?

(a) 4 (D) 5

(vf) A hazardis created due to

(a) Noisemargin

(b) Propagation delay

(c) Setuptime

(d) Holdtime

(c) 6 (d) 8

(vff) Bistable multivibrator has the following number

(vtii) Algorithmic state nrachines (ASM) is a

(a) conrbinational circuit

(b) sequentialcircuit

(rr) Scrial Adder is a

(a) combinationalcircuit

(b) sequentialcircuit

(x) The dr:ration of the output pulse of a monostablemuitivibrator is given bi

(a) T:0.693(& +ZRr)C

(h) 7' -0.693 RC.

(c) 6 (d) 7

ofstate

(") I

(c) o

W'16 : 5AN : CP405/EC 422(1450)

(b)2

(d) None ofthese

( 4 ) (Continued)W'16 : 5 AN : CP 405lEC 422 (1450) ( s ) AG-900


38

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AMIE Study Material & Admission Packages AMIE(I) Study ... · Construct the FSM model for!, = xn-r+ xn (r) Design aMOD-5 synchronouscounterusing Tflip-flops. (c) Derive the characteristic