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Lehigh UniversityLehigh Preserve
Theses and Dissertations
1991
An analysis of propagation delay performanceversus second-order parasitic effects for a 1.25micron CMOS line driverJames M. VelopolcakLehigh University
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This Thesis is brought to you for free and open access by Lehigh Preserve. It has been accepted for inclusion in Theses and Dissertations by anauthorized administrator of Lehigh Preserve. For more information, please contact [email protected].
Recommended CitationVelopolcak, James M., "An analysis of propagation delay performance versus second-order parasitic effects for a 1.25 micron CMOSline driver" (1991). Theses and Dissertations. 5526.https://preserve.lehigh.edu/etd/5526
AN ANALYSIS OF PROPAGATION DELAY PERFORMANCE
VERSUS SECOND-ORDER PARASITIC EFFECTS FOR A
1.25 MICRON CMOS LINE DRIVER
by
James M. Velopolcak
A Thesis
Presented to the Graduate Committee
of Lehigh University
in candidacy for the degree of
Master of Science
in Electrical Engineering
Lehigh University
1991
Cenificatc of Approval
This thesis is accepted and approved in partial
fulfillment of the requirements for the degree of
Master of Science
.i/µµL (date)
·Cbainnan of Department
ii
ACKNOWLEDGEMENTS
Special thanks goes to my family, whose encouragement through
difficult times made my task much easier. In addition, thanks is
extended to Rene Rodriquez for his assistance in the development
of a routine to track 1/V parameters to test data on a per reticle basis.
Finally, I would like to take the opportunity to thank all those at
AT&T Microelectronics whose names are too numerous to mention
but whose assistance has been invaluable .
. . . 111
CONTENTS
ABSTRACT 1 1. INTRODUCTION 3
1.1 Scope of this Thesis 5 1.2 Background of Research on Propagation Speeds 6
2. BODY 8 2.1 S trucure of the MOS FET 8 2.2 First Order Equations for A MOSFET 10 2.3 First Order Propagation Delay Equation 14 2.4 Mobility Degradation Due To Velocity Saturation/Surface Scattering 18 2.5 Propagation Delay Equation- Analytical Model in Saturation 22 2.6 Modified Saturation Drain Currents 26 2. 7 Capacitance Effects 28 2.8 Effect of Series Parasitic Resistance 33 2.9 Effect of Interconnection 41 2.10 Interconnection Propagation Delay of 4-Stage Cascaded Inverters 47 2.11 Test Circuit Schematic 48 2.12 Final Propagation Equation with Second Order Effects 52
3. EXPERIMENT AL RESULTS 54 3.1 Fabrication 54 3.2 Test Description and Environment 56 3.3 Results 60 3.4 Future Work 62 CONCLUSIONS 63
REFERENCES 7 6 VITA 79
....
. lV
LIST OF FIGURES
Figure 1. CMOS Device Structure Figure 2. MOS Device Region of Operation
Figure 3. Equivalent Circuit for Inverter Switching
Figure 4. Velocity Saturation Curve
Figure 5. Gate Level Capacitances Figure 6. Diffusion Capacitances Figure 7. Model of Series Resistance Figure 8. Analytical Model for Equation Development
Figure 9. Doping Versus Resistivity Curves
Figure 10. Interconnect Equivalent Circuit
Figure 11. Interconnect Cross Section Figure 12. Test Circuit Schematic Figure 13. Takeda-Riken Test Environment Model
Figure 14. Propagation Delay Vs. 1.0u N Test Transistor
Figure 15. Propagation Delay Vs. 1.0X30 N Ion Current
Figur~ 16. Propagation Delay Vs. 1.75u P Channel Length
Figure 17. Propagation Delay Vs. 1.75X30 P Ion Current
Figure 18. P l.75X30 Ion Current Vs. P+ Contact Resistance
Figure 19. N l.OX30 Ion Current Vs. N+ Contact Resistance
Figure 20. N l.OX30 Ion Current Vs. N+ Sheet Resistance
Figure 21. P l.75X30 Ion Current Vs. P+ Sheet Resistance
Figure 22. Propagation Delay (Slow Le) Vs. VDD
Figure 23. Propagation Delay (Nominal Le) Vs. VDD
Figure 24. Propagation Delay (Fast Le) Vs. VDD
V
9 13 17 21 31 32 38 39 40 45 .46 51 58 64 65 66 67 68 69 70 71 72-73 74
LIST OF TABLES
TABLE J. 1.0 Micron Twin-Tub Single Level Metal Process Sequence 59
. Vl
ABSTRACT
Propagation delay in CMOS circuits is becoming increasingly critical with
tightened test specifications and inherent accuracy problems with automated test
equipment. In addition, there are considerations of thennal resistance due to
plastic packaging and leadframes. This thesis will analyze the effects of series
parasitic resistances, mobility de_gradation, channel length, and interconnect on
propagation delay in 1.25 micron CMOS technology.
The introduction of the thesis shall contain preliminary infonnation on
research/experimentation concerning propagation delay with a more detailed
account in section 1.2 of this paper. This is followed by a discussion of key
parameters and their effect ori propagation delays. Finally, an equation for
propagation delay will be developed which extrapolates data from experimental
results of varying channel length, contact resistance, poly sheet resistance, and
power supply voltage.
E·xperimentally, a l .25 micron CMOS line driver is being used as the test
vehicle. Contact resistance shall be varied by utilization of a rapid thermal
anneal, poly sheet resistances are varied by diffusion, and channel length is varied
by the use of a compensated reticle. Data collection is performed by 1/V analysis,
1
Takeda-Riken test set readings, and pspice simulation.s.
In conclusion, actual results were compared against theoretical results and it
was found that contact resistance was the primary parasitic effect in l.25µm
technology. The effects of sheet resistances on propagation delay were found to
be negligible or contradictory to theory as in the case of P+ sheet resistance and
can probably be explained by the sn1all stati~tical sample taken for analysis. The
overall value of propagation delay per gate as determined experimentally agreed
within 15 percent of the values predicted analytically, and this discrepancy was
attributed to the test systems capacitive loading.
2
1. INTRODUCTION
The speed and power dissipation of metal oxide semiconductors (MOS)
very large scale integration (V~SI) circuits are based on· the propagation delay
and power dissipation of a basic gate with appropriate loading conditions. With
technology improving and linesizes going sub-micron, it becomes imperative to
find methods of characterizing/reducing power dissipation and propagation delay
effectively. Transistor parameters, used to physically describe the actual
transistors, including gate oxide thickness, channel length and width, contact
resistances, etc .. are the key factors in detennining propagation delay. Studies
have been ongoing to characterize key parameters and model their effects on
propagation delay. Work by Marvin H. White[lJ developed an analytical
expression for propagation delay in terms of device modeling and fabrication
parameters. Propagation delay was broken into an intrinsic delay, the i~ternal
transit time based on carrier mobility and channel length, and an extrinsic delay
based on capacitive loading and saturation drain currents. New methods of
detennining source and drain resistances have been developed by Paul I. Siciu
and Ralph L. Johnstonl21 which take measurements from many identical (except
that their channel lengths differ by a known amount) MOS transistors, setup
current equations for each, and solve ~hese equations simultaneously to arrive at
s9urce/drain resistance. Mechanisms which degrade speed perfonnance in MOS
3
circuitry having received attention include the velocity saturation of channel
carriers, the effect of series parasitic resistances, the delay associated with
interconnect, channel modulation factors, capacitance effects, and voltage/hot
electron limitations.
4
1.1 Scope of this Thesis
The organiz.ation of the thesis shall flow from a discussion of first and
second order current equations for a metal oxide semiconductor field effect
transistor (MOSFET) to the development of an analytical fonnula for propagation
delay. Emphasis will be placed on development of equations for propagation
delay for the inverter and the incorp·oration of carrier mobility effects, series
parasitic resistance effects, capacitance effects, interconnect effects, and channel
length variation into the equation. The experimental data will then be compared
to the theoretical estimates and conclusions will be drawn.
5
1.2 Background of Research on Propagation Speeds
Many papers in this field were inspired by the effects of scaling on the
performance of MOS circuits. Speed limiting factors are discussed by Kamohara,
Matsuzawa, Wada, and Natoril3J in their work with O.lµm MOSFETs. They have
cited drivability enhancement due to velocity overshoot but on the other hand,
dri vability degradation occurs due to parasitic resistances and mobility
degradation. El-Mansy.l4J has cited velocity saturation, parasitic source-drain
series resistance, finite channel thickness, and hot~carrier effects as the
performance limiters when .scaling devices. Shichijol51 examines the relative
contribution to gain/device current degradation of diffusion resistance, high
perpendicular electric fields, con tact resistance,. and . . 1nvers~on layer
capacitance(when gate oxide thickness is the same as the inversion layer
thickness). Other papers concentrated on one. specific area such as Perera and
Krusius'l6l work on measuring parasitic source-drain resistance for ultra small
devices. Their work shows extrinsic resistance, the res'istance associated with the
source/drain region except for gate-source and gate-drain overlap, to be dominant
when source/drain sizes fall below 0.6µm-0~8µm. Additionally, Ngl71 , and
Baccaranil81 have done research on the spreading resistance due to current
crowding at the end-points of a FET channel and conclude that this effect is non
negligible when device channel lengths become very short. Suciu and Johnstonl21
6
derive an experimental method for extracting source and drain resistance from the
measurements of two or more transistors that are identical except that their gate
lengths differ by a known .amount. Interconnection effects have been studied by
Bakoglul91 with an emphasis on modelling and circuit strategies(use of repeaters,
cascaded inverters, etc ... ) to achieve better propagation delay performance.
Finally, research done by White! 11 showed an actual derivation of propagation
delay which included the effects of mobili"ty degradation. CMOS transistors with
varying channel lengths(0.5 to 40µm) and widths (2 to 128µrn) were used to
calculate static modeling parameters and 1-V characteristics. Two-input nand
gate delay chains were used to determine propagation delay and power dissipation
as a function off abrication parameters.
7
2. BODY
2.1 Strucure of the MOSFET
In MOSFET operation, the channel current is controlled by a voltage
applied at a gate electrode which is isolated from the channel by an insulator.
Referring to figure 1, the gate electrode(nonnally polysilicon or aluminum) is
located above a thin layer of insulator, the gate or thin oxide. The two regions
referred to as the source and drain are areas in the substrate implanted with
dopants(Boron, Phosphorus, Arsenic, and others). The substrate, predominately
silicon, is p-type in our figure. The channel refers to the area between the source
and drain regions for each device with its length and width as shown. Figure 1
represents both an n-type and p-type device fabricated in a p-tub and n-tub
respectively. Also shown are the chanstops which are used to electrically separate
adjoining devices.
8
:l
P-TUB
p-101
~l~
N-TUB
1 010
--------------------
ooa BLANKET 80RON-CHANSTOP , • • .PHOSPHORUS CH:. :1STOP
·• •• BORON GATE
Figure 1. CMOS Device Structure
9
2.2 First Order Equations/or A MOSFET
Before studying propagation delay for CMOS circuitry, some basic
equations for drain current are defined along with their effective region of
operation. MOS transistors have three regions of operation and they are the cut
off region, the linear(triode) region, and the saturation(pentode) region. In cut
off, the drain current is very small(approximately zero) since there are no free
minority carriers(in an n-device, the electrons are the minority carriers). Hence,
when V GS -'- VrE < 0 the drain current becomes,
I iJs==O (1)
where V GS represents the voltage from gate to source, VrE is the threshold
voltage, and IDS is the source to drain. current. As the gate voltage. is increased,
minority carriers, attracted by the positive charge between the gate and source,
concentrate at the surface and a channel is fonned between the source and drain.
The linear region of oper~tion begins when V GS - VrE > V DS > 0. The effective
current then becomes:
Vos2 los = P[(V cs - VrE)Vos -
2 ] (2)
where V DS is the voltage from drain to source, and P represents a processing gain
factor given as:
10
where,
E = permittivity of the gate insulator(farads I cm)
L = channel length W = channel width
2
µe.ff = effective carrier mobility cm v-sec
C0 x = capacitance of the thin oxide(-Pf2
) µm
As the gate voltage i.s further increased, the drain current increases to a level
where the current remains f4irly constant. This region of operation is referred to
as saturation and it occurs when O < V cs - VrE < V 05 . The current is then given
by:
where VrE is termed the threshold voltage and represents the value of the voltage
across the gate and source necessary to induce current flow from the. source to the
drain. The equation for VrE is given below by WestellOJ but not further defined in
detail in this thesis:
where Vr0 is the threshold voltage when Vsb(the substrate ·bias) is zero and
11
Tox ----'Y = -v2qNEs; . Figure 2 shows a CMOS device curve with the three regions of
Eox
operauon.
With the basic equations above, further work on propagation delay is
developed. It is important at this point to know that many second order effects
will be incorporated into these basic equations, but they serve as a good reference
point
12
r
0
IV -VI • ,v I ga I ca
SATURATION REGION '1----------- 1V I ' ga,'
~---------- ,v I ~·
.------------ 1V I 11S?I
---------------- IV I ~
Figure 2. MOS Device Region of Operation
13
2 .3 First Order Propagation Delay Equation
Propagation delay in MOS technology is dominated by the switching speed
of a basic gate, the rise and fall times, and can be approximated accordinglyll lJ
An input transition either results in charging the load capacitance towards V DD,
rise time, or discharging the load capacitance towards V55 , fall time. Intrinsically,
the fall time is faster since the carrier mobility of an n- type transistor is faster
than the .P-type. Before going through the derivation, the following tenns are
defined: Rise Time, trise, is the tin1e for a waveform to rise from 10 percent to 90
percent of .its steady-state value. Fall Time, tfall, is the time for a wavefonn to fall
from 90 percent to 10 percent of its steady-state value. Delay Time, tdelay, is the
time difference belween input transition (50 percent level) and the 50 percent
output level. Initially, the n-device is cut-off and the load capacitor is charg~ to
V DD. With the application of an input voltage from zero to 5 volts, the voltage on
the capacitor begins to drop. The n-dev.ice becomes saturated, the capacitor
voltage is greater than VDD minus the threshold voltage for the ·device, as the
equivalent circuit in Figure 3 shows and continues in this mode until the the
voltage on the capacitor is less than or equal to V DD minus the. threshold voltage
for the device. The n-device will operate in the linear region when the capacitor
voltage becomes equal to or less than (no lower than 0.1 V DD) V DD minus the
threshold voltage for the device. There are two separate time periods to
14
distinguish. The .first, r11 , is the period where the capacitor voltage drops from
0.9VDD to (VDD - V,11
). The second, ti 2, is the period where the capacitor voltage
drops from (V DD - V,11
) to 0.1 VDD. The equivalent circuit equation during
saturation is:
Integrating from 0.9VDD, tl, to (Vvo -V1n), t2 gives:
Solving,
When the n-type device enters linear region, the integration becomes,
dVo V 2
o -V 2(V DD - V,n) o
Solving the integral and combining with the saturation equation,
15
Ci Vrn - 0.1 Voo I 9Vov - 20V tn lfall = 2 ( + 0.51n ) (4)
p,.(Vvv - Vrn) Voo - Vrn Vvv
Due to the symmetry of CMOS circuitry, the rise time is derived in the same
manner and the equation is,
Since the propagation delay in MOS circuits is dominated by the rise and fall
times, the delay will be approximated to the first order by the equation,
lfall + t,ise lpdel =
4 (6)
This equation will be termed the ideal equation for predicting propagation delay
and shall be compared to the analytical model developed later which incorporates
second order effects.
16
,-DEVICE .• T ':o p-DEVICE T"::io
c,_ R~
"'·DEVICE '" I i .... "'-DEVICE
t
ti) LINEAR O <V'J sV::,0 - I/~
":::, 'I ::,o
p-OEVICE !,a, i p-OEVICE R C
t t ~ ~ t •0 C
n-OEVICE Tel VO n-OEVlCE ICL v_
1
-.J
1 (b) SATURATION UNEAA
Figure 3. Equivalent Circuit for Inverter Switching
17
2.4 Mobility Degradation Due To Velocity Saturation/Surface Scattering
With increasing channel doping and higher electric field strengths in
smaller devices, the mobility degradation becomes an important criteria for
determining speed perfonnance. The c_arrier mobility at the Si-SiO 2 interface is
affected by both the parallel and perpendicular electric fields. ll 2l A high
perpendicular electric field at the. interface forces carriers closer to the interface.
Consequently, the increased surface scattering causes a decrease in mobility. At
low electric fields, the effect on mobility can be neglected. From experimental
findings by Sabnis,ll3] the critical electric field for surface scattering (for
electrons) is 4.2.XI05volts /cm. The effects of velocity saturation and surface
scattering on mobility have been analyzed by White with mobility being defined
as:
I I 1 1 -=-+-+-µ µo µs µc
Where µ0 is the bulk mobility in the absence of surface scattering(µ5 ) or velocity
saturation(µc) effects. The effect of velocity saturation on mobility, illustrated in
figure 4 , is approximated as:
18
Where L is the channel length and Sc is the electric field parameter for
longitudinal scattering of carriers in the channel(defined in the equation ). The
effect of surf ace scattering is approximated by:
where £5 and E, are the electric fields corresponding to the Si-Si0 2 interface and
the inversion layer, respectively, and Ks is the ratio of the pennittivities. The
mobility can be detennined with the following ~onditions:
where Qc represents the channel charge for a unifonnly doped substrate and
where Q8 is the bulk_ depletion charge and C0 is the insulator capacitance per unit
area. Hence, the mobility is written as·:
19
µ= (7)
where V is the local potential referenced to the grounded source, <t> is the surfac_e
potential at -strong inversion, Ve; is the gate voltage, V 8 is the substrate voltage, a
represents the body factor(detennines the threshold shift as a function of source to
substrate voltage), and V FB is the flat band voltage. The above equation for
mobility will now be used 1n the next section to fonnulate an equauon for
propagation delay.
20
,as ---
I - I J') - I t: 10' u -- • ITIILJI ->- I ~ .J
'.l)
> J 300 K = c..i 1 0° ~
" u 'I
,as ,02 ,oj 10• 105 106
E.lectnc field 0....,ax , './ cm,
-V')
5 1 2 " 0 .-
·; 1 0 t-----------~---..........J 91
>,. -= 0.8 8 ii > C 0,6 Q -"' ... ::, ; 0.4 (fJ
2.4 X 1Q 7
UsAr= ~------~ 1 + 0.8 exp ( J. 600 K)
100
J (K)
1000
Figure 4. Velocity Saturation Curves
21
2 .5 Propagation Delay Equa(ion- Arzalyrical Model in Saturation
In fonn ulating a model for propagation delay, it is necessary to include the
effects of parasitic capacitances, mobility degradation, velocity saturation,
parasitic resistances, and other second order effects. The effects of mobility
degradation have been analyzed in the last section, and the results from equation 4
will be used throughout this section. In. work by Whitelll , a general expression
for propagation delay for a two input nand gate was developed with the
expression broken into an intrinsic delay(internal transit time delay), and an
extrinsic delay (the charging of the node capacitances). With some modification
for the case of an inverter(the line driver is actually a 4 stage cascaded inverter),
the expression becomes:
where,
22 I
Ln = channel length of n-device. LP= channel length of p-device. v" = carrier velocity of n -device. vp = carrier velocity of p-device. V,n = threshold voltage of n-device. V,p = threshold voltage of p -device. In = saturation drain current for n-device. Ip = saturation drain current for p-device. C1 = load capacitance.
To describe the load capacitance in an analy.tical fashion, we write:
where
M = fanout = 2 in the inverter case. Wn = channel width of n-type device. WP = channel width of p-type device. Ln = channel length of n-type device. Lp = channel length of p-type device. C
0x = oxide capacitance per unit area.
Cp = parasitic capacitance per unit area.
(9)
In White's~11 development of an expression for propagation delay, the gates were
identical in regards to their loading effects and also their channel lengths and
widths and therefore he was able to develop his expression on a per gate basis as
opposed to an aggregate delay. However, ·in the case of the cascaded: inverters
studied in this thesis the channel widths vary through each stage of the cascade.
23
The fallowing exercise shows that as long as the ratios of the n-channel widths to
the p-channel widths remains constant throughout each stage, the expression
developed by White! lJ remains valid and calculations can be made on a per gate
basis. Using a first order approach with equations 8 and 9 and considering the
extrinsic delay only, propagation delay becomes:
neglecting V,n, V,p, and C0 x while approximating I as W, the expression becomes, L .
Solving,
Hence, as long as the ratio of W n to WP remains constant, the delay is a function
of channel length. Equations 8 and 9 take into account the second order effects of
velocity saturation due to critical electric field and of surface scattering due to
high electric fields. However, the effects of interconnect and series parasitic
resistances are not included yet. As will be seen in later sections, the series
24
paras1uc resistances have a n1aJor impact 1n the contact areas(windows, v1as,
etcs ... ) where they reduce the drive current which is necessary to charge the load
capacitance of each inverter stage. In addition, a more thorough understanding of
parasitic capacitances needs to be developed.
25
2 .6 Modified Saturation Drain Currents
The saturation current given in equation 3 is good for a first order
approximation, however, for 1nore accurate estimation the effects previously
studied will be incorporated into the equation. The effects of parasitic series
resistances are included in the terms for en and eP where the drain senes
resistance is not included since the drain has little effect in saturation. The
saturation drain currents are written to provide a continuous transition between
low and high longitudinal eiectric .fields and are given by:
where,r 14l
26
(10)
( 11)
(12)
(13)
where T ox is the gate oxide thickness, Ecn and Ecp are the critical electric fields
for surface scattering, £ox is the dielectric constant of ~e oxide, Es; is the
dielectric constant of silicon, vp.rnr is the sa_turated velocity of holes in the p
device, Rr is the total series resistance as given in equation 22, p is the gain
constant as defined on page 11, and vn.rnr is the saturJted velocity of electrons in
the n-device. As equations 12 and ·13. show, the series resistance degrades the
effective velocity and hence the saturation drain current.
27
2. 7 Capacitance £fleets
Equation 9 included a tenn for parasitic capacitances and these will be further
developed in this section. Cp represents the parasitic capacitance due to
interconnect, overlap, and junction capacitances. Figures 5 and 6 visually
represent the parasitic capacitances present.
where,
In saturation, the intrinsic gate capacitances are:
Cgd = 0
2 A Cgs = -(Eox-)
3 Tux
( 14)
(15)
T 0x = oxide thickness of gate o;xide. A = area of the gate. E
0x = di(!lectric constant = 35.416X 10-,--4
Cgd = gate drqin parasitic capacitance.
( 16)
C gb = gate substrate parasitic capacitance.
C gs =.gate source parasitic capacitance.
The diffusion regions, the source and drain, have a capacitance to substrate
that depends on the voltage between the diffusion regions anq substrate, as well as
the effective area of the depletion region separating diffusion and substrate. Total
diffusion capac.itance can be approximated by the following equation:
28
where,
Cja = junction capacitance per wn 2
C1P = periphery capacitance per wn 2
a = width of diffusion region b = extent of diffusion region
Typical v~lues for C1a and C1p are:
C1a" = IXI0-4 pf !wn2
C1ap = IX 10-4 pf lwn 2
C1p" =9XI0-4 pf!wn2
c)Pp = 8XI0-4 pf lwn2
Hence, in saturation:
(18)
(17)
The above equation includes all the parasitic capacitances which are being
considered in this thesis except the capacitance of interconnect which is
developed in that section. For our case of the 4 stage cascaded inverters, the load
capacitance (described above .as Cp) is the sum of the gate capacitance of other
inputs connected to the output( i.e. the next stage), the diffusion capacitance of
the drain regions connec_ted to the output(i.e. the same stage), and routing
29
capacitance between the output and other inputs.
30
GATE J_
CHANNEL -----'.)E..Pl.ETlON LAYER
::::;:: C h
I IJ __ T _____ __ ------T.s: __
SUBSTRATE
Figure 5. Gate Level Capacitances
31
T •
1 SOURCE
OIFRJSION
o-
SOURCE DIFFUSION
AREA
?OLY
:AAJN ~IFRJSION
:.REA
SUBSTRATE
(a) ~ uos smucruAe
i ,.---------, ~ I I X I I /-------------
Tc~ DEPl.ETION LA~
SIDE VIEW
(b) CAPACfT ANCE REPRESENTATION
T
C j_ J)
co
ORAJN :JIFRJSION 70P VIEW
I J·
I I ,
''I CYUNOER
• •
• P ARAU.EL Pl.A TE /
(c, CAPACfT ANCE MOOE1.
Figure 6. Diffusion Capacitances
32
2 .8 Effect of Series Parasitic Resistance
In order to incorporate the effects of series source"'drain resistances in the
equation for propagation delay, a n1odel to analyze parasitic resistances is
presented. The different con1ponents of series resistance was shown by Ng and
Lynchl7J in figure 7 to be contact resistance(Rc0 ), diffusion sheet resistance(R.,.n),
spreading resistance(Rsp ), and a cc urn ulation layer resistance(Roc ). The contact
resistance is defined as the resistance between the top metal and the diffusion
underneath the leading edge of the contact. The sheet resistance is proportional to
the spacing between the contact and gate and can be ignored if the source/drain is
-silicided and self-aligned to the gate. The spreading and accumulation layer
resistances are defined by Ng and Lynch [ISJ with the assumption that the current,
after leaving the channel, is first confined to the accumulation layer before
spreading into the bulk. Equations for each of the·se resistances will be developed
later. Diffusion sheet resistance equations hav~ been proposed by Shichijo[SJ and
Scottf161 which assume the bulk resistivity ·in the n+ or p+ layer is not constant but
actually increases with smaller junction depths. Their equation for sheet
resistance is:
1 n
Pooc X, 1
where n = 5 for a boro_n p+-n junction. However, .recent work by Lunnon[l 71,
33
Mikoshibal 18l, Liul 19l, and Daviesl20J have shown that with rapid thennal
annealing and implantation into pre-amorphized silicon, the assumption of a non
constant bulk resistivity is invalid. N gl7l has shown that the bulk resistivity can
be treated as constant, therefore, the equation for sheet resistance becomes,
where,
PoS Rsh = -
W
W = device ivicitlz.
Po= _e_ = sheet resistance per square.
(19)
X;. p = average bulk resistivity in the n + or p + layer. X1 = junction depth in cm.
The contact resistance is a function of both contact resistivity between the
metal and diffusion layer and sheet resistance per square of the underlying n+ or
p+ layer. Contact resistance has been well characterized by Bergerl211 and
Murrmann and Widmannl221 to be:
Rea= --f PoPc coth(I- ~) W ~\J Pc ,
(20)
where,
34
I= length of window contact W = device width Pc = contact resitivity (ohms I square) Po = sheet resistivity (ohms I square)
Equation 20 shows that an increase in 1 will tend to decrease contact
resistance, decrease the maxinnnn current density, and increase the effect of
current crowding(the relative current change with distance from the edge of the
contact). The limits of con.tact resistance were found by Ng and Lynchl7J to be:
R ::: -"1PoPc. ~ ('() if / > 1.5 Po · iv
and
Rw = ·~:/ if I< 0.6~
The spreading resistance due to current crowding at the ends of a FET's
channel has been analyzed by Baccarani18J and is extremely critical for future
designs since it is insensitive to scaling and increases with the increase of
source/drain junction resistivity. The contribution to total senes parasitic·
resistance becomes a key factor" when dealing with short channel devices.
Analytical expressions for the spreading resistance have been developed by
Baccarani[81 and Ng[231 which describe the· spreading resistance as a function of
junction depth, inversion channel thickness, channel width, and bulk resistivity.
35
The equation as developed by Ngl 23 l ,with the graphical model given by figure 8,
1s:
-~ xJ Rsp, - ln(0.58 . ) n:W Xe
where W is the width of the device, X1 represents the junction depth of the
source/drain, Xe represents the channel thickness, and p represents the local
resistivity in the vicinity of the channel end. This equation differs from
Baccarani' sl81 in that the local resistivity is used instead of the bulk -resistivity and
that the assumption of an abrupt transition between the source and channel is not
used. Using the local resisfivity is important for accuracy as figure 9 shows the
differences in resistivity for different doping concentrations. However, the
agreement of Baccarani'sl8l and Ng'sl 23J equations for spreading resistance are
within 7 percent and are adequate for our development of propagation delay. lri
light of the above discussions on series resistance, some general statements can be
made. From the above limits, contact resistance can be decreased by increasing
the window length but this increases the source/drain area which leads to an
increase . In capacitance and can degrade speed performance . The
spreading(injection) and accu·mulation layer resistances have been shown by Ng
and Lynchl15l to decrease with the decrease of the effective channel length, due to
the increase in the normal field. Studies of the effects of series resistance in both
36
the linear and saturation regions of operation show that series resistance is more
detrimental in the linear region than in the saturation region. In the triode
region(linear), series resistance on the source side reduces the drain bias as well
as the effective gate voltage. In the saturation region, the reduction in drain bias
has no effect on the current. To conclude, Rea dominates the parasitic resistance
if channel lengths are small, but spreading and accumulation layer resistances
become the key parameter for larger channel lengths. Sheet resistance has little
effect and therefore the main advantage of self-aligned silici_ded source and drain
areas is the increased contact area which decreases the contact resistance. Ng and
Lynchl7J have found for CMOS circuits, the maximum degradation in speed due
to series resistance effects was a 12-27 percent compared to the ideal with no
series resistance. Hence, the effect of all the parasitic resistances can be
combined into one total series parasitic and it is given by:
(22)
37
L, I
__ .,.. ___ s ------
CONTACT WINDOW
(a)
\ METALLURGICAL JUNCTION
Figure 7. Model of Series Resistance
38
::iATE
{ , __ CHANNEL i.___,....... .. ~ • .- ;~·,
"I I I X,. I , I I
~ I ; I I I I 1 I I I f
I I I I I I
I I I I I 1 I I I I
I I I I ,
/ / I I ,' JOPING · ::iRAOIENT / /
1 1 '
/ / / / /, - / / / .
-'\- - / / I --- ~ / // ---- -- ....... // __ .... ______ __.-1 / / - . - / -- ~ .-, - --- --- ....., ,_,,,,,,. _._ -- ---- --- -- --- ~ .
---- - --- .... --' ----
' y
METALLURGICAL .,UNCTION
Figure 8. Analytical Model for Equation Development
39
-~El.
., .. ~ ,
~ ""• 10 /CT,. ..
I J.2 1,.4.ffi r, _______ ~
04~r
E u
a -,. ... 2! ... "' .. ... II:
' \ \ '-•O'i '~,o·a --0'7
--0·'
,o· 1 I-
,o·•
0
n-T"ftlt: 1•1 ,,x10• C•O IO o-T"ftlt: ,., uxtO"' c•o ro
,o .... '---,_;_-------------10,. t0'' t0
1• t0
1
'
oonee CONCDTUTlOIIII ccnr-t,
Figure 9. Doping Concentration Curves
40
2 .9 Effect of Interconnection
Propagation delay of interconnection is an important factor in detennining the
speed perfonnance of VLSI circuits since RC time delay increases rapidly as
interconnect dimensions are reduced. The model developed by Sakurail241 uses a
distributed RC line(to model polysilicon interconnect) with a drive MOSFET at
one end and a capacitive load at the other end. Equations for propagation delay
are developed from the equivalent circuit listed in figure 10. The equations
developed by Sakurai!24 l agree with Meind1l9l anµ Hatamian's!251 findings. The
model states that as a step voltage is applied to the gate of the drive MOSFET, the
response at node 2(refer to figure 10) is written as:.
I VDD I
V 2(s ) = , TD(s ) (23a) s
The time domain response can be evaluated using Heaviside's. expansion theorem
where the poles of equation 23a can be denoted by O,cr1, cr2, etc. The time·
domain response becomes,
(23b)
where,
41
.............
Ci=(-1) _,-- 2 2 2 2 . ~o1 ((1 + Rr ak )(1 + Cr a, ) + (Rr + Cr>< 1 + RrCro1))
,, Rr=
R
c, Cr=
C
and ,, is the resistance of the driver, c, 1s the load capacitance including the gate
capacitance to be driven, R is the total resistance of w.iring, C is the total
capacitance of wiring, r is the resistance of wire per unit length, and c is the
capacitance of wire per unit length. In the expansion of equation 23b, terms
higher than the third can be neglectedl 24 I and equation 23b can be approximated
within 4 percent accuracy as:
I
v2(l ) -o1t -- = 1 +C1*e Voo
By noting the linearity of delay versL1s Cr and Rr from experimental data and by
using constants developed by Sakurai124 l and Meindll9l, the equation for
propagation delay can be expressed in a simple form as:
Tpdel . = l .02CR + 2.21 (c1r1 + c1R + r,C) (23) wire ·
Equation 23 is a very accurate (within 1.1 percent) estimate of the interconnect
42
delay and is used in the next section for cascaded inverters. ·All tenns in equation
23 are defined below (please refer to figure 11 for a physical description):
L w
Lmax R = p . .
W wireHwire
The capacitance of the center line of three adjacent lines above a ground plane is
expressedl261 as:
W H . 0.222 W . H . H . 0.222 t Cwire = 1.15 wire + 2.80( wire ) + (0.06 wire + 1.66 wire - 0.14( wire ) )( fox )
f Jox t fox lJox lfox !Jax Wsp
This expression has an error of less than 10 percent over a wide range of
H Yr ire W wire d W sp --,-- --'-· - an The accuracy is consistent with similar work on this f Jox lfox lfox
topic by Ruehli,l271 Dang,l281 and Brennan.1 291 To gain a physical understanding
of the interconnect delay, equation 23 is -rewritten to show the effect of line
length:
From equation 25, the approxirnate delay for very short lines is r, *CL· These
very short connections are typical for interconnections appearing among logic
43
gates within a logic function. For longer line lengths, typical for most on-chip
metal connections ,CL <r1c, and the approximate delay is given by:
_ Lr, 6 Tdely . --3* 10 cm/sec w1.re z
0
where Z0 = -~ = 377p. For very long lines, the delay increases quadratically '.J Ea
with line length and imposes a severe limitation to speed performance. In relation
to interconnect material and circuit size, the delay of aluminum .lines and modest
VLSI circuits are dominated by the on resistance of the drive transistor, r1•
However, for larger VLSI circuits and for polysilicon lines, the iDterconnect delay
is controlled by the resistance of the line, r.
44
0
arive
MOSFET
• Vee I
-~~ I I r --~c I
""
Vee
-
caoocn,ve 1000
R I \(VYVyv--· \~r -- ~ - C ....;,. -- I~ ~ --- -- --- ~ I I I ' .,., -, .,.,. .,,. ..,.,.
(a)
-I I -
I ~
(b)
Figure 10. Interconnect Equivalent Circuit
45
-
-w -w. -, sp nt •
~--1 I 1 fo1 · / / / / / / / / / / / / / /
T I
Figure 11. Interconnect Cross Section
46
2 .10 Interconnection Propagation Delay of 4-Stage Cascaded Inverters· .
Using the results of the previous section, we will derive the equation for
interconnect delay using cascaded drivers. The technique of using cascaded
drivers in driving large capacitive loads is well studied and optimizes the sum of
the delay caused by charging the input capacitances of the drivers and the
interconnection propagation delay. Rearranging equation 23, total delay as.
defined by Meind1[ 9J is expressed as:
(25)
where e is the base of the natural logarithirn, R0 is the output resistance of the
1nini1num size inverter, and C0 is the input (gate) capacitance of the minimum
size inverter.
Inspection of equation 25 reveals that cascaded inverters minimize the r1c term
in equation 23 but have no effect on the re tenn. This method is useful for short
interconnect(R is small as in our case) or when R0 is dominant.
47
25
2.11 Test Circuit Schematic
Figure 12 represents the schematic for the test vehicle, a 1.25um MOS line
driver. Experimentally, propagation delay on the outn channel was collected by
using a Takeda-Riken test machine which i_s accurate to within 125 pico seconds.
The fallowing are the capacitances, resistances, channel lengths and widths for
each stage of figure 12:
Stage 1:
O. l 2picofarads (pf)/ fanout = 0.24pf Ln = 1.Su LP= 2.0u \Vn = 25.75u WP= 73.125u c, = 0.796pf
Stage 2:
o.·12pf If anout = 0.24pf Ln = 1.25u LP= 1.75u Wn = 77.875u WP= 140u c, = 2.3pf
48
Stage 3:
0.12pf If anout - 0.24pf Ln = 1.25u LP= 1.15u Wn = I 95.5u WP= 416u c, = 5.25pf
Stage 4:
C,=I6pf Ln = 1.25u LP = 1.15u ivn = 375u H'p = 1078u c, = 19.14pf
49
)
The fallowing values are the same for all four stages:
VDD = 4.5§V Tax= 220A V1n = 0.66V Vrp = - 1.15V E = 35.4X 10-14
2 µ = 700 cm
no V-s2c cm
µpo= 300 V-sec
µnEWn Pn = .
TaxLn
50
I
-{ ~-tn ,r
l 4:,,, ~
I
J --{~7n
~1 l "191
l1'· 1 rll )t .s r1 .J
• ~
.,.. '-t 1• 111~1· ICIIO,, ' ,.,.
! • ' "- .. [, 0
~ I rl~:-
~
J 4~~11 1~ r-
I
...
a
~
""
... ~
-
•
... Pl
.. ... m&.L
' ..
Figure 12. Test Circuit. Schematic
51
-
-'-"-
lll&flCU.~-...... u....- .. u.1.ti
fJ11140t.l ,-....... c.al24 ...._. -- -~s 1 - C"12'IOU T ·-. -----
!
2 .12 Final Propagation Equation wirli Second Order Effects
Starting with equauon 8, a final equation for propagation delay will be
developed which incorporates all previously discussed effects. The effects of
senes paras1uc resistances are incorporated into the saturallon drain current
equations 10 and 11 by defining the following expression:
I
Vc·l· = V c·c - foe R (26) J.) J.) .)5QJ S
I
where V GS is the external gate voltage, and R5 is the source senes paras1uc
resistance and is given as one-half of Rr(defined in equation 22 earlier) if the
drain and source are syn1metric. As equation 22 shows, the parasitic resistance
includes the diffusion sheet resistance, contact resistance, and spreading
resistance discussed earlier. Equation 8 has already included the effects of
velocity saturation and surface scattering and their effect on carrier mobility so
nothing needs to de done additionally. The effect of interconnect is incorporateq
into equation 8 by the. addition of an ext.ra tenn. The term is TdelYwire' and is
defined in equation 25. Thus, the final equation becomes:
Ln LP . CL Vrn CL Vrp T Final d = 0.5(- + -) + 0.5( (Rs)+ (Rs))+ Tdely . (27)
p V n V p / p / n wire
where Vn and vp are as given by equations 12 and 13 but V cs is now defined as in
equation 26. Equation 27 is valid for each stage of the cascaded inverters and
52
should not be cumulated throughout the four stages(except for the interconnect
term) before comparisons can be n1ade with experimental data. When equation
27 is fully expanded, the ·equation takes the form of:
T Final pd= AL 2 + BL + C
This general fonn of the equation shows the parabolic dependence of propagation
delay to channel lengths above 1 micron, whereas it implies a linear dependence
for channel lengths below 1 n1 icron. The C tenn represents a delay caused by th~
tin1e necessary to charge the parasitic capacitance to a threshold voltage. In the
next section, equation 27 is. contrasted against experimental data with parameters
such as channel length, contact resistance, and poly sheet resistances being varied.
53
3. EXPERIMENTAL RESULTS
3 .1 Fabrication
For this thesis, a 1.0 n1icron CMOS single level metal process was used to
fa bric at~ our devices. The technology uses twin tubs to fa bric ate the n'."device and
p-device. The substrate used was p-type silicon- lightly doped with Boron. The
n-tub is implanted with phosphorus at a dose of l.35El3 cm-2 at 50KEV, while·
the p-tub is implanted with Boron at a dose of 9.0E 12 cm-2 at 50 KEV. Tub
0
drive-in at l 150C .develops a tub depth of 1700A nominally. The process uses a
0
self-aligned polysilicon gate \Vith a gate oxide thickness of 2 lOA nominally and
source/drain implants of the n-drain and p-drain of 50KEV ,. I.OE 16 cm-2 and
60K.EV, 2.3El5 cm-2 respectively. A listing of the critical processing steps is
contained· in table 1 with special attention given to thicknesses and depths which
have a contribution to parasitic capacitances/resistances or ·impact delay directly.
Table 1 also shows the difference for this experiment versus the standard process
by using asteriks to denote the changes to the standard process. There were three
main changes. The first was the rapid thennal anneal(N 2 at 900C for 30 minutes)
where some wafers saw the standard anneal while others saw a limited or no
anneal in an attempt to vary the contact resistance. Channel lengths/widths -were
modified with the use of corn pensated reticles to -insure variation in channel
lengths. Finally, polysilicon sheet resistance was varied from the nominal 25
54
ohm -- by modification of the phosphorus diffusion.
D
55
3.2 Test Description and Environnzent
The propagation delay test was pertormed with the following conditions in
effect. A 50 percent duty cycle on the clock was employed with the input to the
series of cascaded inverters going frorn low to high after 1 ONS. and falling back
fro1n high to low after 60NS. All ti1nes are being referenced to time T0 , which
represents the time before any sti"n1ulus was applied. For propagations from low
to high and high to low on the outputs, the 50 percent points of the output pulse
were used to make the measure1nents. Before these measurements were taken,
hc)\vever, all pin electronics of the auton1ated test machine were calibrated(both
the comparators and the drivers) to insure best possible accuracy. In addition,
offsets should be calculated to detern1ine if there was any difference between the
values used for calibration of the test machine and the intrinsic threshold value of
the device under test, DUT, but t.esr ti1ne constraints prevented the calculation of
the off sets. The logic voltage levels for this test were at the power rails for the
VDD input levels(V DD and Vss) and were at
2 for the output levels. The
temperature was at 25°C and the actual physical test environment is as shown in
figure 13. It is important to ·note that the cable delay quoted in figure 13, 3.2ns,
has already been taken into account in the calibration and all direct readings
obtained from the machine are device related except for the capacitance of the
56
tester, l 7pf, which tends to exaggerate the propagation delay through the last
stage of the inverter.
57
C ,.,.,0 .S
iv-r 01.1 r ?v r 8 I.IF FF~ ~
--
- -I
J
\ 1. ,...11
2.Uv'
-11-11
Figure 13. Takeda-Riken Test Environment Model
58
....
TABLE I. 1.0 Micron Twin-Tub Single Level Metal Process Sequence
process step
Pattern & implant n-tub Grow tub oxide Pattern & implant p-tub Tub drive-in
dosage/thickness
50kEY, l.35El3 Phospurus 0 0
1 OOOC, 3950A-4550A 50kEV, 9.0E12 Boron
0 0
11 SOC, l 600A- l 800A Pattern GASAD & implant chanstops'i<**
0 0
Grow field oxide 9SOC, steam, 6500A-7000A 0 0
Grow gate oxide Deposit poly/diffuse phosphorus'~.,;;," S pu tter/pattem/etch silicide In1plant phosphorus drain Pattern & implant p-drain Nitrogen anneal Deposit TEOS spacer Pattern & unplant n-dra1n Nitrogen anneal Deposit & flow BPSG Pattern & etch windows Sputter & pattern Al Rapid thermal anneal Al*** Sinter Al Deposit & Pattern SINCAPS Etch SINCAPS Backgrind wafers Ship to probe
950C, 190A-230A 0 0
900C, 2700A-3300A 0 0
2 OOOA-2600A 50kEV, 4.0E 13 60kEY, 2.3E 15
tJOOC, N 6, 30 mtns 3750A-4250A 50kEV, l.OE16
900C, N 2 , 30 mins 0 0
I OOOC, 20 mins., 8000A-10000A
o o·
tJOOOA- l lOOOA
330C 0 0
7000A-l 3000A
59
3.3 Results
The split pe_rfonned in this expenn1ent gave vanauons 1n N+ contact
resistance from 2 ohms to 100 ohms with an outlier at 250 ohms and P+ contact
resistance from 15 ohms to 120 ohn1s. Sheet _resistances showed variation from
17 ohm to 40 ohm for the N+ sheet resistance and from 40 ohm to 180 ohm 0 0 . 0 0
for the P+ sheet resistance.
The Results illustrated in figures 14 through 18 were obtained in the following
manner. The wafers were fully pararnetrically tested per reticle using the existing
test transi_stors on the circuit and this was 1natched to the test data(from Takeda
Riken) for the same reticles. These figures clearly show the effect of channel
length(and subsequently / DS) on propagati"on delay perfonnance. The channel
length yariation was broken into three distinct groups for ease of analysis and
these are denoted as "S" for channel lengths from 0.75u - 0.85u for the n-device
and l.20u - l.30u for the p-device, "N" for channel lengths from 0.65u - 0.75u for
the n-device and from 1.1 Ou - l.20u for the p-device, and "F" for channel lengths
from 0.55u - 0.65u for the n-device and fron1 l.OOu - l. lOu for the p-device.
Analysis of these figures show a 15 percent difference between the actual
experimental results and those predicted by equation 27. Analytically, equation
27 was developed with the assun1 ption that the loads on the gates as well as their
60
widths and lengths were the same, however, in our case the loads are different as
well as the device widths and lengths. These differences are for the most part
transparent since the ratio of load capacitance to drive current is fairly constant
throughout each of the stages(and hence the d~lay through each gate is fairly
constant), however, in the fourth stage the ratio is .significantly higher due to the
effect of Takeda's capacitive load. An attempt has been made to compensate for
stage four by subtracting the effect of Takeda 's· load capacitance from the final
result for propagation delay.
Since the effects of series parasitic resistances and .interconnect on propagation
delay were observed to be slight, figures 19 through 22 were used to show the
degradation of IDs due to ihese effects. These figures represent data taken
directly from test transistors for 1.25 rnicron CMOS. In order to keep the effect
of channel length and width on IDs to a n1inin1un1, the data shown was restricted
to nominal values of channel. length and width. The actual data was summarized
and a regression line was drawn to con1pare with the predicted results of solving
equation 26 and equation 3 for/ DSAT.
The degradation effect on current 1s illustrated in figures 18 and 19 and
compare with the results predicted from equation 26 with a somewhat larger than
expected variation.
61
3 .4 Future Work
Additional analytical development of propagation delay needs to inciude
the effects of finite inversion layer thickness (critical for thin insulator devices), a
detailed account .of the dependc nee of threshold voltage on channel length,
cha_nnel wi_dth, and supply voltage, and a n1ore accurate picture of source/drain
profiles.
Continued work 1s needed 1r1- detennining/extracting parameters
experimentally which have an adverse impact on propagation delay perfonnance
and in develqping methods which enable a statistically accurate picture.
62
CONCLUSIONS
An attempt was made in this thesis to analytically develop an equation for
propagation delay performance based on fabrication parameters which also
included some second order effects which become more critical as CMOS
technologies go submicron. Many papers were focused on specific second order
effects, but it seemed that the holistic approach was rarely used.
This thesis compares these separate effects with experimental data from test
transistors and finally compares propagation delay performance with selected
fabrication parameters. A limitation \vas encountered in that the channel lengths
were not able to be varied due to non-technic~il production considerations and that
processing variations had a tendency to skew some of the experimental data; As
stated in the results section, analytical results differed by roughly 15 percent from
experimental findings but· this is attributed predominately to the testiIJg
environn1ent's load capacitance.
There still remains the task of modelling other second order effects into an
equation for propagation delay and effectively extrapolating data from other
processing parameters to determine the.ir effect. on propagation delay
performance.
63
1108C
0
" J>? -
0 N
~ -· t'tJ INtN ~
1-1 LO C'O (0 N N
..-i . ~ 0 N ~N s ffi s . N NN ~ ~
en 1-1 z s s ~ 0 N N
"'d <l) s::i, - r~~"(tss.·,o" \·11"\'t. u\ s
crq ('(j 0 N N N N
s::i, CJ (0 u...c\v.~\.. d~\o.. ~ - N N -· 0 0 <l)
~ (l_
t; ~ F F F N N
ct1 (t) <l) -~ 0 F N
C LO
~ 0 LO . FF Ff N ('D - 0 ~
('(j CJ) N N
0 ('(j F ~t\A ..... ~ "L1 ~ ~
a_
~ ~ 0 N tt) - F n.. fF < 0 00 . LO . ..-i . 0 0 ~ FF ·z F F r4 ('D
LO ~ 0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
N 1.0 Le - Microns S=:=slow N=nominal F=fast
1108C
0 ,...... ------7 0 N ,$ s
~ -· ~ ll'NN ss ~
>--1 l() (t) NN U) -
~ .
~ O· N rfJN Ss; s en N NN ~
~ >--1 z s s ~ 0 N N
"d (l.) p., ...... r~~'(ts>\o" \',r-.4l. u\
s CTQ ro N N
CJ 0 N N p., (0
u..c..~0-\. c\~\u. c-t- ~ N N I-'. 0 0 (l.)
~ a..
u >,. F F N N cu F
(t) (l.) -p., 0 F N N '-< C l[)
~ 0 l() I ·t··~'- ~ ... , . FF N
(t) ...... 0 >--1
ro O> N
0 ro 0) p., 0.
~ c-t- 0 N ('[)
~ F a.. FE IF < 0 r:n l() . ~ 0 . 0 i:: FF z F F L'4 ('[) l()
,q-0
0.50 0.55- 0.60 0.65 0.70 0.75 0.80 0.85
N 1.0 Le - Microns S=slow N=nominal F=fast
1108C
0 t---. 0
1-tj s s N ..... ~ NtDJ~ ~ (D
~ l/') mJ
C.11 <O . 0 s%s ~ Cl) N N'J~ "1'J N N ~·
0 z Sg; § s N t-tJ ~ N ~ Q) crq - s ~ ro 0 N N M-- (9 ..... <O 0 - 0 N ~ Q)
tj a.. >,. F (D ro F --~ Q)
~ 0 N N F ~ C l/') (D 0 l/')
~ . N FF FF - 0 ro
0 O> N N m ~ ro 01 c-t- 0..
(D 0 N N N < - N F F 0.. en . 0 lo-' l/') . . 0 0 ~
z m= FF ~ F 0 ~
l/')
-.:t 0
8.5 9.0 9.5 10.0 10.5 11.0 11 .5 12.0
N 1.0X30 Ion - MA S=slow N=nominal F=fast
1108C
0 -------------
"' 0 N
1-Ij ..... ~ NtltJ ~ ..., ro ~
L() mJ CJl
U) . . 0 sis ~ (/)
N N'J~ ~N N ..., 0 z Sffi § s N~ ~- N p) Q)
crq ..... s p) ro M- CJ 0 N N ..... (0 0 '- 0
N =:, Q)
tj_ (l_
>,. F ro ro
F -p) Q)
~ 0 N N F ~ C ll)
ro 0 L() ..., . N FF FF ..... 0 rn· 0 CJ) N N
m p) rn 01 M- 0.
ro 0 N N N < '- N
(l_ 00 . 0 ~ L() . . 0 0 i:: ~ FF
z F ~
0 =:,
L() V . 0
8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0
N 1.0X30 Ion - MA S=slow N=nominal F=fast
1108C 0
" -- ---- -
0
"'rj N Ss
...... ~ N NNNNrmJ 3-JS
1-1 ~~"e~~·,Ov\ \,re 0 t N s
(t) Lt) C).'-\uo-\ ck.k ~ <O N
"' 0 . ~ (/) N ~N N ~N s NR s s 1-1 z 0 N N s ~§ ~ N N ~ <1>
crq -Pl
ro 0 N 1)/ / s M" CJ (0 ~ ...... .... ci 0 <1> N N ::s a.. u >. N NN N (t) ro F .,_..
Q)
~ 0 ~ ~ C Lt)
(t) 0 LO
1,\..._i;..., 1.., ·- .
IF F 1-1 ...... 0 N ro p O> N en Pl ro
CJ) M" a. (t) 0 N .... < a.. F U) 0 . i,-;..i
LO . . 0 -l CJl r::: ~ F t-t (t) LO
'¢ _l_ l__ ---- --- -0
1.00 1.05 1.10 1.15 1.20 1.25 1 3-0
P 1.75 Le - Microns S=slow N=nominal F=fast
1108C 0 ---
" 0 N Ss
~ ...... ~ N N NNN NrmJ ~ 1-1
~~'<e,)~·1CV\ \",re 0 t s s (0 LO
O.<-., ~\ (jp,,. k >--" <O N
"' 0
~ en N ~N N ~N s NR s s 1-1 z 0 N N s ~§ ~ N N ~
a)
(Tq _... ro
/ s ~ CJ 0 ~ N /
/
M <O ...... . 0 '- 0 N N Q)
~ Cl..
u >- N ~ NN N ·(O ro F - Q) p)
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C I.{)
(0 0 I.{) - l ,,, .... i;.., .. ,
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Q O>
m p) ro
m M 0.
C'O 0 '-
< Cl.. F en 0 .
LO >--" . . 0 . -.:i CJl ~
~ ~-C'O LO
v 1_ 1 ___ ---- -- - - ~ - -
0
1.00 1.05 1.10 1.15 1.20 1.25 1.30
P 1.75 Le - Microns S=slow N==nominal F=fast
1108C 0
"' ----
0
1-rj N -· ~ s N'-JNmJ ~ 1-1 ct)
LO ~ co N N _,
0 ffiS ~ (/) s NNN~ NrmJN 1-1 z ffi s s NN 0
"d N ~ (l) s crq .....
cc, N ~ CJ 0 N N M" (0 -· N N 0 '- 0 (l) t:S 0... u ~ N N N ~ F IF FN ct) cc, - (l)
~ 0 N N F ~ C LO ct) 0 LO
FF FF 1-1 ..... 0 N cc, Q O> N N en ~
cc, F -..J M" a.
ct) 0 ~ '-
< Cl.. F Ul 0 . ~ LO . 0 -..J Ot F ff:FFFfHF ~
~ FF i,.,..,4
0 t:S L{)
"Q"
0
2.4 2.6 2.8· 3.0 3.2 3.4 36
P 1.75X30 Ion - MA S=slow N=nominal F=fast
1108C ..
0 r-..... --- - - -- -- - - ·- -·-·-- --- - - .
0
1-Ij § N
-· ~ s t-NNmJ ttJN 1-1 (t)
ll) ,-.... <D N N -J .
0 s ffiS ~ Cl) NrmJN 1-1 z §; s 0 s NN ~ N ~ (1) s crq
_.. rn N ~ CJ 0 N N
M <D -· 0 ..... . N N (1) 0 ~ o_
v >- NNN t'tJ F IF FN (t) rn -~ (1)
~ 0 N N F ~ C ll)
(t) 0 ll)
FFFF 1-1 _..
0 N rn 0 O> N N
CJ) ~- rn F -:i M a.
(t) 0 NN ..... < o_ F r.n 0 . ,-.... ll) . 0 -:i Cl1 F ff F FFfHF ~
~ FF ~
0 l:j l{)
,q-0
2.4 2.6 2.8 3.0 3.2 3.4 3.6
P 1.75X30 Ion - MA S=slow N=nominal F=fast
~ -· ~
C'D ~
00
~ ..-. ~
°' >< u:> 0 ~
0 t::3 Cl ~
~ C'D t'.j rt
<: m rn . 00 ~
+ . (') 0 ~ rt ~ n rt
~ (Jl
rn· rt-
§ n CD
---<: :? -C 0
0 M X lO f'... ....-CL
0 . ~
co . M
. M
N . M
0 M
co C\l
Current Degradation - Contact Resistance
--------------------- ---- ------- ----------- --- -
•
• • •
• •
• •• • • • •• • •
•
• •
• - . -·. . . : . . . . . . ~ . . .... ,.,.. . \. • • • • • • •
• • • I' JV .Y•: • • } ..... ; .r. ... J • • • • . ...
• L. '-- ..i.... . . .. . ' . ~ -~ ..
•• , .. •• • • •
.v ,~ • •.• •: • -• I • •
~1j· ... w·· ... . ... .,. ·~~ "': )' . , .... ;-... . . i:.., . ., \\• .•.
•• • • \. ;,,, • • I
•
•
• . • • • • • • •
• • . . • • -~· -"a•: \... • •• • •••
•.. :. • •. "'r· .. r. •· r-------~~~~~t:!.~· . .. . . . /.* "7.t•,t I
R€jrf's~,o~. f, t-
-;--. ---------...!.·_· 2/:__ f'I~ h, o. l ~ \" \ • • • • •
0
rr--.
• . • •i' •1... 'r/1 :..·-:. :,~· . .... . . ·. . . 7 . .... A,."" • " • • • • • • . . . . ,· .. )"'' ....
• I\ P.~·. , .. ' . 1' •• •. ••• • • ..,.~ .:"···\ \ ..... • • )')• r 1 .,., I •(• • • • • • • \ • I • . . .. .. .. . . . ~>~·· . . . . .
20
. . . ' .~ . .. , . .. • ·-= ~ • ..,. ·'~\· .
I • • • •
• • • • ••
•
•
•
• • • ••
40
•• • • • • • •
• • • •
• •
•
60
.
• •
.L
• . .. . • • •
• •
•
•
•
__ 1 __________ l _______ _
80 100 120
P+ Contact Resistance (OHMS)
140
~ -· i (t)
...... 00
"'O ~ . -.l CJ1 ~ w 0 lo--4 0 t::l n t::: ~ (t)
t::l rt
(J) ~ < CJ) . 00 ~
+ n 0 ~ rt PJ n rt
~ en cii' §' 0 CD
-~ ~ -C 0
0 (")
X U1 f'... ..--(l_
0 . ~
co . . M
(D . M
N . M
0 M
Current Degradation - Contact Resistance
r---------------- -- -- ---
•
• • •
• •
• •• • • • •• • •
• •
• • - . -· ... : . . \.':.. . . ., . . ... . ~ . \ . • • .1 • . • • •
•
• • , .I ..r.. • • . } .. • v~ J • ... • .. ~ ..... ·• . . . .
• •
•
.vf ,t • *••: :• .:: I'• • ~ 1j· r [·· •. . •. • , · F \-·~~ 1; ) • , .... ; •• • ~ . \ .. \ :. • • • R~res ~.o"' ;
• ~--., • -' \ \ • . • r • • 1'c l lJ l ~ \ °' • . .: ~L. ='.: t';I.: . • . . I .. • • : • : • / • • Q.
r -----~•:....._• ~~ I • •. ~ r •. • ,. • 1 • • • • . \ . . . . . . . • • • \ • • •
I, • 47 I - r" t •,t I • •~ t'~· 'f /1: :..•.;. :,~• ·. I"• * • • f•~ L ---:..__------..!•~~-.,._.. . .._ . . . .. . . • • .• , .... J"· ' . . . . • • •
• • • • •
• • I\ ~"1,.,,. • 1. • '-• • • ."• • • • • -~ • .. i- • • ••
J-~ ~ ..... \. \ ••••• • •~· . ... . . I >• • • •
. . u:.J>~:: : ... '·' . . r, . l .. •• . . . . ' .\ . I . . , . . . • •
•-: I •
_,~ ··~ \• • •
• • • • ••
•
•
•
• • • ••
• • • • • •
• • •• • • • • • • •
•
•
•
• • . • • • •
• • •
/ Ano.l~t,cul Mo~e.\
~-----.&.----------'------4----------------~-------&----------- -
0 20 40 60 80 too 120
P+ Contact Resistance (OHMS)
140
~ ..... ~
0 ...-
co 1--' co . 0)
z ..-. 0 ~ -w ct: 0 ~ 1--4 -0 C = 0
(") 0
~ M X 0
C'O . = T-
rt- z ~
lO
0) • co z
+ LO
("). 0 = rt-p, n rt-
£'' rn En" rt- M
§ n C'O
Current Degradation-N+ Contact Resistance
• • • •
• • . ~· .. . ' . . ., -. . . .. . • •• .. " . . . . . . ~ .,. .
•
·~· -· ' .
.. . •• • . . . . ' : .. . . . ' .. . . ; ... . • • • • • • .. . . . ....
• • •
•
•
• • •
6.----------4.,---------~----- ------ 1 --------- _ 1
0 50 100 150
N+ Contact Resistance {OHMS)
200 2~0
~ ~· ~ ct)
I-' (0 . z ~ . 0 ~ w 0 ~
0 ~ (J
~ ct)
t:S rt
< r.n en . co z
+ (J 0 t:S rt p.) n rt
g; r.n rn· rt
§ n ct)
,-...
<{
::E -C 0
0 M X 0 . ...--z
...-,-
0 ,-
m
CX)
t---
<D.
LO
~
M
Current Degradation-N+ Contact Resistance
------------ -- -
• • •
•
• •
~eJrtSs~~ o.f
• ~ C. "\AA. \ 0.. \o..._ •
!...
.. • . •• • .... -' : ... . . ' ... . ; . " .. • • • • • • .... • ....
• • •
Ano\•::}' c• l Mo cil, \
•
____ 1 ____ 1 ~ - ·----·
0 50 100 150 200 2~)()
N+ Contact Resistance (OHMS)
Current Degradation-N+ Sheet Resistance
.-------------------- ----. ---~
1-rj .... 0
~ ... ... •
ct) • l'v 0 • •
z O> •
• ...... . ' . ·o ~
r-. -~ a, - - - ---- - ------ co . ; ...... • w <x: ~· .
0 ~ 1--4 -0 C t::s 0 • • • • (J 0 t- ~ .. . C M . ~. •
~ X 0 • •
ct) . ,,.. t:l ...- • i.. c-t- z lO ~
~ • • . - •
-.J z 0 + LO
en t::r ct> ct) c-t
fu° ~
en • fn• c-t-
~ M 1 ____ -- ---- -- - - -- - J - -- -- -- - -
n ct) 15 20 25 30 35 40
N+ Stleet Res·istance (OHMS)
Current Degradation-N+ Sheet Resistance
,---.--C-- ------------ - -- ----
• • 1-xj
--· ...
i 0 ... ,- ~ -! •
ro . ,. •
t-0 1( • 0
(J) - • z • ,_... L __
• ' . 0 ~
r-. • -1 ', - -...--.. co
. "' . .. . . . • w <{
~· . 0 ~ ~ -0 C D 0 • • • - ., n 0 t--- - .. . C M . ~. •
~ X ro 0
. ,ti . · l.
D ...- .. rt z U) -
< • • U) • .
-..] z 0 + LO
(/) ~ ro ro rt
£' ,q-
• C/l u;· rt- --- -- -
_L __________ s-- ___ J
§ M
n ro 15 20 25 30 35 40
N+ Sheet Resistance (OHMS)
~ ~ . -l c.n ~ v:, 0 ..... 0 = l.l
~ C'D
~-
~ ~ + rn ~ C'D C'D c-t-
LO . ~
0 . ~
LO •
- C") <(
~ -C 0
0 M >< lO ~ . ,--
Q._
0 . M
LO •
C\l
lO .
-• •
•
40
•
60
Current Degradation - Sheet Resistance
•
•
• • • • •
• • •••
• •
•
•
•
80 ·100 120
P+ Sheet Resistance {OHMS)
•
-------------
• • . •
•
•
•
140
•
• • •
•
••
•
• ·•
160
•
180
-C 0
0 ("')
X l()
~ . ...-
0 . ~
0 . M
CL ·LO
-"1
LO •
-• • •
•
40 60
Current Degradation - Sheet Resistance ----------------- ---- ----- ~----·--· --
•
•
• • • • •
•
• •
•
•
•
80 100 120 140 160 180
P+ Sheet Resistance (OHMS)
Propagation Delay Slow Le Vs. VD_D
co •
• "'rj -· ~ • ~ (t)
t...:) • t...:) . ~ ~ • 0 ~ ~
C7Q • ~- -M- en -· -0 0 t::j > LO • -0 0 (t) 0 - > ~
• ,,-..._ .t"'4
-:i ~ * t'V C7Q
(t)
t"'4 • (t) ._.,
< • 00 .
a *
0 (\J
• ..
2 4 6 8 10 12
Slow Le prop_agation delay (NS)
Propagation Delay Slow Le Vs. VDD
• CX)
•
1-Ij ..... ~ • .., ct)
t'V • t'V . ~ .., • 0
"d ~
.O'Q • ~ -M-
en -..... 0 0 ~ > LO. • -~ 0 ct) 0 .......
~ > •
,,-.._
t"'4 • -.J e; ,q- -
t....:> oq ct) • t"'4 ct) '-"'
< • r:n .
a •
~ •
(\J
2 4 6 8 10 12
Slow Le propagation delay (NS)
Propagation Delay Nominal Le Vs. VDD
- ---- ---- ----
co •
• . 1-rj
. -· ~- t--- •
1-1 ('[)
t--..:) • "" ~ 1-1 co • 0
'"d Po)
(Tq - • Po) en M" --· -0 0 :::1 > ll) • -t::j 0 ro 0 - > • p.,· ~ ,-..._
z 'q" •
-:i 0 -
vj s -· :::1 • e:.. ~ ('[) • -.....;..,
< r:n . • a 0 (\J
- - _l_ -------- --- _ l
2 4 6 8 10 12
Nominal Le propagation delay (NS)
Propagation Delay· N·ominal Le Vs. VDD
- ---.---·~ - .. ----- . - --- ..
CX)
•
~ -· ~ r---- • -
1-1 (D
t'-v .. uJ
~ 1-1 CD • 0
-
"'d OJ
(JQ --- • OJ (/) M --· 0 0 ~ > U) • -t:J 0 (D 0 - > • OJ ~ ,,-..._
z V" •
-.] 0 ..,...
w s I-'.
~ • ~ ~ (D • _.,
< r:n • .
a tj (\J - ,, _____ _J --1-~-
2 4 6 8 10 12
Nominal Le propagation delay (NS)
.Propagation Delay Fast Le Vs. VDD
--- -co •
•
~ -· ~ • 1-$ (t)
~ • ~ . ~ • 1-$ <.O 0
,:j p.,
crq - • p., en c-t-
.... -· 0 0 > ~ LO • -C, 0 (t) 0 - > • ~ ,-..... en •
-l s ~ e.. - •
t"'4 (t) ...._,
< M - • 00 . a • t:, .
C\J
2 3 4 5 6 7 8
Fast Le propagation delay (NS)
Propagation Delay Fast Le Vs. VDD
---------------- - ---------• CX)
•
~ ..... • ~
""1 (t) • t...::i ~
~ • ""1 <D 0
"d p.) •
CTQ --p.) U) -rt ..... 0 0 > ~ LO • -u 0 (D 0 - > • p.)
"< ,,-._ (/) • s 'Q" -
-.l ~ e. - •
~ (t) ...._
• < C') -
en .
a •
u •
(\J
2 3 4 5 6 7 8
Fast Le propagation delay (NS)
75
REFERENCES
1. White, M.H. "Characterization of CMOS Devices for VLSI" IEEE Transactions on Electron Devices. Vol. Ed-29, No. 4. Pgs 578-584. April 1982.
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3. Kamohara, I., Matsuzawa, K., \Vada, T., and Kenji Natori. "Impacts of Modified Characteristics on 0.1 um MOSFET Speed Based on Energy Transport and Parasitic Effects." Pgs. 629-632. IEDM 1989
4. El-Mansy, Y. "MOS Device and Technology Constraints in VLSI." IEEE Transactions on Elecrron Devices. Vol. Ed-29, No. 4. Pgs. 567-573. April 1982.
5. Shichijo, H. "A Re-examination of Practical Perfonnance Limits of Scaled n-channel and p-channel MOS Devices for VLSI." Solid-State Electron. Vol. 26, No. 10. Pgs
969-971. 1983.
6. Perera, A.H., and J. Peter Krusius. "Ultimate CMOS Density Limits: Measured Source Drain Resistance in Ultra Small Devices." Pgs. 625-629. IEDM 1989.
7-. "The Impact of Intrinsic Series Resistance on MOSFET Scaling.'' IEEE Transactions on Electron Devices. Vol. Ed-34, No. 3. March 1987.
8. Baccarani, G., and G.A. Sai-Halasz. "Spreading Resistance in Submicron MOSFETS." IEEE Elecrron Device Letters. Vol. EDL-4, No. 2. February 1983.
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11. Glasser, L.A., and Daniel W. Dobberpuhl. The Design and Analysis of VLSI Circuits. Addison-Wesley Publishing Company. 1985.
12. Coen, R.W., and R.S. Muller. Solid-State Electronics. 1980.
13. Sabnis, A.G., and J.T. Clemens. IEDM Technical Digest 18. 1979.
14. White, M.H., Van de Wiele, F., and Lambot, J.P. "High-Accuracy MOS Mcxiels for Computer Aided Design." IEEE Transactions Electron Devices. Vol. Ed-27. Pgs
899-906. May 1980
76
15. Ng, K.K., Lynch, W.T. "Analysis of The Gate-Voltage-Dependent Series Resistance
of MOSFET'S." IEEE Transactions on Electron Devices. Vol. Ed-33, N0 2. Pr5
965-968. 1986.
16. Scott, D.B., Hunter, W.R., and Shichijo, H. "A Transmission Line Model for
Silicided Diffusions: Impact on The Perfonnance of VLSI Circuits." IEEE
Transactions Electron Devices. Vol. Ed-29, No. 4. Pgs 651-654. 1982.
17. Lunnon, M.E., Chen, J.T., and J.E. Baker. "Furnace and Rapid Thermal Annealing of
p+/n Junctions in BF2 implanted silicon." Journal Electrochemical Society. Vol.
132, No. 10. Pg 2473. 1985.
18. Mikoshiba, H., Abiko, H. "Junction Depth Versus Sheet Resistivity in BF2
Implanted Rapid Thennal Annealed Silicon." IEEE Electron Device Letters. Vol.
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Germanium Preamorphization" 1985 Device Research Conference.
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Journal of Solid-State Circuits. Vol. SC-18, No.4. Pgs. 418-425. August 1983.
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77
2.8. Dang, R.L.M., and N. Shigyo. "Coupling Capacitances for Two-Dimensional Wires." IEEE Electron Device Letters. Vol. EDL-2. Pgs. 196-197. August 1981.
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78
BIOGRAPHY
James M. Velopolcak was born in Easton, Pennsylvania on June
20 1962. He is the son of Dorothy and Joseph Velopolcak. He
graduated from Kansas State University with honors in December
1984 with the degree of B.S.E.E. and has been working with AT&T
Microelectronics-Allentown since January 1985. Ile currently is a
product engineer for linear and digital communication product.
79