An NMOS Telephone Codec for Transmission and Switching Applications

IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27, NO. 2, FEBRUARY 1979 30 5

An NMOS Telephone Codec for Transmission and Switching Applications

MARCIAN E. HOFF, JR., SENIOR MEMBER, IEEE, JOHN HUGGINS, AND BEN M. WARREN, MEMBER, IEEE

Abstruct-This paper describes a monolithic high-feature per-channel companded PCM coder/decoder (codec) and implications of the advanced architecture for fiied and variable time-slot applications. Tech- nology tradeoffs are identified, and implementation of the critical analog circuit functions in nchannel MOS technology is discussed. These circuits include the first commercial embodiment of a novel buried-ion voltage reference.

INTRODUCTION

T HE AVAILABILITY of low-cost integrated codecs [coder/decoders for conversion between analog voice and

digital PCM (pulse code modulation)] offers the promise of new architectures for telephone switching systems. Other LSI components may also impact future telephone switch designs.

Early codec designs were used primarily for transmission between switching sites. The switching of voice signals was handled by analog switching devices such as electromechanical crossbar mechanisms, with the voice being digitized prior to transmission to other switching sites. The digitization of the voice signals allowed the multiplexing of many voice channels over a few wire pairs.

With the availability of low-cost integrated codecs, it becomes reasonable to consider using a codec to digitize the voice signals of each subscriber line. The switching of the voice signals then becomes a digital function which can be performed by low-cost digital logic and memory. The majority of the electromechanical equipment can be eliminated, with correspond- ing savings in cost, size, and audible operating noise.

Codecs for use in digital switching may differ somewhat from those used for transmission. Codecs for transmission have traditionally multiplexed 24 (U.S. standard) or 30 (CCITT standard) voice channels through shared analog-to- digital (A/D) and digital-to-analog (D/A) c9nverters. This multiplexing allowed two pairs of wires to serve as 24 or 30 interoffice trunks. Because such trunks carry high traffic, the shared codec operated continuously using fixed time-slot assignments for each channel. Switching and concentration were performed on the analog side of the codecs.

It is possible to apply the shared converter architecture to the subscriber line service, but there are several disadvantages. The traffic on typical subscriber lines is much less than that of

Manuscript received August 21,1978; revised September 25,1978. M. E. Hoff, Jr., and J. Huggins are with Intel Corporation, Santa

B. M. Warren is a private consultant. Clara, CA 95 05 1.

interoffice trunks. With a fixed time-slot assignment, most time slots would carry no useful information. Because a shared converter must be kept powered for all channels if any channel is active, the shared architecture tends to be wasteful of power when used for t h i s function.

Reliability may also be poorer with a shared converter design. In the transmission application, alternate paths and switching on the analog side can reroute calls in event of a shared converter failure. Unless some redundancy is added, a failure in a shared converter could interrupt service to all 24 or 30 subscribers. However, allocating more than one digital channel per subscriber may be prohibitively expensive, and switching on the analog side would eliminate most of the size and noise reductions associated with the digital conversion.

An alternate architecture made possible by low-cost LSI is that of a single-channel codec per subscriber line which includes logic on-chip for control of the time-slot assignment. The utilization of interconnecting buses and digital switching logic can be improved by connecting more codecs than the number of time slots. The number of codecs which can be used is determined by the traffic expected and the degree of blocking which can be tolerated. By placing idle units in a low-power standby mode, significant power savings can be realized. This paper describes the architecture of such a codec design.

When the authors first approached the design of a telephone codec, there were many options to be examined in process technology, as well as functions. Compatibility with existing transmission standards required the use of industry standard PCM encoding. The interface between a digital switch and digital transmission facilities is greatly simplified if code conversion can be avoided. In addition, the properly designed codec for switching can perform the functions needed for transmission.

The use of PCM over other encoding techniques adds some complexity to the design of D/A and A/D converters. Many earlier codec designs for switching applications avoided PCM and its complexity by using delta modulation techniques. While these techniques simplified the converters, the interfaces to transmission facilities were made more complicated. In addition to the conversion specifications, telephone industry standards for PCM also specify clock rates, framing, and signaling for the digital signals. Both standards specify serial time-multiplexed digital busses. Since microprocessors have been rapidly coming into use as telephone switching system controllers, it is highly desirable to have the codec operate

0090-6778/79/0200-0305$00.75 0 1979 IEEE

306 IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27, NO. 2, FEBRUARY 1979

SAMPLE GATE

SAMPLING SWITCHES

- AGND r -

T

I

POLARITY CONTROL

1 REVERSING POLARITY

SWITCHES

FROM

COMPARATOR

Fig. 1. Sample and hold circuit.

much like an “intelligent” peripheral chip. To reduce the .burden on the system controller, it is also desirable for the codec to accept and retain time-slot assignments and to perform multiplexing and demultiplexing of the data from the digital channels without further intervention by the controller.

CHOICE OF TECHNOLOGY The functions and performance of a codec for telephony

challenge the capabilities of any integrated technology. A codec (encoder/decoder) must perform A/D and D/A conversion of voice data while meeting stringent noise, gain track- ing, and stability specifications.

The choice of a process for implementing a codec must consider not only the analog circuitry but also the extensive logic needed to complete the digital portion of the design.

Because of the large amounts of logic required for even basic codec functions, an n-channel MOS (NMOS) process was pre- ferred. However, at the time the codec development was undertaken, there was very little commercial experience with analog circuits in NMOS. Except for memory sense amplifiers, most analog MOS development was in a research phase, without the extensive characterization and reliability data necessary for a successful commercial product.

The analog requirements for a codec are rigorous enough that once met, the solutions could be extended to many other A/D and D/A applications. An NMOS solution offered the possibility for developing advanced microprocessors with analog input/output capability.

Another potential advantage for NMOS was extension to fdters. All codecs require input and output antialias fdters because of the sampled nature of the system. Switched capacitor and CCD filter techniques are compatible with NMOS and could be included in future products [l] -[3] .

Other process technologies were also considered but did not appear to offer as many advantages as NMOS. Bipolar technologies had traditionally been used for linear circuits but did not offer adequate logic density for the digital portions, nor did they offer good analog switches. I z L may have offered improved logic density but seemed incompatible with linear bipolar processes and also lacked analog switches.

CMOS offered low power and had some established analog capabilities. However, some of the power advantages of CMOS would also be lost in analog circuits, because unlike logic circuits, analog circuits must draw some quiescent current to maintain linearity. CMOS also suffered from poor logic density and process complexity. In addition, many telephone applications require component replacement with the power applied. The CMOS tendency to latch up under such conditions was also felt to be a potential reliability problem. As a result, the first efforts were made in NMOS technology.

Four major analog circuit elements were necessary to complete the codec functions: an analog sample and hold circuit, a D/A converter, a buffer amplifier, and a comparator. It also was deemed highly desirable to provide an on-chip voltage reference to avoid the problems of either distributing a preci- sion voltage throughout a system or providing numerous precise sources in a system. ,

FLIP-SWITCH SAMPLE AND HOLD The availability of zero-offset analog switches in NMOS

technology makes possible a very simple sample and hold circuit. An external capacitor is momentarily connected across the input terminals by the analog sampling switches as shown in Fig. 1.

A simple extension of the circuit permits use of a single- polarity voltage reference and a reduced DAC. Once the input value has been sampled and its sign determined by the comparator, pole changing switches (flip switches) connect the capacitor such that its negative end is grounded. The input to the comparator is then positive so that only positive DAC outputs are needed. The circuit requires the DAC to cover only one-half of the voltage range of the input signal. If desired, the sign-magnitude conversion that results can be converted to two’s complement by logic.

DAC The basic DAC used for the NMOS codec is a diffused resis-

tor string and switch structure. The structure is folded into loops to reduce its area and to simplify connections to a shunt

HOFF et al.: NMOS TELEPHONE CODEC 301

1

! ANALOG

n

1 ANALOG

0 LOGARITHMIC 0 WEIGHTED COMPANDING RESISTORS 0 UNIT INTERPOLATION RESISTORS 0 128:l RESISTOR RATIOS -v- DAC

OUTPUT

Fig. 2. Nonlinea companded D/A converter.

V-

Fig. 3. MOS voltage reference.

resistor network which realizes the companding law. The basic structure is shown in Fig. 2.

The folding of the array also reduces the maximum linear dimension of the array. By this method, the contributions of sheet resistivity gradients to resistor mismatch are reduced. A combination of metal jumpers and dummy contacts spaced throughout the array eliminates discontinuities at the ends of each column.

The companding laws are implemented with shunt resistors having values covering a range of 128: 1, which are matched to the loops of the basic DAC array. These resistors are realized by series-shunt combinations of diffused resistors equivalent to those used in the DAC. Extensive use of simulation was made to ensure meeting the companding laws and to optimize the layout. Dummy structures and symmetry in layout were also used to minimize the impact of the process and masking variation.

BURIED-ION VOLTAGE REFERENCE The gain and stability of a PCM channel can be impacted

by changes in the voltage reference used with the DAC. To meet gain stability requirements, this reference voltage must be held to a tolerance of 0.1 dB. Distributing a common reference voltage can result in inferior performance because of noise pickup and voltage drops. System reliability considera- tions also place a penalty on a common reference voltage.

An on-chip NMOS voltage reference circuit (Fig. 3) was developed using the difference in the threshold of two transistors Q2 and Q3 [ 7 ] , [8] which differ only in the implants they receive. The transistors show very similar sensitivities to substrate bias and temperature, so that the difference in thresholds is determined exclusively by the implants. The implanted ions are immobile in the crystal structure at tem- peratures below 900°C and are sealed in by high-integrity thermal gate oxide. By implanting one device (e,) to make it


INPUT SENSE AMP

DAC k - v - - *I

2

DEMONSTRATEDCOMPARATORPERFORMANCE OFFSET < 100 pV

SPEED I2.5 psec CYCLE TIME RESOLUTION 100 pV

Fig. 4. Low-offset high-gain NMOS voltage comparator.

TRANSMIT SECTION

VFx AUTO

CAPPX CAPIX

* ~ SAMPLE , I - - 6 '

~

SUCCESSIVE =x

-L APPROXIMATION T HOLD REGISTER - - CLKX

-- DX

FSx A

+ COMR T -

I I I CONTROL SECTION + PDN

DAC f k c CLKC

I

INPUT REGISTER

RECEIVE SECTION

GRDA t t t t t OR00 VBB WC M D

Fig. 5 . Codec block diagram.

an enhancement type and the second (Q,) to make it a deple- tion type, the magnitudes of the thresholds add when the threshold difference is taken. In this way, a reference voltage of several volts can be produced.

The manufacturing spread of the reference value shows a larger variation than tolerable for the codec application. To compensate, a buffer amplifier [4] with gain trimming poly- silicon fuses is used to adjust the final value to 3.15 f. 0.02 V. This value was chosen to fall within a range compatible with the chosen power supply voltages yet be related to telephone system voltages. With this reference value, standard telephone levels into 600 are doubled to provide normal codec input levels. The overall variation in the reference voltage with operating conditions and time is equivalent to a gain variation of less than 0.07 dB. Accelerated life tests indicate a 40-year drift equivalent of 0.01 dB.

COMPARATOR One of the most stringent requirements of a telephone codec

is for the comparator. The comparator must have low offset and low noise, because the first A/D conversion level is only 400 pV. The use of chopping techniques for offset nulling makes this specification feasible to achieve in NMOS.

The technique used consists of acquiring the offset voltage of a difference amplifier on a pair of capacitors [ 5 ] , then switching to measure the difference between the sampled input voltage and the DAC output. The use of difference amplifiers with a symmetric layout reduces the sensitivity to power supply variations.

The basic circuit used is shown in Fig. 4. The multiple stages are sequentially clocked to reduce the offset voltage due to circuit imbalance and clock coupling. The final stage is a flip-flop biased at equilibrium and then released to perfom the comparison. This circuit is very similar to those used as dynamic memory sense amplifiers [ 6 ] . Table I shows some of the performance achieved by these techniques. The target specifications were made more severe than the 0 3 specifications to account for use in switching applications.

Fig. 5 shows a block diagram of the NMOS codec. The central portion of the diagram indicates the circuits used by both the encode and decode functions. The DAC and microcomputer control circuits are major shared functions. For transmission applications, the encode (transmit) and decode (receive) portions must operate asynchronously. To permit sharing of the DAC in this environment, an interrupt scheme is used to temporarily suspend A/D conversion when the re-

HOFF et al.: NMOS TELEPHONE CODEC

TABLE I CODEC AC PERFORMANCE

309

P A R A M E T E R 0 3 S P E C

T A R G E T P E R F O R M A N C E S P E C

T Y P I C A L D E V I C E

b

I D L E C H A N N E L N O I S E 12 d B r n c O < 15 d B r n c O < 2 3 d s r n S 0

G A I N T R A C K I N G

@ - 37 d B m O <0.5 d B 1 <0.3 d B 1 0.1 d B I @ - 50 d B m O

I - 5 5 d B m O

~ 0 . 5 d B <1 d B

< 1 d B < 3 d B

S I G N A L I D I S T O R T I O N

@ - 3 9 dBmO

>36 dB >33 d B I - 0 d B m O

>36 dB >33 d B @ - 29 dBmO

>30 d B >27 dB

0 . 5 d B

1 d B

3 3 dB

3 9 d B

4 1 d B I I I

C R O S S T A L K >EO d B 7 5 d B N . A .

ceive channel requires the DAC. This process does not inter- fere with the timing of the sampling circuits.

A/D conversion uses a successive approximation algorithm. Because the DAC implements the companding law directly, no code conversion is needed. The receive decoder includes a sample and hold circuit at its output, whch introduces a sin (x)/x frequency response where x = ~f/f, and f, are the system sample rate, established by frame sync. In normal operation, f, = 8 kHz. Filters used with the device should include sin (x)/x correction. Because any digital code is produced by some analog input signal which falls between two encode levels, the decode level for that digital code is best chosen to fall midway between the two encode levels. The DAC provides 256 steps, half of which are used to define encode decision levels, with the remaining half used for decode levels.

The p-law (U.S. standard) version of this chip is housed in a 24-lead package and includes signaling input and output leads. The A-law (CCITT standard) chip is housed in a 22-lead package. Because the signaling used in the CCITT standard does not involve replacing data bits, provision for signaling was not included in the A-law version. Both versions of the chip are 22 OOO mil2 in area.

USE OF THE MICROPROCESSOR INTERFACE As shown in Fig. 5, two leads control the time-slot assign-

ment. One, the control clock CLKc, serves to shift a control command into internal registers. Each control command consists of one 8-bit word. The control clockmay be asynchronous to other system clocks but should take no more than 125 ps for a burst of eight pulses. To prevent causing system dis- turbance, the internal logic prevents any change in the time- slot assignment until the second frame sync pulse after the completion of the burst.

The data lead D, accepts the eight bits of the control command. The first two bits select one of four control modes, and if an assignment is made, the last six bits select the time slot. The four modes are to set the receive channel time slot, to set the transmit channel time slot, to set both, or to set to a standby low-power condition.

An alternative operating mode is provided for transmission or other fixed time-slot applications. To activate this “direct control” mode, the clock lead (CLKc) is tied high, and the data lead becomes an active low chip select. When this lead is

low, both time-slot control registers are set to time-slot zero. When the data lead is high, the chip goes into the low-power standby mode. In this direct control mode, the 24-30 codecs used in a transmission system must then each receive differently timed frame sync pulses which are generated by common control logic.

For switching applications, a simple interface converts each I-byte microprocessor command to an 8-bit sequence and simultaneously gates a burst of eight clock pulses to the selected codec. By connecting the two digital data paths to- gether, small switching systems can perform call routing without any additional switching hardware. The microprocessor assigns two time slots per conversation, one for each direction. One time slot is assigned to the calling party’s transmitter and the called party’s receiver, the second to the called party’s transmitter and the calling party’s receiver.

In large systems, a single multiplexed data path (typically 24-32 time slots) will not be sufficient to handle the traffic. These applications will require digital interchange modules to perform switching between numerous multiplexed data paths. Although a shared codec with a fixed time-slot assignment could be used once a digital interchange is required, the codec with a variable time-slot assignment can still provide an overall cost reduction. The cost of the digital interchange is determined primarily by the number of multiplexed data paths to be serviced. The number of codecs (i.e., subscriber lines) serviced by each multiplexed data path is typically doubled or trebled by conversion from a fixed to variable time-slot assignment. Thus the per-line cost of the digital interchange is less when variable time-slot assignment codecs are used.

A second “cost” associated with the digital interchange is delay. Current specifications limit acceptable delay through the switching system to 1 ms. Approximately half of this figure is associated with the fiters and codecs. Each digital interchange will also contribute some delay, up to one sample interval (125 ys). Reducing the number of digital interchange modules needed can reduce the overall delay. A variable time- slot assignment can be used to reduce the number of interchange modules needed and, in some cases, to reduce the overall delay by proper selection of time-slot assignments.

Fig. 6 shows the architecture of a small switching system. The PCM clock generator produces the basic timing signals used by the codecs. The microprocessor interface module


I

LINE INTERFACE, LINE

FILTER, ETC.

O R 4

4 I

-. I

1 ETC. TRUNK

TRUNK INTERFACE,

I SOURCES

CODEC SELECTION CONTROL

PCM TIMING GENERATOR INSERTION,

SIGNAL

EXTRACTION

MICRO- COMPUTER

Fig. 6. Small telephone switching system.

Fig. 7. Control for dualdigitaldata paths.

HOFF et al.: NMOS TELEPHONE CODEC 31 1

progress tones. The remainder are used for local lines or telecommunications product development. He is the inventor or trunks. co-inventor on 10 U.S. patents.

An expansion of the basic architecture of Fig. 6 can be made Dr. Hoff is a member of Eta Kappa Nu, Tau Beta Pi, and Sigma Xi.

by providing one or more additional multiplexed data paths, with interfaces between codecs and data paths which allows data path selection. The NMOS codec described in this paper provides an output lead which provides a signal indicating when transmission is occurring. This signal may be used to enable buffer gates onto the multiplexed data paths. Fig. 7 shows an interface which allows two data paths to be used. This architecture provides a degree of redundancy as well as additional capacity.

CONCLUSION An NMOS technology has been utilized to implement a

telephone codec which can serve transmission applications yet also includes special features for switching. Techniques for D/A and A/D conversion have been developed within the technology, and excellent performance specifications have been achieved. The high. functional density of NMOS has resulted in a small and economical chip.

REFERENCES G. Weckler, “The serial analog processor,” in Int. Solid-state Circuits Con5 Dig. Tech. Papers, 1975, p. 142. J. Mattern and D. Lampe, “A reprogrammable filter bank using CCD discrete analog signal processing,” in Int. Solid-state Cir- cuits Confi Dig. Tech. Papers, 1975, p. 148. Smith et al., “Active bandpass fdtering with bucket brigade delay lines,” IEEE J. Solid-state Circuits, vol. SC-7, p. 421, Oct. 1972. D. Senderowicz, D. A. Hodges, and P. R. Gray, “High-performance NMOS operational amplifier,” IEEE J. Solid-State Cir- cuits, vol. SC-13, p. 760-766, Dec. 1978. R. Poujois, B. Boylac, D. Barbier, and J. J. Ittel, “Low-level MOS transistor amplifier using storage techniques,” in Int. Solid-state ’

Circuits Con$ Dig. Tech. Papers, Feb. 1973, p. 152. C. N. Ahlquist et al., “A 16K dynamic RAM,” in Int. Solid-state Circuits ConJ Dig. Tech. Papers, Feb. 1976, p. 128. M. Hoff, “MOS reference voltage circuit,” U.S. Patent #4 100 437, fded 7/29/76, issued 7/11/78. M. Tobey, D. Giuliani, and B. Ashkin, “Flat band voltage reference,” U.S. Patent #3 975 648, fded 6/16/75, issued 8/17/76.

IEEE,vol. 66, pp. 182-191, Feb. 1978. D. Melvin, “Microcomputer applications in telephony,” Proc.

J. Huggins, M. E. Hoff, and B. Warren, “A single chip NMOS PCM voice CODEC,” in Int. Solid-state Circuits ConJ Dig. Tech. Papers, Feb. 1978, p. 178.

Marcian E. Hoff, Jr. (SY55-M’62-SM’78) was born on October 28, 1937, in Rochester, NY. He received the B.E.E. degree from Rensselaer Polytechnic Institute, Troy, NY, in 1958, and the M.S. and Ph.D. degrees from Stanford Uni- versity, Palo Alto, CA, in 1959 and 1962, respectively.

From 1962 to 1968 he worked at Stanford University as a Research Associate dealing with adaptive systems. He joined Intel Corporation, Santa Clara, CA, in 1968, as Manager of Ap-

John Huggins was born in Billings, MT, on March 9, 1945. He received the B.S.E.E. and M.S.E.E. degrees from the University of Min- nesota, Minneapolis, in 1971 and 1973, respectively.

He joined the Applications Research Group at Intel Corporation, Palo Alto, CA, in 1973, where he became involved in the advanced development, modeling, and application of highdensity MOS circuit techniques. Since 1976 he has been engaged in the design of a

monolithic NMOS voice coder-decoder. He has been granted a patent on a voltage-controlled monolithic low-pass filter and is coauthor of a patent on an integrated D/A converter. He is coauthor of a paper presented at the International Solid-state Circuits Conference in February 1978, on the monolithic NMOS coder-decoder.

Ben M. Warren (”70) was born in Tucson, AZ, on February 25,1943. Hereceived the B.S.E.E. degree from California State University, Long Beach, in 1967, and the M.S.E.E. degree from California State University, San Diego, in 1970.

In 1967 he joined Stromberg Data Graphics as a Digital Design Engineer on various computer to microfdm systems. In 1969 he joined Union Carbide Microelectronics in the development of p-channel MOS integrated circuits. He worked on simulation programs for circuit de-

sign and circuit development. Upon dissolution of those activities when Union Carbide was pur-

chased by Solitron Corporation, he and others in the MOS operation formed Unisem Corporation in an existing division set up by United Aircraft Corporation.

In 1971 he joined Intel Corporation, Palo Alto, CA, working in microcomputer development on the 8008 and other products. In 1973, he spent a year as Product Engineer for the 1103 dynamic RAM, co-

returned to design, this time to RAM’S, designing Intel’s 5101 CMOS ordinating testing, production, and customer interfaces. In 1974, he

RAM. He then headed the design group that was responsible for the 2115 high-speed static products, including ROM’s. In 1976, he formed the nucleus of a group to develop process and products for the telecommunications industry. The 2910 codec and the 2912 PCM fiiter are two of those products. He left Intel in September 1978, to pursue other interests.

Documents

An NMOS Telephone Codec for Transmission and Switching Applications