Analog Design Methodology Jnotor r3

7/30/2019 Analog Design Methodology Jnotor r3

1/17

INVEN

T

IVE

Analog Design Methodology in a Time

to Market Environment

John NotorJuly 17, 2009Rev 3


2/17

July 20, 20092

Overview

Cadence Services Overview

Cadence AMS Project Flow and Management

Cadence Projects vs Academic Research

Example Designs


3/17

July 20, 20093

Cadence Holistic SolutionsEnabling customers to achieve breakthrough results

Ex

tendingCus

tomerCapabilities

Maximizing Results from Cadence Technology Platforms

BoardPkgDFT

&DFM

TimingElectrical

Verify

PhysicalImplement

FunctionalVerification

Digital IP

Verif IP

AMS IP

SystemDesign

CadenceLeading-edge

EDA

Products

Custom, On Site, On Line, Public Course Offerings

Design Ready Process Design Kits

Design Centric Flows, Methodologies, CAD Support

Training

DesignEnvironment

Enablement

Partners: Verification IP, Silicon IP, Silicon & Board Mfg, Packaging, Test

DesignAugmentation

ALLEGRO

Package

and PCB

VIRTUOSO

CustomIC

ENCOUNTER

DigitalIC

INCISIVE

Verification


4/17

July 20, 20094

Worldwide Services Team

USA

San Jose

Livingston

Columbia

Shanghai

Paris

Bracknell

Cary

Munich

Yokohama

Bangalore

Collaboration HubHosting Hub

Noida

Zelenograd

Melbourne


5/17

July 20, 20095

Analog/RF/Mixed-signal Design and Methodology

Broad and Deep Design Expertise 83% SoC designs, 90% low power, hi-perf CMOS

111 analog specific tapeouts in the last 4 years

Package/IO interactions, digital substrate

coupling/isolation, multiple power, device matching,

stress, well, NBTI/LOD feature implementation AFEs, Datacom, RF, Synthesizers, PLLs, A/D, D/A

Efficient and Effective Design Environment

Design and methodology project collaborations

Experts in design environment enablement

Design-ready PDK customization

Reliable Tape-out Success

98.1% First Pass Functionality

87.4% First Pass to Production

96.1% Full Parametric Operation with 1 metal spin 100+ products in volume production

.35u to 40nm for CMOS, Bipolar, BICMOS, SiGe

System-on-Chip

Logic Design & Verification

Silicon/Package/Board

Analog/Mixed Signal/RF


6/17

July 20, 20096

Design Flow Focused on Achieving First Pass Success

Extraction

Re-Simulation

System DesignSystem Design Matlab Custom

Spectre (RF)

Analog Design & Simulation

Spectre

VSE-L

ADE-XL (Corners)

Spec Review, PartitioningSpec Review, Partitioning White board NC SIM

Architectural SimulationArchitectural Simulation AMS Designer

Physical Design VLS-XL VCAR - Custom routing

Digital Synthesis

Digital Place & Route (VDIO)FE SE

RTL Compiler NCSIM

Simulation VerificationSimulation VerificationMMSim: NCSIM, Spectre, Ultrasim

FloorplanningFloorplanning VLS-GXL Encounter

MS Design & Simulation

Chip Assembly VLS-XL

NC SIM

Spectre/Verilog AMS

MS Design & Simulation

UltraSim

VSE-L

ADE-XL (Corners)First Encounter - Floorplanning

AMS Designer

VCAR power grid

Spectre UltraSim

Chip VerificationAssura DRC/LVS/RCX/RF

VAVO/VAEO EM/IR

PVS DRC

UltraSim

SOC Encounter

DFIIbased

design

Excel SystemVue

Verilog (D, A, AMS)

PVS DRC

Verilog (D, A, AMS)

Conformal

Excel

Assura DRC/LVS/RCX/RF


7/17

July 20, 20097

Emphasis on Top Down Mixed Signal Design Flow

HDLSchematicAbstract

HDLSchematic

Functional Sim(Pin for Pin)

Block Level:Design / SynthesisCorner VerificationSparesLayout constrains

Top Level SimulationDevelopment

Top LevelDevice Verification

Functional

Simulation

AnalogCircuits

Analog

Circuits

Mixed SignalBlocks

Logic

HDL

HDL

Verilog/HDL

Verilog

HDLSchematicAbstract

HDLSchematic

HDL/VerilogSchematicAbstract

HDL/VerilogSchematic

VerilogRTL

Abstract

VerilogRTL

Block Level:Abstract Creation

Schematic

HDL

Verilog/HDL

Verilog

Paper Spec

Spec Verification

Simulation strategytest bench(s), modes,startups, I/O considerations

Top-Down Design Methodology

(INVITED Tutorial)E1-1 Proceedings of the IEEE 2007


8/17

July 20, 20098

Program Flow Emphasizes Review at Key Milestones

Tech. Table Devel

Model ExtractionDesign Kit

Analog Design,Schematic Entry

PDR

AnalogSimulations

CompositeSimulation

CDR

AnalogLayout

ParasiticExtraction

DigitalLayout

CompSim

FDR

PhysicalVerificationDRC, LVS,EM/IR etc.

FloorPlan

Partitioning,Interfaces,

Prelim FloorPlan,

Testability

FabProtoTest

DigitalSimulations

OR

Digital Design,Schematic Entry

Synthesis

TR

Customer

DesignDefinition

SpecificationDevelopment

Tech DefinitionFoundry Selection

Customer Participation

Customer Participation

Customer

FunctionalModel:AMS

Designer

DeliverablesDeliverablesDeliverables

Deliverables

Deliverables

CustomerParticipation

KOR

RFD


9/17

July 20, 20099

Project Management Focused on Clear Communication

Program Manager Primary point of contact

Program execution ownership

Project Communication Plan

Weekly Meetings Weekly Status Report

Deliverables

Action Items

Open Issues/Risks Agreements

Project Tracking

Schedule

Formal Design Reviews Design Milestone Deliveries

Steering Committee Meetings

Rating

Resp

Resp

Project Status - Summary

Plans for next week

Key Risks

Executive Summary

Key Issues

Status

No new actions.

Actions closed this week (see Actions tab for details)

New Actions (see Actions tab for details)

No new agreements

New Agreements (see Agreements tab for details)

At a glanceAt a glance weekly status clearly reports onweekly status clearly reports on

all aspects of the onall aspects of the on--going projectgoing project


10/17

July 20, 200910

Cadence Design-ReadyPDKs Increase Productivity

Additional components to standard baseline foundry PDK Metal resistors for each level of metal with a unique recognition shape

Metal fingered interconnect capacitor PCells

Symmetrical center-tapped inductors

MOS varactor

Native devices

Guard ring structures

Enhanced simulation features Device parameters minimum set to recommended

Corner models for Parasitic resistors and capacitors

MOS cells that allow the user to anticipate LOD (STI) effects at schematic level and control theeffect in simulation

Model and control well proximity effects

MOS layout-XL multiplier separate from simulation multiplier to enable interdigitation whilesimulating as a single multi-fingered device

Analog layout capabilities Recommended rules followed in all PDK device layouts

Minimum area diodes for use as antenna diodes Guard rings that can create multiple contact rows

Integrated dummy gates on each end of MOS device

Ability to merge source drains of devices and reflect in callback


11/17

July 20, 200911

Cadence Projects Differ from Academic Research

Project length fixed in the range ~18-26 weeks. Project team expands to complete the design effort in the allotted time.

Dedicated layout personnel work with the circuit designers to create/completelayout.

Server resources are sufficient to meet the needs of multiple projects,resources are scheduled appropriately for the project phase.

The core team has worked together on multiple projects, cooperates well inthe midst of complex and diverse competing projects.

For the most part, technology objectives for the project, including performance

requirements and process limitations, are well understood before the designeffort begins.

The technical approach taken most often involves evolution from an existing,proven approach.


12/17

July 20, 200912

13.2 GHz Frequency Synthesizer Macro

Synthesizer Output from ~11.5 to 13.2 GHz

66 MHz Reference

Differential Quadrature I & Q outputs

Very low phase noise operation

Jitter < 60 fs rms, integrated from 3.5 MHzto 1 GHz

Internal Self-Calibrating LC VCO

Internal regulator for power supply immunity

Integrated Analog Test Bus

No external loop filter required

Power Down Mode

TSMC 90 nm G Logic Process

Area ~ 1.2 sq mm

In Production


13/17

July 20, 200913

AFE for Next Generation Wireless Multimedia

Dual 6-Bit 2.6 GHz ADC Interpolating Flash Architecture

Dual 6-Bit 2.6 GHz DAC Programmable current source output

Low Jitter 2.6 GHz PLL LC VCO architecture

7 to 8 GHz Frequency Synthesizer 4th order, dual path

Low jitter LC VCO Low Phase Noise Crystal Oscillator

1:8 and 8:1 data serializer/deserializer

TSMC 65 nm LP Process

Multiple versions of this macro delivered

In Pre-Production


14/17

July 20, 200914

900 MHz Zigbee Transceiver RF Macro

Low IF RX Complex BPF

Complex CT Delta Sigma ADC (IQ)

Direct upconversion TX

Integrated -10 to +14 dBm PA

Fully integrated synthesizer

TSMC 180 nm CMOS

2

I

Q

IQ-ADC

PGAsComplex Bandpass

FilterMixer Digital Modem

4

Demod

AGC

AFC

Modulation

Control

Synthesizer

refclk_m

Bias

Cal

control

pgagain

pga_gain

bias_rext

adcclk

lnagain

LNA

gain ctrl

lna_rf_p

lna_rf_m

2

Mixer

PA

Tx pwr ctrl

io_rf_p

io_rf_m

daci

dacq

Tx I_DAC

Tx Q_DAC

Tx I_LPF

Tx Q_LPF

Antennaanttune

atbaddr

ATB MUX

4

adc_q

adc_i

Tx IQ_DAC_LPF

adc_ref

_p

adc_ref

_m

atb_

patb_

m

adcclk

dacclk

offseti

offsetqrefclk_p


15/17

July 20, 200915

12-bit Bandpass Complex Delta-Sigma ADC

Application: Zigbee Transceiver

Topology: Fourth Order Hybrid Delta-SigmaModulator with 4-bit Internal ADC/DAC

Tunable loop filter

Integrated ATB test bus

Specifications: 1 Vpp differential inputs (I/Q)

IF = 1 MHz

Bandwidth = 1.2 MHz

Sampling Rate = 30 MHz SNDR = 72.4 dB

6.3 mW typical at 1.7 V

Area of 0.7 sq mm

TSMC 180 nm CMOS


16/17

July 20, 200916

10-bit 12 channel SAR ADC architecture All 12 channels share a master sample

and hold

Differential analog input

ENOB: 8.8 (typ) @500 Msps; 250 MHz

input rate

500 MHz maximum sample rate

Integrated reference

Integrated offset trim DAC

Power down modes Integrated analog test bus

No off-chip components required

Low power: 62 mW typical

Area = 0.82 sq mm TSMC 90 nm G process 1.0 V/1.8 V

First silicon success

10-bit 500MHz ADC in 90nm


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Documents

Analog Design Methodology Jnotor r3