Plan-Based Analog Verification Methodology White Paper

Introduction

When talking about analog verification, the discussion often dives immediately into details of SPICE solver performance or statistical variation due to small geometries. In addition, the simulation environment—namely the Virtuoso Analog Design Environment—is discussed as the main working cockpit for analog designers. However, higher level questions, such as “When is the analog verification complete?”, “What are the verification goals”, or “Are the verification resources distributed correctly?” are seldom discussed.

The typical set of analog blocks used in modern designs is relatively limited: PLL, ADC, DAC, filter, LDO, and maybe another handful of other functional blocks cover most of the analog functionality. However, the functional and performance complexity of these blocks and the possible implementation variants have increased significantly over the years. Virtually all analog designs are mixed signal today. With shrinking process nodes, digital logic comes almost “for free,” while the analog parts are expensive due to their physical geometry limitations. Given that, calibrations and mode switching are done in the digital domain.

At the same time, the verification requirements on analog design are increasing. Standards—such as the ISO 262621 for automotive—require the whole design flow to be not only documented, but also traceable to guarantee the standards are being met. Even in the consumer market the requirements are increasing drastically, as failures in the analog domain are often fatal for systems on chip (SoCs) because severe failures in the analog blocks cannot be corrected by firmware updates during a product’s life cycle.

Plan-Based Analog Verification Methodology By Dr. Walter Hartong, Cadence

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence® Virtuoso® ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier presents that verification status in an easy-to-use cockpit inside the Virtuoso tool. Updates to the results or to the specifications are automatically reflected in the cockpit and thus the verification status is kept up to date. Verification holes can be identified and the process is automatically documented. If specification failures are found, it is simple to trace the exact test and owner to ensure that changes will be made.

ContentsIntroduction ......................................1

Analog Verification Problem ..............2

Digital-Centric Approaches ...............3

Plan-Based Analog Verification Methodology ....................................4

Conclusion ........................................9

References .........................................9

Analog Verification Problem

The Virtuoso Analog Design Environment is the design and verification cockpit for most analog designers. It is designed to support the interactive use model most analog designers favor, and it suits their needs by providing a set of features needed in the everyday work, including:

• Nominal, corner, and Monte Carlo simulation

• Set-up of measurements / specification

• Multiple testbench analyses within one cockpit

• Sophisticated set of analyses for analog, RF, and mixed signal

• Special statistical methods for high-yield and sub-16nm FinFET verification

In parallel to the Virtuoso ADE L/XL/GXL products, Cadence has recently introduced the Virtuoso ADE Explorer and the Virtuoso ADE Assembler. The third product of this new family—the Virtuoso ADE Verifier—addresses the need for a more formalized verification methodology.

The Virtuoso ADE family—be it Virtuoso ADE L, XL, Explorer, or Assembler—provides a perfect environment to support the interactive working style. However, a significant part of this verification is done ad hoc, meaning the analog designer knows the verification goals and he/she works iteratively to achieve those goals. There are no particular standards followed and the process is documented manually. Only a limited subset of the tasks are automated and repeated regularly in a regression set-up. In particular, there is no tool-based concept of high-level analog verification planning as has been introduced over the last few years in digital. Analog verification strat-egies and the tools have been developed and enhanced over the years to cater to people’s needs—why would this methodology run out of steam now?

Functional safety and first time right

With electronics rapidly entering every part of modern life, a growing need for electronic safety has developed. The most popular example is the ISO 26262 standard in the automotive industry 2, but similar standards can be found in other areas, such as medical devices, which are heavily regulated by the FDA3 in the US and similar organizations in other countries. Effectively, it requires the whole design/verification flow to be risk/safety aware.

These requirements reach out through the whole flow including analog design and verification. Documentation of the verification flow, including traceability into the analog domain, is an immediate outcome for the requirements. Minimizing the risk of harmful failures involves complete verification of the analog blocks in all working conditions and possible scenarios of the controlling environment. Detection of malfunctions and counter measurements must be considered.

Even in the consumer industry, the desire for a well-documented and structured analog verification approach is increasing to the point where companies demand certain verification steps/flows be followed. Why? The complexity of the SoCs is increasing year after year and “first time right” is still key. It is not acceptable that large mixed-signal chips fail due to analog problems. Digital/software problems can sometimes be worked around by a firmware update. Failures in the analog components are often fatal for the complete design. At the same time, the shrinking geometries make a robust analog design even harder.

Moving more and more functionality into the digital domain—digitally assisted analog—is a great strategy to overcome some of the problems, but the growing connection between analog and digital creates the need for well-structured mixed-signal verification in return.

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Plan-Based Analog Verification Methodology

Functional verification vs. performance verification

Verification tasks are often divided into either functional or performance-based tasks. The performance of a circuit—e.g., the open-loop gain of an amplifier or the timing performance of a multiplier—has a hard limit where a low performance would break the functionality, but circuits should be designed with a margin even above the limit. More gain and faster switching is always better. However, functional verification looks at the essential behavior: Does the register contain the correct value after initialization? Is the band-gap switched off when the power-down pin is high? The answer to these functional verification questions is Boolean.

Current digital verification flows are clearly separated into functional verification and performance/timing verifi-cation. The analog verification process is often focused on performance aspects, but the functional verification tasks should not be underestimated. With growing digital controls in analog, the functional aspect can definitely not be ignored anymore.

Plan-based or metric-driven verification (MDV) is often associated purely with functional verification, which is useful in the context of the digital verification. When analog verification is included, this assumption is not valid anymore. Performance verification is an essential part of the analog front-end design and verification process, so must be considered. Moreover, there is no reason why the verification methodology should be limited to functional only. The concept works perfectly fine for performance verification as is shown in the next sections.

Digital-Centric Approaches

Digital verification has changed and evolved drastically over the last 10-15 years. New languages, tools, and methodologies have been invented to increase the verification efficiency at the same rate as the complexity of the functionality is increasing.

MDV

The metric-driven verification (MDV) methodology is the de-facto standard for digital functional verification today. The universal verification methodology (UVM) even defines a standardized methodology framework 4. The core idea is a separation of the verification metric—a measurement of how much of a verification goal is achieved—and the actual verification tasks themselves. As long as the verification metric and the verification goals are correct and complete, the specific verification tasks are less important.

Separation of the verification metrics and tasks opens up the possibility to use random stimulus and combina-tions of different verification techniques, such as formal verification, assertion-based verification, emulation, etc. Whichever verification approach is used, the metric will tell how close the process is in relation to the overall verifi-cation goal.

One essential assumption in the MDV methodology is to have a complete and detailed verification plan defining all the verification requirements. The metric can only be as good as the definition of the goals.

UVM-MS

While the UVM methodology is clearly targeted to digital functional verification, it is possible to extend the idea to mixed-signal designs5. The languages SystemVerilog and e are both capable of dealing with real numbers, random-izing them, and measuring coverage on real values—an excellent way of extending the digital verification into the analog/mixed-signal domain.

This approach should be used when the verification task/team is mainly digital-centric and some analog function-ality should be included—preferably as a high-performance real number model. However, this approach is not well suited to cover analog-centric verification as the analog tools, working environment, and methodologies are funda-mentally different—and therefore the analog verification problem is different.

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Does this mean that plan-based verification should not be used for analog? Not at all! There is a lot to improve in the analog flow. From a high-level point of view, different verification problems and possible solutions look very similar. However, the working style, the detailed verification tasks, and the working environments are different. The Virtuoso Analog Design Environment with its different tools (Virtuoso ADE L, XL, GXL, Explorer, and Assembler) is the de-facto standard environment for analog verification. In these environments, analog users set-up their simula-tions, create measurements, set specifications, debug waveforms, etc. Historically, the analog verification approach is very interactive. The “art” of analog design is often hard to capture in formulas and boundaries. An experienced analog designer can tell in a fraction of a second if a waveform looks right or wrong, while trying to capture this knowledge in a precise measurement can be tedious.

Nevertheless, analog verification is automated more and more. Measurements and specifications are used in literally all designs and the use of assertions and device checks is growing rapidly. These checks help the analog designer to focus their attention on the important and complex problems while simple and easy-to-formalize tasks are automated in the environment.

Analog verification planning

The central part of a structured verification approach is a verification plan that defines the verification requirements and goals. Only well-defined goals for the overall verification tasks allow a formalized approach and provide a big picture overview. It is useful to structure the plan hierarchically following roughly the structure of the design and the different aspects of verification for each block.

The verification plan is influenced by various factors, such as:

• Functionality of each block

• Specifications (internal/external)

• Interfaces

• Architecture of the design

• Designer’s experience

• External requirements

• Existing simulation set-up

• Brainstorming and change management

It is important to cover all the different aspects of verification—listing all the specification values is certainly not sufficient. A verification plan is a living document that should be created by all parties involved in the process. Parts of the plan might be very well defined—like the specification values—while other parts of the plan heavily rely on human experience and common sense. The plan will and should change during the verification cycle. Some requirements will be missing after the initial steps. Others might be found to be too aggressive and thus need to be removed/relaxed later. Building the plan is a useful process as it focuses the team on the specific needs of the project.

Reuse is an important aspect for verification planning, as it is likely that a plan created for one project can—at least partly—be reused in the next project. Over time the plan will grow and mature.

A largely underestimated aspect of the verification plan is communication. The simple fact that people sit in the same room and try to formulate a verification goal often uncovers misunderstandings and communication problems—in particular when the parties are not working together every day.

Virtuoso ADE Verifier

The Virtuoso ADE Verifier is part of the new Virtuoso ADE product suite introduced in Virtuoso IC6.1.7 6. It allows users to connect their Virtuoso ADE Explorer and Virtuoso ADE Assembler-based verifications with an overall verifi-cation plan defined in the Virtuoso ADE Verifier. The tool has access to the results information produced in the Virtuoso ADE Explorer and the Virtuoso ADE Assembler and can thus connect the requirements with the results. The Virtuoso ADE Verifier user gains a detailed overview over the verification status of the team and can identify potential problems early. Moreover, the process is documented and failures can be traced to their root cause.

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Virtuoso ADE Verifier requirements

Verification requirements cover a wide range of different aspects—anything and everything that should be verified in the project should be listed. How these requirements can be fulfilled and whether or not they can be automati-cally tracked or have to be checked manually is not important for the plan.

The requirement plan in analog often starts with specification values of the different blocks followed by the modes of operation and environment conditions, such as temperature, supply voltage levels, and process variations. Expanding verification requirements even further offers more areas of verification that can and should be covered in a plan, such as yield targets, digital bus/register configurations, internal specification values, common-sense assumptions (stability, noise level, etc.), behavioral modeling requirements, design flow requirements, and post layout simulation. All of these requirements should be listed.

The goal is to collect requirements and initiate the discussion, so the format of the verification plan is not important. Spreadsheets or simple text documents can help to gather and list the requirements. Later, these requirements can be imported or entered directly into the Virtuoso ADE Verifier. Figure 1 shows an example of a plan created in a spreadsheet. Various requirements and specification limits are listed, owners are called out, and comments and color codes are used to track the status.

Figure 1: Example of a spreadsheet being used as planning and tracking tool

Keeping this plan and the status information up to date is the main challenge. The Virtuoso ADE Verifier can fulfill this task automatically and will create a link between the requirements and the implementation. The status of the verification is automatically kept in sync with the latest project results.

Figure 2: Verification plan captured in the Virtuoso ADE Verifier

The Virtuoso ADE Verifier allows the requirements to be entered directly in the Setup tab. An integrated editor (right side of Figure 2) allows details to be specified. The left pane provides a hierarchical tree structure of all the requirements entered so far.

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Requirements can be imported from existing formats, such as spreadsheets or CSV text representations. In addition, requirements can be created from the bottom up, meaning that there might be Virtuoso ADE Explorer or Virtuoso ADE Assembler cellviews that fulfill some of the verification requirements. These cellviews can be loaded and initial requirements will be automatically created for them. These bottom-up requirements can later be edited/modified to fit them into the overall verification plan.

As mentioned previously, the plan is meant to be a living document. It is almost impossible to create a set of requirements that is exact, complete, and practical at the very beginning of the design. Allowing the plan to change and evolve over time is the better approach. However, it is important to control when and how the changes to the plan are performed so that the team is kept aware of the latest expectations.

Defining the measurement implementations for the requirement plan

Once the requirements plan is completed or has at least reached a reasonable status, the next step is to create or reference the implementations that fulfill these requirements. Implementations in this context are Virtuoso ADE Explorer or Virtuoso ADE Assembler cellviews that simulate, measure, and verify certain aspects of the design. (For more information about the Virtuoso ADE Explorer and the Virtuoso ADE Assembler, refer to the user guides.7, 8)

The user can simply browse to the library, cell, or cellview in question and load it into the Virtuoso ADE Verifier. It is shown on the right side of the Setup tab (Figure 3). The tests and output measurements with the specification values are shown in a tree structure.

Figure 3: Implementation and mapping in the Virtuoso ADE Verifier

The obvious next step is to add a correlation between the requirements and the implementations—this process is called mapping in the context of the Virtuoso ADE Verifier. The user can select one or multiple requirements and one or multiple implementations, and map them. In most cases, a one-to-one mapping will be sufficient. The mapping indicates that the particular requirement will be fulfilled by the selected implementation.

The Virtuoso ADE Verifier is now able to double check that the specification values in the plan and in the imple-mentation match. If this it is not the case, the user will be informed about the problem and can take counter-measures. The Virtuoso ADE Verifier can, for example, push the correct specification values down into the implementations or—if is the specification values in the plan that were incorrect—can pull the values up and correct the plan. This connection ensures specification values are formally tracked in a top-down manner, but keeps the tools independent in case there is a good reason for having different specification values—for example, as a short-term experiment or if the same implementation is used in different design contexts.

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Executing implementations

The designer might have the latest simulation results already available, in which case it is possible to point the Virtuoso ADE Verifier directly to the appropriate history item to be loaded. In other cases, it might be beneficial to rerun the simulation from within the Virtuoso ADE Verifier to ensure that the results are up to date. The results tab shown in Figure 4 enables the Virtuoso ADE Verifier user to manage the current simulation.

Figure 4: Results tab allows designer to run implementation

The named history items in the Virtuoso ADE Assembler allow users to control which set-up is executed or which results are loaded. The default option is the “active” set-up, meaning the latest simulation set-up available. If the designers are doing experiments and run a lot of simulations interactively, active set-up might not be the best choice. In this case, it is better to agree on a history item name that should be used in the Virtuoso ADE Verifier, such as “LatestResults.” If this status is selected in the Virtuoso ADE Verifier, any changes to the active set-up and other history items being created do not influence the Virtuoso ADE Verifier status. Only when the designer has reached a new status that should be populated to the Virtuoso ADE Verifier view, can the respective history item be called “LatestResults.” The Virtuoso ADE Verifier will now refer to this new status.

The Virtuoso ADE Verifier provides a command-line interface that allows the user to set up an automatic batch regression script to run the implementations in predefined intervals, such as nightly. This approach ensures the behavior of the analog blocks in the regressions remains as expected and is not altered by a mistake.

How many implementations are executed by a centralized regression set-up in the Virtuoso ADE Verifier and how many individual designers run the simulations will largely vary and thus it is hard to give clear recommendations. In general, it makes more sense to have a centralized regression set-up for mature and stable design blocks, tests, and testbenches. For active design and verification phases with many changes and iterations and for very long simulation runs, it is probably more useful to run simulations interactively by the designers as needed.

The Virtuoso ADE Assembler provides a capability called “incremental simulation,” which can be used in the Virtuoso ADE Verifier to avoid unnecessary simulations to be performed on a nightly basis. Effectively, the design and simulation set-up status will be captured with the simulation results. If the tool cannot detect any changes compared to the latest results, it will assume the results to be still up to date and will skip this particular simulation.

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Verification results

The Virtuoso ADE Verifier has access to the verification goals, the implementations, the mapping relationship between the two, and the results for the verification run. With this information, it can present a detailed status of the verification project. Figure 5 shows the results tab of the Virtuoso ADE Verifier. The structure follows the hierarchical plan previously entered. The red and green icons give a clear indication of the status of each item, and percentage numbers sum up the results hierarchically in the tree.

Figure 5: Verification results shown in the Virtuoso ADE Verifier results tab

This overview enables the verification team to plan the next steps and focus on problematic areas. The results might indicate the following scenarios:

• Specific failures in some verification tasks

• Missing implementations and/or mapping for requirements

• Incomplete requirements

• Overly aggressive verification requirements

• Resource limitations with respect to the project schedule

• Unexpected status differences among the team

Once the major problems are identified, countermeasures can be implemented. The Virtuoso ADE Verifier flow can be used iteratively until the verification is complete, also known as “verification closure.”.

The Virtuoso ADE Verifier provides various report capabilities to capture the status as an HTML page or to send out a text report by email. If the verification status should be reported into third-party tools, an XML report can be created to share the status information or SKILL® APIs can allow a direct integration of tracking tools used.

Reuse

The effort to create a precise verification plan listing all verification aspects and capturing all the changes applied over time might initially look inefficient. For the first project, it might well be that a less structured, less formal verification approach is faster. However, reuse is an important aspect in the verification methodology.

Most designs go through cycles and variants. It is likely that the next verification project will be similar to a previous project. An existing verification plan from a previous project is an excellent starting point. With minor modifica-tions, a good verification structure can be put in place. On top of the major verification tasks, the reused plan will also provide information about less obvious verification items, areas that need special attention, and possible resource bottlenecks in terms of verification planning.

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Conclusion

The Virtuoso ADE Verifier fills a long-standing gap in the custom design world by providing an infrastructure to follow a formalized verification methodology that takes the special needs of the analog design flow into account. The Virtuoso ADE Verifier provides an overarching tool for an entire design team. Updates are automatically reflected in the cockpit, and verification status can be shared and monitored.

Once the Virtuoso ADE Verifier has been set up with all the appropriate tests, a command-line regression can be set up to provide constant access to the verification status across the entire team. If specification failures are found, the exact measurement, specification, and owner of that test can be traced to alert that changes need to be made.

The Virtuoso ADE Verifier is fully integrated into the Virtuoso ADE framework and thus is easy for the analog community to access.

References1 ISO 26262-1:2011 Automobiles—Functional Safety: http://www.iso.org/iso/catalogue_detail?csnumber=43464

2 Cadence white paper: Meeting Functional Safety Requirements Efficiently via Electronic Design Tools and Techniques: http://www.cadence.com/rl/Resources/white_papers/Functional_Safety_wp.pdf

3 FDA Standards (Medical Devices): http://www.fda.gov/medicaldevices/deviceregulationandguidance/standards/default.htm

4 UVM Standard: http://accellera.org/downloads/standards/uvm

5 N. Khan and Y. Kashai 2012, “From Spec to Verification Closure: a case study of applying UVM-MS for first-pass success to a complex mixed-signal SoC design”, DVCon 2012: http://events.dvcon.org/2012/proceedings/papers/06_1.pdf

6 Cadence Virtuoso ADE Verifier User Guide, Product Version IC6.1.7: http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:TechPubDocs;src=pubs;q=/adeVerifier/adeVerifierIC6.1.7/adeVerifierTOC.html

7 Cadence Virtuoso ADE Explorer User Guide, Product Version IC6.1.7: http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:TechPubDocs;src=pubs;q=/Explorer/ExplorerIC6.1.7/ExplorerTOC.html

8 Cadence Virtuoso ADE Assembler User Guide, Product Version IC6.1.7: http://support.cadence.com/wps/mypoc/ cos?uri=deeplinkmin:TechPubDocs;src=pubs;q=/assembler/assemblerIC6.1.7/assemblerTOC.html

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Plan-Based Analog Verification Methodology White Paper