anupama_maam

8/3/2019 anupama_maam

1/275

Sequential CircuitsIntroduction- Latches & Flip Flops


2/275

Combinational Circuit o/p levels atany instant of time depends only

on the i/p levels at that instant

Absence of Memory


3/275


4/275

Intro of memory element

Time hasbeen introduced logic operations performed sequentially- info stored inmemory location and released at

particular pt of time

Sequentially operated circuits


5/275

Control Signal

Synchronous Asynchronous

Behavior defn atdiscrete intervals oftime

Behavior changes atany instant of time


6/275

Change when control applied

speed depends upon control i/p????


7/275


8/275

SR- Latch


9/275

S

R

Q

Q


10/275

G1

G2

Q

Q

S R Q Q

S

R

1

01

0 S R Q Q

1 0 0 1

1

11

0 S R Q Q

1 0 0 1

1 1 0 1

0

1

1

0

S R Q Q

1 0 0 1

1 1 0 1

0 1 1 0

1

1

S R Q Q

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0

01

S R Q Q

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

UndesirableState


11/275

Q

Q

S

RS R Q Q

0 1 0 1

0 0 0 1

1 0 1 0

0 0 1 0

1 1 0 0

Function Table

UndesirableState


12/275

S R QP Qp Q Q

1 0 0 1 1 0

1 0 1 0 1 0

0 0 0 1 0 1

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 0 1

1 1 X X U U

S R QP Qp Q Q

1 0 0 1 1 0

1 0 1 0 1 0

0 0 0 1 0 1

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 0 1

1 1 X X U U


13/275

QP Q S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

Steering Table


14/275

G1

G2

Q

Q

S

R

C

0

1

1

1

S

R

Controlled SR Latch


15/275

S R Q Q

1 0 0 1

1 1 0 1

0 1 1 0

1 1 1 0

0 0 1 1

C S R S R Q QC S R S R Q Q

0 X X X X QP

QP

C S R S R Q Q

0 X X X X QP

QP

1 0 0 1 1 QP QP

C S R S R Q Q

0 X X X X QP

QP

1 0 0 1 1 QP QP

1 0 1 1 0 0 1

C S R S R Q Q

0 X X X X QP

QP

1 0 0 1 1 QP QP

1 0 1 1 0 0 1

1 1 0 0 1 1 0

C S R S R Q Q

0 X X X X QP

QP

1 0 0 1 1 QP QP

1 0 1 1 0 0 1

1 1 0 0 1 1 0

1 1 1 0 0 U U


16/275

S

R

Q

Q

C


17/275

D-Latch


18/275

G1

G2

Q

Q

S

R

C

0

1

1

1

0

0

1

D Q Q

D

D Q Q

0 0 1

1

0

0

1

1

0

D Q Q

0 0 1

1 1 0

C D Q Q

1 0 0 1

1 1 1 0

C D Q Q

1 0 0 1

1 1 1 0

0 X Qp QP


19/275

D Q

QC

C D Q Q

1 0 0 1

1 1 1 0

0 X Qp QP

D Q(t+1)D Q(t+1)

0 0

1 1

Characteristic Table


20/275


21/275

Sequential CircuitsLatches & Flip Flops


22/275


23/275

Intro of memory element Time hasbeen introduced logic operations performed sequentially- info stored inmemory location and released at

particular pt of time

Sequentially operated circuits


24/275

Control Signal

Synchronous Asynchronous

Behavior defn atdiscrete intervals oftime

Behavior changes atany instant of time


25/275

S

R

Q

Q

C


26/275

D Q

QC


27/275


28/275

D-Flip Flop


29/275

D Q

QC

D Q

QC

D

C

Q1

Q2

o/pi/p

Set-up Hold


30/275

G

1

G2

Q

Q

G1

G

2

Q

Q

DD

CC


31/275

J K -Flip Flop


32/275

J Q

Q

C

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q(t)


K


33/275

J K Qt Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

JK

Qt

00

01

11

10

1

1

1 1

D = JQ + KQ


34/275

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q(t)


D Q

QC

J

K


35/275

T-Flip Flop


36/275

T Q

QC

T Q(t+1)

0 Q(t)

1 Q(t)



37/275

J Q

Q

C


K

T Q(t+1)

0 Q(t)

1 Q(t)


38/275

T Q Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

D = TQ + TQ

D = T Q

D Q

QC

T


39/275

D Q

QC R

Reset - Clear Preset -Set

Asynch or Direct Inputs


40/275

Sequential CircuitsRegisters


41/275

Clocked Sequential Circuitsgroupof FFs and Combinational Gates


42/275

Counters a specail type of registers

Registers

Storage

Counters

Goes a set of pre-determined states


43/275

1 bit data 1 D FF

1 nibble - 4 D FFs


44/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

CLRCLK

I0

I1

I2

I3

Parallel Load


45/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

CLRCLK

I0

I1

I2

I3

LOAD


46/275

Cascade of FFs in a single IC packageData shift

left- to rightright to left

Shift Registers


47/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

C

D

Q1

Q2

Q3

Q4

CLR

CLK


48/275

SIPO

SISO

PISO PIPO

Single Rail

Double Rail


49/275

Types

Unidirectional

Bidirectional

Universal


50/275

Universal Shift Registers

SISOSIPO

PISO

PIPO

Shift Left

Shift RightClear

Control


51/275

S1 S0

0 0 No Change

0 1 Shift Right

1 0 Shift Left

1 1 Parallel load


52/275

Sequential CircuitsRegisters


53/275



54/275

Counters a specail type of registers

Registers

Storage

Counters



55/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

CLRCLK

I0

I1

I2

I3

LOAD


56/275

Cascade of FFs in a single IC packageData shift

left- to rightright to left

Shift Registers


57/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

C

D

Q1

Q2

Q3

Q4

CLR

CLK


58/275

SIPO

SISO

PISO PIPO

Single Rail

Double Rail


59/275

Types

Unidirectional

Bidirectional

Universal


60/275

Universal Shift Registers

SISOSIPO

PISO

PIPO

Shift Left

Shift RightClear

Control


61/275

S1 S0

0 0 No Change

0 1 Shift Right

1 0 Shift Left

1 1 Parallel load


62/275

D Q

QC R

D Q

QC R

D Q

QC R

D Q

QC R

4X1 4X1 4X1 4X1s1s0

I3 I2 I1 I0SR SL

CLR

CLK


63/275

Reg A Reg BSO SISI SO

CLK

CONTROL

Timing SA SBInitial 1011 0010Timing SA SBInitial 1011 0010

T1 1101 1001

Timing SA SBInitial 1011 0010

T1 1101 1001

T2 1110 1100


T1 1101 1001

T2 1110 1100T3 0111 0110


T1 1101 1001

T2 1110 1100T3 0111 0110

T4 1011 1011

SerialTransfer


64/275

SI x3 x2 x1 x0

CNCL

SI y3 y2 y1 y0

CNCL

FA

S

Ci+1Ci

DQ

CN CL

LOAD

A

B

SI x3 x2 x1 x0

CNCL

0 1 0 1

SI y3 y2 y1 y0

CNCL

0 1 1 1

0

1

SI x3 x2 x1 x0

CNCL

0 0 1 0

1

SI y3 y2 y1 y0

CNCL

1 0 1 1

SI x3 x2 x1 x0

CNCL

0 0 0 1

SI y3 y2 y1 y0

CNCL

1 1 0 1

1

SI x3 x2 x1 x0

CNCL

1 0 0 0

SI y3 y2 y1 y0

CNCL

1 1 1 0

0

SI x3 x2 x1 x0

CNCL

1 1 0 0

SI y3 y2 y1 y0

CNCL

0 1 1 1

0


65/275

Counters - Ripple


66/275

Follow a particular sequence

Sequence - Binary

Binary Ripple counter

2- bit counter counts from 0 -3

N-bit counter counts from 0

2n-1


67/275

T TQ Q

A0 A1

C C

1

CLK

CLK

0

0

1

0

0

1

1

1

0

0

2-binary up counter


68/275

T Q

A1

C

A0

1

Q

T Q

C Q

CLK

CLK

0

0

1

1

0

1

1

0

0

0


69/275

T Q

C

T Q

CCLK

T Q

C

T Q

C

T Q

C


70/275

Ripple counterAsynchronous counteras

they do not have a common clock


71/275

Sequential CircuitsCounters


72/275



73/275

Counters a special type of registers

Registers

Storage

Counters



74/275

Counters - Ripple


75/275


Sequence - Binary

Binary Ripple counter


N-bit counter counts from 0 2n-1


76/275

T Q

C

T Q

C

CLK

T Q

C

T Q

C

T Q

C


77/275




78/275

Counters -Synchronous


79/275


Sequence - Binary

Binary Synchronous counter



Clk common to all Flip Flops


80/275

Present State Next State Input

QC QB QA QC QB QA TC TB TA



0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0 0 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0 0 1

0 0 1 0 1 0

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0

1 0 1

1 1 0

1 1 1



0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1



0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 0 0



0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 0 1

1 1 1 0 0 0 1 1 1


81/275

00

01

11

10

00

01

11

10

TB 0 1 TC 0 1

1

1

1

1

1

1

TB = QA

TC = QBQA


82/275

T Q

C

T Q

C

T Q

C

CLK

1

QA QB QC

CLKDIR


83/275

T Q

C

T Q

C

TQ

C

Q

Q

Q


84/275

Mod 8 counter

3-bit counter

Mod N countergoes through n sequences

Sequence need not be binary


85/275

000

001

010

100

101

110

State Diagram

Design


86/275

Present Next

C B A C B A

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0


87/275

000

001

010

100

101

110

State Diagram

011

111

J K Qt Q(t 1)


88/275

J K Qt Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Qt Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

State Table


89/275

Present Next

C B A C B A

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0

Present Next

C B A C B A

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0

0 1 1 1 0 0

1 1 1 0 0 0

Inputs

JC KC JB KB JA KA

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

Input

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

X 0 0 X 1 X

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

X 0 0 X 1 X

X 0 1 X X 1

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

X 0 0 X 1 X

X 0 1 X X 1

X 1 X 1 0 X

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

X 0 0 X 1 X

X 0 1 X X 1

X 1 X 1 0 X

1 X X 1 X 1

Inputs

JC KC JB KB JA KA

0 X 0 X 1 X

0 X 1 X X 1

1 X X 1 0 X

X 0 0 X 1 X

X 0 1 X X 1

X 1 X 1 0 X

1 X X 1 X 1

X 1 X 1 X 1

JA 0 1 JB 0 1 J 0 1


90/275

00

01

11

10

1 X

0 X

0 X

1 X

JA = QB

00

01

11

10

0 1

X X

X X

0 1

JB = QA

00

01

11

10

JC 0 1

0 X

1 1

X X

0 X

JC = QB

00 01 11 10KC

0

1

X X X X

0 0 1 1

KC = QB

Input Equations/

Excitation Equations


91/275

J Q

C

J Q

C

J Q

C

K K K

CLK

C B

A

1

QQ Q

A


92/275

Design a Synchronous BCD counter


93/275

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

00 01 11 10


94/275

X X X X

X X

00 01 11 10

00

01

11

10

T8

X X X X

X X

00 01 11 10

00

01

11

10

T4

X X X X

X X

00 01 11 10

00

01

11

10

T2

1

X X X X

1 X X

T8 = Q8 Q1 + Q4 Q2 Q1

1

1

X X X X

X X

T4

= Q2Q

1

1 1

1 1

X X X X

X X

T2 = Q8 Q1

T1 = 1


95/275

T1 = 1

T2

= Q8

Q1

T4 = Q2 Q1

T8 = Q8 Q1 + Q4 Q2 Q1


96/275



97/275


Storage Goes a set of pre-


98/275


Registers

Storage

Counters



99/275

T Q

C

T Q

C

CLK

T Q

C

T Q

C

T Q

C


100/275




101/275



102/275


Sequence - BinaryBinary Synchronous counter




CLKDIR


103/275

T Q

C

T Q

C

TQ

C

Q

Q

Q

Mod 8 counter


104/275

Mod 8 counter

3-bit counter

Mod N countergoes through n sequences

Sequence need not be binary


105/275

Design a Synchronous BCD counter


106/275

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 11 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

00 01 11 10T 00 01 11 10T


107/275

X X X X

X X

00 01 11 10

00

01

11

10

T8

X X X X

X X

00 01 11 10

00

01

11

10

T4

X X X X

X X

00 01 11 10

00

01

11

10

T2

1

X X X X

1 X X

T8 = Q8 Q1 + Q4 Q2 Q1

1

1

X X X X

X X

T4 = Q2 Q1

1 1

1 1

X X X X

X X

T2 = Q8 Q1

T1 = 1


108/275

T1 = 1

T2

= Q8

Q1

T4 = Q2 Q1

T8 = Q8 Q1 + Q4 Q2 Q1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

Present Next Inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1


109/275

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 0 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 0 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 0

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 T8 T4 T2 T1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

1 0 1 0 0 0 0 0 1 0 1 0

1 0 1 1 0 0 0 0 1 0 1 1

1 1 0 0 0 0 0 0 1 1 0 0

1 1 0 1 0 0 0 0 1 1 0 1

1 1 1 0 0 0 0 0 1 1 1 0

1 1 1 1 0 0 0 0 1 1 1 1


110/275

T1 = Q8 + Q1 + Q4 Q2

T2

= Q8

Q1

+ Q8

Q2

T4 = Q8 Q4 + Q8 Q2 Q1

T8 = Q8 Q4 + Q8 Q2 + Q8 Q1 + Q4 Q2 Q1


111/275

Design a BCD Ripple counter

O


112/275

Outputs

Q8 Q4 Q2 Q1

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

0 0 0 0

J1 = K1 = 1

J2 = Q8 K2 = 1

J3 = K3 = 1

J4 = Q4 Q2 K4 = 1

J Q J Q J Q

J Q

COUNT


113/275

J Q

C

J Q

C

J Q

C

K K K

CLKQ1

A

QQ Q

J Q

CK Q

Q2 Q4 Q8


114/275

BCDCOUNTER COUNT

BCDCOUNTER COUNT

BCDCOUNTER COUNT

Three Decade Counter


115/275

Design a 4-bit ring counter

Design


116/275

1000

0100

0010

0001

State Diagram

Design

DeBruijn


117/275

Present State Next State Inputs

QD Qc QB QA QD Qc QB QA JD KD JC KC JB KB JA KA

1 0 0 0 0 1 0 0

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0 1 X 0 X 0 X X 1



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0 1 X 0 X 0 X X 1

00 01 11 10JD 00 01 11 10J


118/275

00

01

11

10

JD

X X

X X X

X X X X

X X X

00 01 11 10

00

01

11

10

JC

X X

X X X

X X X X

X X X

X 1 X 0

0 X X X

X X X X

X X X X

JD = QA

X 0 X 0

X X X X

X X X X

1 X X X

JC = QD

00 01 11 10JB 00 01 11 10JA


119/275

00

01

11

10

JB

X X

X X X

X X X X

X X X

00 0 0

00

01

11

10

JA

X X

X X X

X X X X

X X X

X 0 X X

1 X X X

X X X X

0 X X X

JB= QC

X X X 1

0 X X X

X X X X

0 X X X

JA = QB

J Q J Q J Q J Q

1


120/275

J Q

C

J Q

C

J Q

CK K K

CLK

QDA

QQ Q

J Q

CK Q

QCQB QA


121/275



122/275


Storage Goes a set of pre-


123/275


Registers Counters

determined states

T Q T Q T Q T Q T Q


124/275

T Q

C

T Q

CCLK

T Q

C

T Q

C

T Q

C


125/275




126/275



127/275


Sequence - BinaryBinary Synchronous counter


N-bit counter counts from 0 2

n-1


T Q

CLKDIR


128/275

T Q

C

T Q

C

T Q

C

Q

Q

Q

Mod 8 counter


129/275

3-bit counter

Mod N countergoes through n sequencesSequence need not be binary


130/275

Design a 4-bit ring counter

Design


131/275

1000

0100

0010

0001

State Diagram

Design

DeBruijn


132/275



1 0 0 0 0 1 0 0

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0 1 X 0 X 0 X X 1



1 0 0 0 0 1 0 0 X 1 1 X 0 X 0 X

0 1 0 0 0 0 1 0 0 X X 1 1 X 0 X

0 0 1 0 0 0 0 1 0 X 0 X X 1 1 X

0 0 0 1 1 0 0 0 1 X 0 X 0 X X 1

00 01 11 10JD 00 01 11 10JC


133/275

00

01

11

10

X X

X X X

X X X X

X X X

00

01

11

10

X X

X X X

X X X X

X X X

X 1 X 0

0 X X X

X X X X

X X X X

JD = QA

X 0 X 0

X X X X

X X X X

1 X X X

JC = QD

00 01 11 10JB 00 01 11 10JA


134/275

00

01

11

10

X X

X X X

X X X X

X X X

00

01

11

10

X X

X X X

X X X X

X X X

X 0 X X

1 X X X

X X X X

0 X X X

JB= QC

X X X 1

0 X X X

X X X X

0 X X X

JA = QB

J Q J Q J QQ

J QQ Q

1


135/275

C C

J

C

K K K

CLK

QDA

QQ Q

C

K Q

QCQB QA

QD QC QB QA


136/275

2-BIT COUNTER

MUXO0 O1 O2 O3

CLK

S1 S0

D Q D QQ

D QQ Q


137/275

C C

CLK

QDA

Q Q

C

Q

QCQB QA

Present Next

C B A C B A

0 0 0

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0 1 1 0

1 1 0

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0 1 1 0

1 1 0 1 1 1

1 1 1

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0 1 1 0

1 1 0 1 1 1

1 1 1 0 1 1

0 1 1

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0 1 1 0

1 1 0 1 1 1

1 1 1 0 1 1

0 1 1 0 0 1

0 0 1

Present Next

C B A C B A

0 0 0 1 0 0

1 0 0 1 1 0

1 1 0 1 1 1

1 1 1 0 1 1

0 1 1 0 0 1

0 0 1 0 0 0


138/275

Design a Counter with Load


139/275

Clear CLK Load Count Func

0 X X X Clear all FFs

1 1 X Load all FFs

1 0 1 Count

1

0 0 No Change


140/275

PresentState

NextState

Inputs

QB QA QB QA JB KB JA KA

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

PresentState

NextState

Inputs


0 0 0 1 0 X 1 X

0 1 1 0

1 0 1 1

1 1 0 0

PresentState

NextState

Inputs


0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1

1 1 0 0

PresentState

NextState

Inputs


0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0

PresentState

NextState

Inputs


0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0 X 1 X 1

PresentState

NextState

Inputs


0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0 X 1 X 1

1


141/275

J Q

C

K Q

J Q

C

K Q

CLK

1

R R

CLEAR

Load Count J1 K1 J0 K0Load Count J1 K1 J0 K0Load Count J1 K1 J0 K0Load Count J1 K1 J0 K0Load Count J1 K1 J0 K0


142/275

0 0

0 1

1 0

1 1

0 0 0 0 0 0

0 1

1 0

1 1

0 0 0 0 0 0

0 1 Q0 Q0 Q0 Q0

1 0

1 1

0 0 0 0 0 0

0 1 Q0 Q0 Q0 Q0

1 0 I1 I1 I0 I0

1 1

0 0 0 0 0 0

0 1 Q0 Q0 Q0 Q0

1 0 I1 I1 I0 I0

1 1 I1

I1

I0

I0

J0 = Load.I0 + Load.Count

K0 = Load.I0 + Load.Count

J1 = Load.I1 + Load.Count.Q0

k1 = Load.I1 + Load.Count.Q0

State Reduction


143/275

State ReductionReduce no of states

Should not affect i/p o/p relationship

Can be done only when internal states notimportant

Two states are equivalent


144/275

Same o/p

Set of i/ps go to same or equivalent set

a

0/0

0/0 0/0


145/275

b

d

c

g

0/0

0/0

0/0

0/0

1/0

1/0

1/1

1/1

f

e

0/0

1/1

1/1

01010110100

0/01/0

Present Next OutputPresent Next OutputPresent Next OutputPresent Next OutputPresent Next Output


146/275

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g a f 0 1

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f e f 0 1

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

x = 0 x = 1 x = 0 x = 1

a a b 0 0

b c d 0 0

c a d 0 0

d e d 0 1

e a d 0 1

a

0/0

0/0 0/0


147/275

b

d

ce

0/0

0/0

0/0

0/0

1/0

1/01/1

1/1


148/275

State Assign1 Assign2 Assign3

a 000 000 00001

b 001 001 00010

c 010 011 00100

d 011 010 01000

e 100 110 10000


149/275



150/275



151/275

Sequential CircuitsDesign


152/275

Models Moore & Mealy

Moore

o/p depends only

Mealy

o/p depends on


153/275

o/p depends onlyon the present state

o/p depends onpresent state andi/p

Moore Model


154/275

00

1

1

00,01

10,11

00,10

01,11


155/275

Design a sequential circuit that will

detect a sequence of 3 or more 1s

00/0 00/0


156/275

S0

1S1

1/0

1

S2

1/000/0

11/1

0 0


157/275

S00 S10

S2

0

S3

1

1

0

10

1

1

0


158/275

Present Next Outputs

x = 0 x =1 x = 0 x =1

S0

S1S2

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1

S1S2

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1S2

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2S2

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2 0 0S2

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2 0 0S2 S0 S3

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2 0 0S2 S0 S3 0 0

S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2 0 0S2 S0 S3 0 0

S3 S0 S3


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S0 S2 0 0S2 S0 S3 0 0

S3 S0 S3 1 1

State Assignment


159/275

S0 00

S1 01

S2 10

S3 11



160/275


x = 0 x =1 x = 0 x =1

00 00 01 0 0

01 00 10 0 0

10 00 11 0 0

11 00 11 1 1

Prese Next Inputs OutputsPrese Next Inputs OutputsPrese Next Inputs OutputsPrese Next Inputs OutputsPrese Next Inputs OutputsPrese Next Inputs Outputs


161/275

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 0 0

01 00 10 0 0

10 00 11 0 0

11 00 11 1 1

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 0 0

01 00 10 0 0

10 00 11 0 0

11 00 11 1 1

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 01 0 0

01 00 10 0 0

10 00 11 0 0

11 00 11 1 1

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 01 0 0

01 00 10 00 10 0 0

10 00 11 0 0

11 00 11 1 1

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 01 0 0

01 00 10 00 10 0 0

10 00 11 00 11 0 0

11 00 11 1 1

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 01 0 0

01 00 10 00 10 0 0

10 00 11 00 11 0 0

11 00 11 00 11 1 1

BA 00 01 11 10 BA 00 01 11 10


162/275

0

1

0

1

BA 00 01 11 10

0

1

0 0 0 0

0 1 1 1

DB = xB + xA

0 0 0 0

1 0 1 1

DB = x(B + A)

DA = xB + xADA = x(B+ A)

0 0 1 0

0 0 1 0

y = AB

D Q

Bx


163/275

D Q

QC

D Q

QC

y

A


164/275


detect a sequence 101 overlapping

sequences are allowed

00/011/0


165/275

S0

1S1

1/0

0

S2

0/0

00/0 11/1


166/275


x = 0 x =1 x = 0 x =1

S0 S0 S1 0 0

S1 S2 S1 0 0S2 S0 S1 0 1

State Assignment


167/275

S0 00

S1 01

S2 11

S3 10



168/275


x = 0 x =1 x = 0 x =1

00 00 01 0 0

01 11 01 0 0

11 00 01 0 1

10 00 00 0 0

Prese Next Inputs Outputs


169/275

Present

Next InputsD

BD

A

Outputs

x = 0 x =1 x =0 x=1 x = 0 x =1

00 00 01 00 01 0 0

01 11 01 11 01 0 0

11 00 01 00 01 0 1

10 00 00 00 00 0 0

DA = xAB


170/275

BA 00 01 11 10

0

1

0 1 0 0

1 1 1 0

DAB = BA+xA+xB


171/275


detect a sequence 101 10overlapping

sequences are allowed

00/0 11/0


172/275

A B

1/01C

0/00

00/0

1

D

1/0

1E 1/0

00/011/0 00/1


173/275

Sequential Circuits


174/275



175/275

Models Moore & Mealy

Moore

o/p depends only

Mealy

o/p depends on


176/275

on the present state present state and

i/p


177/275

Sequential CircuitsAnalysis

Custom designed to generate any countsequence


178/275

Analysis

To find out behavior of a circuit

J J

A

JQC QB QA


179/275

C C

K K

CLK

A

Q Q

C

K Q

JA = KA = QC

JB = KB = QAJC = QBQA

KC = QC

Present State JC Kc JB Kb Ja KA Next State

QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


QC QB QA QC QB QA


180/275

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 0 1 0 0 0 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 0 1 0 0 0 0 0 1 0

1 1 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 0 1 0 0 0 0 0 1 0

1 1 1 1 1 1 1 0 0

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 0 1 0 0 0 0 0 1 0

1 1 1 1 1 1 1 0 0 0 0 1

0 0 0 0 0 0 0 1 1 0 0 1

0 0 1 0 0 1 1 1 1 0 1 0

0 1 0 0 0 0 0 1 1 0 1 1

0 1 1 1 0 1 1 1 1 1 0 0

1 0 0 0 1 0 0 0 0 0 0 0

1 0 1 0 1 1 1 0 0 0 1 1

1 1 0 0 1 0 0 0 0 0 1 0

1 1 1 1 1 1 1 0 0 0 0 1

000


181/275

001

010

011

100

110

StateDiagram

101

111

T QA

C Q

CLKx y


182/275

T QB

CQ

TA = xQB

TB = xy = QAQB

Q(t+1) = TQ+TQ

QA(t+1) = (QBx)QA + (QBx)QA

QA(t+1) = QBQA + QAx+ QAQBx

QB(t+1) = x QB

Present State I/P Next State O/P

QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


QB QA x QB QA y


183/275

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0 1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 1 0 0

1 0 0 1 0 0

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 1

00/0

0


184/275

01/0

10/0

11/1

StateDiagram

1

11

1

0

0

0


185/275

Q(t+1) = Q(t)

x

y

D Q

QC

xy

Present State x Y Next State

0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


0 0 0 0


186/275

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1


187/275

0 1

10,01

10,01

00,11

00,11

StateDiagram


188/275

ROM

Random Logic ICs LSI


189/275

.. So Far

Random Logic ICs

SSI MSI Gates, FFs, Counters

Mux, Demux

Encoder/ Decoders

Now ..

LSI

Memory Microprocessors Peripheral chips PLD


190/275

Array of identical cells have same function

Arrays can be programmed

Each cell AND-OR /may include FFs

Combinational/Sequential

R d


191/275

Random

PLD

VLSI


192/275

Memory

ROM/PROM PLA

PAL

FPGA

Typical PLD may have hundreds of millions of

gates


193/275


194/275

Random Access Sequential Access

ROM

RAM

FDD

HDD


195/275

Volatile Non-volatile

SRAM

DRAM

Read -Write

ROM

PROM

EPROM

EEPROM (ICP)


196/275

Look at it as a combinational Logic


197/275

A0

A1

A2

An-3

An-2

An-1

D0

D1

D2

Dm-3

Dm-2

Dm-1

2n x m

O0


198/275

A0

A1

A2

3 x8decoder

O1O2

O3

O4

O5O6

O7

D0 D1 D2 D3

Inputs Outputs


199/275

p p

A2 A1 A0 D3 D2 D1 D00 0 0 0 0 0 1

0 0 1 0 1 0 1

0 1 0 1 0 0 0

0 1 1 1 1 0 11 0 0 0 1 1 0

1 0 1 0 0 0 0

1 1 0 1 0 1 0

1 1 1 1 0 0 1

O0

VCC


200/275

A0

A1

A2

3 x8decoder

O1O2

O3

O4

O5O6

O7

D0 D1 D2 D3

VCC

PROM


201/275

GND

dataline

decoder o/p

10

EPROM/EEPROM - MOSFETs

Reg 0

Reg 1

ROMOrganization


202/275

Address

Decoder

Reg 1

Reg 2

Reg 2n - 1

o/p tristate bufferCSOE

axa


203/275

Q8

Q4

Q2

Q1

BCD 7segment

b

c

d

e

f

x

a

bcdefg

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0

0 0 0 1

0 0 1 0

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1

0 0 1 0

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

BCD Segment outputs

8 4 2 1 x a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 0 1 1 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

ProgrammingTable


204/275

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0 0 0 1 1 0 0 1 1

0 1 0 1

0 1 1 0

0 1 1 11 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 1 0 1 1

0 1 1 0 0 0 0 1 1 1 1 1

0 1 1 1 0 1 1 1 0 0 0 01 0 0 0 0 1 1 1 1 1 1 1

1 0 0 1 0 1 1 1 0 0 1 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 1 0 1 1

0 1 1 0 0 0 0 1 1 1 1 1

0 1 1 1 0 1 1 1 0 0 0 01 0 0 0 0 1 1 1 1 1 1 1

1 0 0 1 0 1 1 1 0 0 1 1

1 0 1 0 0 0 0 0 0 0 0 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 1 0 1 1

0 1 1 0 0 0 0 1 1 1 1 1

0 1 1 1 0 1 1 1 0 0 0 01 0 0 0 0 1 1 1 1 1 1 1

1 0 0 1 0 1 1 1 0 0 1 1

1 0 1 0 0 0 0 0 0 0 0 0

1 0 1 1 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 0

0 0 1 0 0 1 1 0 1 1 0 1

0 0 1 1 0 1 1 1 1 0 0 1

0 1 0 0 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 1 0 1 1

0 1 1 0 0 0 0 1 1 1 1 1

0 1 1 1 0 1 1 1 0 0 0 01 0 0 0 0 1 1 1 1 1 1 1

1 0 0 1 0 1 1 1 0 0 1 1

1 0 1 0 0 0 0 0 0 0 0 0

1 0 1 1 0 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0 0

Table


205/275

ROM



206/275

.. So Far

g


Mux, Demux

Encoder/ Decoders

Now ..



207/275

Array of identical cells have same function

Arrays can be programmed

Each cell AND-OR /may include FFs

Combinational/Sequential


208/275

Memory ROM/PROM PLA

PAL

FPGA


gates


209/275

Volatile Non-volatile

SRAM

DRAM

Read -Write

ROM

PROM

EPROM

EEPROM (ICP)


210/275

Look at it as a combinational Logic

A D


211/275

A0

A1

A2

An-3

An-2

An-1

D0

D1

D2

Dm-3

Dm-2

Dm-1

2n x m


212/275

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0

0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1


213/275

0 1 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0 1 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0 1 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1

1 0 0

1 0 11 1 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0

1 0 11 1 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 11 1 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 1 0 1 1 0 0 11 1 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 1 0 1 1 0 0 11 1 0 1 0 0 1 0 0

1 1 1

0 1 0 0 0 0 1 0 0

0 1 1 0 0 1 0 0 1

1 0 0 0 1 0 0 0 0

1 0 1 0 1 1 0 0 11 1 0 1 0 0 1 0 0

1 1 1 1 1 0 0 0 1

Programming Table

A2 A1 A0 B5 B4 B3 B2 B1 B0

0 0 0 0 - - - - -

0 0 1 0 - - - - 1


214/275

0 1 0 0 - - 1 - -

0 1 1 0 - 1 - - 1

1 0 0 0 1 - - - 0

1 0 1 0 1 1 - - 11 1 0 1 - - 1 - 0

1 1 1 1 1 - - - 1

Programming Table

O0

B1B0

0


215/275

A0

A1

A2

O1

O2

O3

O4

O5

O6

O7

B2 B3 B4 B5

Mask


216/275

A E1/0

G1/0

H0,1/0

0,1/1


217/275

B

0/0

C

0,1/0

D

0,1/0

0,1/0F

0/0

0/0

1/0

Present Next Output

x = 0 x =1 x = 0 x =1

A B E 0 0


218/275

B C C 0 0

C D D 0 0

D A A 0 0

E F G 0 0

F D H 0 0

G H H 0 0

H A A 1 1

State Binary

A 000


219/275

B 001C 010

D 011

E 100

F 101

G 110

H 111

Present Next Output

x = 0 x =1 x = 0 x =1

000 001 100 0 0


220/275

001 010 010 0 0

010 011 011 0 0

011 000 000 0 0

100 101 110 0 0

101 011 111 0 0

110 111 111 0 0

111 000 000 1 1

Present Next FF inputs Output

x = 0 x =1 x = 0 x =1 x = 0 x =1

000 001 100 001 100 0 0


221/275

001 010 010 010 010 0 0

010 011 011 011 011 0 0

011 000 000 000 000 0 0

100 101 110 101 110 0 0

101 011 111 011 111 0 0

110 111 111 111 111 0 0

111 000 000 000 000 1 1

QC QB QA x DC DB DA y0 0 0 0 0 0 1 0

0 0 0 1 1 0 0 0

0 0 1 0 0 1 0 0

0 0 1 1 0 1 0 0


222/275

0 0 1 1 0 1 0 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 0

0 1 1 0 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 1 0 1 0

1 0 0 1 1 1 0 0

1 0 1 0 0 1 1 0

1 0 1 1 1 1 1 0

1 1 0 0 1 1 1 01 1 0 1 1 1 1 0

1 1 1 0 0 0 0 1

1 1 1 1 0 0 0 1

ProgrammingTable

O0

O1

O2QA

DA DB QC yDA DB QC y


223/275

A0

A1

A2

3 x8decoder

O2

O3

O4

O5

O6

O7

QA

QB

QC

x

x'

Mask


224/275

PLA

Inputs Inputs


225/275

ROM PLA

Fixed AND

Programmable OR

Outputs

Programmable AND

Programmable OR

Outputs


226/275

x

y

z

F1 F2 F3

1 0


227/275

x

y

z

F1

F2

F3

Minterms Outputs


228/275

AND OR

Reduce no .of gatesreduce expression

F1 (x, y, z) = (0,1,2,4) 1 1 0 1

00 01 11 10


229/275

F2 (x, y, z) = (0,5,6,7) F3 (x, y, z) = (0,3,5,7)

1 1 0 1

1 0 0 0

01

1 0 0 0

0 1 1 1

00 01 11 10

0

1

1 0 1 0

0 1 1 0

00 01 11 10

0

1

F1 = xy + yz + xz


230/275

F1 = xy + xz + yzF2 = xy + xz + xyz

F2 = xz + xz + xyz

F3

= xz + yz + xyz

F3 = yz + xz + xyz


231/275

Product Inputs F1 F2 F3

x y z C T T

xy 1

xz 2yz 3

xyz 4


x y z C T T

xy 1 1 1 - 1 1 -

xz 2yz 3

xyz 4


x y z C T T

xy 1 1 1 - 1 1 -

xz 2 1 - 1 1 1 1yz 3

xyz 4


x y z C T T

xy 1 1 1 - 1 1

xz 2 1 - 1 1 1 1yz 3 - 1 1 1 - 1

xyz 4


x y z C T T

xy 1 1 1 - 1 1

xz 2 1 - 1 1 1 1yz 3 - 1 1 1 - 1

xyz 4 0 0 0 - 1 1

1 0


232/275

x

y

z

F1

F2

F3


233/275

PAL



234/275

.. So Far


Mux, Demux

Encoder/ Decoders

Now ..


Memory ROM/PROM


235/275

y /

PLA

PAL

FPGA


gates

Inputs Inputs


236/275

ROM PLA

Fixed AND

Programmable OR

Outputs

Programmable AND

Programmable OR

Outputs


237/275

x

y

z

F1 F2 F3

1 0


238/275

x

y

z

F1

F2

F3

Minterms Outputs


239/275

AND OR

Reduce no .of gatesreduce expression


240/275

PAL


241/275

x

y

z

F1

F2

F1


242/275

x

y

z

F2

PAL

2 wide PAL

Programmable AND

Inputs

Programmable AND

Inputs


243/275

PLA PAL

Programmable OR

Outputs

Fixed OR

OutputsCommon minterms

Reduce Total no. ofminterms

o/p fedback as i/p

Reduce minterms/eqn

F1 (A, B, C, D) = (2,12,13)


244/275

F2 (A, B, C, D) = (7,8,9,10,11,12,13,14,15) F3 (A, B, C, D) = (0,2,3,4,5,6,7,8,10,11,15)

F4 (A, B, C, D) = (1,2,8,12,13)

00 01 11 10 00 01 11 10F1 F4


245/275

1

1 1

00

01

11

10

1 1

1 1

1

00

01

11

10

F1 = ABC + ABCD F4 = ABC + ABCD+ABCD +ACD

F4 = F1+ABCD +ACD

00 01 11 10

00

00 01 11 10

00

F2 F3


246/275

1

1 1 1 1

1 1 1 1

00

01

11

10

1 1 1

1 1 1 1

1

1 1 1

00

01

11

10

F2 = A + BCD F3 = AB + CD+BD

Product Inputs Outputs

1

2

3

Product Inputs OutputsA B C D F1

1 1 1 0 - - F1 = ABC + ABCD

2 0 0 1 0 -

3 - - - - -


247/275

4

5

6

7

8

9

10

11

12

4 1 - - - - F2 = A + BCD

5 - 1 1 1 -

6 - - - - -

7 0 1 - - - F3 = AB + CD+BD

8 - - 1 1 -

9 - 0 - 0 -

10 - - - - 1 F4 = F1+ABCD+ACD11 0 0 0 1 -

12 1 - 0 0 -

A

F1


248/275

B

C

D

F2

F3

F4


249/275

A1 A0

B B

A1 A0

B B

A1 A0

B B

A1 A0

B B

Multiplicand

M l i li


250/275

B1 B0B1 B0

A1 B0 A0 B0

B1 B0

A1 B0 A0 B0

A1 B1 A0 B1

B1 B0

A1 B0 A0 B0

A1 B1 A0 B1

C A1 B1 + C A1 B0 + A0 B0 A0 B0

Multiplier

B1 B0 A1 A0 P3 P2 P1 P00 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

B1 B0 A1 A0 P3 P2 P1 P00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

B1 B0 A1 A0 P3 P2 P1 P00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

B1 B0 A1 A0 P3 P2 P1 P00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0

B1 B0 A1 A0 P3 P2 P1 P00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 1 0 0 0 0 0

0 0 1 1 0 0 0 0


251/275

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 01 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 01 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0 0 0 0 0

0 1 0 1 0 0 0 1

0 1 1 0 0 0 1 0

0 1 1 1 0 0 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 01 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0 0 0 0 0

0 1 0 1 0 0 0 1

0 1 1 0 0 0 1 0

0 1 1 1 0 0 1 1

1 0 0 0 0 0 0 0

1 0 0 1 0 0 1 0

1 0 1 0 0 1 0 0

1 0 1 1 0 1 1 0

1 1 0 01 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0 0 0 0 0

0 1 0 1 0 0 0 1

0 1 1 0 0 0 1 0

0 1 1 1 0 0 1 1

1 0 0 0 0 0 0 0

1 0 0 1 0 0 1 0

1 0 1 0 0 1 0 0

1 0 1 1 0 1 1 0

1 1 0 0 0 0 0 01 1 0 1 0 0 1 1

1 1 1 0 0 1 1 0

1 1 1 1 1 0 0 1

ROM 16 x 4

0 1 1 1

0 0 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1

0 1 1 1

0 0 1 1

0 0 0 0 0 1 1 1


252/275

0 0 0 0 0 1 1 10 0 0 0 0 1 1 10 0 0 0 1 1 10 0 0 0 0 1 1 10 0 0 0 1 1 1

0 0 0 0 0 0

0 0 0 0 0 1 1 10 0 0 0 1 1 1

0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 1 1 10 0 0 0 1 1 1

0 0 0 0 0 0

0 0 0 0 0

0 0 0 0 0 1 1 10 0 0 0 1 1 1

0 0 0 0 0 0

0 0 0 0 0

0 0 0 1 0 1 0 1


253/275

Methods & Algorithms

A Q M

0 0 0 0 0 0 0 1 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111

A Q M

0 0 0 0 0 0 0 1 1 0111

0 0 1 1 1 0 0 1 1 0111

0 0 0 1 1 1 0 0 1 0111


254/275

0 0 0 1 1 1 0 0 1 01110 0 0 1 1 1 0 0 1 01110 1 0 1 0 1 0 0 1 01110 0 0 1 1 1 0 0 1 01110 1 0 1 0 1 0 0 1 0111

0 0 1 0 1 0 1 0 0 0111

0 0 0 1 1 1 0 0 1 01110 1 0 1 0 1 0 0 1 0111

0 0 1 0 1 0 1 0 0 0111

0 0 0 1 0 1 0 1 0 0111

0 0 0 1 1 1 0 0 1 01110 1 0 1 0 1 0 0 1 0111

0 0 1 0 1 0 1 0 0 0111

0 0 0 1 0 1 0 1 0 01110 0 0 0 1 0 1 0 1 0111

0 0 0 1 1 1 0 0 1 01110 1 0 1 0 1 0 0 1 0111

0 0 1 0 1 0 1 0 0 0111

0 0 0 1 0 1 0 1 0 01110 0 0 0 1 0 1 0 1 0111

0 0 0 0 1 0 1 0 1 0111

1. A 00000, Q Multiplier, M Multiplicand

C t 0


255/275

Count = 0

2. If LSB of Q =1 then A = A+M

3. Shift AQ right by 1 bit Logical Shift

4. Count = Count +1

5. If Count = n stop ; else go step 2

0 0 0 0 0 0 0 1 1


256/275

0 1 1 1

4-bit adder Shift & Controlcount

7 X -3

0 1 1 1

1 1 0 1

0 1 1 1

1 1 0 1

0 1 1 1

1 1 0 1

0 1 1 1

1 1 0 1

0 1 1 1

1 1 0 1

0 1 1 1

1 1 0 1


257/275

1 1 0 11 1 0 10 0 0 0 0 1 1 1

1 1 0 10 0 0 0 0 1 1 1

0 0 0 0 0 0 0

1 1 0 10 0 0 0 0 1 1 1

0 0 0 0 0 0 0

0 0 0 1 1 1

1 1 0 10 0 0 0 0 1 1 1

0 0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 1 1

1 1 0 10 0 0 0 0 1 1 1

0 0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 1 1

0 1 0 1 1 0 1 1

M l i li i


258/275

Methods & Algorithms

Multiplication

1 A 00000 Q M ltiplier M M ltiplicand Co nt = 0

Shift & Add Method


259/275

1. A00000, QMultiplier, MMultiplicand Count = 0

2. If LSB of Q =1 then A = A+M

3. Shift AQ right by 1 bitLogical Shift

4. Count = Count +1

5. If Count = n stop ; else go step 2

0 0 0 0 0 0 0 1 1

Implementation of Shift & Add Algo


260/275

0 1 1 1

0 0 0 0 0 0 0 1 1

4-bit adder Shift & Controlcount

1 C M l i li M l i li d i i

Signed Multiplication


261/275

1. Convert Multiplier Multiplicandto positive

numbers

2. Perform Multiplication3. Takes twos complement of result if the sign of

two nos. are different

Start

A =0 M = Multiplier

Q = Multiplicand Q-1 = 0

Count = n


262/275

Count = n

Q0 Q-1?

0110

A= A-M A= A+M

ASR :AQQ-1Count = Count -1

Count ?

Stop

0

Booths

Algorithm

A Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

M

Booths Algorithm 7x-3


263/275

0 0 0 0 1 1 0 1 0 01110 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 1 1 1 1 1 0 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 1 1 1 1 1 0 0111

1 0 1 0 1 1 1 1 0 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 1 1 1 1 1 0 0111

1 0 1 0 1 1 1 1 0 0111

1 1 0 1 0 1 1 1 1 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 1 1 1 1 1 0 0111

1 0 1 0 1 1 1 1 0 0111

1 1 0 1 0 1 1 1 1 0111

1 1 1 0 1 0 1 1 1 0111

0 0 0 0 1 1 0 1 0 0111

1 0 0 1 1 1 0 1 0 0111

1 1 0 0 1 1 1 0 1 0111

0 0 1 1 1 1 1 0 1 0111

0 0 0 1 1 1 1 1 0 0111

1 0 1 0 1 1 1 1 0 0111

1 1 0 1 0 1 1 1 1 0111

1 1 1 0 1 0 1 1 1 0111

1 1 1 0 1 0 1 1 1 0111

A Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

MA Q Q-1

M

Booths Algorithm -7x-3


264/275

0 0 0 0 1 1 0 1 0 10010 0 0 0 1 1 0 1 0 1001

0 1 1 1 1 1 0 1 0 1001

0 0 0 0 1 1 0 1 0 1001

0 1 1 1 1 1 0 1 0 1001

0 0 1 1 1 1 1 0 1 1001

0 0 0 0 1 1 0 1 0 1001

0 1 1 1 1 1 0 1 0 1001

0 0 1 1 1 1 1 0 1 1001

1 1 0 0 1 1 1 0 1 1001

0 0 0 0 1 1 0 1 0 1001

0 1 1 1 1 1 0 1 0 1001

0 0 1 1 1 1 1 0 1 1001

1 1 0 0 1 1 1 0 1 1001

1 1 1 0 0 1 1 1 0 1001

0 0 0 0 1 1 0 1 0 1001

0 1 1 1 1 1 0 1 0 1

Documents

anupama_maam