60
w w w . c h i n a f i x . c o m N69 MLB - EVT BRD 820-00282 BOM 639-00931 (N69 BETTER) SCH 051-00648 MCO 056-01352 BOM 639-01271 (N69 ULTRA) BOM 639-01272 (N69H ULTRA) BOM 639-01231 (N69 BEST) BOM 639-01012 (N69H BETTER) BOM 639-01232 (N69H BEST) 1 OF 60 46 CAMERA:FOREHEAD FLEX B2B CAMERA:REAR CAMERA B2B AUDIO:CALTRA CODEC (1/2) SENSORS:MOTION SENSORS LAST_MODIFICATION=Wed Aug 19 11:42:47 2015 SYSTEM POWER:CHARGER RF TRANSCEIVER (1 0F 3) QFE DCDC 44 RX DIVERSITY (2) SOC:SERIAL & GPIO I/O:BUTTON FLEX B2B BASEBAND PMU (2 OF 2) MESA POWER AND IO FILTERS 38 BASEBAND (1 OF 2) 7 9 SOC:OWL SOC:POWER (2/3) SYSTEM:MECHANICAL 51 MOBILE DATA MODEM (2 OF 2) SYSTEM POWER:PMU (1/3) 21 DISPLAY FLEX I/O:TRISTAR 2 AUDIO:CALTRA CODEC (2/2) 27 WIFI/BT: MODULE AND FRONT END STOCKHOLM OMIT_TABLE_RF ANTENNA FEEDS RX DIVERSITY HIGH BAND SWITCH ANTENNA SWITCH HIGH BAND PAD 2 13 11 9 SYSTEM:BOM TABLES SYSTEM POWER:PMU (2/3) AUDIO:SPEAKER DRIVER TABLE OF CONTENTS SYSTEM:N69 SPECIFIC [4] SOC:JTAG,USB,XTAL SOC:PCIE 3 SOC:CAMERA & DISPLAY CAMERA:STROBE DRIVER D403 (TOUCH B2B, DRIVER ICS) 29 SYSTEM POWER:PMU (3/3) SYSTEM POWER:BATTERY CONN DISPLAY:POWER I/O:DOCK FLEX B2B BASEBAND:RADIO SYMBOL page1 CELL:ALIASES AP INTERFACE & DEBUG CONNECTORS RF TRANSCEIVER (2 OF 3) RF TRANSCEIVER (3 OF 3) 2G PA VERY LOW BAND PAD LOW BAND PAD MID BAND PAD GPS Radio Subdesign Ports 3 4 5 8 10 11 12 14 15 16 17 18 19 20 22 23 24 26 28 30 33 34 35 36 37 39 40 41 42 43 45 47 48 49 50 52 53 54 55 56 57 58 59 60 1 4 5 6 7 15 13 12 10 8 31 30 24 23 22 21 20 32 33 35 36 37 41 42 43 45 51 46 49 50 25 NAND SOC:POWER (3/3) SOC:POWER (1/3) 1 32 31 40 6 BASEBAND (1 OF 2) BASEBAND PMU (1 0F 2) SCH,MLB,N69 051-00648 2015-08-24 0004752417 4 ENGINEERING RELEASED 1 OF 49 4.0.0 TABLE OF CONTENTS CONTENTS SYNC SYNC <CSA> PAGE DATE PAGE DATE CONTENTS <CSA> PROPRIETARY PROPERTY OF APPLE INC. REVISION ECN REV DESCRIPTION OF REVISION DRAWING TITLE 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. CK APPD 2 1 1 2 4 5 6 7 8 B D 6 5 4 3 C A PAGE C A D DATE R SHEET D SIZE DRAWING NUMBER BRANCH 7 B 3 II NOT TO REPRODUCE OR COPY IT IV ALL RIGHTS RESERVED 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 8 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE THE POSESSOR AGREES TO THE FOLLOWING: THE INFORMATION CONTAINED HEREIN IS THE NOTICE OF PROPRIETARY PROPERTY: Apple Inc. .com 83768 7

APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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Page 1: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

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m

N69 MLB - EVT

BRD 820-00282

BOM 639-00931 (N69 BETTER)

SCH 051-00648

MCO 056-01352

BOM 639-01271 (N69 ULTRA)BOM 639-01272 (N69H ULTRA)

BOM 639-01231 (N69 BEST)BOM 639-01012 (N69H BETTER)

BOM 639-01232 (N69H BEST)

1 OF 60

46

CAMERA:FOREHEAD FLEX B2B

CAMERA:REAR CAMERA B2B

AUDIO:CALTRA CODEC (1/2)

SENSORS:MOTION SENSORS

LAST_MODIFICATION=Wed Aug 19 11:42:47 2015

SYSTEM POWER:CHARGER

RF TRANSCEIVER (1 0F 3)

QFE DCDC

44

RX DIVERSITY (2)

SOC:SERIAL & GPIO

I/O:BUTTON FLEX B2B

BASEBAND PMU (2 OF 2)

MESA POWER AND IO FILTERS

38

BASEBAND (1 OF 2)

79

SOC:OWL

SOC:POWER (2/3)

SYSTEM:MECHANICAL

51

MOBILE DATA MODEM (2 OF 2)

SYSTEM POWER:PMU (1/3)

21

DISPLAY FLEX

I/O:TRISTAR 2

AUDIO:CALTRA CODEC (2/2)

27 WIFI/BT: MODULE AND FRONT END

STOCKHOLM

OMIT_TABLE_RF

ANTENNA FEEDS

RX DIVERSITY

HIGH BAND SWITCH

ANTENNA SWITCH

HIGH BAND PAD

2

13

11

9

SYSTEM:BOM TABLES

SYSTEM POWER:PMU (2/3)

AUDIO:SPEAKER DRIVER

TABLE OF CONTENTS

SYSTEM:N69 SPECIFIC [4]

SOC:JTAG,USB,XTAL

SOC:PCIE

3

SOC:CAMERA & DISPLAY

CAMERA:STROBE DRIVER

D403 (TOUCH B2B, DRIVER ICS)29

SYSTEM POWER:PMU (3/3)

SYSTEM POWER:BATTERY CONN

DISPLAY:POWER

I/O:DOCK FLEX B2B

BASEBAND:RADIO SYMBOL

page1

CELL:ALIASES

AP INTERFACE & DEBUG CONNECTORS

RF TRANSCEIVER (2 OF 3)

RF TRANSCEIVER (3 OF 3)

2G PA

VERY LOW BAND PAD

LOW BAND PAD

MID BAND PAD

GPS

Radio Subdesign Ports

3

4

5

8

10

11

12

14

15

16

17

18

19

20

22

23

24

26

28

30

33

34

35

36

37

39

40

41

42

43

45

47

48

49

50

52

53

54

55

56

57

58

59

60

1

4

5

6

7

15

13

12

10

8

31

30

24

23

22

21

20

32

33

35

36

37

41

42

43

45

51

46

49

50

25

NAND

SOC:POWER (3/3)

SOC:POWER (1/3)

1

32

31

40

6

BASEBAND (1 OF 2)

BASEBAND PMU (1 0F 2)

SCH,MLB,N69

051-00648

2015-08-2400047524174 ENGINEERING RELEASED

1 OF 49

4.0.0

TABLE OF CONTENTS

CONTENTS SYNCSYNC<CSA>PAGE DATE PAGE DATECONTENTS <CSA>

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CKAPPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

DSIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

IV ALL RIGHTS RESERVED

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

功夫手机维修培训

手机维修培训 承

接同行机

www.AppleGF.com

手机和微信13737083768

Q:3383230657

Page 2: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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PMU/SOC BOM OPTIONS

SOC ALTERNATES

SCHEMATIC & PCB BOM CALLOUTS

USED 10 TIMES IN DESIGN.

USED 4 TIMES IN DESIGN.

USED 5 TIMES IN DESIGN.

USED 9 TIMES IN DESIGN.

USED 35 TIMES IN DESIGN.

USED 1 TIME IN DESIGN.

USED 20 TIMES IN DESIGN.

USED 1 TIME IN DESIGN.

USED 61 TIMES IN DESIGN.

USED 61 TIMES IN DESIGN.

USED 5 TIMES IN DESIGN.

USED 91 TIMES IN DESIGN.

USED 91 TIMES IN DESIGN.NOT ALL REFERENCE DESIGNATORS LISTED.

USED 4 TIMES IN DESIGN.

USED 1 TIME IN DESIGN.

USED 1 TIME IN DESIGN.

USED 1 TIME IN DESIGN.

USED 1 TIME IN DESIGN.

USED 1 TIME IN DESIGN.

USED 8 TIMES IN DESIGN.

USED 51 TIMES IN DESIGN.

POWER INDUCTOR ALTERNATES

SHIELD PART NUMBERS

COMPASS PART NUMBER

S3E NAND BOM OPTIONS

USED 1 TIME IN DESIGN.

USED 9 TIMES IN DESIGN.

USED 51 TIMES IN DESIGN.

ALTERNATE BOM OPTIONS

CARBON BOM OPTIONS

2 OF 60

3 OF 49

4.0.0

051-00648

117S0202 1 RES,MF,20OHM,5%,1/32W,01005 INVENSENSE_CARBONR3021

1 U3010 INVENSENSE_CARBON_1_1338S00087 IC,CARBON,MPU-6800-00,LGA16

1 INVENSENSE_CARBON117S0202 RES,MF,20OHM,5%,1/32W,01005 R3022

SYNC_MASTER=N/A

SYSTEM:BOM TABLESSYNC_DATE=N/A

1 RES,MF,20OHM,5%,1/32W,01005 INVENSENSE_CARBONR3020117S0202

C3022 INVENSENSE_CARBON1 CAP,CER,X5R,0.1UF,20%,6.3V,01005132S0316

CAP,CER,X5R,0.1UF,20%,6.3V,010051132S0316 INVENSENSE_CARBONC3020

IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 INVENSENSE_CARBONU3020338S1163 1

C3021 INVENSENSE_CARBON138S0692 1 CAP,CER,X5R,1UF,20%,6.3V,0201

U3010338S00017 1 INVENSENSE_CARBONIC,CARBON,MPU-6700-12,LGA16

335S00085 NAND_32G U1500 TOSHIBA 16G SLGA70335S00072

ALTERNATE339S00122 339S00121 MALTA DEV, H DRAMU0600

339S00123 339S00121

ALTERNATE339S00096339S00097 U0600 MAUI DEV, M DRAM

U0600ALTERNATE339S00096 MAUI DEV, S DRAM339S00098

138S0867138S00020 C1100ALTERNATE MURATA,10UF,0402

ALTERNATE335S0946 U0900 IC,EEPROM,16KX8,1.8V,I2C,WLCSP4335S00066

EEEE CODE FOR 639-01231 32GB CRITICAL EEEE_32GEEEE_GN7J1825-6838

EEEE CODE FOR 639-01232 32GB825-6838 1 CRITICALEEEE_GN7H EEEE_32GH

825-6838 EEEE_64GHCRITICALEEEE_GP3WEEEE CODE FOR 639-01272 64GB1

138S0652 ALTERNATE TY,4.7UF,0402C3650138S0648

825-6838 EEEE CODE FOR 639-01271 64GB EEEE_GP3V EEEE_64G1 CRITICAL

IC,COMPASS,MAGNESIUM,601A-19,FLGA14338S00084 U3000 COMMON1

SHIELD,EMI,LOWER FRONT,N69806-03630 1 COMMONSH0501

132S0436132S0400 ALTERNATE C1280 CAP,CER,X5R,0.22UF,20%,6.3V,01005

TY,10UF,0402C1100138S0867138S00022 ALTERNATE

ALTERNATE155S00095 FL1280155S00068 FERR BD,100 OHM,25%,100MA,2 OHM,01005

C5302_RFALTERNATE MURATA,CAP,CER,1UF,20%,10V,X5R,0201138S0739138S0706

ALTERNATE138S0945 KYOCERA,CAP,CER,1UF,20%,10V,X5R,0201C5302_RF138S0739

DIODES INC. ACT DIODEALTERNATE376S00047 Q2300376S00106

TY,4.3UF,0402ALTERNATE138S0835 C1106138S00006

ALTERNATE L2060 CYNTEC,1UH,1608152S1929152S2052

335S00054 NAND_16G U1500335S00071 HYNIX 16G SLGA70

1 EEEE_GJYD825-6838 CRITICAL EEEE_16GHEEEE CODE FOR 639-01012 16GB

PCBF,MLB,N69820-00282 PCB CRITICAL ?1

SCHSCH,MLB,N69051-00648 1 CRITICAL ?

EEEE CODE FOR 639-00931 16GB825-6838 CRITICAL1 EEEE_GH6K EEEE_16G

SHIELD,EMI,UPPER FRONT,N69 SH0500 COMMON1806-03629

SHIELD,EMI,BACK,N69 SH05031 COMMON806-03556

152S00123 TAIYO 3225 15UH? L4020152S1936

TAIYO 2016 1.2UHL3700152S00075152S00118 ?

152S00120 152S00077 TAIYO 2016 1.0UH 0.65MML2070?

152S00121 152S00081 L2001 TAIYO 2012 0.47UH?

155S0453 FL3101 TY,FERR,120-OHM,01005ALTERNATE155S0773

TDK,VARISTOR,6.8V,100PF,01005377S0168 377S0140 DZ3150ALTERNATE

MURATA,CHOKE,65-OHM,0605155S00009155S00012 L3100ALTERNATE

TDK,FERR,240-OHM,0201ALTERNATE FL4200155S0581155S00067

138S00003 ALTERNATE138S00005 TY,15UF,0402C1500

?152S00117 L2000 TAIYO 2016 1.0UH152S00074

138S0831 KYOCERA,2.2UF,0201ALTERNATE C0610138S00049

KYOCERA,15UF,0402C1500138S00048 138S00003 ALTERNATE

FL3100155S0513 ALTERNATE MURATA,FERR,22-OHM155S0660

118S0764 PANASONIC,3.92K-OHM,0201R2250ALTERNATE118S0717

138S0831138S00032 ALTERNATE TY,2.2UF,0201C0610

CUMULUS 2ND FLOWALTERNATE U4301343S0638343S0688

335S00072 NAND,1YNM,32GX8,S3E,64G,T,SLGA70 U15001 NAND_32GCRITICAL

C0731132S0316 NOSTUFF1 CAP,CER,X5R,0.1UF,20%,6.3V,01005

MALTA1 R0651118S00025 RES,MF,330OHM,1%,1/32W,01005

1 U0600POP,MALTA+2GB 25NM DDR,A1,M,DEV339S00121 MALTA

1 R0730 MAUIRES,MF,100OHM,1%,1/32W,01005118S0631

131S0307 C07301 MAUICAP,CER,NPO/COG,100PF,5%,16V,01005

339S00096 1 U0600 MAUIPOP,MAUI+2GB 25NM DDR,C0,H,DEV

132S0316 1 C0731CAP,CER,X5R,0.1UF,20%,6.3V,01005 MAUI

U20001 MAUI338S00171 IC,PMU,ANTIGUA,D2255A1,OTP-YG

117S0161 R06511 MAUIRES,MF,0OHM,1/32W,01005

1338S00170 U2000 MALTAIC,PMU,ANTIGUA,D2255A1,OTP-BG

1 NOSTUFFC0730131S0307 CAP,CER,NPO/COG,100PF,5%,16V,01005

R0730118S00009 RES,MF,3.01KOHM,1%,1/32W,010051 MALTA

NAND,1YNM,16GX8,S3E,64G,T,SLGA70335S00054 U1500 CRITICAL1 NAND_16G

ALTERNATE138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402C5201_RF138S00024

ALTERNATE FERR BD,70 OHM,25%,300MA,0.4 DCR,01005FL3151155S0941155S0960

NAND_64GU1500NAND,1YNM,64GX8,S3E,TLC,128G,H,ULGA70335S00076 1 CRITICALTABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTYTABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTYTABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

TABLE_5_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTYTABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

TABLE_5_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

PART# DESCRIPTIONQTYTABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_ALT_ITEM

TABLE_5_ITEM

PART# DESCRIPTIONQTYTABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

Page 3: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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SELECTED -->

SELECTED -->

BOOTSTRAPPING:BOARD REVBOARD ID

0110110X

N/A

0X6C0X36

1100011XLED DRIVER

REAR CAM

0X29

N69 I2C DEVICE MAPI2C BUS

BACKLIGHT

TIGRIS

0X63

OWL

1110 PROTO1 1111 PROTO0 MLB

BOARD_ID[4:0]

00010 N69 MLB

FLOAT=LOW, PULLUP=HIGH

00011 N69 DEV

BOOT_CONFIG[2:0]

000 SPI0001 SPI0 TEST MODE010 NVME0 x2 MODE011 NVME0 x2 TEST MODE

0100111X

N/AN/AUNUSED

N/AN/AUNUSED

FRONT CAM

CHESTNUT

0X34

TRISTAR ACCESSORY ID

TRISTAR USB

RESET

VBUS

TOUCH I2C

I2C1

0xA20x511010001XSEP EEPROMSEP I2C

ISP I2C1

TBD TBDTBD

0XC6

N/A

ALS

0X80

0X52

0011010X 0X1A

0X401000000X

0X75

0X4E0X27

0X741110100X

100 NVME0 x1 MODE101 NVME0 x1 TEST MODE

111 FAST SPI0 TEST MODE

SELECTED -->

RESISTOR NOSTUFF = LOW '0'

RESISTOR STUFF = HIGH '1'

7-BIT HEX

0XEA

I2C0

I2C2

FORCE DFU PROCEDURE:

LCM

MOJAVE

FLOAT=LOW, PULLUP=HIGH

VBATT

POWER GROUND

POWER

TESTPOINTS

SOC & BB RESET

FIXTURE SI

AMUX

BINARY

ANTIGUA PMU

DEVICE

0101001X

0XE8

8-BIT HEX

SPEAKER AMP

1110101X

0X62 0XC4

BOOT CONFIG

ISP I2C0

TRISTAR

1100010X

110 SLOW SPI0 TEST MODE

FLOAT=LOW, PULLUP=HIGH

XXXX DVT XXXX CARRIER

ACCESSORY POWER

TRISTAR DEBUG UART

E75

DFU

2. PLUG IN E75 CABLE TO FORCE DFU1. FROM OFF MODE SHORT TP07 TO PP07

TP 24 FOR USB

BOARD_REV[3:0]

1100 EVT 1101 PROTO2

3 OF 60

4 OF 49

4.0.0

051-00648

PP1V8

BOARD_ID2

BOARD_REV2

PMU_TO_SYSTEM_COLD_RESET_L

PP1V8

DFU_STATUS

PMU_AMUX_BY

PP_LCM_BL_ANODE_CONN

PP11V3_MESA

BOARD_ID0

BOARD_ID4

PP_LCM_BL_CAT2_CONN

BOOT_CONFIG2

BOOT_CONFIG1

BOOT_CONFIG0

PP_TRISTAR_ACC2

TRISTAR_CON_DETECT_L

FORCE_DFULCD_TO_AP_PIFA_CONN

PP5V0_USB

PP_TRISTAR_ACC1

90_TRISTAR_DP1_CONN_P

90_TRISTAR_DP1_CONN_N

90_TRISTAR_DP2_CONN_P

90_TRISTAR_DP2_CONN_N

PMU_AMUX_AY

PP_LCM_BL_CAT1_CONN

MESA_TO_BOOST_EN

PP_BATT_VCC

BOARD_ID3

BOARD_REV0

BOARD_REV3

BOARD_REV1

SYSTEM:N69 SPECIFIC [4]SYNC_MASTER=N/A SYNC_DATE=N/A

TP-P55ROOM=TEST

TP051

MF 1/32W1.00K

5%

ROOM=SOC

01005R0411 1 2

1.00K01005 5% 1/32WMF

ROOM=SOCR0410 1 2

NOSTUFF

1/32W5%

1.00K01005 MF

ROOM=SOCR0409 1 2

TP-P55ROOM=TEST

TP141

8

8

8

8

8

8

8

8

8

8

8

8 1.00KROOM=SOC

5%MF01005 1/32WR0400 1 2

5% 1/32WMF010051.00KROOM=SOCR0401 1 2

NOSTUFF

01005 MF

ROOM=SOC 1.00K1/32W5%

R0402 1 2

ROOM=SOC

1/32W1.00K

NOSTUFF

01005 MF 5%

R0404 1 2

NOSTUFF1.00K

1/32W5%MF01005

ROOM=SOCR0403 1 2

1/32W

ROOM=SOC 1.00KMF01005

NOSTUFF

5%

R0406 1 2

NOSTUFF1.00K

5%MF 1/32W

ROOM=SOC

01005R0405 1 2

5%MF 1/32W1.00KROOM=SOC

01005R0407 1 2

NOSTUFFROOM=SOC

1/32W01005 MF 5%

1.00KR0408 1 2

TP-P55ROOM=TEST

TP071

TP-P55ROOM=TEST

TP161

ROOM=TESTTP-P55

TP061

TP-P55ROOM=TEST

TP171

ROOM=TESTTP-P6

TP031

TP-P6ROOM=TEST

TP001

TP-P6ROOM=TEST

TP011

TP-P55ROOM=TEST

TP221

ROOM=TESTTP-P55

TP211

ROOM=TESTTP-P55

TP201

TP-P55ROOM=TEST

TP151

TP-P55ROOM=TEST

TP131

TP-P55ROOM=TEST

TP121

TP-P55ROOM=TEST

TP111

TP-P55ROOM=TEST

TP101

TP-P55ROOM=TEST

TP091

ROOM=TESTTP-P55

TP081

ROOM=TESTTP-P55

TP191

TP-P55ROOM=TEST

TP181

ROOM=TEST

P4MM-NSMSM

PP071

P4MM-NSM

ROOM=TEST

SM

PP081

TP-P55ROOM=TEST

TP241

TP-P55ROOM=TEST

TP231

ROOM=TESTTP-P6

TP021

29 28 21 20 14 13 12 9 8 7 6 5 3

16 9 5

2928 21 20 14 13 12 9 8 7 6 5 3

8

16

28

27 26

28

31 30

31 30

8

28

31 30 17

31 30

31 30

31 30

31 30

31 30

16

28

27 26

33 18 17

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

A

A

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

PP

PP

A

A

A

Page 4: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

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f i x

. c o

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COMPASS RETURN CURRENTS

BOARD STANDOFFS

TOP-SIDE, EAST

TOP-SIDE, WEST

AND AC COUPLING CAPS FOR

LOWER FRONT SHIELD

FIDUCIALSSHIELDS

TOP-SIDE, GROUND SPRING

PLATED SHIELD SLOT

UPPER FRONT SHIELD

NORTH WIFI UNDERFILL BLOCKING

COMPASS AC GROUNDING CAPS

4 OF 60

5 OF 49

4.0.0

051-00648

EAST_STANDOFF_AC_GND_SCREW

WEST_STANDOFF_AC_GND_SCREW

COMPASS_AC_GND_SCREW

SYNC_MASTER=N/A SYNC_DATE=N/A

SYSTEM:MECHANICAL

SPRING-SUPER-COWLING-GROUND-X145

CLIP-SM

SP05021

STDOFF-2.7OD1.4ID-1.04H-SM-1BS0502

1

STDOFF-2.7OD1.4ID-1.04H-SM-1BS0501

1

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05151

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05141

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05121

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05111

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05101

ROOM=ASSEMBLY

FID0P5SM1P0SQ-NSP

FD05051

ROOM=ASSEMBLY

FID0P5SM1P0SQ-NSP

FD05041

ROOM=ASSEMBLY

FID0P5SM1P0SQ-NSP

FD05031

ROOM=ASSEMBLY

FID0P5SM1P0SQ-NSP

FD05021

MF 1/32W0%

0.0001005

CKPLUS_WAIVE=TERMSHORTED

R0501 1 2

0% 1/32W

0.00MF01005

CKPLUS_WAIVE=TERMSHORTED

R0500 1 2

56PF

NP0-C0G01005

5%16V

C05231

2

NP0-C0G

56PF5%16V

01005

C05131

2

3.3PF

CERM01005

16V+/-0.1PF

C05221

2

3.3PF

01005CERM+/-0.1PF16V

C05121

2

56PF

NP0-C0G01005

5%16V

C05211

2

16V5%

01005NP0-C0G

56PFC05111

2

100PF

NP0-C0G01005

5%16V

C05201

2

100PF

NP0-C0G01005

5%16V

C05101

2

ROOM=ASSEMBLY

FID0P5SQ-SMP3SQ-NSP

FD05161

ROOM=ASSEMBLY

3.3PF

C0G-CERM0201

+/-0.1PF25V

C05431

2

ROOM=ASSEMBLYNP0-C0G-CERM2%

0201

50V

56PFC05421

2

ROOM=ASSEMBLY

100PF

C0G0201

2%50V

C05411

2

ROOM=ASSEMBLY

0.01UF

X5R-CERM0201

10%25V

C05401

2

SL-1.20X0.40-1.50X0.70-NSP

TH-NSPSL05011

P4MM-NSMSMPP05011

SHLD-EMI-LOWER-FRONT-N69

SM

OMIT_TABLE

SH05011

SM

SHLD-EMI-UPPER-FRONT-N69OMIT_TABLE

SH05001

ROOM=ASSEMBLY

FID0P5SM1P0SQ-NSP

FD05011

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

Page 5: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

i n a

f i x

. c o

m

SOC - USB, JTAG, XTAL

VDD12_PLL_SOC: 1.14-1.26V @12mA MAXVDD12_PLL_CPU: 1.14-1.26V @2mA MAX

VDD18_USB: 1.71-1.89V @20mA MAXVDD18_XTAL:1.62-1.98V @2mA MAX

VDD33_USB:3.14-3.46V @5mA MAX

VDD12_PLL_LPDP:1.14-1.26V @2mA MAX

051-00648

4.0.0

6 OF 49

5 OF 60

45_SOC_24M_O

45_XTAL_AP_24M_IN

USB_REXT

45_XTAL_AP_24M_OUT

USB_VBUS_DETECT

PP1V2_PLL PP1V8

90_USB_AP_DATA_AP_P90_USB_AP_DATA_N90_USB_AP_DATA_P

AP_TO_PMU_AMUX_OUT

AP_TO_PMU_WDOG_RESET

AP_TO_NAND_RESET_L

PMU_TO_SYSTEM_COLD_RESET_L

PP1V8_XTAL

PP3V3_USB

PMU_TO_OWL_ACTIVE_READY

SWD_DOCK_BI_AP_SWDIO

90_USB_AP_DATA_AP_N

45_AP_XTAL_GND

PP1V2

50_AP_BI_BB_HSIC0_DATA50_AP_BI_BB_HSIC0_STB

AP_TO_PMU_TEST_CLKOUT

SWD_DOCK_TO_AP_SWCLK

SOC:JTAG,USB,XTALSYNC_MASTER=N/A SYNC_DATE=N/A

ROOM=SOC

P2MM-NSMSM

PP06211

ROOM=SOC

P2MM-NSMSM

PP06201

33

33

0201 ROOM=TRISTAR

15NH-250MAL0601

1 2

ROOM=TRISTAR0201

15NH-250MAL0602

1 2

30

30

20%6.3V0.22UF

ROOM=PMU0201X5R

C06041

2

P3MM-NSMSM

ROOM=SOC

PP0610 1

FCMSP

ROOM=SOC

SC58980X0B-A040

MAUI-2GB-25NM-DDR-H

CRITICALOMIT_TABLE

U0600

AP24

H33

AC31

AL22AG25

H32

Y32

AA31

AA32AB31

AB32

AC32

AN23

AF6

AR23

AN22AN21

C16D15

AT19AT20

AR19

AP18

AP19

AF13

F22

U20

T19

W19

AP21

C15

AL21

AL34

AN20

Y33

AK35AL35

16

1%

MF1/32W

511K

01005ROOM=SOC

R06501

2

01005ROOM=SOC

1/32W0%

OMIT_TABLE

MF

0.00R0651

1 2

17

6.3VX5R-CERM0201

2.2UF

ROOM=SOC

20%

C06101

26.3V

01005

20%

ROOM=SOC

0.1UF

X5R-CERM

C06111

2

1KOHM-25%-0.2A

0201ROOM=SOC

FL06101 2

13

16

16

30 26 16 9

16 9 3

30

30

ROOM=SOC01005

16V5%CERM

12PFC06511

2

CRITICAL

1.60X1.20MM-SM24.000MHZ-30PPM-9.5PF-60OHM

ROOM=SOC

Y0600

2 4

1 3

01005ROOM=SOC

CERM16V5%12PFC06501

2

01005X5R-CERM

ROOM=SOC

6.3V20%0.1UF

C06011

2

6.3V20%0.1UF

ROOM=SOC01005X5R-CERM

C06201

2

ROOM=SOC

SHORT-10L-0.1MM-SMXW0650

1 2

0.1UF20%

ROOM=SOC01005X5R-CERM6.3V

C06121

26.3V

ROOM=SOC

X5R01005

0.01UF10%

C06031

2

1/32W

0.00

01005MF

ROOM=SOC

0%

R06001 2

10%

X5R01005

6.3V

0.01UF

ROOM=SOC

C06021

26.3V

0.1UF

X5R-CERM

20%

ROOM=SOC01005

C06001

2

2001%

MF01005

1/32W

ROOM=SOC

R06401

2

29 28 21 20 14 13 12 9 8 7 6 3

15

15 7 6

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

PP

NCNC

BI

BI

BI

BI

PP

SYM 1 OF 14

USB_D_NUSB_D_P

S3E_RESET*

TST_CLKOUT

HOLD_RESET

TESTMODE

WDOG

XO0XI0

USB_REXT

FUSE1_FSRCFUSE2_FSRC

COLD_RESET*

JTAG_TCKJTAG_TMSJTAG_TDI

CFSB

JTAG_TRST*JTAG_TDO

UH2_HSIC1_DATA

UH1_HSIC0_DATAUH1_HSIC0_STB

JTAG_SEL

UH2_HSIC1_STB

USB_IDVD

D12_

UH1_

HSIC

0VD

D12_

UH2_

HSIC

1

VDD1

8_XT

AL

VDD3

3_US

B

VDD1

2_PL

L_LP

DP

ANALOGMUX_OUT

USB_VBUS

VDD1

8_US

B

VDD1

2_PL

L_CP

U

VDD1

2_PL

L_SO

C

OUT

IN

OUT

OUT

OUT

IN

IN

IN

BI

NC

NCNCNC

Page 6: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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SOC - PCIE INTERFACES

VDD12_PCIE_REFBUF:1.08-1.26V @50mA MAX

VDD12_PCIE: 1.14-1.26V @115mA MAXVDD12_PCIE_TXPLL: 1.08-1.32V @10mA MAX

PCIE

LIN

K 0

PCIE

LIN

K 1

VDD085_PCIE:0.802-TBDV @TBDmA MAX

6 OF 60

7 OF 49

4.0.0

051-00648

90_PCIE_AP_TO_NAND_REFCLK_P

90_PCIE_AP_TO_NAND_TXD1_C_N

PP_FIXED

90_PCIE_NAND_TO_AP_RXD0_C_P

PCIE_AP_TO_NAND_RESET_LPCIE_AP_TO_WLAN_RESET_L

90_PCIE_AP_TO_NAND_TXD0_C_P

90_PCIE_NAND_TO_AP_RXD1_C_N

90_PCIE_AP_TO_WLAN_TXD_N90_PCIE_AP_TO_WLAN_TXD_P

90_PCIE_AP_TO_NAND_TXD1_N

90_PCIE_AP_TO_NAND_TXD0_P90_PCIE_AP_TO_NAND_TXD0_N 90_PCIE_AP_TO_NAND_TXD0_C_N

90_PCIE_AP_TO_WLAN_TXD_C_N

90_PCIE_AP_TO_NAND_REFCLK_N

90_PCIE_WLAN_TO_AP_RXD_N90_PCIE_WLAN_TO_AP_RXD_P

90_PCIE_AP_TO_NAND_TXD1_P

90_PCIE_NAND_TO_AP_RXD0_P

90_PCIE_WLAN_TO_AP_RXD_C_P

90_PCIE_AP_TO_WLAN_TXD_C_P

90_PCIE_AP_TO_NAND_TXD1_C_P

PP1V2

PCIE_EXT_C

90_PCIE_NAND_TO_AP_RXD1_P 90_PCIE_NAND_TO_AP_RXD1_C_P

45_PCIE_RCAL_N

90_PCIE_WLAN_TO_AP_RXD_C_N

90_PCIE_NAND_TO_AP_RXD0_N

PP1V2_PCIE_TXPLL

90_PCIE_NAND_TO_AP_RXD0_C_N

PCIE_WLAN_TO_AP_CLKREQ_L

PP1V8

90_PCIE_AP_TO_WLAN_REFCLK_P90_PCIE_AP_TO_WLAN_REFCLK_N

PCIE_NAND_TO_AP_CLKREQ_L

90_PCIE_NAND_TO_AP_RXD1_N

SYNC_DATE=N/ASYNC_MASTER=N/A

SOC:PCIE

P2MM-NSMSM

PP07011

P2MM-NSMSM

PP07001

0.1UF20%6.3VX5R-CERM01005ROOM=SOC

C07441

2

3.01K1%1/32WMF01005ROOM=SOC

OMIT_TABLE

R07301

2

ROOM=SOC

SHORT-10L-0.1MM-SMXW0740

1 2

CRITICAL

ROOM=SOC

FCMSP

MAUI-2GB-25NM-DDR-H

SC58980X0B-A040

OMIT_TABLE

U0600

AT11AP12AR12AT12

AP29

AT33AR33

AR10AT10AP11AR11

AR30AT30

AP35AN35

AP34AN34

AN32AM32

AN31AM31

AN30AM30

AN28AM28

AN27AM27

AN26AM26

AN25AM25

AR29AT29

AR32AT32

AR31AT31

AR28AT28

AR26AT26

AT24AR24

AK28

AK25

AL24

AL27

AJ26

AL26

AH28

AJ25

AL23

AJ29

AL29

AJ24

AK27

AJ27

01005

1/32W

100K

MF

5%

ROOM=SOC

R07211

2

100K

01005ROOM=SOC

MF

5%1/32W

R07201

2

33

13

33

33

13

13

100K5%

MF

ROOM=SOC

1/32W

01005

R07001

2

100K5%

ROOM=SOC

MF1/32W

01005

R07011

2

33

13

NP0-C0G

ROOM=SOC

5%16V

01005

100PF

OMIT_TABLE

C07301

2

OMIT_TABLE

0.1UF

X5R-CERM01005

6.3V

ROOM=SOC

20%

C07311

2

33

33

33

33

13

13

13

13

13

13

20%ROOM=SOC0.1UF

010056.3VX5R-CERM

C0712 1 2

ROOM=SOC X5R-CERM6.3V

0.1UF20%

01005

C0711 1 2

0.1UF20%ROOM=SOC

6.3V 01005X5R-CERM

C0710 1 2

20%0.1UF

6.3VROOM=SOC

01005X5R-CERM

C0709 1 2

0.1UFROOM=SOC

6.3V20%

01005X5R-CERM

C0707 1 2

6.3VROOM=SOC 20%

01005X5R-CERM

0.1UFC0708 1 2

6.3VX5R-CERM20%ROOM=SOC01005

0.1UFC0706 1 2

X5R-CERM6.3V20%ROOM=SOC

01005

0.1UFC0705 1 2

01005X5R-CERM20%ROOM=SOC

6.3V

0.1UFC0704 1 2

13

13

20%ROOM=SOC0.1UF

01005X5R-CERM

6.3V

C0703 1 2

6.3V20%ROOM=SOC

0.1UFX5R-CERM01005

C0702 1 2

X5R-CERM6.3V20%ROOM=SOC

01005

0.1UFC0701 1 2

20%

ROOM=SOC0201

2.2UF6.3VX5R-CERM

C07501

2ROOM=SOC

X5R-CERM

2.2UF

0201

20%6.3V

C07401

2

ROOM=SOC0201-1

6.3V1.0UF

X5R20%

C07411

201005X5R-CERM20%0.1UF

ROOM=SOC

6.3V

C07521

2X5R-CERM01005

0.1UF20%6.3V

ROOM=SOC

C07431

2

0.1UF

X5R-CERM20%

ROOM=SOC

6.3V

01005

C07421

2X5R6.3V20%

ROOM=SOC0201-1

1.0UFC07511

2

14 11 7 15 7 5

29 28 21 20 14 13 12 9 8 7 5 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

PP

NC

NCNC

NC

NCNC

NCNC

SYM 2 OF 14

PCIE_RX4_P

VDD1

2_PC

IE

PCIE_REF_CLK2_P

PCIE_REF_CLK1_N

PCIE_REF_CLK0_P

PCIE_PERST3*

PCIE_PERST0*

PCIE_PERST2*PCIE_PERST1*

PCIE_CLKREQ3*

PCIE_CLKREQ1*PCIE_CLKREQ0*

PCIE_CLKREQ2*

PCIE_RX_TX_BYPASS_CLK_PPCIE_RX_TX_BYPASS_CLK_N

PCIE_EXT_REF_CLK_NPCIE_EXT_REF_CLK_P

PCIE_REF_CLK3_NPCIE_REF_CLK3_P

PCIE_REF_CLK2_N

PCIE_RCAL_NPCIE_RCAL_P

PCIE_TX4_NPCIE_TX4_P

PCIE_RX4_N

PCIE_TX3_NPCIE_TX3_P

PCIE_RX3_NPCIE_RX3_P

PCIE_TX2_NPCIE_TX2_P

PCIE_RX2_NPCIE_RX2_P

PCIE_TX1_NPCIE_TX1_P

PCIE_RX1_PPCIE_RX1_N

PCIE_TX0_PPCIE_TX0_N

PCIE_EXT_C

PCIE_RX0_N

PCIE_REF_CLK1_P

PCIE_REF_CLK0_NPCIE_RX0_P

VDD1

2_PC

IE_T

XPLL

VDD1

2_PC

IE_R

EFBU

F

VDD0

85_P

CIE

NC

BI

BI

NCNC

OUT

OUT

OUT

OUT

NC

OUT

OUT

NCNC

NCNC

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

Page 7: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

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SOC - CAMERA & DISPLAY INTERFACES

NOTE:VDD12_LPDP SHOULD BE POWERED

1.62-1.98V @23mA MAX

EVEN WHEN LPDP IS NOT USED

0.756-0.893V @11mA MAX

7 OF 60

8 OF 49

4.0.0

051-00648

90_MIPI_RCAM_TO_AP_DATA2_CONN_N90_MIPI_RCAM_TO_AP_DATA2_CONN_P

90_MIPI_RCAM_TO_AP_DATA1_CONN_N

90_MIPI_RCAM_TO_AP_CLK_CONN_P

90_MIPI_RCAM_TO_AP_DATA3_CONN_N

90_MIPI_RCAM_TO_AP_DATA1_CONN_PI2C_ISP_BI_FCAM_SDAI2C_ISP_TO_FCAM_SCL

I2C_ISP_TO_RCAM_SCLI2C_ISP_BI_RCAM_SDA

90_MIPI_FCAM_TO_AP_CLK_P

PP1V2

PP1V8

PP_FIXED

90_MIPI_AP_TO_LCM_DATA0_N

45_RCAM_REXT

90_MIPI_AP_TO_LCM_DATA0_P

45_AP_TO_RCAM_CLK

45_AP_TO_FCAM_CLK

90_MIPI_RCAM_TO_AP_CLK_CONN_N

90_MIPI_RCAM_TO_AP_DATA3_CONN_P

90_MIPI_RCAM_TO_AP_DATA0_CONN_N90_MIPI_RCAM_TO_AP_DATA0_CONN_P

90_MIPI_FCAM_TO_AP_DATA0_P90_MIPI_FCAM_TO_AP_DATA0_N

PP1V8

90_MIPI_AP_TO_LCM_CLK_N90_MIPI_AP_TO_LCM_CLK_P

90_MIPI_AP_TO_LCM_DATA1_P

45_LCM_REXT 90_MIPI_FCAM_TO_AP_CLK_N

90_MIPI_AP_TO_LCM_DATA1_N

AP_TO_STOCKHOLM_DWLD_REQUEST

AP_TO_RCAM_SHUTDOWN_L

45_AP_TO_FCAM_CLK_R

45_FCAM_REXT

45_AP_TO_RCAM_CLK_R

AP_TO_FCAM_SHUTDOWN_L

AP_TO_MUON_BL_STROBE_EN

SYNC_DATE=N/ASYNC_MASTER=N/A

SOC:CAMERA & DISPLAY

26

CRITICAL

FCMSP

ROOM=SOC

MAUI-2GB-25NM-DDR-H

SC58980X0B-A040

OMIT_TABLE

U0600

H35

AL4

B29A29

D24

D25

B33A33

B32A32

B31A31

B30A30

E23

E25

E27

F24

MAUI-2GB-25NM-DDR-H

CRITICAL

SC58980X0B-A040

ROOM=SOC

FCMSP

OMIT_TABLE

U0600

G31G32

F35G34

B12A12

A8B8

B9A9

B13A13

A14B14

D12

B18A18

A17B17

A19B19

D14

G35

B5A5

B3A3

A4B4

A6B6

B7A7

D9

D33

D34

D32

F32

F33

C35

E34

C34

D10

E7 D8 E11

E14

E10

E13

E8 D13

20

20

20

20

33

20

21

20

21

33.21/32W

ROOM=SOC

MF1%01005

R08091 2

28

28

28

28

28

28

21

21

21

21

21

21

21

21

21

21

20

20

22 21

22 21

1/32W

1.00K

01005MF

5%

ROOM=SOC

R08071

2

5%1/32W

1.00K

01005ROOM=SOC

MF

R08061

2

1.00K

01005

1/32W

ROOM=SOC

MF

5%

R08051

201005ROOM=SOC

1.00K5%1/32WMF

R08041

2

20%0.1UF

01005X5R-CERM6.3V

ROOM=SOC

C08151

220%0.1UF

01005X5R-CERM6.3V

ROOM=SOC

C08141

2

0.1UF

01005X5R-CERM6.3V

ROOM=SOC

20%

C08021

2

4.02K1%

1/32W

01005MF

ROOM=SOC

R0802 1

2

4.02K1%1/32W

01005ROOM=SOC

MF

R08031

201005

4.02K1%

1/32W

ROOM=SOC

MF

R0801 1

2

ROOM=SOC

1/32W01005

33.2MF1%

R08081 2

20%0.1UF

01005X5R-CERM6.3V

ROOM=SOC

C08011

2

15 6 5

29 28 21 20 14 13 12 9 8 7 6 5 3

14 11 6 29

2821 20 14 13 12 9 8 7 6 5 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

NCNC

NC

NCNC

NCNC

SYM 4 OF 14

LPDP_TX3_PLPDP_TX3_N

LPDP_TX2_PLPDP_TX2_N

LPDP_TX1_PLPDP_TX1_N

LPDP_TX0_PLPDP_TX0_N

VDD1

2_LP

DP

LPDP_AUX_PLPDP_AUX_N

EDP_HPD

DP_WAKEUP

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

SYM 3 OF 14

MIPID_DATA3_P

MIPID_DATA2_P

MIPID_DATA1_P

MIPID_DATA0_P

MIPID_CLK_P

MIPID_DATA3_N

MIPID_DATA2_N

MIPID_DATA1_N

MIPID_DATA0_N

MIPID_CLK_N

MIPI1C_DATA1_P

MIPI1C_DATA0_P

MIPI1C_CLK_P

MIPI1C_DATA1_N

MIPI1C_DATA0_N

MIPI1C_CLK_N

MIPI0C_DATA3_P

MIPI0C_DATA2_P

MIPI0C_DATA1_P

MIPI0C_DATA0_P

MIPI0C_CLK_P

MIPI0C_DATA3_N

MIPI0C_DATA2_N

MIPI0C_DATA1_N

MIPI0C_DATA0_N

MIPI0C_CLK_N

ISP_I2C0_SDAISP_I2C0_SCL

SENSOR0_RSTSENSOR0_CLK

ISP_I2C1_SCLISP_I2C1_SDA

SENSOR1_XSHUTDOWN

SENSOR0_XSHUTDOWNSENSOR0_ISTRB

SENSOR1_RST

SENSOR1_ISTRB

SENSOR1_CLK

MIPICSI_MUXSEL

MIPI1C_REXT

MIPI0C_REXT

MIPID_REXT

VDD1

8_M

IPI

VDD0

85_M

IPI

IN

IN

IN

IN

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

BI

OUT

NC

NC

NC

NCNC

NCNC

NCNC

NCNC

NCNC

NC

NC

Page 8: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

SOC - GPIO & SERIAL INTERFACES

SPI PROBE POINTS

128kbit

.

APN:335S0946

ANTI-ROLLBACK EEPROM

BUTTON PULL-UP RESISTORS AND BUFFERS

I2C PROBE POINTS

8 OF 60

9 OF 49

4.0.0

051-00648

AP_TO_PMU_SOCHOT1_L

PP1V8_ALWAYS

I2C0_AP_SDA

I2C2_AP_SCLI2C2_AP_SDA

PP1V8

PMU_TO_AP_SOCHOT0_R_L PMU_TO_AP_SOCHOT0_L

45_I2S_AP_TO_SPEAKERAMP_MCLK_R

AP_TO_VIBE_TRIG

SPEAKERAMP_TO_AP_INT_L

BOARD_ID2BOARD_ID1BOARD_ID0

SPI_TOUCH_TO_AP_MISO

SPI_AP_TO_CODEC_MOSI

SPI_CODEC_TO_AP_MISO

45_AP_TO_TOUCH_CLK32K_RESET_L

SPI_AP_TO_CODEC_CS_LSPI_AP_TO_CODEC_SCLK

UART_AP_TO_STOCKHOLM_TXD

UART_BB_TO_AP_CTS_L

SPI_AP_TO_TOUCH_MOSI

SPI_AP_TO_TOUCH_CS_L

SPI_MESA_TO_AP_MISOSPI_AP_TO_MESA_MOSISPI_AP_TO_MESA_SCLK_R

I2S_AP_TO_CODEC_MSP_DOUTI2S_CODEC_TO_AP_MSP_DIN

45_I2S_AP_TO_BB_BCLK

SPI_CODEC_TO_AP_MISO

I2S_AP_TO_CODEC_MSP_LRCLK

I2S_AP_TO_BB_LRCLK

BUTTON_VOL_UP_LBUTTON_VOL_DOWN_L

AP_TO_BT_WAKEAP_TO_SPEAKERAMP_RESET_L

AP_TO_BB_RESET_L

I2S_BT_TO_AP_DINI2S_AP_TO_BT_DOUT

ALS_TO_AP_INT_L

SPI_AP_TO_CODEC_MOSI

SPI_AP_TO_MESA_SCLK

45_I2S_AP_TO_SPEAKERAMP_MCLK

45_I2S_AP_TO_CODEC_MCLK_R45_I2S_AP_OWL_TO_CODEC_XSP_BCLK

45_I2S_AP_TO_BT_BCLK

I2S_CODEC_TO_AP_OWL_XSP_DINI2S_AP_OWL_TO_CODEC_XSP_LRCLK

45_I2S_AP_TO_CODEC_MCLK

I2S_CODEC_TO_AP_ASP_DIN

I2C_SEP_BI_EEPROM_SDA

I2S_AP_TO_CODEC_ASP_LRCLK

I2C1_AP_SCLI2C1_AP_SDA

I2C_SEP_TO_EEPROM_SCL

I2S_AP_TO_BT_LRCLK

I2S_AP_TO_CODEC_ASP_DOUT

PP1V8

I2S_AP_TO_CODEC_XSP_DOUT

AP_TO_NAND_SYS_CLK

PP1V8

I2C_SEP_BI_EEPROM_SDA

SPI_AP_TO_TOUCH_SCLK

45_I2S_AP_TO_CODEC_ASP_BCLK

I2S_BB_TO_AP_DIN

45_I2S_AP_TO_CODEC_MSP_BCLK

AP_TO_NAND_SYS_CLK_R

I2C_SEP_TO_EEPROM_SCL

PP1V8_SDRAM

PP1V8_SDRAM

BUTTON_HOLD_KEY_L

BUTTON_MENU_KEY_L

TRISTAR_TO_AP_INT

I2S_AP_TO_BB_DOUT

PMU_TO_AP_IRQ_L

BB_TO_AP_GPS_TIME_MARK

FORCE_DFU

UART_AP_TO_WLAN_RTS_LUART_WLAN_TO_AP_CTS_L

UART_AP_TO_BB_RTS_L

UART_STOCKHOLM_TO_AP_CTS_L

UART_AP_TO_BT_RTS_LUART_BT_TO_AP_CTS_L

UART_AP_TO_ACCESSORY_TXDUART_ACCESSORY_TO_AP_RXD

UART_AP_TO_BB_TXD

UART_WLAN_TO_AP_RXDUART_AP_TO_WLAN_TXD

SWI_AP_BI_TIGRIS

UART_BB_TO_AP_RXD

AP_TO_TOUCH_RESET_LAP_TO_LED_DRIVER_EN

AP_TO_LCM_RESET_L

BOOT_CONFIG0AP_TO_BB_WAKE_MODEM

BOARD_ID3AP_TO_STOCKHOLM_DEV_WAKE

LCM_TO_AP_HIFA_BSYNCBB_TO_AP_HSIC_DEVICE_RDY

AP_TO_BB_HSIC_HOST_RDYBB_TO_AP_RESET_DETECT_LBOOT_CONFIG1

BOOT_CONFIG2BOARD_ID4CODEC_TO_AP_PMU_INT_LAP_TO_BB_RADIO_ON_L

TOUCH_TO_AP_INT_LBOARD_REV3BOARD_REV2BOARD_REV1BOARD_REV0AP_TO_BB_COREDUMPBB_TO_AP_IPC_GPIOBUTTON_RINGER_AAP_TO_BB_MESA_ONCAM_EXT_LDO_EN

UART_STOCKHOLM_TO_AP_RXD

UART_AP_TO_BT_TXD

UART_AP_DEBUG_TXD

UART_BT_TO_AP_RXD

UART_AP_DEBUG_RXD

BUTTON_RINGER_A

PP1V8_ALWAYS

BUTTON_HOLD_KEY_BUFF_L

BUTTON_MENU_KEY_BUFF_L

UART_AP_TO_STOCKHOLM_RTS_L

I2C0_AP_SCL

PP1V8

PCIE_AP_TO_WLAN_DEV_WAKE

DFU_STATUS

AP_TO_NAND_FW_STRAP

SPI_AP_TO_TOUCH_MOSI

MESA_TO_AP_INT

SPI_AP_TO_TOUCH_SCLK_R

SPI_TOUCH_TO_AP_MISO

SPI_AP_TO_CODEC_SCLKI2C0_AP_SDAI2C0_AP_SCL

I2C2_AP_SDAI2C2_AP_SCL

I2C1_AP_SDAI2C1_AP_SCL SYNC_DATE=N/A

SOC:SERIAL & GPIOSYNC_MASTER=N/A

P3MM-NSMSM

ROOM=SOC

PP09041

ROOM=SOCP3MM-NSM

SM

PP09051

P3MM-NSMROOM=SOC

SM PP09021

ROOM=SOCP3MM-NSM

SM

PP09031

P3MM-NSMROOM=SOC

SM

PP09011

SM

ROOM=SOCP3MM-NSM

PP09001

ROOM=SOC

5%2.2K1/32W

MF01005

R09001

2

01005ROOM=SOC

10K

MF

5%1/32W

R09411

2

ROOM=SOC

SMP2MM-NSMPP09010

1

ROOM=SOC

P2MM-NSMSM

PP09091

P2MM-NSMSM

ROOM=SOC

PP09081

SM

ROOM=SOC

P2MM-NSMPP0907

1

ROOM=SOC

SMP2MM-NSMPP0906

1

33

33

33

33

33

33

33

33

01005

392K1/32W1%

MF

R09521

216 9

16 9

32

27

74LVC1G34GXSOT1226

U0902

2

31

5

4

SOT122674LVC1G34GXU0901

2

31

5

4

33

33

33

33

392K

MF

1%1/32W

01005

R09501

2

32

21

ROOM=SOC

0.0001005 0% 1/32W MF

R09601 2

1/32W

1.33K

01005ROOM=SOC

1%

MF

R0905 1

2ROOM=SOC

MF1/32W

01005

1%1.33K

R0904 1

2

24

24

24

24

29

ROOM=SOC01005

1/32WMF

0%

0.00R0945

1 2

CRITICAL

FCMSP

ROOM=SOCMAUI-2GB-25NM-DDR-H

SC58980X0B-A040

OMIT_TABLE

U0600

H34

H31

E31D35

AH1AG4

L31M32

R34

N35M33

N34

P34

M3

N3L4

P1

M4

V33

T33V34

U33

U32

AM4

AP1AN1

AN2

AM3

R31

P31P32

V32

R32

AM24

Y3AB4

V3Y4

AA4U2

W3

AM1

AM2

AD4AC3AB2AD3

P33V35N32M31

E33E35F34F31

AA2Y2

AA3AC4

SC58980X0B-A040

ROOM=SOC

CRITICAL

FCMSP

MAUI-2GB-25NM-DDR-H

OMIT_TABLE

U0600C1D2D1F1E2F3F2H3G3J1H4K1J3K2J4L2K3L3N1

AH2AH3AH4AJ1AJ2AJ3AJ4AK1AP3AN4AP4AP5AR2AR3AR4AP6AT3AT4AR6AP7AT5AP8AP9

AP10

AE1AF2AF3

AE3AE4

K31K32L33L32

AT23AR20AP23AP22

N4P3R3R2

J33J34J35K33

T32

AF1AE2

J31J32

13

30 16

24

24 9

24 9

24 9

25 24

25 24

25 24

25 24

25

24

33

01005MF

5%100K1/32W

ROOM=SOC

R09511

2

ROOM=SOC

1/32W MF0%01005

0.00R0930

1 229

33

3

33

32 16 8

33 29 28 9

16

29

33

33

33

24 16

16

16

0.00

010051/32W

ROOM=SOC

MF0%

R09401 2

01005

NOSTUFF

ROOM=SOC

MF1/32W

5%10K

R09101

2

8

8

8

8

2.2K

MF01005

1/32W

ROOM=SOC

5%

R0907 1

2

1/32W5%

01005MF

ROOM=SOC

2.2KR0906 1

2

WLCSPM34128-FCS6_P/T

ROOM=SOCCRITICAL

U0900B1 A2

A1B2

27

27

27

27

29

29 8

29 8

24

24 8

24 8

24 8

20

33

33

33

33

33

33

33

33

30

30

33

33

33

33

33

33

33

33

30

30

13

3

3

28

29

33

25

25

32 16

32 16

33

3

3

3

3

3

3

3

3

3

3

3

33

22

17 9

1/32WMF

01005ROOM=SOC

2.2K5%

R0902 1

2 ROOM=SOC

5%

MF01005

2.2K1/32W

R0903 1

2

26 16 8

26 16 8

30 25 17 8

30 25 17 8

20 8

20 8

1.0UF

0201-1

6.3VX5R20%

ROOM=SOC

C09001

2

01005

33.2

ROOM=SOC

MF

1%1/32W

R09221 2

01005

10K

ROOM=SOC

5%1/32WMF

R09091

2

01005MF

1/32W

2.2K5%

ROOM=SOC

R0901 1

2

33.2

1%

MF

ROOM=SOC01005

1/32W

R09201 2

17 15 12 8

29 28 21 20 14 13 12 9 8 7 6 5 3

29 8

24 8

24 8

29 28 21 20 14 13 12 9 8 7 6 5 3

2928 21 20 14 13 12 9 8 7 6 5 3

33 30 26 24 17 16 15 14 12 8

33 30 26 24 17 16 15 14 12 8

32 16 8

17 15 12 8

29 28 21 20 14 13 12 9 8 7 6 5 3

29 8

24 8 26 16 8

26 16 8

20 8

20 8

30 25 17 8

30 25 17 8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

NC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

IN

IN

NC

NC

NCNC

NCNC

OUT

NC

NC

NC

OUT

IN

OUT

OUT

NC

OUT

OUT

IN

OUT

OUT

OUT

SYM 6 OF 14

CPU_ACTIVE_STATUS

CLK32K_OUT

NAND_SYS_CLK

SOCHOT0

SOCHOT1

SEP_SPI0_SCLKSEP_SPI0_MISOSEP_SPI0_MOSI

SEP_I2C_SCLSEP_I2C_SDA

SEP_GPIO0SEP_GPIO1

SPI2_SCLK

I2S0_MCKI2S0_BCLKI2S0_LRCK

I2S2_MCK

I2S1_DOUT

SPI1_SSINSPI1_SCLKSPI1_MOSISPI1_MISO

SPI0_SSINSPI0_SCLKSPI0_MOSISPI0_MISO

I2S4_LRCK

I2S4_DOUTI2S4_DIN

I2S4_BCLK

I2S3_DINI2S3_DOUT

I2S3_MCK

I2S2_BCLK

I2S2_DIN

I2S3_BCLK

I2S1_LRCKI2S1_DIN

I2S0_DOUT

I2S1_BCLKI2S1_MCK

I2C0_SCL

I2C1_SCL

I2C2_SCL

I2C0_SDA

SPI2_SSIN

SPI2_MOSISPI2_MISO

SPI3_MISOSPI3_MOSISPI3_SCLKSPI3_SSIN

I2C1_SDAI2S0_DIN

I2S2_DOUT

I2C2_SDA

I2S4_MCK

I2S3_LRCK

I2S2_LRCK

SYM 5 OF 14

GPIO_13

GPIO_22

TMR32_PWM0

GPIO_1

GPIO_26

UART0_RXD

UART4_RTS*UART4_CTS*

UART3_RTS*UART3_CTS*

UART2_RTS*UART2_CTS*

UART1_RTS*UART1_CTS*

UART6_TXDUART6_RXD

TMR32_PWM2TMR32_PWM1

UART3_TXD

UART4_RXDUART4_TXD

UART5_RTXD

UART3_RXD

UART7_RXDUART7_TXD

GPIO_9GPIO_8GPIO_7

GPIO_11GPIO_10

GPIO_12

GPIO_14

GPIO_18GPIO_19

GPIO_17GPIO_16GPIO_15

GPIO_20GPIO_21

GPIO_23GPIO_24GPIO_25

GPIO_27GPIO_28GPIO_29GPIO_30GPIO_31GPIO_32GPIO_33GPIO_34GPIO_35GPIO_36GPIO_37GPIO_38GPIO_39GPIO_40GPIO_41GPIO_42

UART2_RXDUART2_TXD

UART1_TXDUART1_RXD

UART0_TXD

GPIO_6GPIO_5GPIO_4GPIO_3GPIO_2

GPIO_0

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

NCNC

OUT

OUT

IN

NC

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

BI

BI

OUT

NCNCNC

SDASCL

VCC

VSS

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

NC

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

OUT

BI

OUT

BI

OUT

BI

NC

NC

NC

Page 9: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

SOC - OWL

OWL SYSTEM SHUTDOWN OPTION

POWER STATE CONTROL PROBE POINTS

9 OF 60

10 OF 49

4.0.0

051-00648

OWL_TO_PMU_ACTIVE_REQUESTPMU_TO_OWL_ACTIVE_READY

45_DWI_PMGR_TO_PMU_SCLK45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI

PMU_TO_OWL_CLK32K

SWD_AP_PERIPHERAL_SWCLK

SWD_AP_BI_BB_SWDIO

BUTTON_HOLD_KEY_BUFF_L

SPI_OWL_TO_DISCRETE_ACCEL_CS_LACCEL_TO_OWL_INT1_R

SPI_OWL_TO_IMU_SCLK

OWL_TO_WLAN_CONTEXT_AOWL_TO_WLAN_CONTEXT_B

SPI_OWL_TO_ACCEL_GYRO_CS_L

I2S_AP_OWL_TO_CODEC_XSP_LRCLK

UART_BB_TO_OWL_RXD

45_I2S_AP_OWL_TO_CODEC_XSP_BCLKI2S_CODEC_TO_AP_OWL_XSP_DIN

PP1V8

SWI_AP_BI_TIGRIS

OWL_TO_PMU_SHDN

PMU_TO_OWL_SLEEP1_READY

OWL_TO_PMU_ACTIVE_REQUEST

OWL_TO_PMU_SHDN_BI_TIGRIS_SWI

SPI_OWL_TO_COMPASS_CS_L

PMU_TO_OWL_SLEEP1_READY

COMPASS_TO_OWL_INT

OWL_TO_PMU_SLEEP1_REQUEST

UART_OWL_TO_BB_TXD

OWL_TO_PMU_SLEEP1_REQUEST

PMU_TO_OWL_ACTIVE_READY

45_DWI_PMGR_TO_BACKLIGHT_SCLK

BUTTON_MENU_KEY_BUFF_L

PMU_TO_SYSTEM_COLD_RESET_L

SWD_AP_BI_NAND_SWDIO

ACCEL_TO_OWL_INT2_RACCEL_GYRO_TO_OWL_INT1

ACCEL_GYRO_TO_OWL_INT2

LCM_TO_AP_HIFA_BSYNCOWL_TO_PMU_SHDN_BI_TIGRIS_SWI

SPI_OWL_TO_IMU_MOSISPI_IMU_TO_OWL_MISO

SPI_OWL_TO_IMU_MOSI

SPI_IMU_TO_OWL_MISO

SPI_OWL_TO_IMU_SCLK

SPI_OWL_TO_DISCRETE_ACCEL_CS_L

SPI_OWL_TO_COMPASS_CS_L

SPI_OWL_TO_ACCEL_GYRO_CS_L

DWI_PMU_TO_PMGR_MISO

SOC:OWLSYNC_MASTER=N/A SYNC_DATE=N/A

16 9 ROOM=SOC

FCMSPMAUI-2GB-25NM-DDR-H

SC58980X0B-A040

CRITICAL

OMIT_TABLE

U0600

AA33AD32

W33

U3

V4

AD30AB33

AF35AH32AG32AG31AG30AF33AE34AF34AF31AF32

AH31AH33

AD34AA34

AE31AE32

AK31AK32AL33

AE33AD35AC33

AJ32AK33

AH30AJ31

AJ34AJ33

AL2AL1AK4AL3

AD31

W4

U31T31

16 9

NOSTUFF

01005ROOM=SOC

1/32W5%MF

10R1021

1 2

5%1/32W01005MF

10

NOSTUFF

ROOM=SOC

R10201 2 17 8

16

30 26 16 9 5

16 5 3

33 29 28 8

19

19 9

19

33

19 16

26

26 16

16

33

19 9

19 9

19 9

24 8

24 8

24 8

33

19 9

16 8

33

16 8

13

P2MM-NSMSMPP1010 1

P2MM-NSMSMPP1009 1

P2MM-NSMSMPP1008 1

P2MM-NSMSMPP1007 1

P2MM-NSMSMPP1006 1

33 13

P2MM-NSMSMPP1005 1

P2MM-NSMSM PP10041

SM

P2MM-NSMPP10031

33

19

19

19 9

16

P2MM-NSMSM PP10021

ROOM=SOC

MF

5%1/32W

01005

1.00KR10021

2

ROOM=SOC

SMP3MM-NSM

PP10201

P3MM-NSMROOM=SOC

SM PP10221

ROOM=SOC

SMP3MM-NSM

PP10231

P3MM-NSMSM

ROOM=SOC

PP10211

16 11 9

29 28 21 20 14 13 12 8 7 6 5 3

16 11 9

16 9

9

16 9

30 26 16 9 5

9

19 9

19 9

19 9

19 9

19 9

19 9

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

OUTSYM 7 OF 14

OWL_DDR_REQ

OWL_I2CM_SCL

OWL_FUNC_1

OWL_FUNC_3

OWL_UART2_TXDOWL_UART2_RXD

OWL_UART1_TXDOWL_UART1_RXD

OWL_UART0_TXDOWL_UART0_RXD

OWL_SWD_TMS1OWL_SWD_TMS0

OWL_SPI_SCLKOWL_SPI_MOSIOWL_SPI_MISO

OWL_I2S_MCKOWL_I2S_LRCK

OWL_I2S_DINOWL_I2S_BCLK

OWL_I2CM_SDA

OWL_FUNC_9OWL_FUNC_8

OWL_FUNC_2

OWL_FUNC_0

CFSB_AOP

AWAKE_RESET*

PMGR_SCLK0PMGR_SSCLK1

RT_CLK32768

HOLD_KEY*

MENU_KEY*

SKEY*

AWAKE_REQ

PMGR_MISOPMGR_MOSI

OWL_FUNC_4OWL_FUNC_5OWL_FUNC_6OWL_FUNC_7

OWL_SWD_TCK_OUT

SWD_TMS3SWD_TMS2

OWL_DDR_RESET*OUT

NC

BI

OUT

IN

NC

NC

IN

IN

IN

OUT

IN

OUT

ININ

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

BI

PP

PP

PP

PP

PP

OUT

PP

PP

PP

BI

IN

IN

OUT

NCNC

INNC

NC

PP

PP

PP

PP

PP

IN

Page 10: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

SOC - CPU, GPU & SOC RAILS

0.8V @10.5A MAX

1.0V @12.5A MAX

0.625V @TBDA MAX

0.825V @4.7A MAX0.725V @TBDA MAX

0.9V @10.5A MAX

10 OF 60

11 OF 49

4.0.0

051-00648

45_BUCK1_PP_GPU_FB

PP_CPU

45_BUCK0_PP_CPU_FB

PP_CPU

45_BUCK2_PP_SOC_FB

PP_GPU

AP_SOC_SENSE_N

AP_SOC_SENSE_P

AP_GPU_SENSE_N

AP_GPU_SENSE_P

AP_CPU_SENSE_N

AP_CPU_SENSE_P

PP_SOC

PP_GPU

SOC:POWER (1/3)SYNC_MASTER=N/A SYNC_DATE=N/A

0402

ROOM=SOC

1UF20%

CERM4V

C1156

1

2

3

4

P2MM-NSMSM

ROOM=SOC

PP11051

P2MM-NSMSM

ROOM=SOC

PP11041

P2MM-NSMSM

ROOM=SOC

PP1103 1

SM

ROOM=SOCP2MM-NSMPP1102 1

P2MM-NSMSM

ROOM=SOC

PP1101 1

P2MM-NSMSM

ROOM=SOC

PP1100 1

0.50MMSM

TP11001

SM0.50MM

TP11201

SHORT-10L-0.1MM-SM

ROOM=SOC

XW11201 2 14

14

ROOM=SOC

SHORT-10L-0.1MM-SMXW1100

12

16 14

ROOM=SOC

SHORT-10L-0.1MM-SMXW1110

1 2 CRITICALROOM=SOC

FCMSP

SC58980X0B-A040

MAUI-2GB-25NM-DDR-H

OMIT_TABLE

U0600AA17AA19AA23AB14AB16AB20AB22AB24AB26AC17AC19AC23AD16AD20AD22AD24AD26

AE5AE15AE17AE19AE23AF14AF16AF20AF22AF24AF26AG17AG19AG23AH16AH20AH22AH24AH26AJ15AJ17AJ19AJ23AK14

J29G23

AK22F6

F14AL15AM5G25G27H24H26H28J27K24K26K28L27L23M26M28

AL19N7

N27P24P26P28R17R27R29T22T26

T7T28U17

V8V20V22V24V26W7

W11Y28

W23Y14Y16Y20Y22Y24Y26G29AA27F17F20L29N29V28

AJ20

L22L24L26L28M1M5M7M9M11M13M17M21M23M25M27M29M35N6N10N12N14N16N18G19N22N24N26N28N30N33P9P11P13P15P17P19P21P23P25P27P29P35R4R6R8R10R12R14M19R18R20R22R24R26R28R30T1T2R33T9T11T13T15T17P7T23T25T27T30T35U6U10U12

AK21

SC58980X0B-A040FCMSP

MAUI-2GB-25NM-DDR-H

ROOM=SOC

CRITICAL

OMIT_TABLE

U0600AA7AA9

AA11AB6

AB10AB12AC13

AD6AD8

AD10AD12

AE7AE9

AE11AE13

AF8AF10AF12AH6AH8

AH10AH12

AJ5AJ7AJ9

AJ11AJ13AK6

AK10AL7AL9

AL11AM6AM8

AM10AN7

AN11AL13

Y8Y10Y12

AM12

Y6

G15W13T12M6U9V12W9M12M18N15N21N9F10H14H16H20H22H6H8J11J13J17J19J23J7K10K14K16K20K22K6K8L11L13L15L17L19L21M24L7L9F8M8N11N13N17N19P10G11P12P14P16P20R15R19G13R9T10T14T16U11V14V16G7R23G9H10T24P22W17N23G17G21T18T20

G20

Y7 H19

20%

ROOM=SOC0201

2.2UF6.3VX5R-CERM

C11221

2 6.3V

2.2UF20%

ROOM=SOC

X5R-CERM0201

C11231

2

6.3V

ROOM=SOC

X5R-CERM0201

20%2.2UFC11031

2

X5R-CERM

ROOM=SOC0201

6.3V

2.2UF20%

C11251

2

2.2UF

ROOM=SOC

X5R-CERM0201

6.3V20%

C11051

2X5R-CERM6.3V20%

ROOM=SOC0201

2.2UFC11041

2

6.3V20%

0.47UF

0402CERM

ROOM=SOC

C1157

1

2

3

4

ROOM=SOC

1UF20%4V

0402CERM

C1154

1

2

3

4

4V

0402

ROOM=SOC

1UF20%

CERM

C1155

1

2

3

4

ROOM=SOC

0402

4VCERM

4.3UF20%

C1153

1

2

3

4

6.3V

ROOM=SOC

CERM-X5R20%10UF

0402-9

C11501

2 CERM-X5R20%

0402-9

6.3V10UF

ROOM=SOC

C11511

2

0402CERM

ROOM=SOC

4V

1UF20%

C1134

1

2

3

4

ROOM=SOC

4VCERM

1UF

0402

20%

C1135

1

2

3

4

0402

ROOM=SOC

CERM

1UF20%4V

C1136

1

2

3

4

0402

4VCERM

1UF20%

ROOM=SOC

C1137

1

2

3

4

ROOM=SOC

4VCERM0402

20%4.3UF

C1130

1

2

3

4

4V

0402CERM

4.3UF

ROOM=SOC

20%

C1131

1

2

3

4

0402

4VCERM

4.3UF

ROOM=SOC

20%

C1110

1

2

3

4

4V

0402

4.3UF

CERM

ROOM=SOC

20%

C1111

1

2

3

4

0.47UF6.3V

ROOM=SOC

CERM

20%

0402

C1117

1

2

3

4

CERM

0.47UF6.3V20%

0402

ROOM=SOC

C1116

1

2

3

4

20%

ROOM=SOC

1UF

CERM4V

0402

C1113

1

2

3

4

CERM

1UF4V

0402

ROOM=SOC

20%

C1112

1

2

3

4

ROOM=SOC

1UF4V20%

CERM0402

C1114

1

2

3

4

20%

ROOM=SOC

CERM4V

0402

4.3UFC1106

1

2

3

4

0402-9ROOM=SOC

6.3VCERM-X5R20%10UFC11001

2

0402CERM4V20%1UF

ROOM=SOC

C1115

1

2

3

4

4V

0402CERM

ROOM=SOC

4.3UF20%

C1107

1

2

3

4

0402CERM4V

ROOM=SOC

4.3UF20%

C1108

1

2

3

4

4V

4.3UF

0402CERM

20%

ROOM=SOC

C1109

1

2

3

4

10UF20%6.3V

ROOM=SOC

CERM-X5R0402-9

C11011

2

10UF

CERM-X5R0402-9

6.3V

ROOM=SOC

20%

C11201

20402-9ROOM=SOC

10UF6.3V20%CERM-X5R

C11211

2

4.3UF4V

0402CERM

ROOM=SOC

20%

C1126

1

2

3

4

ROOM=SOC

4V

0402

20%4.3UF

CERM

C1127

1

2

3

4

ROOM=SOC

4.3UF4V

0402CERM

20%

C1128

1

2

3

4

4V

0402

ROOM=SOC

CERM

4.3UF20%

C1129

1

2

3

4

0.47UF

CERM0402

ROOM=SOC

6.3V20%

C1138

1

2

3

4

CERM

0.47UF

0402

ROOM=SOC

6.3V20%

C1139

1

2

3

4

0.47UF

0402CERM

ROOM=SOC

6.3V20%

C1140

1

2

3

4

0402CERM

ROOM=SOC

6.3V20%

0.47UFC1141

1

2

3

4

4VCERM

4.3UF

ROOM=SOC

20%

0402

C1132

1

2

3

4

ROOM=SOC

0402

4VCERM

4.3UF20%

C1133

1

2

3

4

14 10

14 10

14 10

14

14 10

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

PP

PP

PP

PP

PP

PP

PP

OUT

OUT

OUT

SYM 9 OF 14

VSS

VDD_SOC

VDD_SOC_SENSE

VSS_SOC_SENSE

VDD_SOC

SYM 8 OF 14

VSS_CPU_SENSE

VDD_CPU_SENSE

VDD_GPU

VDD_GPU_SENSE

VSS_GPU_SENSE

VDD_CPU

Page 11: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

SOC - POWER SUPPLIES

1.0V @1.0A MAX

0.8V @TBDA MAX

0.756-TBDV @44mA MAX

1.06 - 1.17V

0.8V @0.5A MAX

DDR IMPEDANCE CONTROL

INTERNALLY SUPPLIES VDDQ

0.802-TBDV @1.1A MAX

1.1V @7mA MAX

1.06 - 1.17V @635mA MAX

0.9V @TBDA MAX

11 OF 60

12 OF 49

4.0.0

051-00648

45_PP1V1_DDR_PLL

PP_GPU_SRAM

PP_FIXED

PMU_TO_OWL_SLEEP1_READY

PP_CPU_SRAM

PP1V1

PP1V1_SDRAM

SYSTEM_ALIVE

PP1V1

PP1V1

PP0V8_OWL

45_DDR0_ZQ

45_DDR3_RREF45_DDR2_RREF

45_DDR0_RREF

45_DDR3_ZQ

45_DDR1_RREF

SOC:POWER (2/3)SYNC_MASTER=N/A SYNC_DATE=N/A

6.3V20%X5R

ROOM=SOC0201-1

1.0UFC12491

2

ROOM=SOC0201-1X5R6.3V20%1.0UFC12471

2

4.3UF

CERM4V

0402

20%

ROOM=SOC

C1228

1

2

3

4

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C12441

2

ROOM=SOC

6.3VX5R-CERM0201

2.2UF20%

C12481

2

100OHM-25%-0.12A

01005ROOM=SOC

FL12801 2

17 16 13

20%

X5R01005-1

0.22UF

ROOM=SOC

6.3V

C12801

2

CRITICAL

FCMSP

SC58980X0B-A040

MAUI-2GB-25NM-DDR-H

OMIT_TABLE

ROOM=SOC

U0600

C18

C21

C19

B21

AP15

AP17

AP16

Y31

V31

W32

U4

P5

T3

P2

A20A22B11B15B23B25D16D20D22E15E17E19E21

AN19AR18AR21

AR8AT13AT16AM14AM16AM18AM20AR15AN13AN15

AB29V29Y29Y35

AB35AG34

M34R35T29T34

AA30U30

AC30

AA1AC2

V6W2H2M2U5P6T6U1N5R5W5

F19AK18W26P8

D19AN17W31T4

CRITICALROOM=SOC

FCMSPSC58980X0B-A040

MAUI-2GB-25NM-DDR-H

OMIT_TABLE

U0600 AC11AC7AC9AA13AG11AG7AG9AK12

AA15AA21AA25AB18AC15AC21AC25AD14AD18AE21AE25AF18AG15AG21AH25AH14AH18AJ21AK16

F12G10V18

AL17J25L25N25R25

R7AN6U25W15W21W25Y18F21F26

AB28AC27

G18AK20

F16R16

T8V7

U19W27U27AF4

AF27U21

H12H18R21U15J15J21J9K12K18M10M14M16M20P18R11R13U13V10M22

AH29AD29AF29

20%2.2UF

X5R-CERM6.3V

ROOM=SOC0201

C12271

2

6.3V

0201

20%2.2UF

X5R-CERM

ROOM=SOC

C12231

2

ROOM=SOC

6.3V

2.2UF20%

X5R-CERM0201

C12431

2

1.0UF

0201-1

6.3V

ROOM=SOC

X5R20%

C12501

2

20%

0201ROOM=SOC

6.3VX5R-CERM

2.2UFC12421

220%2.2UF

0201ROOM=SOC

6.3VX5R-CERM

C12411

2ROOM=SOC

1/32W1%

01005MF

240R12041

2 ROOM=SOC

240

MF01005

1/32W1%

R12051

2

16 9

6.3VCERM0402

ROOM=SOC

0.47UF20%

C1220

1

2

3

4

1UF

CERM0402

4V20%

ROOM=SOC

C1221

1

2

3

4

4.3UF20%

0402

ROOM=SOC

4VCERM

C1222

1

2

3

4

4.3UF

ROOM=SOC

20%

0402

4VCERM

C1226

1

2

3

4

0402CERM4V

1UF

ROOM=SOC

20%

C1225

1

2

3

4

0.47UF6.3VCERM

ROOM=SOC

0402

20%

C1224

1

2

3

4

0402

6.3V

ROOM=SOC

CERM

0.47UF20%

C1203

1

2

3

4

4V

0402CERM

ROOM=SOC

1UF20%

C1202

1

2

3

4

ROOM=SOC

20%

CERM0402

4V

4.3UFC1245

1

2

3

4

6.3VCERM-X5R

10UF

0402-9

20%

ROOM=SOC

C12401

2

ROOM=SOC

CERM

20%4V

1UF

0402

C1246

1

2

3

4

ROOM=SOC

240

MF01005

1/32W1%

R12031

2

1/32W1%

MF

240

01005ROOM=SOC

R12021

2ROOM=SOC01005MF1/32W

2401%

R12011

2

1%

ROOM=SOC

1/32W

240

01005MF

R12001

2

6.3V

0402-9CERM-X5R

10UF

ROOM=SOC

20%

C12001

24.3UF

CERM4V

ROOM=SOC

0402

20%

C1201

1

2

3

4

14

14 7 6 14

14 11

15 14 12

14 11

14 11

15

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

SYM 11 OF 14

DDR0_RET*

DDR3_ZQDDR0_ZQ

DDR2_RET*

VDDIO11_DDR3

VDDIO11_DDR2

VDDIO11_DDR1

VDDIO11_DDR0

DDR1_SYS_ALIVE

DDR3_SYS_ALIVEDDR2_SYS_ALIVE

DDR0_SYS_ALIVE

VDDIO11_RET_DDR

VDDIO11_PLL_DDR

DDR0_RREFDDR1_RREFDDR2_RREFDDR3_RREF

DDR1_RET*

DDR3_RET*

SYM 10 OF 14

VDD_CPU_SRAM

VDD_GPU_SRAM

VDD_FIXED

VDD_LOW

IN

Page 12: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

SOC - POWER SUPPLIES

VDD18_TSADC:1.645-1.89V @2mA MAX

VDD18_UVD :1.62-1.98V @5mA MAXVDD18_FMON :1.62-1.98V @1mA MAX

(AON)

(OWL)

1.62-1.98V @1mA MAX

VDDIO18_GRP10:1.62-1.98V @8mA MAX

VDD18_AMUX :1.62-1.98V @1mA MAX

VDDIO18_LPOSC:1.62-1.98V @1mA MAX

1.62-1.98V @41mA MAX

1.06-1.17V @1.3A(TBD) MAX

1.70-1.95V @100mA(TBD) MAX

12 OF 60

13 OF 49

4.0.0

051-00648

PP1V8_SDRAM

PP1V8

PP1V8_IMU_OWL

PP1V8_ALWAYS

PP1V8

PP1V1_SDRAM

SYNC_DATE=N/ASYNC_MASTER=N/A

SOC:POWER (3/3)

FCMSP

SC58980X0B-A040

CRITICALROOM=SOC

OMIT_TABLE

MAUI-2GB-25NM-DDR-HU0600AN12

AN14AN18AN29AN33

AP2AP13AP14AP20AP25AP26AP27AP30AP31AP32AP33AR1AR5AR9

AR14AR16AR25AR34AR35

AT1AT2AT6AT8AT9

AT14AT17AT18AT21AT25AT34AT35

B1B2

B16B20B22B24B27B34B35C2C3C4C5C6C7C8C9

C10C11C12C13C14C20C22C23C24C25C26C27C28C29C30C31C32C33

D3D4D5D6

D11D17D21D23D26D27D28D29D30

E1E3E4E5D7E9

E12E16E18E20E22E24E26E29E32F4F5F7F9F11F13F15F18D18F23E30F25F27F28F29G4G5G6G8G12G14G16E6G22G24G26G28G33H1H7H9H11H13H15H17E28H21H23H25H27H29J2J5J6J30J8J10J12J14J16J18J20J22J24J26J28K7K9K11K13K15K17K19K21K23K25K27K29K34K35L1L5L6K4L8L10L12L14L16L18L20

FCMSPSC58980X0B-A040

ROOM=SOC

CRITICAL

OMIT_TABLE

MAUI-2GB-25NM-DDR-HU0600A1

A2A11A16A21A24A25A27A34A35AA6AA8

AA10AA12AA14AA16AA18AA20AA22AA24AA26

N8AA28AA35

AB1C17AB3AB5AB7AB9

AB11AB13AB15AB17AB19AB21AB23AB25AB27AB30AC1AC6AC8

AC10AC12AC14AC16AC18AC20AC22AC24AC26

T5AC28AC34AC35

AD5AD7AD9

AD11AD15AD17AD19AD21AD23AD25AD27AD33

AE6AE8

AE10AE12AE14AE16AE18AE20AE22AE24AE26AE29AE30AE35

AF5AF7AF9

AF11AF15AF17AF19AF21

AF23AF25AF30AG1AG2AG3AG6AG8AG10AG14AG16AG18AG20AG22AG24U7AG29AG33AG35AH5AH7AH9AH11AH13AH15AH17AH19AH21AH23AH27AJ6AJ8AJ10AJ12AJ14AJ16AJ18W8AJ22AG12AK24AJ28AK2AK3AK5AK7AK9AK11AK13AK15B28AK17M15AP28AK26AK30AK34AK29AL6AL8AL10AL12AF28AL14AM29AL16AR27AL18Y30AL20AL25AL28AL30AL31AM7AM9AM11AM13AM15AM17AM19AM21AM33AM34AM35AN3AN5AN16AN8AN10

FCMSP

ROOM=SOC

SC58980X0B-A040

MAUI-2GB-25NM-DDR-H

CRITICAL

OMIT_TABLE

U0600A10A26AD1

AH35AT22

AT7G1

L35

A15A23

AB34AD2

AH34AR13AR17AR22

AR7AT15

B10B26G2

L34N2R1

U34V2

W35

AN24

AM22AG26

AG13AK8AB8N20U23

AK23

AD13

F30H30K30M30N31P30H5K5

AN9AA5AC5AG5AL5

AM23AE28AG28

Y5

U14U16U18U22U24U26U28U35V1V5AA29U29V9V11V13V15V17V19V21V23V25V27W30W1W6W10W12W14W16W18W20W22W24W28W29W34Y1Y9Y11Y13Y15Y17Y19Y21Y23Y25Y27Y34AC29AD28AE27AG27AJ30AJ35AK19AT27D31G30L30P4U8V30A28AL32T21

20%2.2UF

ROOM=SOC

X5R-CERM0201

6.3V

C13141

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13001

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13301

2

2.2UF

ROOM=SOC

X5R-CERM6.3V

0201

20%

C13131

2

2.2UF

ROOM=SOC

X5R-CERM0201

6.3V20%

C13121

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13231

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13221

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13211

2

0201

2.2UF

ROOM=SOC

X5R-CERM6.3V20%

C13021

2

ROOM=SOC

X5R-CERM0201

6.3V

2.2UF20%

C13011

2

ROOM=SOC

CERM0402

1UF4V20%

C1316

1

2

3

4

ROOM=SOC

CERM

1UF

0402

4V20%

C1317

1

2

3

4

10UF

ROOM=SOC

CERM-X5R6.3V20%

0402-9

C13101

2

CERM-X5R

10UF

ROOM=SOC0402-9

6.3V20%

C13201

2

33 30 26 24 17 16 15 14 8

2928 21 20 14 13 12 9 8 7 6 5 3

19 14

17 15 8

2928 21 20 14 13 12 9 8 7 6 5 3

15 14 11

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 14 OF 14

VSS VSS

SYM 13 OF 14

VSSVSS

SYM 12 OF 14

VDDIO18_GRP4

VDD18_AMUXVDD18_UVDVDD18_FMON

VDD18_TSADC

VDD18_LPOSC

VDDIO18_GRP11

VDDIO18_GRP10

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

VDD2

VDD1

VSS

Page 13: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

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PCIE RECEIVE-SIDE PROBE POINTS

S3E NAND

13 OF 60

15 OF 49

4.0.0

051-00648

PP0V9_NAND

PP1V8_NAND_AVDD

90_PCIE_NAND_TO_AP_RXD1_N

AP_TO_NAND_RESET_L

45_NAND_ZQ

NAND_AGND

90_PCIE_NAND_TO_AP_RXD0_N

90_PCIE_NAND_TO_AP_RXD1_P

AP_TO_NAND_SYS_CLK

90_PCIE_AP_TO_NAND_TXD1_P

SWD_AP_PERIPHERAL_SWCLK

SWD_AP_BI_NAND_SWDIO

AP_TO_NAND_FW_STRAP

SYSTEM_ALIVE

PCIE_AP_TO_NAND_RESET_L

NAND_AGND

90_PCIE_AP_TO_NAND_TXD1_N

PCIE_NAND_TO_AP_CLKREQ_L

90_PCIE_NAND_TO_AP_RXD0_P

90_PCIE_AP_TO_NAND_TXD0_N90_PCIE_AP_TO_NAND_TXD0_P

PP1V8

PMU_TO_NAND_LOW_BATT_BOOT_LNAND_VREF

90_PCIE_AP_TO_NAND_TXD0_N90_PCIE_AP_TO_NAND_TXD0_P

90_PCIE_AP_TO_NAND_TXD1_N90_PCIE_AP_TO_NAND_TXD1_P

90_PCIE_AP_TO_NAND_REFCLK_N90_PCIE_AP_TO_NAND_REFCLK_P

45_PCIE_NAND_RESREF

90_PCIE_AP_TO_NAND_REFCLK_N90_PCIE_AP_TO_NAND_REFCLK_P

PP3V0_NAND

PP1V8

SWD_AP_BI_NAND_SWDIO_R

SWD_AP_NAND_SWCLK_R

SYNC_DATE=N/A

NANDSYNC_MASTER=N/A

ROOM=NANDP3MM-NSM

SM PP15201

ROOM=NANDP3MM-NSM

SM

PP15211

SM

ROOM=NANDP3MM-NSM

PP15041

SMP3MM-NSMROOM=NAND

PP15051

SMP3MM-NSMROOM=NAND

PP15021

SM

ROOM=NANDP3MM-NSM

PP15031

ROOM=NANDP3MM-NSM

SM PP15001

ROOM=NANDP3MM-NSM

SM

PP15011

2.2UF6.3VX5R-CERM0201

20%

ROOM=NAND

C15281

2

2.2UF

X5R-CERM

20%6.3V

0201ROOM=NAND

C15271

2

15UF

0402-1

6.3VX5R

20%

ROOM=NAND

C15051

2

100PF

NP0-C0G

ROOM=NAND

5%16V

01005

C15101

2

100PF

NP0-C0G

ROOM=NAND

5%

01005

16V

C15091

2

ROOM=NAND

NP0-C0G01005

16V5%100PFC15261

2 6.3V

15UF20%

0402-1ROOM=NAND

X5R

C15231

2

ROOM=NAND

15UF20%6.3V

0402-1X5R

C15461

2

ROOM=NAND0402-1

6.3V20%15UF

X5R

C15481

2

15UF

0402-1

6.3VX5R

20%

ROOM=NAND

C15041

20402-1

6.3VX5R

20%15UF

ROOM=NAND

C15061

2

ROOM=NAND

THGBX5G7D2KLFXGWLGA

BOMOPTION=OMIT_TABLE

CRITICAL

U1500

C3

D2

D4

H4

G3J3H2E3E7F6C7B8

G1

F4

C5

G5

M4

J5 J7

M6

K4 K6

G9

H6H8

K8M8

N3N5

N7P8

K2M2

F8

D8

OA0

OA1

0O

D0O

D10

OG

0O

G10

A3 A7 F2 J1 J9 R3 R7 A5 OB0

OB1

0O

F0O

F10

R5E5

B4 B6 G7 L3 L5 L7

OC0

OC1

0O

E0

OE1

0 P2 P4 P6B2

D6

5%16V

100PF

01005NP0-C0G

ROOM=NAND

C15251

2

33 9 0.00

01005ROOM=NAND

1/32WMF0%

R15211 2

9

1/32W0%

0.00MF 01005

ROOM=NAND

R15201 2

ROOM=NAND01005

10%6.3VX5R

0.01UFC15611

2

01005ROOM=NAND

0.01UF10%6.3VX5R

C15601

2

01005

10K

MF

1%

ROOM=NANDNOSTUFF

1/32W

R15611

2

ROOM=NAND01005MF1/32W1%10K

NOSTUFFR15601

2

2.2UF20%6.3V

0201ROOM=NAND

X5R-CERM

C15301

2

1000PF10%6.3VX5R-CERM

ROOM=NAND01005

C15541

2

MF1/32W0.5%

ROOM=NAND

34.8

01005

R15001

2

X5R

ROOM=NAND

20%6.3V

0402-1

15UFC15031

26.3V

ROOM=NAND0402-1X5R

20%15UFC15021

220%15UF

ROOM=NAND

6.3VX5R0402-1

C15011

2

15UF

0402-1

6.3VX5R

20%

ROOM=NAND

C15001

2

20%15UF

ROOM=NAND

6.3VX5R0402-1

C15411

2

ROOM=NAND

15UF

0402-1

6.3VX5R

20%

C15401

2

ROOM=NAND0402-1X5R

15UF6.3V20%

C15211

20402-1ROOM=NAND

6.3V

15UF20%

X5R

C15201

2

0.1UF

01005X5R-CERM6.3V20%

ROOM=NAND

C15311

2

MF

1%

24.9

01005ROOM=NAND

1/32W

R15301 2

16VNP0-C0G01005ROOM=NAND

100PF5%

C15081

2

100PF5%16VNP0-C0G

ROOM=NAND01005

C15071

2

ROOM=NAND

X5R-CERM

20%6.3V

0.1UF

01005

C15241

26.3V20%10UF

CERM-X5R

ROOM=NAND0402-9

C15221

2

ROOM=NAND

0.1UF

01005X5R-CERM6.3V20%

C15511

26.3VX5R-CERM01005

20%

ROOM=NAND

0.1UFC15501

2

CERM-X5R0402-9ROOM=NAND

20%10UF6.3V

C15421

2

10UF6.3V20%

ROOM=NAND

CERM-X5R0402-9

C15431

2

17 16 11

16

8

8

6

5

6

6

6

6

6

13 6

13 6

13 6

13 6

13 6

13 6

201MF

3.01K1%1/20W

ROOM=NAND

R15011

2

15

13

13

2928 21 20 14 13 12 9 8 7 6 5 3

13 6

13 6

13 6

13 6

13 6

13 6

15

2928 21 20 14 13 12 9 8 7 6 5 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PP

PP

PP

PP

PP

PP

PP

PP

VER-1

PCI_

AVDD

_CLK

1PC

I_AV

DD_C

LK2

CLK_IN

PCIE_REFCLK_PPCIE_REFCLK_M

PCI_

VDD1

PCI_

VDD2

VREF

VDDI

OVD

DIO

VDDI

OVD

DIO

VDDI

O

VCC

VDDI

O

VCC

VCC

VCC

VCC

VCC

AVDD

1

VDD

VDD

VDD

VDD

VDD

VDD

VDD

EXT_ALE

EXT_CLE

EXT_RNB

EXT_NWE

EXT_NRE

EXT_NCE

EXT_D7EXT_D6EXT_D5EXT_D4EXT_D3EXT_D2EXT_D1EXT_D0

VSSA

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

ZQ

PCIE_RX1_P

PCI_RESREF

PCIE_RX0_MPCIE_RX0_P

VSS

VSS

PCIE_TX0_MPCIE_TX0_P

PCIE_RX1_M

RESET*

TRST*

PCIE_CLKREQ*

PCIE_TX1_PPCIE_TX1_M

PCI_

AVDD

_H

IN

BI

NC

NC

NC

NCNCNCNCNC

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

Page 14: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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ANTIGUA PMU - Buck Supplies

REMOVED FOR N69

0.70V/0.80V/0.9V

BUCK1

2X 15UF BULK CAPSREMOVED FOR N69

10.5A MAX

0.625V/0.9V/1.03V

4.7A MAXBUCK3

BUCK

81.1A MAX

BUCK

6

0.80V/0.90V/1.0V

1.5A MAXBUCK2

1.1A MAX

BUCK

5400mA MAX

BUCK

71.1A MAX 0.80V/0.90V/1.0V

BUCK44.7A MAX

0.725V/0.825V

12.5A MAXBUCK0

4TH PHASE INDUCTOR

14 OF 60

VOLTAGE=1.1V

VOLTAGE=1.8V

VOLTAGE=1.8V

VOLTAGE=1.8V

VOLTAGE=1.8V

VOLTAGE=1.1V

VOLTAGE=1.0V

VOLTAGE=1.0V

VOLTAGE=1.2V

VOLTAGE=0.825V

VOLTAGE=0.9V

VOLTAGE=1.03V

VOLTAGE=0.85V

20 OF 49

4.0.0

051-00648

PP1V1_SDRAM

PP1V8_SDRAM

PP1V8_IMU_OWLPP1V8_TOUCH

PP1V8

PP1V1

PP_CPU_SRAM

PP_GPU_SRAM

PP_VCC_MAIN

BUCK1_LX2

BUCK0_LX2

BUCK1_LX1

45_BUCK1_PP_GPU_FB

BUCK2_LX0

BUCK1_LX0

45_BUCK2_PP_SOC_FB

45_BUCK8_FB

45_BUCK7_FB

BUCK8_LX0

45_BUCK6_FB

45_BUCK5_FB

45_BUCK4_FB

BUCK4_LX0

BUCK4_LX1

45_BUCK3_FB

BUCK2_LX1

VCC_MAIN_SNS

BUCK5_LX0

BUCK6_LX0

BUCK7_LX0

BUCK3_LX0

BUCK0_LX1

45_BUCK0_PP_CPU_FB

BUCK0_LX3

BUCK0_LX0

PP1V2_CAMERA

PP_SOC

PP_GPU

PP_CPU

PP_FIXED

SYNC_MASTER=N/A

SYSTEM POWER:PMU (1/3)SYNC_DATE=N/A

0.47UH-20%-3.8A-0.048OHM

PIQA20121T-SM

CRITICALROOM=PMU

L200312

10UF20%CERM-X5R0402-9ROOM=SOC

VOLTAGE=6.3V

C20951

2

CRITICALROOM=PMU

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHML2012

12

1.0UH-20%-3.6A-0.060OHM

CRITICALROOM=PMU

PIQA20161T-SM

L200212

NP0-C0G01005

100PF5%

ROOM=PMU

VOLTAGE=16V

C20621

2

15

ROOM=PMU

CSP

CRITICALOMIT_TABLE

ANTIGUA-D2255A080U2000

F8

A3B3C3

A5B5C5

A7B7C7

A9B9C9

F12

A17B17C17

A15B15C15

A13B13C13

A11B11C11

J14

H17H18H19

K17K18K19

V19

R18R19

U18V18Y18Z18

U16U15

T9

V11Y11Z11

V13Y13Z13

V16Y16Z16

M13

M17M18M19

J5

H1H2

C1

F1F2

C19

F17F18F19

U17V17Y17Z17

V15Y15Z15

A4B4C4

A8B8C8

A16B16C16

A12B12C12

J17J18J19

T18T19

V12Y12Z12

N17N18N19

J1J2

E1E2

E17E18E19

F10

L5L13

R6

R8L4

V3

ROOM=PMU

NP0-C0G

100PF

01005

5%VOLTAGE=16V

C20441

20.47UH-20%-3.8A-0.048OHM

PIQA20121T-SMROOM=PMUCRITICAL

L20411 2

PIQA20121T-SMROOM=PMU

CRITICAL

0.47UH-20%-3.8A-0.048OHML2021

1 2

ROOM=PMUCRITICAL

0.47UH-20%-3.8A-0.048OHM

PIQA20121T-SM

L20111 2

CRITICALROOM=PMU

PIQA20121T-SM

0.47UH-20%-3.8A-0.048OHML2001

1 2

ROOM=PMU

1.0UH-20%-2.25A-0.15OHM

CRITICALPIXB2016FE-SM

L208012

1.0UH-20%-2.25A-0.15OHM

CRITICAL

PIXB2016FE-SMROOM=PMU

L207012

ROOM=PMU

CRITICAL

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHML2050

12

PIQA20161T-SMROOM=PMU

CRITICAL

1.0UH-20%-3.6A-0.060OHML2040

1 2

CRITICALROOM=PMU

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHML2030

1 2

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHM

ROOM=PMUCRITICAL

L20201 2

1.0UH-20%-3.6A-0.060OHM

ROOM=PMUPIQA20161T-SM

CRITICAL

L20101 2

CRITICALROOM=PMU

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHML2000

1 2

21

X5R-CERM

2.2UF

ROOM=PMU0201

20%VOLTAGE=6.3V

C20941

2X5R-CERM0201

2.2UF20%

ROOM=PMU

VOLTAGE=6.3V

C20931

2

X5R-CERM

2.2UF20%

ROOM=PMU0201

VOLTAGE=6.3V

C20921

2

ROOM=PMU

X5R-CERM0201

2.2UF20%VOLTAGE=6.3V

C20911

20201ROOM=PMU

X5R-CERM

20%2.2UFVOLTAGE=6.3V

C20901

2

2.2UF

0201

20%

X5R-CERM

ROOM=PMU

VOLTAGE=6.3V

C20891

2

5%100PF

ROOM=PMU

NP0-C0G01005

VOLTAGE=16V

C20321

2

0402-1

15UF

ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20811

2

ROOM=PMU0402-1X5R

20%15UFVOLTAGE=6.3V

C20711

2

20%

X5R

15UF

ROOM=PMU0402-1

VOLTAGE=6.3V

C20611

2

15UF

0402-1ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20511

2

0402-1

15UF

ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20801

2

0402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20701

2

20%

X5R0402-1ROOM=PMU

15UFVOLTAGE=6.3V

C20601

2

ROOM=PMU

15UF

0402-1X5R

20%VOLTAGE=6.3V

C20501

2

0402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20431

2

15UF

ROOM=PMU0402-1X5R

20%VOLTAGE=6.3V

C20421

20402-1

15UF

ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20411

220%

0402-1ROOM=PMU

X5R

15UFVOLTAGE=6.3V

C20401

2

ROOM=PMU0402-1

15UF

X5R

20%VOLTAGE=6.3V

C20311

20402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20301

2

15UF

ROOM=PMU0402-1X5R

20%VOLTAGE=6.3V

C20261

20402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20251

20402-1

15UF

ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20241

20402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20231

20402-1ROOM=PMU

X5R

20%15UFVOLTAGE=6.3V

C20221

2

15UF

0402-1ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20191

2

ROOM=PMU

X5R

20%15UF

0402-1

VOLTAGE=6.3V

C20181

20402-1

20%

ROOM=PMU

15UF

X5RVOLTAGE=6.3V

C20171

2

ROOM=PMU0402-1X5R

20%15UFVOLTAGE=6.3V

C20161

220%15UF

0402-1ROOM=PMU

X5RVOLTAGE=6.3V

C20151

20402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20141

20402-1X5R

ROOM=PMU

20%15UFVOLTAGE=6.3V

C20131

2X5R

ROOM=PMU0402-1

20%15UFVOLTAGE=6.3V

C20121

2

15UF

0402-1ROOM=PMU

X5R

20%VOLTAGE=6.3V

C20111

2

ROOM=PMU

15UF

0402-1X5R

20%VOLTAGE=6.3V

C20101

2X5R

ROOM=PMU0402-1

15UF20%VOLTAGE=6.3V

C20091

2

15UF

ROOM=PMU0402-1X5R

20%VOLTAGE=6.3V

C20081

2

15UF20%

X5R0402-1ROOM=PMU

VOLTAGE=6.3V

C20071

20402-1ROOM=PMU

20%

X5R

15UFVOLTAGE=6.3V

C20061

2

X5R

ROOM=PMU

15UF20%VOLTAGE=6.3V

0402-1

C20051

20402-1ROOM=PMU

15UF

X5R

20%VOLTAGE=6.3V

C20041

2

ROOM=PMU0402-1

15UF

X5R

20%VOLTAGE=6.3V

C20031

2

15UF

ROOM=PMU0402-1X5R

20%VOLTAGE=6.3V

C20021

2

15UF

ROOM=PMU0402-1X5R

20%VOLTAGE=6.3V

C20011

2

01005

5%

NP0-C0G

100PF

ROOM=PMU

VOLTAGE=16V

C20991

2

10

CERM-X5R

10UF

ROOM=PMU0402-9

20%VOLTAGE=6.3V

C20881

2

ROOM=PMU

SHORT-10L-0.1MM-SMXW2080

12

SHORT-10L-0.1MM-SM

ROOM=PMU

XW207012

ROOM=PMU

SHORT-10L-0.1MM-SMXW2050

12

16 10

10

0603ROOM=PMU

CRITICAL

1UH-20%-1.2A-0.320OHML2060

12

SHORT-10L-0.1MM-SM

ROOM=PMU

XW20301 2

SHORT-10L-0.1MM-SM

ROOM=PMU

XW20401 2

CERM-X5R0402-9

10UF

ROOM=PMU

20%VOLTAGE=6.3V

C20871

2

ROOM=PMU

CERM-X5R0402-9

10UF20%VOLTAGE=6.3V

C20861

2

10UF20%

0402-9CERM-X5R

ROOM=PMU

VOLTAGE=6.3V

C20851

2

15UF

0402-1X5R

20%

ROOM=PMU

VOLTAGE=6.3V

C20001

2

15 12 11

33 30 26 24 17 16 15 12 8

19 12

29

29 28 21 20 13 12 9 8 7 6 5 3

11

11

11

33 26 25 24 22 21 17 15

21

10

10

10

11 7 6

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NCNCNC

IN

BU

CK

INP

UT

BA

T/U

SB

SYM 2 OF 5

BUCK0_LX1

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

VBUCK3_SW

BUCK2_FB

BUCK3_FB

BUCK3_LX0

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK1_01

VDD_BUCK3

BUCK8_FB

BUCK8_LX0

BUCK7_LX0

BUCK7_FB

BUCK6_LX0

BUCK6_FB

BUCK5_FB

BUCK3_SW3

BUCK4_SW1

BUCK5_LX0

VDD_BUCK8

BUCK3_SW1

BUCK3_SW2

VDD_BUCK6

VDD_BUCK5

VDD_BUCK7

VDD_BUCK4

VDD_BUCK2

VDD_BUCK1_23

VBUCK4_SW

BUCK4_FB

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

BUCK4_LX0

BUCK4_LX1

BUCK1_LX1

BUCK1_LX2

BUCK1_LX3

VDD_MAIN_SNS

VDD_MAIN

BUCK0_LX0

BUCK0_LX2

IN

IN

IN

IN

Page 15: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

LDO15 (B) 1.2-2.0V

1.2-1.9V

200MA

200MA

50MA

+/-2.5%

+/-25MV

+/-2.5%

+/-2.5%

LDO2 (B) +/-2.5%

LDO#

2.5-3.3V

50mA

LDO1LDO2

ANTIGUA LDO SPECS

+/-2.5%

+/-2.5%

+/-2.5%

2.5-3.3V

2.5-3.3V

0.7-1.2V

2.5-3.3V

LDO13 (C)

LDO14 (H)

LDO8LDO7

+/-2.5%

LDO12

150mA

LDO7 (C) 2.5-3.3V

LDO12 (E)

LDO11 (C)

LDO6 (C1)

LDO8 (C)

LDO9 (C)

0.8-1.5V

2.5-3.3V

1.2-3.6V

1.8V

LDO5 (F)

LDO4 (D)

LDO3 (A)

LDO1 (A)

ADJ.RANGE

2.5-3.3V

0.7-1.2V

2.5-3.3V

ACCURACY

+/-25mV

+/-25mV

+/-25mV

+/-2.5%

+/-5%

50mA

250mA

250mA

10mA

50mA

50mA

MAX.CURRENT

1000mA

250mA

LDO9

LDO6

LDO4

LDO10 (G) 1335mA

+/-25mV

250mA

LDO11

LDO10

LDO15

VPUMP:10nF min. @ 4.6V

NOTE: T3 IS XTAL REF GND

LDO5

LDO14LDO13

LDO3

ANTIGUA PMU - LDOs

15 OF 60

VOLTAGE=3.1V

VOLTAGE=3.0V

VOLTAGE=3.3V

VOLTAGE=3.0V

VOLTAGE=3.0V

VOLTAGE=1.8V

VOLTAGE=3.3V

VOLTAGE=3.1V

VOLTAGE=1.8V

VOLTAGE=3.0V

VOLTAGE=2.5V

VOLTAGE=0.9V

VOLTAGE=1.2V

VOLTAGE=1.9V

VOLTAGE=0.8V

21 OF 49

4.0.0

051-00648

PP3V1_VIBEPP3V0_PROX_ALS

PP3V3_ACC

PP3V0_NAND

PP3V0_TRISTARPP1V8_VAPP3V3_USB

PP3V1_MESAPP1V8_ALWAYSPP3V0_PROX_IRLED

45_PMU_VPUMP

PP_VCC_MAIN

PP1V8_SDRAM RCAM_AF_FB

PP1V1_SDRAM

VCC_MAIN_SNS

45_PMU_VSS_RTC

PP2V5_RCAM_AF

PP0V9_NAND

PP1V2PP1V9_MESA

PP0V8_OWL

SYNC_DATE=N/ASYNC_MASTER=N/A

SYSTEM POWER:PMU (2/3)

ROOM=SOC

20%

01005X5R-CERM

0.1UF6.3V

C21121

2

2.2UF20%

0201ROOM=PMU

6.3VX5R-CERM

C21151

220%

0201ROOM=PMU

6.3VX5R-CERM

2.2UFC21161

2

ROOM=PMU

X5R-CERM0201

6.3V

2.2UF20%

C21111

220%2.2UF6.3V

0201X5R-CERM

ROOM=PMU

C21071

2

ROOM=PMU01005X5R-CERM

47NF20%6.3V

C21001

2

SHORT-10L-0.1MM-SMROOM=PMU

XW21001 2

ROOM=PMU0402-9CERM-X5R

10UF6.3V20%

C21201

2

14

SHORT-10L-0.1MM-SM

ROOM=PMU

XW210512

ROOM=PMU

CRITICAL

CSPANTIGUA-D2255A080

OMIT_TABLE

U2000

D10D11D12D13D14D15D16D17D18

D2D5D6D7D8D9D3

E10E11E12E13D4

E15E16

E3E4E5E7E8E9

F14F15F16

F3F4

G14G15G16

G3G4

H15H16

H3H4

J15J16J3J4K15K16L15L16M14M15M16N14N15N16P13P14P15P16P17R13R14R15R16R17T10T11T12T13T14T15T17U10U11U12U13U14U4U5U6V4V5V6

ROOM=PMU

CSP

CRITICAL

ANTIGUA-D2255A080

OMIT_TABLE

U2000

A1A10A14A18A19

A2A6B1

B10B14B18B19

B2B6

C10C14C18

C2C6D1

D19E14G1

G17G18G19

G2H7J6

K12K7

L17L18L19

L6L7

L9M8M9N10N12N13N9P10P11P18P19P5R10R11R12R9T16T3T6T8U3U9V10V14V8V9Y1Y10Y14Y19Z1Z10Z14Z19Z2

CSP

ROOM=PMU

ANTIGUA-D2255A080

CRITICALOMIT_TABLE

U2000

K2

K3

M3V2M2U1U2L2Y6Y4Y3Y9Z9R3Y5Y7N2

M1V1L1N1T1T2K1

Z6Z4Z3Y2Y8Z8R2K6Z5Z7P2

P12

U19

0201ROOM=PMU

2.2UF6.3V20%

X5R-CERM

C21091

2

X5R-CERM0201ROOM=PMU

6.3V20%2.2UFC21081

2

ROOM=PMU

X5R-CERM0201

6.3V20%

2.2UFC2131 1

2

2.2UF

ROOM=PMU

X5R-CERM0201

6.3V20%

C2132 1

2

ROOM=PMU

X5R-CERM0201

6.3V

2.2UF20%

C2130 1

2

2.2UF20%

0201

6.3VX5R-CERM

ROOM=PMU

C21131

2

ROOM=PMU

6.3VX5R-CERM

20%2.2UF

0201

C21141

2

2.2UF

X5R-CERM

ROOM=PMU

20%6.3V

0201

C21061

2

ROOM=PMU

X5R-CERM0201

6.3V

2.2UF20%

C21101

220%

ROOM=PMU

X5R-CERM0201

6.3V

2.2UFC21041

2

ROOM=PMU0201X5R-CERM

20%6.3V

2.2UFC21031

2

ROOM=PMU

X5R-CERM0201

6.3V

2.2UF20%

C21021

2

20%2.2UF6.3V

0201X5R-CERM

ROOM=PMU

C21011

2

ROOM=PMU

10UF

0402-9CERM-X5R6.3V20%

C21271

20402-9ROOM=PMU

CERM-X5R

10UF6.3V20%

C21261

2

0402-9

10UF

CERM-X5R

ROOM=PMU

6.3V20%

C21231

2

ROOM=PMU0402-9CERM-X5R

10UF6.3V20%

C21241

2

ROOM=PMU0402-9CERM-X5R

10UF6.3V20%

C21211

2

10UF20%

ROOM=PMU0402-9CERM-X5R6.3V

C21251

2

ROOM=PMU

CERM-X5R

10UF6.3V20%

0402-9

C21221

2

32

20

30

13

33 31 30 26

25 24

5

27

17 12 8

20

33 26 25 24 22 21 17 14

33 30 26 24 17 16 14 12 8

14 12 11

16

21

13

7 6 5

27

11

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

SYM 5 OF 5

NC NC

SYM 4 OF 5

VSS

SYM 1 OF 5

LDO

INP

UT

LDO

VDD_LDO2VDD_LDO4

VDD_LDO6VDD_LDO7

VDD_LDO5

VPP_OTP

VDD_BYPASSVDD_LDO15VDD_LDO14VDD_LDO13VDD_LDO11

VDD_LDO10

VDD_LDO9VDD_LDO8

VPUMP

VLDO9_FBVLDO9VLDO8VLDO7

VLDO6

VLDO5

VLDO4VLDO3VLDO2

VLDO15VLDO14VLDO13VLDO12VLDO11

VLDO10

VLDO1

VBYPASS

VDD_LDO1_3

Page 16: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m(2)

(3)

(4)

(1)

BUTTON1 + BUTTON2 ASSERTED FOR>TBD SECONDS CAUSES TWO-FINGER RESET

REAR CAMERA NTC

(1)

ANTIGUA PMU - GPIOs, NTCs

(1)

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

RADIO PA NTC

AP NTC

(1)

(1)

(3)

CONTROL PIN NOTES:

NOTE (2):INPUT PULL-DOWN 1MNOTE (3):INPUT PULL-UP OR DOWN 100k-300kNOTE (4):OUTPUT OPEN-DRAIN, REQUIRES PULL-UP

NOTE (1):INPUT PULL-DOWN 100-300k

(4)

(3)

FOREHEAD NTC

NOTE:VDROOP_DET R/C Low-pass Fc=1.06MHz(4)

16 OF 60

22 OF 49

4.0.0

051-00648

PMU_TO_BB_PMIC_RESET_R_LTRISTAR_TO_AP_INTSTOCKHOLM_TO_PMU_HOST_WAKEPMU_TO_NAND_LOW_BATT_BOOT_LWLAN_TO_PMU_HOST_WAKECODEC_TO_PMU_MIKEY_INT_LPMU_TO_BT_REG_ON

CHESTNUT_TO_PMU_ADCMUX

BUTTON_HOLD_KEY_BUFF_L

DWI_PMU_TO_PMGR_MISO

I2C0_AP_SCL

PMU_TO_AP_IRQ_L

I2C0_AP_SDA

PMU_TO_WLAN_REG_ON

PMU_TO_BB_USB_VBUS_DETECTCODEC_TO_AP_PMU_INT_LPMU_TO_CODEC_DIGLDO_PULLDN

WLAN_TO_PMU_PCIE_WAKE_L

PMU_TO_LCM_PANICB

I2C0_AP_SCL

PMU_TO_STOCKHOLM_EN

PMU_TO_BB_PMIC_RESET_L

AP_TO_PMU_AMUX_OUT

LCM_TO_CHESTNUT_PWR_ENTRISTAR_TO_PMU_USB_BRICK_IDCHESTNUT_TO_PMU_ADCMUX

PMU_VDROOP_DET_IN

BUTTON_MENU_KEY_BUFF_L

45_PMU_TO_WLAN_CLK32K

45_PMU_XTAL145_PMU_XTAL2

PA_NTC_RETURN

FOREHEAD_NTC_RETURN

AP_NTC_RETURN

PP1V8_SDRAM

45_BUCK1_PP_GPU_FB

OWL_TO_PMU_SLEEP1_REQUEST

AP_TO_PMU_SOCHOT1_L

45_PMU_VSS_RTC

PMU_VDD_RTC

45_PMU_IREFAP_TO_PMU_WDOG_RESET

OWL_TO_PMU_ACTIVE_REQUESTPMU_TO_OWL_ACTIVE_READY

PMU_VREF

BB_TO_PMU_HOST_WAKE_L

TRISTAR_TO_PMU_USB_BRICK_ID

PMU_TO_AP_SOCHOT0_L

PMU_TO_OWL_SLEEP1_READY

PMU_AMUX_BY

PMU_TO_SYSTEM_COLD_RESET_L

PMU_VDROOP_OUT

BUTTON_RINGER_A

TIGRIS_TO_PMU_INT_L

BB_TO_PMU_AMUX_SMPS4

TRISTAR_TO_PMU_HOST_RESET

OWL_TO_PMU_SHDN

PMU_TO_OWL_CLK32K

BUTTON_MENU_KEY_BUFF_L

FOREHEAD_NTC

AP_TO_PMU_TEST_CLKOUT

REAR_CAMERA_NTCRADIO_PA_NTCAP_NTC

BB_TO_PMU_AMUX_LDO11

45_PMU_TCAL

RCAM_NTC_RETURN

BT_TO_PMU_HOST_WAKE

BB_TO_PMU_AMUX_LDO5

BB_TO_PMU_AMUX_SMPS1

45_PMU_TO_WLAN_CLK32K

BUTTON_VOL_UP_L

BUTTON_VOL_DOWN_L

PMU_AMUX_AY

BUTTON_RINGER_A

45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI45_DWI_PMGR_TO_PMU_SCLK

BUTTON_HOLD_KEY_BUFF_L

SYSTEM_ALIVE

SYNC_DATE=N/ASYNC_MASTER=N/A

SYSTEM POWER:PMU (3/3)

SHORT-10L-0.1MM-SM

ROOM=PMU XW22301 2

SHORT-10L-0.1MM-SM

ROOM=PMU XW22101 2

26 16 8

16 9 8

32 8

16 9 8

26 16

30 16

0.00010050%MF

ROOM=PMU

1/32W

R22011 2

33

33

100K1/32WMF01005

5%

ROOM=PMU

R22601

2

28

33

01005ROOM=CHESTNUT

6.3V10%1000PF

X5R-CERM

C22031

2

24

ROOM=PMU

CRITICAL

1.60X1.00-SM

32.768KHZ-20PPM-12.5PFY22001 2

ANTIGUA-D2255A080

ROOM=PMU

CSP

OMIT_TABLE

CRITICAL

U2000

P4P3

R5F13G13J12H13H14K10K11K13J13

N11M12L11M10L14L12M11L10K14

T5

G6F6E6F5

F7G7J7G8H8J8K8F9G9H9J9G10H10J10F11G11H11K9J11G12H12

K5

L8

V7U8

R4

M5

K4

P7P8P9

R7

U7

T7

N8

N7N3

T4

H6

N6

M6M7N4N5

L3

P6

G5

H5

M4

P1R1

5

24 8

17 13 11

9 5 3

ROOM=PMU

6.3V10%1000PF

01005X5R-CERM

C22601

2

8

33

3

32 8

33

33 16

33

3

8

1/32WMF

ROOM=PMU01005

5%100KR22611

2

33 16

9

9

30 26 9 5

9

11 9

9

8

30

5

9

26 9

9

26 8

26 16 8

28 26

5

32 16 8

33

33

33

33

24

33

13

33

30 8

33

SHORT-10L-0.1MM-SM

ROOM=PMU XW22201 2

17

ROOM=PMU

5%

01005

1/32WMF

1.00KR2200

1 2 33

26 16

30 16

ROOM=PMU

10%

01005

1000PF

X5R10V

C22051

2

NO_XNET_CONNECTION=1

01005

ROOM=PMU150

1/32W1%MF

R22051 2

ROOM=PMU

X5R20%

0201

0.22UF6.3V

C22701

2 1/20W

ROOM=PMU

200K1%

MF201

R22701

2

14 10

ROOM=PMU

SHORT-10L-0.1MM-SMXW2200

1 2

0.22UF

0201ROOM=PMU

X5R6.3V20%

C22021

2

18PF

CERM16V

ROOM=PMU01005

5%

C22011

2

18PF5%

01005CERM16V

ROOM=PMU

C2200 1

2

32 16 8

16 9 8

16 9 8

5%100PF

01005NP0-C0G

16V

ROOM=PMU

C2240 1

25%100PF

01005NP0-C0G16V

ROOM=PMU

C22501

2

3.92K

ROOM=PMU

MF1/20W0.1%

0201

R22501

2

01005ROOM=PMU

10KOHM-1%R2240

1

2

0100510KOHM-1%

ROOM=PMU

R22301

2

0100510KOHM-1%

ROOM=PMU

R22201

2

5%100PF

01005NP0-C0G

16V

ROOM=PMU

C2210 1

2

5%100PF

01005NP0-C0G

16V

ROOM=PMU

C2220 1

2

5%100PF

01005NP0-C0G

16V

ROOM=PMU

C2230 1

2

0100510KOHM-1%

ROOM=PMU

R22101

2

SHORT-10L-0.1MM-SM

ROOM=PMU XW22401 2

33 30 26 24 17 15 14 12 8

15

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

IN

NC

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

NC

NC

NC

RE

SE

TS

RE

FS

PM

GR

AD

CB

UT

TO

NS

AM

UX

NT

CX

TA

L

SYM 3 OF 5

CO

MP

AR

AT

OR

GP

IO

VDD_RTC

XTAL2XTAL1

TDEV4TDEV3

TCAL

TDEV2TDEV1

AMUX_BYAMUX_B7AMUX_B6AMUX_B5AMUX_B4

AMUX_B2AMUX_B3

AMUX_B0AMUX_B1

AMUX_A7AMUX_A6

AMUX_AY

AMUX_A4AMUX_A5

AMUX_A1AMUX_A2AMUX_A3

AMUX_A0

GPIO21GPIO20GPIO19

GPIO17GPIO18

GPIO16GPIO15GPIO14GPIO13GPIO12GPIO11GPIO10

GPIO9GPIO8GPIO7GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1

BUTTON4BUTTON3BUTTON2BUTTON1

BRICK_IDADC_IN

SCLKMOSIMISO

IRQ*

SCLSDA

TMPR_DET

SYS_ALIVE

OUT_32KSLEEP_32K

ACTIVE_RDYACTIVE_REQSLEEP1_RDYSLEEP1_REQ

RESET*SHDN

RESET_IN2RESET_IN3

RESET_IN1

PRE_UVLO

VDROOP

VDROOP_DET

VREF

IREF

IN

IN

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

BI

IN

IN

IN

IN

NC

OUT

OUT

IN

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

Page 17: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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m

APN:343S00033

TIGRIS CHARGER

17 OF 60

VOLTAGE=4.3V

23 OF 49

4.0.0

051-00648

VBATT_SENSE

TIGRIS_BUCK_LX

TIGRIS_LDO

PP_BATT_VCC

SWI_AP_BI_TIGRISTIGRIS_TO_BATTERY_SWI_1V8

TIGRIS_ACTIVE_DIODE

TIGRIS_TO_BATTERY_SWI_1V8TIGRIS_TO_BATTERY_SWI_1V8_RTIGRIS_TO_BATTERY_SWI

PP1V8_SDRAM

TIGRIS_PMID

SYSTEM_ALIVE

TRISTAR_TO_TIGRIS_VBUS_OFF

TIGRIS_TO_PMU_INT_R_L

TIGRIS_VBUS_DETECT

TIGRIS_TO_PMU_INT_L

USB_VBUS_DETECT

PP1V8_ALWAYS

I2C1_AP_SCLI2C1_AP_SDA

PP5V0_USB TIGRIS_BOOT

PP_VCC_MAIN

SYSTEM POWER:CHARGERSYNC_MASTER=N/A SYNC_DATE=N/A

16V10%

0402-1

4.2UF

X5R-CERM

ROOM=CHARGER

C23201

2

ROOM=CHARGER

16V5%

01005

100PF

NP0-C0G

C23061

2

16

5

30

30 25 8

30 25 8

ROOM=CHARGER

NOSTUFF

MF1/32W

5%100K

01005

R2300 1

2

0402-9CERM-X5R

10UF20%6.3V

ROOM=CHARGER

C23301

2

9 8

18

100PF16V5%

NP0-C0G

ROOM=CHARGER01005

C2301 1

25%

100PF

NP0-C0G

ROOM=CHARGER01005

16V

C2302 1

2100K

01005ROOM=CHARGER

1/32W5%

MF

R23101

2

ROOM=CHARGER

4.2UF

0402-1

10%16VX5R-CERM

C23101

2

18

ROOM=CHARGER

100

MF01005

5%1/32W

R23031 2

1/32WMF 0%

NOSTUFF01005

0.00R2301

1 2

40.2K1%

01005

1/32WMF

R23021

2

DFN0806DMN2990UFAQ2301

3

2

1

SN2400AB0

ROOM=CHARGERCRITICAL

WCSP

U2300

E2

A1B1D1C1

E1

G5

A4B4D4C4

F2G1

G2

G4

A3 B3 D3 C3

F5

E4G3

E3

F3

A5B5D5C5E5

F1

F4

A2 B2 D2 C2

100PF35VNP0-C0G

ROOM=CHARGER

5%

01005

C23221

2

100PF

NP0-C0G

5%35V

ROOM=CHARGER01005

C23111

2

CRITICAL

BGAROOM=CHARGER

CSD68827WQ2300

C1 C2 C3

A1

A2 A3 B1 B2 B3

01005MF

30.1K

1%1/32W

ROOM=CHARGER

R23201 2

ROOM=CHARGER

1.0UH-20%-3.6A-0.060OHM

CRITICAL

PIQA20161T-SM

L23001 2

X5R0201

ROOM=CHARGER

16V10%

0.047UFC2300

1 2

ROOM=CHARGER01005MF

100

1%1/32W

R23111 2

ROOM=CHARGER

10UF20%6.3VCERM-X5R0402-9

C23311

2

ROOM=CHARGER

16VNP0-C0G

100PF

01005

5%

C23071

2

20%2.2UF6.3V

0201X5R-CERM

ROOM=CHARGER

C23041

220%2.2UF6.3V

0201X5R-CERM

ROOM=CHARGER

C23031

2

6.3VX5R-CERM

ROOM=CHARGER

20%2.2UF

0201

C23051

24.2UF

0402-1

16V10%

ROOM=CHARGER

X5R-CERM

C23211

2

33 18 3

17

17

33 30 26 24 16 15 14 12 8

16 13 11

15 12 8

31 30 3

33 26 25 24 22 21 15 14

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

IN

IN

BI

BI

IN

BI

D

SG

PMID

VBUS

PGND

PGND

PGND

PGND

HDQ_HOSTHDQ_GAUGE

ACT_DIODE

BAT_SNS

BATBATBATBAT

BUCK_SWBUCK_SWBUCK_SWBUCK_SW

BOOT

LDO

TEST

VBUS_DET

INT

VBUS_OVP_OFF

SCLSDA

SYS_ALIVE

VBUS

VBUSVBUSVBUS

VDD_

MAI

NVD

D_M

AIN

VDD_

MAI

NVD

D_M

AIN

G

S

D

Page 18: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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m516S00104 (RCPT)

516S00105 (PLUG)

THIS ONE ON MLB --->

BATTERY CONNECTOR

18 OF 60

VOLTAGE=4.3V

24 OF 49

4.0.0

051-00648

VBATT_SENSE

TIGRIS_TO_BATTERY_SWI TIGRIS_BATTERY_SWI_CONN

PP_BATT_VCC

SYNC_DATE=N/ASYNC_MASTER=N/A

SYSTEM POWER:BATTERY CONN

10V10%

01005X7R-CERM

220PF

ROOM=BATTERY_B2B

C24121

2

100PF

ROOM=BATTERY_B2B

NP0-C0G01005

5%16V

C24111

2NP0-C0G

56PF5%16V

ROOM=BATTERY_B2B01005

C24101

2

01005ROOM=BATTERY_B2B

120-OHM-210MAFL2400

1 2

ROOM=BATTERY_B2B

NP0-C0G01005

27PF5%16V

C24141

2

ROOM=BATTERY_B2B

NP0-C0G

56PF16V

01005

5%

C24131

2

CRITICALROOM=BATTERY_B2B

F-ST-SMRCPT-BATT-2BLADES

J2400

123

4

5

6

7 8

9 10

11

1201005ROOM=BATTERY_B2B

NP0-C0G16V5%56PFC24001

2

17

17

ROOM=BATTERY_B2B

SHORT-10L-0.25MM-SMXW2400

1 2

33 17 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

OUT

Page 19: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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MAGNESIUM - COMPASSINVENSENSE (APN 338S00017): C3013=0.22UFINVENSENSE 1.1 (APN 338S00087): C3013=0.22UF

CARBON - ACCEL & GYROALPS (APN:338S00084)

114K INT PD

114K INT PU

1.09M INT PU

BOSCH (APN:338S1163)

DISCRETE ACCEL

19 OF 60

30 OF 49

4.0.0

051-00648

SPI_OWL_TO_IMU_MOSI

ACCEL_TO_OWL_INT2ACCEL_TO_OWL_INT1

SPI_OWL_TO_DISCRETE_ACCEL_CS_L

ACCEL_TO_OWL_INT2_R

ACCEL_TO_OWL_INT1_R

SPI_OWL_TO_IMU_SCLK

PP1V8_IMU_OWLSPI_OWL_TO_IMU_MOSISPI_IMU_TO_OWL_MISO

ACCEL_GYRO_TO_OWL_INT1

SPI_OWL_TO_IMU_SCLK

ACCEL_TO_OWL_SDO

PP1V8_IMU_OWL

SPI_IMU_TO_OWL_MISO

SPI_OWL_TO_IMU_MOSI

SPI_OWL_TO_IMU_SCLK

SPI_OWL_TO_COMPASS_CS_L

COMPASS_TO_OWL_INTACCEL_GYRO_TO_OWL_INT2

SPI_IMU_TO_OWL_MISO

PP1V8_IMU_OWL

GYRO_CHARGE_PUMP

SPI_OWL_TO_ACCEL_GYRO_CS_L

PP1V8_IMU_OWL

SYNC_MASTER=N/A SYNC_DATE=N/A

SENSORS:MOTION SENSORS

01005-1

6.3V

0.22UF

X5R

20%

ROOM=CARBON

C30131

2

9

MPU-6700-12-COMBO

CRITICALOMIT_TABLEROOM=CARBON

LGA

U3010

5

6

8

9 10 11 12 13 157

14 4

23

16 1

CRITICALROOM=MAGNESIUMOMIT_TABLE

FLGA-POP

COMPASS-MODULEU3000

A2

A1

D4

B1B3D1D2

A3

A4

B4

C3

C4

C2

C1

9

9

9

19 9

19 9

19 9 20.0

OMIT_TABLE

5%1/32WMF

01005

R30221 2

1/32W

01005MF

OMIT_TABLE

5%

20.0R3020

1 2

20.0

OMIT_TABLE

01005MF

1/32W5%

R30211 2

1.0UF20%

X5R0201-1

OMIT_TABLE

6.3V

C30211

2

0.1UF20%6.3V

01005OMIT_TABLE

X5R-CERM

C30201

2

0.1UF

OMIT_TABLE

X5R-CERM6.3V

01005

20%

C30221

2

OMIT_TABLELGA

BMA282U3020

4

9 11 12 14 10

65

13

1

32

8 7

9

9

19 9

19 9

19 9

ROOM=MAGNESIUM

6.3V

0201X5R-CERM

20%2.2UFC30001

22.2UF20%6.3V

ROOM=CARBON0201X5R-CERM

C30121

2ROOM=MAGNESIUM

0.1UF20%6.3VX5R-CERM01005

C30011

25%56PF

NOSTUFF

NP0-C0G16V

01005ROOM=MAGNESIUM

C30021

2

ROOM=CARBON

6.3VX5R-CERM

0.1UF20%

01005

C30101

2

19 9

19 9

9

9

19 9

0.1UF20%6.3VX5R-CERM01005ROOM=CARBON

C30111

2

19 14 12

19 14 12

19 14 12

19 14 12

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

CSFSYNC/GNDREGOUT/GND_CAP

INT/INT2

GND

1

GND

2

GND

3

GND

4

GND

5

GND

6

SCL/SPC

DRDY/INT1

SDA/SDISA0/SDO

VDDIOVDD

NC

VPP

RSVRSV

RSV

VDD

VSS

SDO

SCL/SCK

SDA/SDI

CSB

TRG/SE

DRDY

RSV

RST*

OUT

OUT

IN

IN

IN

OUT

CS*

PS

VDDIO

SCX

INT1INT2

GNDIOGND

VDD

SDOSDX

IN

OUT

OUT

IN

IN

NC

NC

NCIN

IN

IN

OUT

OUT

Page 20: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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mPROX & ALS INTERFACE

MIC3/HAC/RCVR INTERFACE

PROX & ALS POWER

CAMERA POWER

FOREHEAD FLEX (FCAM)

CAMERA MIPI

CAMERA I/O

FOREHEAD CONNECTOR516S0986 (RCPT)

516S0987 (PLUG)

THIS ONE ON MLB --->

20 OF 60

31 OF 49

4.0.0

051-00648

ALS_TO_AP_INT_L

I2C2_AP_BI_ALS_SDA_CONN

I2C2_AP_BI_ALS_SDA_CONN

I2C_ISP_TO_FCAM_SCL_CONNAP_TO_FCAM_SHUTDOWN_CONN_L

PP3V0_PROX_CONN

FRONTMIC3_TO_CODEC_AIN4_CONN_N

I2C_ISP_BI_FCAM_SDA_CONN

I2C2_AP_TO_ALS_SCL_CONN

CODEC_TO_HAC_CONN_P

CODEC_TO_HAC_N

I2C_ISP_TO_FCAM_SCL_CONN

I2C_ISP_BI_FCAM_SDA_CONN

I2C_ISP_TO_FCAM_SCL

AP_TO_FCAM_SHUTDOWN_L

I2C_ISP_BI_FCAM_SDA

CODEC_TO_RCVR_CONN_P

PP3V0_ALS_CONN

PP3V0_PROX_CONN

CODEC_TO_RCVR_N

90_MIPI_FCAM_TO_AP_CLK_P 90_MIPI_FCAM_TO_AP_CLK_CONN_P

CODEC_TO_HAC_CONN_N

CODEC_TO_HAC_CONN_P

MAKE_BASE=TRUEI2C2_AP_SCL

I2C2_AP_SDAMAKE_BASE=TRUE

45_PROX_TO_CUMULUS_RX

CUMULUS_TO_PROX_TX_EN_BUFF

PGND_IRLED_D

ALS_TO_AP_INT_CONN_L

I2C2_AP_TO_ALS_SCL_CONN

PGND_IRLED_K

FRONTMIC3_TO_CODEC_AIN4_P

FRONTMIC3_TO_CODEC_AIN4_N

CODEC_TO_RCVR_P

CODEC_TO_HAC_P

PP_CODEC_TO_FRONTMIC3_BIAS

FRONTMIC3_TO_CODEC_AIN4_CONN_P

FRONTMIC3_TO_CODEC_AIN4_CONN_N

CODEC_TO_RCVR_CONN_N

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

PP1V8

PP2V85_CAM_AVDD_LDO PP2V85_FCAM_AVDD_CONN

90_MIPI_FCAM_TO_AP_CLK_N 90_MIPI_FCAM_TO_AP_CLK_CONN_N

CODEC_TO_RCVR_CONN_N

90_MIPI_FCAM_TO_AP_DATA0_CONN_P

PP1V8_FCAM_CONN

CODEC_TO_HAC_CONN_N

AP_TO_FCAM_CLK_CONN

90_MIPI_FCAM_TO_AP_CLK_CONN_P

PP_CODEC_TO_FRONTMIC3_BIAS_CONN

FRONTMIC3_TO_CODEC_AIN4_CONN_P

PP3V0_PROX_IRLEDPGND_IRLED_K

PP2V85_FCAM_AVDD_CONN

90_MIPI_FCAM_TO_AP_DATA0_N 90_MIPI_FCAM_TO_AP_DATA0_CONN_N

90_MIPI_FCAM_TO_AP_DATA0_CONN_P

AP_TO_FCAM_CLK_CONN

ALS_TO_AP_INT_CONN_L

CODEC_TO_RCVR_CONN_P

90_MIPI_FCAM_TO_AP_CLK_CONN_N

AP_TO_FCAM_SHUTDOWN_CONN_L

CUMULUS_TO_PROX_RX_EN_1V8_CONN

PP3V0_ALS_CONN

PP3V0_PROX_ALSPP1V8_FCAM_CONN 90_MIPI_FCAM_TO_AP_DATA0_CONN_N

90_MIPI_FCAM_TO_AP_DATA0_P

45_PROX_TO_CUMULUS_RX_CONN

PP3V0_PROX_IRLED

45_PROX_TO_CUMULUS_RX_CONN

45_AP_TO_FCAM_CLK

SYNC_MASTER=N/A

CAMERA:FOREHEAD FLEX B2BSYNC_DATE=N/A

5%16V56PF

NP0-C0G01005ROOM=CG_B2B

C31441

2

20

20 MF 0%

0.0001005

ROOM=CG_B2B

1/32W

R31031 2

MF 0%ROOM=CG_B2B

010051/32W0.00

R31021 2

01005

120-OHM-210MAFL3102

1 2

01005

120-OHM-210MAFL3101

1 2

11.5

201MF

1%1/20W

R31011

2

F-ST-SMAA22L-S034VA1

J3100

35 36

37 38

39

40

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 34

NP0-C0G16V5%

100PF

ROOM=CG_B2B01005

C31111

2

ROOM=CG_B2B

NP0-C0G16V5%

100PF

01005

C31101

2

01005120-OHM-210MA

ROOM=CG_B2B

FL31261 2

01005120-OHM-210MA

ROOM=CG_B2B

FL312512

ROOM=CG_B2B01005

120-OHM-210MA

FL31111 2

ROOM=CG_B2B01005

120-OHM-210MA

FL31101 2

CRITICAL

65-OHM-0.1A-0.7-2GHZ

ROOM=CG_B2B

TAM0605

L31021

23

4

TAM0605

ROOM=CG_B2B

65-OHM-0.1A-0.7-2GHZ

CRITICALL3100

1

23

4

29

ROOM=CG_B2B01005MF

5%1.00M1/32W

R31401

2

CRITICAL

DMN3730UFB4DFN1006H4-3

ROOM=CG_B2B

Q3140

3

1

2

ROOM=CG_B2B

0.00

01005MF

0%1/32W

R31431 2

2.2UF20%

0201X5R-CERM

ROOM=CG_B2B

6.3V

C31241

2

2.2UF6.3V

0201X5R-CERM

20%

ROOM=CG_B2B

C3130 1

2

0.1UF20%

ROOM=CG_B2B01005X5R-CERM6.3V

C31271

2

6.3VX5R-CERM

ROOM=CG_B2B01005

0.1UF20%

C31211

2

X5R-CERM

2.2UF6.3V

0201

20%

ROOM=CG_B2B

C3128 1

20201

ROOM=CG_B2B

20%6.3V

2.2UF

X5R-CERM

C3129 1

2

2.2UF6.3V

0201X5R-CERM

20%

ROOM=CG_B2B

C31221

2

2.2UF6.3V

ROOM=CG_B2B

20%

0201X5R-CERM

C31231

2

2.2UF

0201X5R-CERM

ROOM=CG_B2B

20%6.3V

C3106 1

2

23

23

23

23

23

23

8

8

29

7

7

7

7

7

7

8

7

7

ROOM=CG_B2B

NP0-C0G01005

16V5%100PFC31261

2

ROOM=CG_B2B

100PF16V5%

NP0-C0G01005

C31251

2

ROOM=CG_B2B

NP0-C0G16V5%100PF

01005

C31201

2

16V

ROOM=CG_B2B

NP0-C0G

100PF5%

01005

C31041

2

ROOM=CG_B2B

100PF5%

NP0-C0G16V

01005

C31001

2

0201ROOM=CG_B2B

FERR-22-OHM-1A-0.055OHMFL3104

1 2

56PF5%16V

01005ROOM=CG_B2B

NP0-C0G

C31131

2

56PF

NP0-C0G16V5%

01005ROOM=CG_B2B

C31121

2

6.3VX5R-CERM01005ROOM=CG_B2B

20%0.1UFC31051

2

6.3VX5R-CERM20%

ROOM=CG_B2B01005

0.1UFC31011

2

0201

FERR-22-OHM-1A-0.055OHM

ROOM=CG_B2B

FL31001 2

01005

100PF16VNP0-C0G

5%

ROOM=CG_B2B

C31461

2

01005ROOM=CG_B2B

120-OHM-210MA

FL314612

01005ROOM=CG_B2B

70-OHM-25%-0.28AFL3151

12

01005

70-OHM-25%-0.28A

ROOM=CG_B2B

FL315212

ROOM=CG_B2B

70-OHM-25%-0.28A

01005

FL31541 2

01005ROOM=CG_B2B

70-OHM-25%-0.28AFL3153

1 2

NO_XNET_CONNECTION=1

01005-1ROOM=CG_B2B

12V-33PFDZ31511

2

NO_XNET_CONNECTION=1

ROOM=CG_B2B

12V-33PF01005-1

DZ31521

2

NO_XNET_CONNECTION=1

01005ROOM=CG_B2B

6.8V-100PFDZ31551

2

NO_XNET_CONNECTION=1

01005ROOM=CG_B2B

6.8V-100PFDZ31561

2

01005ROOM=CG_B2B

120-OHM-210MAFL3156

12

01005

120-OHM-210MA

ROOM=CG_B2B

FL31551 2

01005ROOM=CG_B2B

6.8V-100PFDZ31501

2

120-OHM-210MA

01005ROOM=CG_B2B

FL31501 2

NOSTUFF

56PF

NP0-C0G16V

ROOM=CG_B2B

5%

01005

C31431

2

56PF

01005NP0-C0G16V5%

ROOM=CG_B2B

C31451

2NO_XNET_CONNECTION=1

12V-33PFROOM=CG_B2B01005-1

DZ31541

2

NO_XNET_CONNECTION=1

12V-33PF01005-1ROOM=CG_B2B

DZ31531

2

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

20

24

20

20

20

20

29 28 21 14 13 12 9 8 7 6 5 3

21 20

20

20

20

20

20

20

20

20

20

20 15

20

20

20

20

20

20

20

20

20

28

20

15 20 20

20

20 15

20

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

BI

SYM_VER-2

SYM_VER-2

INS

D

SYM_VER_1

G

IN

IN

IN

OUT

IN

OUT

IN

BI

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

BI

IN

Page 21: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

CAMERA POWER

MIPI COMMON-MODE CHOKES

516S00101 (PLUG)

516S00100 (RCPT)

RCAM CONNECTORTHIS ONE ON MLB --->

DIGITAL I/O

REAR CAMERA FLEX

PLACEHOLDER FOOTPRINTS

21 OF 60

VOLTAGE=2.85V

32 OF 49

4.0.0

051-00648

PP2V5_RCAM_AF_CONN90_MIPI_RCAM_TO_AP_DATA3_CONN_N

PP1V8_RCAM_CONN

PP2V5_RCAM_AF_CONN

PP2V85_RCAM_AVDD_CONN

PP1V2_RCAM_DIGITAL_CONN

RCAM_TO_LED_DRIVER_STROBE_EN_CONN

AP_TO_RCAM_SHUTDOWN_L

RCAM_TO_LED_DRIVER_STROBE_EN

AP_TO_RCAM_SHUTDOWN_CONN_L

90_MIPI_RCAM_TO_AP_DATA2_CONN_P

RCAM_TO_LED_DRIVER_STROBE_EN_CONN

PP2V5_RCAM_AF_COMP

45_BUCK6_FB

PP1V8

PP2V5_RCAM_AF

AP_TO_RCAM_CLK_CONN

PP_VCC_MAIN

45_AP_TO_RCAM_CLK

I2C_ISP_TO_RCAM_SCL I2C_ISP_TO_RCAM_SCL_CONN

I2C_ISP_BI_RCAM_SDA_CONNI2C_ISP_BI_RCAM_SDA

PP1V2_CAMERA

CAM_EXT_LDO_EN

PP2V5_RCAM_AF

PP2V85_RCAM_AVDD_CONN

90_MIPI_RCAM_TO_AP_CLK_CONN_N90_MIPI_RCAM_TO_AP_CLK_CONN_PPP1V8_RCAM_CONN

I2C_ISP_TO_RCAM_SCL_CONNI2C_ISP_BI_RCAM_SDA_CONN

90_MIPI_RCAM_TO_AP_DATA0_CONN_N90_MIPI_RCAM_TO_AP_DATA0_CONN_P

90_MIPI_RCAM_TO_AP_DATA2_CONN_NAP_TO_RCAM_CLK_CONN

AP_TO_RCAM_SHUTDOWN_CONN_L

90_MIPI_RCAM_TO_AP_DATA1_CONN_N90_MIPI_RCAM_TO_AP_DATA1_CONN_P

90_MIPI_RCAM_TO_AP_DATA3_CONN_PPP1V2_RCAM_DIGITAL_CONN

PP2V85_CAM_AVDD_LDO

SYNC_DATE=N/A

CAMERA:REAR CAMERA B2BSYNC_MASTER=N/A

21

AA27D-S030VA1

ROOM=RCAM_B2B

F-ST-SM

CRITICAL

J3200

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

0201ROOM=RCAM_B2B

2.2UF

X5R-CERM

20%6.3V

C32001

2 6.3V

ROOM=RCAM_B2B

X5R-CERM

2.2UF

0201

20%

C32111

2

0.00010050%MF1/32W

ROOM=RCAM_B2B

R32031 2

01005ROOM=RCAM_B2B

1/32WMF 0%

0.00R3204

1 2

21

21

21

7

7

7

7

7

7

7

7

7

7

21

21

MF1/32W1%

3.00

01005

R32021 2

ROOM=RCAM_B2B

SHORT-10L-0.1MM-SMXW3202

1 2

SHORT-10L-0.1MM-SMROOM=RCAM_B2B

XW32031

2

6.3VX5R-CERM0201

20%2.2UFC32101

2

0201-1

20%X5R6.3V

ROOM=RCAM_B2B

1.0UFC32081

2

ROOM=RCAM_B2B0201-1X5R20%6.3V1.0UFC32071

2

FERR-22-OHM-1A-0.055OHM

ROOM=RCAM_B2B0201

L32051 2

100PF

ROOM=RCAM_B2B

16V

01005

5%NP0-C0G

C32091

2

ROOM=RCAM_B2B01005

56PF16V5%NP0-C0G

C32341

2

LP5907SNX-2.85

ROOM=RCAM_B2B

X2SON

U3200

3

2 5

4 1

01005

16VNP0-C0G

5%100PF

ROOM=RCAM_B2B

C32321

2

5%100PF

NP0-C0G16V

01005ROOM=RCAM_B2B

C32311

2

ROOM=RCAM_B2B01005

10-OHM-1.1AFL3200

1 2

100PF5%16V

NP0-C0G01005

ROOM=RCAM_B2B

NOSTUFF

C32991

2

01005

120-OHM-210MA

ROOM=RCAM_B2B

FL32311 2

65-OHM-0.1A-0.7-2GHZ

NOSTUFFROOM=RCAM_B2B

TAM0605

L32041

23

4

NOSTUFF

TAM0605

ROOM=RCAM_B2B

65-OHM-0.1A-0.7-2GHZL3203

1

23

4

65-OHM-0.1A-0.7-2GHZTAM0605

NOSTUFFROOM=RCAM_B2B

L32021

23

4

TAM0605

NOSTUFF

65-OHM-0.1A-0.7-2GHZ

ROOM=RCAM_B2B

L32011

23

4

NOSTUFFROOM=RCAM_B2B

65-OHM-0.1A-0.7-2GHZTAM0605

L32001

23

4

ROOM=RCAM_B2B

NP0-C0G

100PF

01005

16V5%

C3230 1

2

FERR-22-OHM-1A-0.055OHM

ROOM=RCAM_B2B0201

FL32011 2

2.2UF20%6.3V

0201ROOM=RCAM_B2B

X5R-CERM

C32031

220%

0201

2.2UF

ROOM=RCAM_B2B

X5R-CERM6.3V

C32041

2

ROOM=RCAM_B2B01005NP0-C0G16V

100PF5%

C32051

2

ROOM=RCAM_B2B01005NP0-C0G16V5%56PFC32331

2

X5R-CERM

2.2UF20%6.3V

ROOM=RCAM_B2B0201

C32061

2

ROOM=RCAM_B2B

NP0-C0G01005

100PF16V5%

C32211

2ROOM=RCAM_B2B

0201-1

20%X5R6.3V1.0UFC32201

2

FERR-22-OHM-1A-0.055OHM

0201ROOM=RCAM_B2B

FL32201 2

7

7

ROOM=RCAM_B2B

120-OHM-210MA

01005

FL32321 222

21

21

22 7

22 7

16V100PF

ROOM=RCAM_B2B01005NP0-C0G5%

C32021

2

ROOM=RCAM_B2B01005

120-OHM-210MAFL3230

1 2

ROOM=RCAM_B2B

0.1UF20%6.3V

01005X5R-CERM

C32011

2

21

21

21

21

21

21

14

29 28 20 14 13 12 9 8 7 6 5 3

21 15

21

33 2625 24 22 17 15 14

14

8

21 15

21

21

21

20

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

IN

OUT

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI

VIN

ENEPADGND

VOUT

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

IN

IN

OUT

BI

OUT

BI

IN

Page 22: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

mDUAL LED STROBE DRIVER

INT 200K PD

INT 200K PD

INT 200K PD

APN:353S3899

INT 200K PD

22 OF 60

VOLTAGE=5.0V

VOLTAGE=5.0V

VOLTAGE=5.0V

VOLTAGE=5.0V

33 OF 49

4.0.0

051-00648

PP_LED_BOOST_OUT

PP_LED_DRIVER_SW

PP_LED_DRIVER_WARM_LED

PP_LED_DRIVER_COOL_LED

PP_VCC_MAIN

LED_MODULE_NTC

BB_TO_LED_DRIVER_GSM_BURST_IND

RCAM_TO_LED_DRIVER_STROBE_EN

I2C_ISP_BI_RCAM_SDA

AP_TO_LED_DRIVER_EN

I2C_ISP_TO_RCAM_SCL

CAMERA:STROBE DRIVERSYNC_MASTER=N/A SYNC_DATE=N/A

0402-9ROOM=STROBE

CERM-X5R6.3V20%10UFC33941

2

ROOM=STROBE

NP0-C0G

100PF5%16V

01005

C33081

2

20%

X5R-CERM

2.2UF6.3V

0201ROOM=STROBE

C3384 1

2

ROOM=STROBE

100PF

NP0-C0G01005

5%16V

C33731

2

20%2.2UF

6.3V

0201ROOM=STROBE

X5R-CERM

C3385 1

20201

ROOM=STROBE

6.3VX5R-CERM

20%2.2UF

C3386 1

2

ROOM=STROBE

CRITICAL

PIQA20161T-SM

1.0UH-20%-3.6A-0.060OHML3300

1 2

32

8

21

33 26

6.3V20%

0402-9CERM-X5R

10UF

ROOM=STROBE

C33961

2

21 7

21 7

6.3V20%

10UF

ROOM=STROBE0402-9

CERM-X5R

C3387 1

2

ROOM=STROBEWLCSP

LM3564A1TMX

CRITICAL

U3300

C1

D3

A1 B1

D1

A4B4

C4D4

A3B3C3

D2E2

E3

A2B2

E1

C2E4

32

32

33 26 25 24 21 17 15 14

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

IN

IN

IN

IN

BI

INOUT

GND AGND

SCL

TXSDA

TORCH

ENABLESTROBE

TEMP

LED2

LED1

SW

NC

Page 23: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

ANC ERROR MIC

ANC REF MIC

VOICE MIC

CALTRA AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

23 OF 60

35 OF 49

4.0.0

051-00648

90_MIKEYBUS_DATA_N

CODEC_TO_HPHONE_HS3_REF

FRONTMIC3_TO_CODEC_AIN4_NFRONTMIC3_TO_CODEC_AIN4_P

REARMIC2_TO_CODEC_AIN3_PREARMIC2_TO_CODEC_AIN3_N

LOWERMIC1_TO_CODEC_AIN1_N

90_MIKEYBUS_CALTRA_DATA_P90_MIKEYBUS_CALTRA_DATA_N

MBUS_REF_U3500

CODEC_TO_HAC_P

CODEC_TO_RCVR_NCODEC_TO_RCVR_P

CODEC_TO_HPHONE_L

CODEC_HSIN_NCODEC_HSIN_P

CODEC_TO_HAC_N

CODEC_TO_HPHONE_HS4

CODEC_TO_HPHONE_HS3

CODEC_TO_HPHONE_R

HPHONE_TO_CODEC_DETECT

CODEC_TO_HPHONE_HS4_REF

90_MIKEYBUS_DATA_P

CODEC_HSIN_R_P

CODEC_HSIN_R_N

LOWERMIC1_TO_CODEC_AIN1_P

SYNC_MASTER=N/A SYNC_DATE=N/A

AUDIO:CALTRA CODEC (1/2)

100PF

NP0-C0G

5%

01005

16V

ROOM=CODEC

C35541 2

ROOM=CODEC

5%

01005MF

1/32W

20.0R3503

1 2

5%

01005ROOM=CODEC

20.0

1/32WMF

R35021 2

100PF

5%

01005NP0-C0G

16V

ROOM=CODEC

C35521 2

ROOM=CODECSHORT-10L-0.1MM-SM

XW35001 2

WLCSP-1

CS42L71

ROOM=CODEC

CRITICAL

U3500

L1L2

L3K3

K1K2

J4J3

G1F1

F3F2

G3G2

M9L9

M8L8

A4B4

C4C3

A3B3

A2B2

H12J12

J9

K10K11

M5

L10

M4

M10

E1D1

G10

A9B9

010056.3V20%

X5R-CERMROOM=CODEC

0.1UFC3506

1 2

6.3V01005

ROOM=CODECX5R-CERM

20%

0.1UFC3505

1 2

01005

1%

MF1/32W

1.33K

ROOM=CODECNO_XNET_CONNECTION=1

R35501 2

01005MF

1%

1.33K

ROOM=CODEC

NO_XNET_CONNECTION=1

1/32W

R35151 2

01005

10VX7R-CERM

ROOM=CODEC

10%220PFC35041

2

30

31

20

20

32

32

31

20

20

20

31

20

31

31

31

31

31

30

31

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NCNC

NCNC

SYM 1 OF 3

HS3_REFHS4_REF

HPDETECT

HPOUTB

HS3

HS4

AOUT2-

HSIN+HSIN-

HPOUTA

AOUT1+AOUT1-

AOUT2+

MBUS_REF

DNDP

AIN1+AIN1-

AIN2+AIN2-

AIN3+AIN3-

AIN4-AIN4+

AIN5-AIN5+

AIN6-AIN6+

AIN7+AIN7-

DMIC3_DATADMIC3_CLK

DMIC2_CLKDMIC2_DATA

DMIC4_CLK

DMIC1_DATADMIC1_CLK

PDM_CLK

DMIC4_DATA

PDM_DATA

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

Page 24: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

CALTRA AUDIO CODEC (POWER & I/O)

24 OF 60

36 OF 49

4.0.0

051-00648

SPI_CODEC_TO_AP_MISO

CALTRA_FLYP

CALTRA_FLYC

CALTRA_FLYN

CALTRA_GNDCP

CALTRA_LP_FILTP

PMU_TO_CODEC_DIGLDO_PULLDN

PP1V8_SDRAM

PP_VCC_MAIN

PP1V8_SDRAM

CODEC_TO_PMU_MIKEY_INT_L

CODEC_TO_AP_PMU_INT_L

I2S_CODEC_TO_AP_ASP_DIN

45_I2S_AP_OWL_TO_CODEC_XSP_BCLKI2S_AP_OWL_TO_CODEC_XSP_LRCLK

SPI_AP_TO_CODEC_CS_LSPI_AP_TO_CODEC_SCLK

45_I2S_AP_TO_CODEC_ASP_BCLK

I2S_AP_TO_CODEC_ASP_DOUTI2S_AP_TO_CODEC_ASP_LRCLK

I2S_AP_TO_CODEC_MSP_DOUTI2S_CODEC_TO_AP_MSP_DIN

45_I2S_AP_TO_CODEC_MSP_BCLK

SPI_AP_TO_CODEC_MOSI

I2S_CODEC_TO_AP_OWL_XSP_DINI2S_AP_TO_CODEC_XSP_DOUT

45_I2S_AP_TO_CODEC_MCLK

I2S_AP_TO_CODEC_MSP_LRCLK

CODEC_RESET_L

PP_CODEC_TO_FRONTMIC3_BIAS

PP1V8_VA

PP1V2_VD_FILT

CALTRA_VCP_FILTP

CALTRA_VCP_FILTN

CALTRA_FILTP

CODEC_AGND

PP_CODEC_TO_LOWERMIC1_BIASLOWERMIC1_BIAS_FILT_IN

REARMIC2_BIAS_FILT_INPP_CODEC_TO_REARMIC2_BIAS

FRONTMIC3_BIAS_FILT_IN

CALTRA_HS_BIAS_FILT_IN

CALTRA_HS_BIAS_FILT

REARMIC2_BIAS_FILT_RET

LOWERMIC1_BIAS_FILT_RET

CODEC_AGND

FRONTMIC3_BIAS_FILT_RET

AUDIO:CALTRA CODEC (2/2)SYNC_MASTER=N/A SYNC_DATE=N/A

SHORT-10L-0.1MM-SM

ROOM=CODEC

XW36301 2

ROOM=CODEC

SHORT-10L-0.1MM-SMXW3620

1 22.2UF

ROOM=CODEC

X5R-CERM0201

6.3V20%

C36611

2

ROOM=CODEC

X5R-CERM0201

6.3V

2.2UF20%

C36601

2

ROOM=CODEC

X5R-CERM0201

6.3V

2.2UF20%

C36401

2

CERM-X5R

10UF

0402-9

6.3V20%

ROOM=CODEC

C36001

2

ROOM=CODEC

0.1UF

X5R-CERM01005

6.3V20%

C36011

2 6.3VX5R-CERM

ROOM=CODEC01005

0.1UF20%

C36021

2

0201-1ROOM=CODEC

1.0UF6.3VX5R20%

C36701

2

4.7UF

ROOM=CODEC

6.3V

402X5R-CERM1

20%

C36531 2

01005

6.3V0.1UF

ROOM=CODEC

X5R-CERM20%

C36121

2

0.1UF

X5R-CERM6.3V20%

01005ROOM=CODEC

C36111

2

ROOM=CODEC

X5R-CERM1402

4.7UF6.3V20%

C36541

2

01005X5R-CERM

ROOM=CODEC

0.1UF6.3V20%

C36651

2

ROOM=CODEC0402-9

10UF

CERM-X5R6.3V20%

C36101

2

ROOM=CODEC

20%6.3V

402X5R-CERM1

4.7UFC3651

1 2

6.3V

ROOM=CODEC

20%

4.7UF

402X5R-CERM1

C36501 2

0402-9ROOM=CODEC

CERM-X5R

10UF6.3V20%

C36641

2

ROOM=CODEC

SMXW3660

1 2

ROOM=CODEC

4.7UF

402

6.3V20%X5R-CERM1

C36631

2

ROOM=CODEC402X5R-CERM1

4.7UF6.3V20%

C36621

2

SHORT-10L-0.1MM-SM

ROOM=CODEC

XW36001 2

1/32W5%

01005ROOM=CODEC

MF

1.00KR36501

2

CS42L71

ROOM=CODECCRITICAL

WLCSP-1

U3500

C5C6

B5B6

C8C9

J5H5

A1A12B12E2E3E4E10F4F5F6F7F8F9F10G4G5G6G7G8G9H6H7H8H9

J8

K9

D4D2C2

D3

C12

A8B8

C7B7

D8A7

H3

C10D10D7D9E8E9G11H4M1

D11B10D5D6E5E6E7K4

K8

C11B11

A11A10

WLCSP-1

CS42L71

ROOM=CODECCRITICAL

U3500

H2

H1

L12

M12

K12

J2

L11

A6 B1 E11

F11 L4 L7

M3M2

F12

M11

M6K7

L6J7

K6L5

J6K5

J10

J1J11

D12

G12

C1 E12

A5 M7

H10

H11

8

16

33 30 26 24 17 16 15 14 12 8

33 26 25 22 21 17 15 14

33 30 26 24 17 16 15 14 12 8

16

16 8

25 8

9 8

9 8

8

8

25 8

25 8

25 8

8

8

8

8

9 8

8

8

8 20

25 15

24

31

32

31

24

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NCNC

NCNCNCNCNCNC

NCNC

SYM 3 OF 3

DIGLDO_PDNGND

TSTO

TSTOTSTO

RESET*

GND

MSP_LRCK/FSYNC

MCLK

XSP_SDIN/DAC2B_MUTEXSP_SDOUT

GND

TSTI

TSTI

MOSI

GNDDIGLDO_PULLDN

MSP_SCLK

MSP_SDOUTMSP_SDIN

ASP_LRCK/FSYNCASP_SDIN

ASP_SCLK

MISO

CCLKCS*

WAKE*

GNDGNDGNDGNDGNDGND

GNDGNDGND

GND

GNDGNDGND

GNDGNDGNDGND

GND

GND

GNDGND

TSTITSTI

TSTITSTI

TSTI

TSTOTSTO

TSTI

TSTI

TSTOTSTO

JTAG_TCKJTAG_TDI

JTAG_TDO

TSTO

JTAG_TMS

XSP_LRCK/FSYNCXSP_SCLK

ASP_SDOUT

INT*

SYM 2 OF 3

VP_M

BUS

VPRO

G_C

P

HS_BIAS_FILTHS_BIAS_FILT_REF

MIC4_BIAS_FILT

MIC2_BIASMIC2_BIAS_FILT

MIC3_BIASMIC3_BIAS_FILT

MIC1_BIAS_FILTMIC1_BIAS

GND

P

GND

A

FILT-

FILT+

FLYP

GNDCP

FLYN

LP_FILT+

-VCP_FILT

+VCP_FILT

FLYC

VCP VDVD VL

VD_F

ILT

VD_F

ILT VP VA

MIC4_BIAS

GND

HS

GND

DG

NDD

GND

D

GND

D

NCNCNCNC

Page 25: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

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1M INT PD

APN: 338S1285

SPEAKER AMPLIFIER

1M INT PD

1M INT PD

1M INT PD

1M INT PD

1M INT PD

25 OF 60

VOLTAGE=8.0V

VOLTAGE=8.0V

37 OF 49

4.0.0

051-00648

PP_SPKR_VBOOST

PP_SPEAKERAMP_SW

PP_VCC_MAIN

SPEAKERAMP_TO_SPEAKER_OUT_POS

PP1V8_VA

SPEAKERAMP_LDO_FILT

AP_TO_SPEAKERAMP_RESET_L

SPEAKERAMP_FILT

I2S_CODEC_TO_AP_ASP_DIN

VSENSE_POSVSENSE_NEG

SPEAKERAMP_IREF

SPEAKERAMP_TO_SPEAKER_OUT_NEG

I2S_AP_TO_CODEC_ASP_DOUT

I2C1_AP_SDA

45_I2S_AP_TO_SPEAKERAMP_MCLK

45_I2S_AP_TO_CODEC_ASP_BCLK

I2S_AP_TO_CODEC_ASP_LRCLK

SPEAKERAMP_TO_AP_INT_L

I2C1_AP_SCL

AUDIO:SPEAKER DRIVERSYNC_MASTER=N/A SYNC_DATE=N/A

SHORT-10L-0.1MM-SMXW3704

1 2

SHORT-10L-0.1MM-SMXW3703

1 2

20%10V

0603-1X5R-CERM

22UFC37421

2 NP0-C0G01005

ROOM=SPKR_AMP

16V5%100PFC37461

2

ROOM=SPKR_AMP

X5R

1000PF

01005

10V10%

C3760 1

2

ROOM=SPKR_AMP

44.2K

MF1/32W

01005

1%

R37351

2

X5R

ROOM=SPKR_AMP01005

10V10%1000PFC37631

2 X5R10%10V

1000PF

01005ROOM=SPKR_AMP

C3700 1

2 X5R01005

10V1000PF10%

ROOM=SPKR_AMP

C37021

2

0402ROOM=SPKR_AMP

CER-X5R

4.7UF20%6.3V

C37401

2CS35L21-XWZR

ROOM=SPKR_AMP

CRITICAL

WLCSP

U3700

C7

D7

F2

B5 B6 C6 E4 F3 F4A3 B3 B4 C3 C4 D3 D4

A7

B7

F1E1

C5

F6

E7

C2D2

A6

D6

E6

D5

F7

E5

A2B2

F5A1 B1 C1 D1 A4 A5

E3E2

CRITICAL

ROOM=SPKR_AMPPIQA20161T-SM

1.2UH-20%-3.0A-0.080OHML3700

1 2

24 8

8

24 8

24 8

24 8

30 17 8

30 17 8

ROOM=SPKR_AMP

2.2UF6.3V20%

X5R-CERM0201

C37291

2

20%6.3V

0201X5R-CERM

2.2UF

ROOM=SPKR_AMP

C37301

2

8

8

5%

MF1/32W

100K

01005ROOM=SPKR_AMP

R37291

2

20%

0402-8

10V10UF

ROOM=SPKR_AMP

X5R-CERM

C37411

2

01005

20%6.3V0.1UF

ROOM=SPKR_AMP

X5R-CERM

C37091

2

16V

ROOM=SPKR_AMP

10%

0201X5R-CERM

0.1UFC37451

2

33 26 24 22 21 17 15 14

31

24 15

31

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NCNC

VER1

SDOUT

SDIN

LRCK/FSYNC

SCLK

MCLK

ALIVE

RESET*

INT*

GNDP

LDO_FILT

VSENSE-VSENSE+

ISENSE-ISENSE+

OUT-OUT+

IREF+

GNDA

SW

VBST

ADO

VA

SDA

VP

SCL

FILT+

IN

IN

IN

IN

OUT

IN

BI

IN

OUT

Page 26: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

CHESTNUT DISPLAY PMUAPN:338S1172

MOJAVE MESA BOOSTAPN:353S4207 (A1)

200K INT PD

NO INT PULL

NO INT PULL

DISPLAY & TOUCH - POWER SUPPLIES

APN:353S00640LED BACKLIGHT DRIVER

26 OF 60

VOLTAGE=6.0V

VOLTAGE=5.7V

VOLTAGE=5.7V

VOLTAGE=6.0V

VOLTAGE=21V

VOLTAGE=21V

VOLTAGE=25V

VOLTAGE=25V

VOLTAGE=6.3V

VOLTAGE=35V

VOLTAGE=-6.0V

VOLTAGE=18.0V

VOLTAGE=12.0V

VOLTAGE=5.1V

VOLTAGE=-5.7V

VOLTAGE=11.5V

40 OF 49

4.0.0

051-00648

PP_CHESTNUT_CP

PP5V7_LCM_AVDDH

PP5V7_SAGE_AVDDH

PP6V0_LCM_BOOST

PP_LCM_BL_CAT2PP_LCM_BL_CAT1

PP_BL_SW1

PP_BL_SW2

PP_VCC_MAIN

I2C0_AP_SCL

I2C0_AP_SDA

LCM_TO_CHESTNUT_PWR_EN

PMU_TO_OWL_ACTIVE_READY

PP_VCC_MAIN

PP3V0_TRISTAR

BB_TO_LED_DRIVER_GSM_BURST_INDAP_TO_MUON_BL_STROBE_ENI2C0_AP_SCLI2C0_AP_SDA

45_DWI_PMGR_TO_BACKLIGHT_SCLK

CHESTNUT_TO_PMU_ADCMUX

PP1V8_SDRAM

45_DWI_PMGR_TO_PMU_BACKLIGHT_MOSI

MESA_TO_BOOST_EN

PP_VCC_MAIN

PP_CHESTNUT_SW

PP_LCM_BL_ANODE

PN_CHESTNUT_CN

PP13V0_MESA_SW

PP12V0_MOJAVE_LDOIN

PP5V1_GRAPE_VDDH

PN5V7_SAGE_AVDDN

PP11V3_MESA

SYNC_DATE=N/ASYNC_MASTER=N/A

DISPLAY:POWER

X5R-CERM

10UF20%VOLTAGE=10V

ROOM=CHESTNUT0402-8

C40021

2

CERM-X5R

ROOM=BACKLIGHT

20%

0402-9

10UFVOLTAGE=6.3V

C4020 1

2 CERM-X5R

ROOM=BACKLIGHT0402-9

20%10UF

VOLTAGE=6.3V

C4021 1

2

LM3539A1DSBGA

CRITICAL

ROOM=BACKLIGHT

U4020

B3 B4

D4

D2

C1B1

A1

C3

A2B2

C2

C4

A3A4

D1

D3

33 22

7

9

16 9

0402-1ROOM=MOJAVE

X5R-CERM

20%2.2UFVOLTAGE=25V

C40411

2

0201

5%56PF

ROOM=MOJAVE

NP0-C0GVOLTAGE=25V

C40421

20402-1ROOM=MOJAVE

2.2UF20%

X5R-CERMVOLTAGE=25V

C40431

2

BGAROOM=MOJAVE

LM3638A1

CRITICAL

U4040

B3

B2A3

C2

A1

C1

B1

A2 C3

20%

X5R-CERM

ROOM=CHESTNUT0603-1

22UFVOLTAGE=10V

C40071

2

27 3

33 31 30 15

ROOM=BACKLIGHTNSR05F30NXT5G

DSN2

CRITICALD4021A K

ROOM=BACKLIGHT

100PF5%

01005NP0-C0GVOLTAGE=35V

C40221

2

10UF20%

ROOM=BACKLIGHT0603X5R-CERMVOLTAGE=35V

C40231

2

PIXB2016FE-SMROOM=CHESTNUT

CRITICAL

1.0UH-20%-2.25A-0.15OHML4000

1

2

ROOM=BACKLIGHT

1.0UH-20%-3.6A-0.060OHM

CRITICAL

PIQA20161T-SM

L40211 2

0403ROOM=MOJAVE

CRITICAL

1.0UH-20%-0.4A-0.636OHML4040

1 2

ROOM=CHESTNUT

20%1UF

0201CER-X5RVOLTAGE=16V

C40031

2

1%200K1/32W

01005MF

ROOM=BACKLIGHT

R40201

2

SOD-923-1

NSR0530P2T5G

CRITICAL

ROOM=BACKLIGHT

D4020KA

26 16 8

26 16 8

26 16 8

26 16 8

16

28 16

30 16 9 5

ROOM=BACKLIGHT

CRITICAL

PITA32251T-SM

15UH-20%-0.72A-0.9OHML4020

1 2

10UF20%

CERM-X5R0402-9

ROOM=MOJAVE

VOLTAGE=6.3V

C4040 1

2

X5R-CERM

10UF

ROOM=CHESTNUT

20%

0402-8

VOLTAGE=10V

C40041

2

10UF20%

ROOM=CHESTNUT0402-8X5R-CERMVOLTAGE=10V

C40051

220%

X5R-CERM0402-8ROOM=CHESTNUT

VOLTAGE=10V

10UFC40061

2

20%10UF

CERM-X5R0402-9

ROOM=CHESTNUT

VOLTAGE=6.3V

C4000 1

2

ROOM=CHESTNUT

BGA

CRITICAL

TPS65730A0PYFFU4000

E1

C1

C4E4

B4

A4

A3

A1

C3

B3

B1 D4

C2

D3

D2

B2

A2

D1

E3

E2

28

29

28

28

33 26 25 24 22 21 17 15 14

33 26 25 24 22 21 17 15 14

33 30 24 17 16 15 14 12 8

33 26 25 24 22 21 17 15 14

28

29

29 28

27 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SDI

VIO/HWEN

SCK

SDA

TRIG

SW2_1SW2_2

SCL

SW1

IN OUT

LED1LED2

INHIBIT

GND

GND

IN

IN

IN

IN

PMID

VOUT

EN_S

LDOIN

EN_M

SW

VIN

PGND

AGND

IN

IN

IN

BI

IN

BI

OUT

IN

IN

HVLDO3

HVLDO2

HVLDO1

VNEG(SUB)

VNEG

AGND

PGND

2PG

ND1

CPUMPLCMBST

CF1CF2

ADCMUX

RESET*

LCM_EN

SDA

SCL

SYNC

SW

VIN

Page 27: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

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MESA POWER AND IO FILTERS

MESA POWER

MESA DIGITAL I/O

27 OF 60

41 OF 49

4.0.0

051-00648

PP11V3_MESA_CONN

MESA_TO_AP_INT

MESA_TO_BOOST_EN

SPI_AP_TO_MESA_SCLK_CONN

MESA_TO_AP_INT_CONN

SPI_MESA_TO_AP_MISO SPI_MESA_TO_AP_MISO_CONN

SPI_AP_TO_MESA_MOSI_CONN

BUTTON_MENU_KEY_L

PP1V9_MESA_CONN

SPI_AP_TO_MESA_SCLK

PP11V3_MESA

SPI_AP_TO_MESA_MOSI

PP3V1_MESA

PP1V9_MESA

PP3V1_MESA_CONN

MESA_TO_BOOST_EN_CONN

BUTTON_MENU_KEY_CONN_L

SYNC_MASTER=N/A SYNC_DATE=N/A

MESA POWER AND IO FILTERS

1%1/32W

01005MF

681

ROOM=MAMBA_MESA

R41161 2

01005ROOM=MAMBA_MESA

120-OHM-210MAFL4114

1 2

0201ROOM=MAMBA_MESA

80-OHM-25%-1000MAFL4100

1 2

01005-112V-33PF

NOSTUFFDZ41011

2

ROOM=MAMBA_MESA

5%

01005NP0-C0G16V

56PFC41171

2

01005ROOM=MAMBA_MESA

120-OHM-210MAFL4143

1 2

5%16VNP0-C0G01005

56PF

ROOM=MAMBA_MESA

C41161

2

5%

01005NP0-C0G

100PF

ROOM=MAMBA_MESA

35V

C41071

2

01005

5%100PF16VNP0-C0G

ROOM=MAMBA_MESA

C41151

2

ROOM=MAMBA_MESA

5%

01005NP0-C0G

100PF16V

C41051

2

01005ROOM=MAMBA_MESA

70-OHM-25%-0.28AFL4107

1 2

ROOM=MAMBA_MESA01005

70-OHM-25%-0.28AFL4105

1 2

6.3V20%

ROOM=MAMBA_MESA

X5R-CERM0201

2.2UFC41061

2

26 3

ROOM=MAMBA_MESA

5%56PF

01005NP0-C0G16V

C41101

2

01005

5%

NP0-C0G

56PF16V

ROOM=MAMBA_MESA

C41111

2

16V5%

NP0-C0G01005ROOM=MAMBA_MESA

56PFC41121

2

01005ROOM=MAMBA_MESA

120-OHM-210MAFL4112

1 2

01005MF

0%1/32W

0.00

ROOM=MAMBA_MESA

R41111 2

120-OHM-210MA

ROOM=MAMBA_MESA01005

FL41101 28

8

8

8

8

6.3V20%

ROOM=MAMBA_MESA

X5R-CERM0201

2.2UFC41041

220%

X5R-CERM

ROOM=MAMBA_MESA

6.3V

0201

2.2UFC41031

2 6.3V20%

ROOM=MAMBA_MESA

X5R-CERM0201

2.2UFC41021

2

0.1UF6.3V20%X5R-CERM01005ROOM=MAMBA_MESA

C41011

2

ROOM=MAMBA_MESA

100PF5%

01005NP0-C0G16V

C41001

2

31

31

31

31

31

31

26 3

15

15

31

31

31

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

IN

OUT

IN

OUT

OUT

Page 28: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

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f i x

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516S1051 (RCPT)

DISPLAY CONTROL SIGNALS

DISPLAY FLEXDISPLAY POWER

OWL TO TOUCH INTERFACE

PROX TO TOUCH INTERFACE

DISPLAY MIPI

BACKLIGHT

THIS ONE ON MLB --->

DISPLAY CONNECTOR516S1050 (PLUG)

28 OF 60

42 OF 49

4.0.0

051-00648

90_MIPI_AP_TO_LCM_CLK_CONN_P

PN_SAGE_TO_TOUCH_VCPL

PP_LCM_BL_CAT1_CONN

LCM_TO_CHESTNUT_PWR_EN_CONN

LCD_TO_AP_PIFA_CONN

LCM_TO_CHESTNUT_PWR_EN

90_MIPI_AP_TO_LCM_DATA1_N

90_MIPI_AP_TO_LCM_DATA1_P

90_MIPI_AP_TO_LCM_DATA0_N

90_MIPI_AP_TO_LCM_DATA0_P

90_MIPI_AP_TO_LCM_CLK_N

90_MIPI_AP_TO_LCM_CLK_P 90_MIPI_AP_TO_LCM_CLK_CONN_P

90_MIPI_AP_TO_LCM_CLK_CONN_N

90_MIPI_AP_TO_LCM_DATA0_CONN_P

90_MIPI_AP_TO_LCM_DATA0_CONN_N

90_MIPI_AP_TO_LCM_DATA1_CONN_P

90_MIPI_AP_TO_LCM_DATA1_CONN_N

PP_LCM_BL_CAT2

PP_LCM_BL_CAT1

PP_LCM_BL_ANODE

CUMULUS_TO_PROX_RX_EN_1V8

LCM_TO_AP_HIFA_BSYNC

PMU_TO_LCM_PANICB

AP_TO_LCM_RESET_L

PP_LCM_BL_CAT2_CONN

PP_LCM_BL_ANODE_CONN

PMU_TO_LCM_PANIC_CONN

AP_TO_LCM_RESET_CONN_L

CUMULUS_TO_PROX_RX_EN_1V8_CONN

LCM_TO_AP_HIFA_BSYNC_CONN

PP5V7_LCM_AVDDH

90_MIPI_AP_TO_LCM_DATA1_CONN_N

90_MIPI_AP_TO_LCM_DATA0_CONN_P90_MIPI_AP_TO_LCM_DATA0_CONN_N

PN5V7_SAGE_AVDDN_CONN

LCM_TO_CHESTNUT_PWR_EN_CONN

90_MIPI_AP_TO_LCM_DATA1_CONN_P LCM_TO_AP_HIFA_BSYNC_CONNPMU_TO_LCM_PANIC_CONN

AP_TO_LCM_RESET_CONN_L

PP1V8_LCM_CONN

PP_LCM_BL_CAT2_CONN

LCD_TO_AP_PIFA_CONNPP_LCM_BL_ANODE_CONNPP_LCM_BL_CAT1_CONN90_MIPI_AP_TO_LCM_CLK_CONN_N

PN5V7_SAGE_AVDDN PN5V7_SAGE_AVDDN_CONN

PP5V7_LCM_AVDDH_CONN

PP5V7_LCM_AVDDH_CONNPP1V8_LCM_CONNPP1V8

DISPLAY FLEXSYNC_MASTER=N/A SYNC_DATE=N/A

28 3

56PF5%

01005ROOM=LCM_B2B

NP0-C0G16V

C42081

2

M-ST-SM

ROOM=LCM_B2BCRITICAL

BM15AP-0.8-22DP-0.35VJ4200

2324

2526

12345678910111213141516171819202122

ROOM=LCM_B2B01005

16V5%100PF

NP0-C0G

C42411

2

ROOM=LCM_B2B

16V5%

01005NP0-C0G

100PFC42221

2

ROOM=LCM_B2B01005NP0-C0G

100PF16V5%

C42211

2

70-OHM-25%-0.28A

ROOM=LCM_B2B01005

FL420712

ROOM=LCM_B2B

240OHM-350MA

0201

FL420012

0201ROOM=LCM_B2B

240OHM-350MAFL4205

12

0201

240OHM-350MA

ROOM=LCM_B2B

FL42131 2

0201

240OHM-350MA

ROOM=LCM_B2B

FL42121 2

0201

240OHM-350MA

ROOM=LCM_B2B

FL42111 2

CRITICAL

65-OHM-0.1A-0.7-2GHZTAM0605

ROOM=LCM_B2B

L42021

23

4

65-OHM-0.1A-0.7-2GHZ

CRITICAL

TAM0605

ROOM=LCM_B2B

L42011

23

4

65-OHM-0.1A-0.7-2GHZTAM0605

CRITICAL

ROOM=LCM_B2B

L42001

23

4

X5R-CERM

ROOM=LCM_B2B

2.2UF

0201

6.3V20%

C42051

2

ROOM=LCM_B2B

120-OHM-210MA01005

FL42411 229

5%100PF

01005NP0-C0G35V

ROOM=LCM_B2B

C42131

2

5%

01005NP0-C0G35V100PF

ROOM=LCM_B2B

C42121

2

26 16

16

0201

6.3V

ROOM=LCM_B2B

20%

X5R-CERM

2.2UFC42031

2

ROOM=LCM_B2B

20%

X5R-CERM0201

6.3V

2.2UFC4202 1

2

2.2UF

ROOM=LCM_B2B

X5R-CERM0201

6.3V20%

C4201 1

2

ROOM=LCM_B2B

2.2UF20%

6.3VX5R-CERM

0201

C4200 1

2

33 29 9 8

8

7

7

7

7

7

7

100PF

ROOM=LCM_B2B

NP0-C0G16V

01005

5%

C42041

2

ROOM=LCM_B2B

100PF5%

16VNP0-C0G

01005

C42071

2

ROOM=LCM_B2B

100PF16V

NP0-C0G01005

5%

C42061

2

35V5%100PF

01005NP0-C0G

ROOM=LCM_B2B

C42111

2

ROOM=LCM_B2B

120-OHM-210MA

01005

FL422212

ROOM=LCM_B2B01005

120-OHM-210MAFL4230

12

ROOM=LCM_B2B01005NP0-C0G5%56PF16V

C42301

2

ROOM=LCM_B2B

100K

MF01005

1/32W1%

R4220 1

2

ROOM=LCM_B2B01005

120-OHM-210MAFL4221

12

ROOM=LCM_B2B01005

16VNP0-C0G

100PF5%

C42201

2

ROOM=LCM_B2B

120-OHM-210MA

01005

FL422012

28

29

28 3

28

28

28

28

28

28

28

26

26

26

28 3

28 3

28

28

20

28

26

28

28

28

28

28

28 28

28

28

28

28 3

28 3

28 3

28 3 28

29 26 28

28

28

28 29 21

20 14 13 129 8 7 6 5 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

SYM_VER-2

SYM_VER-2

SYM_VER-2

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

Page 29: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

THESE ARE ROUTED TOGETHER

VGH

GS0

VGL

APN: 343S0645 (CD3246C0, T6)

3.5V

SAGE2 C0

NOTE: LCM_TO_AP_HIFA_BSYNC_BUFF

C1

516S1070 RCPT

R18

R12

C5

GS2

VGH_REF

C6

VGL_REF

ON MLB ->

R9

R0_LEFT

13.5V

C0

-12V

R2

R3

R4

R10

R7

C2

R19

R11

C9

R15

R17

R13

R14

GS3

C7

GS4

R0_RIGHT

R8

R6

GS1

C3

C4

C8

VCOM

R16

SPECIAL - CANNOT SWAP

516S1071 PLUGON FLEX-> TOUCH B2B

5.45-5.98V

D403 (B2B,DRIVER ICS)

TO CLAMP THENEGATIVE RAILCUMULUS C1

(TURN OFF SAME TIME AS PP1V8_TOUCH)

SPECIAL - CANNOT SWAP

(TURN ON LATER THAN PP1V8_TOUCH)

R5

R1

343S0638

29 OF 60

43 OF 49

4.0.0

051-00648

CUMULUS_TO_SAGE_VSTM_OUT<13>

TOUCH_TO_SAGE_SENSE_IN<14>

SAGE_TO_TOUCH_VSTM_OUT<2>

SAGE_TO_TOUCH_VSTM_OUT<19>

SAGE_TO_TOUCH_VSTM_OUT<9>

SAGE_TO_TOUCH_VSTM_OUT<0>

SAGE_TO_TOUCH_VSTM_OUT<10>

LCM_TO_AP_HIFA_BSYNC

SAGE_TO_TOUCH_VSTM_OUT<4>

SAGE_TO_TOUCH_VSTM_OUT<17>

SAGE_TO_TOUCH_VSTM_OUT<15>

SAGE_TO_TOUCH_VSTM_OUT<1>

SAGE_TO_TOUCH_VSTM_OUT<12>

SAGE_TO_TOUCH_VSTM_OUT<6>

SAGE_TO_TOUCH_VSTM_OUT<8>

SAGE_TO_TOUCH_VSTM_OUT<14>

SAGE_TO_TOUCH_VSTM_OUT<13>

SAGE_TO_TOUCH_VSTM_OUT<16>

SAGE_TO_TOUCH_VSTM_OUT<3>

CUMULUS_TO_SAGE_VSTM_OUT<1>

SAGE_TO_CUMULUS_IN<1>

SAGE_TO_CUMULUS_IN<8>

SAGE_TO_CUMULUS_IN<14>

SAGE_TO_CUMULUS_IN<9>

TOUCH_TO_SAGE_SENSE_IN<6>

CUMULUS_TO_SAGE_VSTM_OUT<16>

CUMULUS_TO_SAGE_VSTM_OUT<16>

TOUCH_TO_SAGE_VCM_IN

PP5V7_SAGE_AVDDH

LCM_TO_AP_HIFA_BSYNC_BUFF

PP1V8_CUMULUS_VDDLDO

PP1V8_CUMULUS_VDDLDO

PP_SAGE_LY

PP_SAGE_TO_TOUCH_VCPH

PP5V7_SAGE_AVDDH

CUMULUS_TO_SAGE_VSTM_OUT<0>

PP_SAGE_VCPL_F

TOUCH_TO_SAGE_SENSE_IN<12>

SAGE_TO_TOUCH_VSTM_OUT<11>

TOUCH_TO_SAGE_SENSE_IN<13>

TOUCH_TO_SAGE_SENSE_IN<2>

CUMULUS_TO_PROX_RX_EN_1V8

CUMULUS_TO_SAGE_BOOST_EN

CUMULUS_TO_SAGE_VSTM_OUT<6>

TOUCH_TO_SAGE_SENSE_IN<7>

TOUCH_TO_SAGE_SENSE_IN<1>

CUMULUS_TO_SAGE_VSTM_OUT<5>

CUMULUS_TO_SAGE_BOOST_EN

U12_GPIO_3

CUMULUS_TO_SAGE_GCM_SEL

PP1V8_TOUCH

TOUCH_TO_SAGE_SENSE_IN<7>

45_PROX_TO_CUMULUS_RX_FILT

SAGE_TO_CUMULUS_IN<1>

TOUCH_TO_SAGE_SENSE_IN<10>

TOUCH_TO_SAGE_SENSE_IN<0>

SAGE_TO_CUMULUS_IN<12>

SAGE_TO_CUMULUS_IN<7>

SAGE_TO_CUMULUS_IN<4>

SAGE_TO_CUMULUS_IN<5>

SAGE_TO_CUMULUS_IN<0>

SAGE_TO_CUMULUS_IN<14>

CUMULUS_TO_SAGE_VSTM_OUT<11>

CUMULUS_TO_SAGE_VSTM_OUT<8>

TOUCH_TO_SAGE_SENSE_IN<5>

CUMULUS_TO_SAGE_VSTM_OUT<17>

CUMULUS_TO_SAGE_VSTM_OUT<2>

CUMULUS_TO_SAGE_VSTM_OUT<3>

CUMULUS_TO_SAGE_VSTM_OUT<4>

45_PROX_TO_CUMULUS_RX

SAGE_TO_CUMULUS_IN<8>

SAGE_TO_CUMULUS_IN<6>

SAGE_TO_CUMULUS_IN<3>

CUMULUS_TO_SAGE_GCM_SEL

CUMULUS_TO_SAGE_VSTM_OUT<13>

SAGE_TO_CUMULUS_IN<4>

SAGE_TO_CUMULUS_IN<3>

SAGE_TO_CUMULUS_IN<5>

SAGE_TO_CUMULUS_IN<0>

SAGE_TO_CUMULUS_IN<7>

SAGE_TO_CUMULUS_IN<10>

SAGE_TO_CUMULUS_IN<11>

SAGE_TO_CUMULUS_IN<2>

SAGE_TO_CUMULUS_IN<13>

SAGE_TO_CUMULUS_IN<6>

SAGE_TO_TOUCH_VSTM_OUT<11>

TOUCH_TO_SAGE_SENSE_IN<3>

TOUCH_TO_SAGE_SENSE_IN<11>

TOUCH_TO_SAGE_SENSE_IN<8>

TOUCH_TO_SAGE_SENSE_IN<13>

CUMULUS_TO_SAGE_VSTM_OUT<7>

CUMULUS_TO_SAGE_VSTM_OUT<12>

CUMULUS_TO_SAGE_VSTM_OUT<6>

CUMULUS_TO_SAGE_VSTM_OUT<18>

CUMULUS_TO_SAGE_VSTM_OUT<14>

TOUCH_TO_SAGE_SENSE_IN<9>

CUMULUS_TO_SAGE_VSTM_OUT<19>

SAGE_TO_TOUCH_VSTM_OUT<18>

SAGE_TO_TOUCH_VSTM_OUT<0>

SAGE_TO_TOUCH_VSTM_OUT<12>

SAGE_TO_TOUCH_VSTM_OUT<13>

SAGE_TO_TOUCH_VSTM_OUT<14>

SAGE_TO_TOUCH_VSTM_OUT<15>

SAGE_TO_TOUCH_VSTM_OUT<17>

TOUCH_TO_SAGE_SENSE_IN<14>

SAGE_TO_TOUCH_VSTM_OUT<0>

SAGE_TO_TOUCH_VSTM_OUT<2>

SAGE_TO_TOUCH_VSTM_OUT<4>

SAGE_TO_TOUCH_VSTM_OUT<8>

SAGE_TO_TOUCH_VSTM_OUT<6>

SAGE_TO_TOUCH_VSTM_OUT<5>

TOUCH_TO_SAGE_SENSE_IN<1>

TOUCH_TO_SAGE_SENSE_IN<3>

TOUCH_TO_SAGE_SENSE_IN<9>TOUCH_TO_SAGE_SENSE_IN<10>

TOUCH_TO_SAGE_VCM_IN

SAGE_TO_TOUCH_VCPL_REF

SAGE_TO_TOUCH_VCPH_REF

TOUCH_TO_SAGE_SENSE_IN<8>

SAGE_TO_TOUCH_VSTM_OUT<16>

SAGE_TO_TOUCH_VSTM_OUT<19>

PP1V8_TOUCH

CUMULUS_TO_PROX_TX_EN_1V8_L

SPI_AP_TO_TOUCH_CS_L

SPI_AP_TO_TOUCH_SCLK

SAGE_TO_TOUCH_VSTM_OUT<9>

TOUCH_TO_SAGE_SENSE_IN<2>

TOUCH_TO_SAGE_SENSE_IN<6>

SAGE_TO_TOUCH_VSTM_OUT<3>

SAGE_TO_TOUCH_VSTM_OUT<1>

CUMULUS_TO_SAGE_VSTM_OUT<19>

CUMULUS_TO_SAGE_VSTM_OUT<15>

CUMULUS_TO_SAGE_VSTM_OUT<0>

CUMULUS_TO_SAGE_VSTM_OUT<12>

CUMULUS_TO_SAGE_VSTM_OUT<8>

CUMULUS_TO_SAGE_VSTM_OUT<4>

CUMULUS_TO_SAGE_VSTM_OUT<1>

CUMULUS_TO_SAGE_VSTM_OUT<14>

TOUCH_TO_SAGE_SENSE_IN<12>

PP1V8

CUMULUS_TO_PROX_TX_EN_1V8_L

LCM_TO_AP_HIFA_BSYNC

PP1V8_TOUCH

SAGE_TO_CUMULUS_IN<9>

SAGE_TO_CUMULUS_IN<10>

SAGE_TO_CUMULUS_IN<11>

SAGE_TO_CUMULUS_IN<12>

TOUCH_TO_AP_SPI1_MISO_R

CUMULUS_TO_PROX_TX_EN_BUFF

SPI_AP_TO_TOUCH_MOSI

SPI_TOUCH_TO_AP_MISO

45_AP_TO_TOUCH_CLK32K_RESET_L 45_AP_TO_TOUCH_CLK32K_RESET_L_XW

PN_SAGE_TO_TOUCH_VCPL

SAGE_TO_CUMULUS_IN<13>

TOUCH_TO_SAGE_SENSE_IN<5>

TOUCH_TO_SAGE_SENSE_IN<11>

TOUCH_TO_SAGE_SENSE_IN<0>

TOUCH_TO_SAGE_SENSE_IN<4>

SAGE_TO_TOUCH_VSTM_OUT<7>

SAGE_TO_TOUCH_VSTM_OUT<10>

PN5V7_SAGE_AVDDN

PP_SAGE_VBST_OUTH

PN_SAGE_VBST_OUTL

PN_SAGE_TO_TOUCH_VCPL

PP_SAGE_TO_TOUCH_VCPH

PN5V7_SAGE_AVDDN_INT

PP_SAGE_LX

SAGE_TO_TOUCH_VCPL_REF

SAGE_TO_TOUCH_VCPH_REF

SAGE_VBIAS

CUMULUS_TO_SAGE_VSTM_OUT<17>

CUMULUS_TO_SAGE_VSTM_OUT<18>

CUMULUS_TO_SAGE_VSTM_OUT<5>

CUMULUS_TO_SAGE_VSTM_OUT<2>

SAGE_TO_TOUCH_VSTM_OUT<7>

SAGE_TO_TOUCH_VSTM_OUT<18>

CUMULUS_TO_SAGE_VSTM_OUT<15>

SAGE_TO_TOUCH_VSTM_OUT<5>

SAGE_TO_CUMULUS_IN<2>

CUMULUS_TO_SAGE_VSTM_OUT<11>

CUMULUS_TO_SAGE_VSTM_OUT<7>

CUMULUS_TO_SAGE_VSTM_OUT<3>

CUMULUS_TO_SAGE_VSTM_OUT<9>

TOUCH_TO_SAGE_SENSE_IN<4>

CUMULUS_TO_SAGE_VSTM_OUT<10>

AP_TO_TOUCH_RESET_L

45_PROX_TO_CUMULUS_RX_IN

PP_CUMULUS_VDDCORE

PP5V1_GRAPE_VDDH

PP_CUMULUS_VDDANA

TOUCH_TO_AP_INT_L

D403 (TOUCH B2B, DRIVER ICS)

ROOM=SAGE0402-1

20%10UF

X5R-CERM10V

C43171

2

74AUP2G3404GNSOT1115

ROOM=CUMULUS

U4302

16

34

25

ROOM=CUMULUS

1% MF

22.1K

010051/32W

R43011 2

ROOM=CUMULUS01005

MF10.2 1/32W

1%

R43021 2

16V10%

ROOM=SAGE

1UF

0402X6S-CERM

C43091

2 16V

0402

10%1UF

X6S-CERM

ROOM=SAGE

C43111

2

ROOM=SAGE

X6S-CERM

1UF16V10%

0402

C43161

210%

ROOM=SAGE0201

16VX5R-CERM

0.1UFC43071

2

6.3VX5R-CERM

1000PF

01005

10%

ROOM=CUMULUS

C43011 2

ROOM=SAGE

X5R-CERM16V

0.1UF

0201

10%

C4325 1

2

ROOM=CUMULUS

SMXW4302

1 2

X5R

20%

ROOM=CUMULUS

1.0UF6.3V

0201-1

C43061

2

10%0.1UF

X5R-CERM

ROOM=SAGE

16V

0201

C43081

2

16VNP0-C0G

5%

01005ROOM=CUMULUS

27PFC4303 1

2

5%

ROOM=CUMULUS01005MF1/32W

100KR43031

2

4.7UF20%6.3V

ROOM=CUMULUS402X5R-CERM1

C43041

2

4.7UF20%

X5R-CERM16.3V

402ROOM=CUMULUS

C43051

2

ROOM=CUMULUS

MF01005

5%1/32W

100KR4305 1

2

01005

ROOM=CUMULUS

MF1/32W

100K5%

R43061

2

ROOM=CUMULUS

1/32WMF01005

5%

220KR4304

1 2

0.01UF10%

01005X5R

ROOM=SAGE

6.3V

C4313 1

2

0.01UF

ROOM=SAGE01005

10%

X5R6.3V

C4310 1

2

ROOM=SAGEGDZ-0201

GDZT2R6.2BDZ4301A

K

SM

P4MM-NSMROOM=SAGE

PP43061

M-ST-SMAA21

ROOM=TOUCH_B2BJ4300

1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 42

43 44

45 46

SM

P4MM-NSMROOM=SAGE

PP43051

10UF20%

ROOM=SAGE0402-4

X5R-CERM10V

C4323 1

2

X5R-CERM0201

ROOM=SAGE

10%25V

0.01UFC4326 1

2

0.1UF10%

6.3VCERM-X5R

0201ROOM=SAGE

C4318 1

2

ROOM=CUMULUSSM

P2MM-NSMPP4302 1

ROOM=CUMULUSSM

P2MM-NSMPP4301 1

ROOM=SAGE

20%25VTANT

0603-LLP

1UF-10OHMC4315 1

2

ROOM=CUMULUS

SMXW4301

1 2

10UF

0402-1ROOM=SAGE

X5R-CERM10V20%

C43121

2

1/32W

ROOM=SAGE

1%

4.7

MF01005

R43071 2

ROOM=SAGE

SAGE2-C06CSP

U4300

C2 B3 F4 F8 E3 L5

D2 A3 F3 F6 H5

B2

K5

G1H1J1K1L1G2H2J2K2L2L3K3J3H3G3L4K4J4H4G4

G6H6J6K6L6G7H7J7K7L7L8K8J8H8G8L9K9J9H9G9

F9

F7

F5G5

C1D1

E4D4C4B4A4A6B6C6D6E6E8D8C8B8A8

E5D5C5B5A5A7B7C7D7E7E9D9C9B9A9

D3

B1E1

J5

A1

A2

F1 E2

F2

C3

0.1UF

ROOM=SAGE01005

6.3V20%

X5R-CERM

C43271

2

SM

P4MM-NSMROOM=SAGE

PP43041

P4MM-NSMROOM=CUMULUS

SM PP43031

0402-1

10VX5R-CERM

ROOM=CUMULUS

20%10UFC43021

2

ROOM=SAGE

10UH-0.32A-1.56OHMPSB12101T-SM

L4301

1

2

10%16V

X5R-CERM

0.1UF

ROOM=SAGE0201

C4324 1

2

20%

0402

20VTANT

ROOM=SAGE0.33UFC4314 1

2

1000PF25V10%

X7R-CERM0201

ROOM=SAGE

C4320 1

2 25VX7R-CERM

10%

ROOM=SAGE0201

1000PFC4322 1

2

ROOM=SAGE

25VX7R-CERM

0201

10%1000PFC4319 1

2 25V10%

0201ROOM=SAGE

X7R-CERM

1000PFC4321 1

2

ROOM=CUMULUS

CUMULUS-C1WLBGA

U4301

E3D1

C7 C9 G2

G1D4F2F3

E4F1D3D2E1

B9B8A9B7B6A8B5B4A7B3A6A3A5A4B2A2

C4C3E2C6

D9

C2G3

B1 C1 C8 C5 F4 A1

E9E5F7E6E7F8G9D6D7D8F9D5F6F5G4E8G8G7G6G5

29

29

29

29

29

29

29

33 29 28 9 8

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29 26

29

29

29

29 26

29

29

29

29

29

28

29

29

29

29

29

29

29

29 14

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

20

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29 29

29

29

29

29

29

29

29 14

29

8

8

29

29

29

29

29

29

29

29

29

29

29

29

29

29

28 21 20 14 13 12 9 8 7 6 5 3

29

33 29 28 9 8

29 14

29

29

29

29

20

8

8

8

29 28

29

29

29

29

29

29

29

28 26

29 28

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

29

8

26

8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.1Y

GND

2Y 2A

1A

VCC

PP

PP

NCNC

NC

NC

PP

PP

BSYNC

DRV_OUT14

BOOST_EN

VCM_IN

AVDD

H1

DRV_OUT3

AVDD

H2AV

DDH3

AVDD

H4

SNS_IN0

SNS_IN2SNS_IN3SNS_IN4SNS_IN5

I2C_SDA

GCM_TEST

I2C_SCL

SNS_IN7

SNS_IN9

DRV_IN13

VDDI

O

VCPL

_F

VCPL

VCPH

SNS_OUT12

SNS_OUT0SNS_OUT1SNS_OUT2

SNS_OUT4SNS_OUT3

SNS_OUT5SNS_OUT6SNS_OUT7SNS_OUT8SNS_OUT9

SNS_OUT11SNS_OUT10

SNS_OUT13SNS_OUT14

DRV_OUT1DRV_OUT0

DRV_OUT2

DRV_OUT4DRV_OUT5DRV_OUT6DRV_OUT7

DRV_OUT9DRV_OUT8

DRV_OUT10DRV_OUT11DRV_OUT12DRV_OUT13

DRV_OUT16DRV_OUT15

DRV_OUT18DRV_OUT19

DRV_OUT17

GO

AGND

4AG

ND5

AGND

3AG

ND2

AGND

1

SNS_IN1

SNS_IN8

SNS_IN6

SNS_IN14SNS_IN13SNS_IN12SNS_IN11SNS_IN10

DRV_IN3DRV_IN4

DRV_IN2DRV_IN1DRV_IN0

DRV_IN9DRV_IN8DRV_IN7DRV_IN6DRV_IN5

DRV_IN14DRV_IN15

DRV_IN12DRV_IN11DRV_IN10

DRV_IN16

DRV_IN18DRV_IN17

DRV_IN19

VBIAS

L_YL_X

VCPH_REF/ENVCPL_REF/EN

VBST_OUTHVBST_OUTL

AVDD

L1

AGND

6

PP

PP

VDDH

IN8_0VSTM_9VSTM_8VSTM_7VSTM_6VSTM_5VSTM_4VSTM_3VSTM_2

VSTM_16VSTM_15

VSTM_13VSTM_12VSTM_11VSTM_10

VSTM_1VSTM_0

VDDIO

VDDC

ORE

VDDA

NA

RSTOVR*

IN9_0

IN7_0IN6_0IN5_0IN4_0IN3_0IN2_0

IN14_1IN14_0IN13_0IN12_0IN11_0IN10_0

IN1_0

H_SDOH_SDIH_SCLKH_INT*

GPIO_4GPIO_3

GPIO_2/SDGPIO_1/CK

GND

VSTM_18VSTM_19

TM_OVR

VSTM_17

IN0_0

H_CS*

VSTM_14VD

DLDO

JTAG_TMSJTAG_TDOJTAG_TDIJTAG_TCK

CLKIN/RESET*BCFG_RTCK

TM_ACS*

Page 30: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

TRISTAR 2 (A3)APN:343S0695

30 OF 60

45 OF 49

4.0.0

051-00648

PMU_TO_OWL_ACTIVE_READY

TRISTAR_CON_DETECT_L

PP3V0_TRISTAR

TRISTAR_TO_PMU_HOST_RESET

TRISTAR_TO_PMU_USB_BRICK_ID

UART_AP_TO_ACCESSORY_TXD

SWD_DOCK_TO_AP_SWCLK

UART_AP_DEBUG_RXD

90_USB_BB_DATA_N

90_USB_AP_DATA_P

TRISTAR_USB_BRICK_ID_R

90_MIKEYBUS_DATA_P

90_USB_AP_DATA_N

UART_AP_DEBUG_TXD

SWD_DOCK_BI_AP_SWDIO

90_USB_BB_DATA_P90_TRISTAR_DP1_CONN_P90_TRISTAR_DP1_CONN_N

90_TRISTAR_DP2_CONN_P90_TRISTAR_DP2_CONN_N

TRISTAR_TO_TIGRIS_VBUS_OFFUART_ACCESSORY_TO_AP_RXD

90_MIKEYBUS_DATA_N

I2C1_AP_SCL

TRISTAR_BYPASS

I2C1_AP_SDA

TRISTAR_TO_AP_INT

PP_TRISTAR_PINPP_TRISTAR_ACC1PP_TRISTAR_ACC2

PP5V0_USB

REVERSE_GATE

TRISTAR_TO_TIGRIS_VBUS_OFF

PP3V3_ACC

PP1V8_SDRAM

I/O:TRISTAR 2SYNC_DATE=N/ASYNC_MASTER=N/A

20%X5R

1.0UF6.3V

0201-1ROOM=TRISTAR

C45041

2

6.3V

01005X5R

ROOM=TRISTAR

0.01UF10%

C45021

2

ROOM=TRISTARP3MM-NSM

SM PP45001

CBTL1610A3UK

ROOM=TRISTAR

WLCSP

CRITICAL

U4500

C5E5

D5

C2

E6

E3

C4C3

B2

B4

A2

A4

A6C1F5

B6

C6A5B5

F6

D6

D4D3

E4

E1E2

F1F2

D1D2

B3A3

B1A1

F3 F4

20%1UF

ROOM=TRISTAR0201CER-X5R16V

C45031

2

23

23

CSD68822F4

CRITICAL

0402ROOM=TRISTAR

Q4500

3

1

210K5%1/32W

ROOM=TRISTAR01005MF

R45001

2

31 3

31 3

31 3

31 3

31 3

25 17 8

25 17 8

ROOM=PMU01005MF

1/32W1%

6.34KR4510

1 216

0.01UF

01005X5R6.3V10%

ROOM=PMU

C45101

2

26 16 9 5

16

16 8

8

8

8

8

5

5

5

5

33

33

30 17

20%0.1UF

01005X5R-CERM6.3V

ROOM=TRISTAR

C45011

220%X5R

1.0UF

ROOM=TRISTAR

6.3V

0201-1

C45001

2

33 31 26 15

31 3

31 3

31 17 3

30 17

15

33 26 24 17 16 15 14 12 8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

PP

BRICK_ID

POW_GATE_EN*

BYPASS

SCLINT

SDA

SWITCH_ENHOST_RESET

CON_DET_L

DN2DP2

DN1DP1

ACC2ACC1P_IN

VDD_

1V8

VDD_

3V0

ACC_

PWR

JTAG_DIO

UART2_RX

JTAG_CLK

UART1_RX

UART2_TX

UART0_RX

UART1_TX

USB0_DN

UART0_TX

USB0_DP

USB1_DNUSB1_DP

DIG_DN

DVSS

DVSS

DVSS

DIG_DPBI

BI

D

S

G

BI

BI

BI

BI

IN

BI

IN

OUT

IN

OUT

OUT

IN

OUT

IN

OUT

BI

OUT

BI

BI

BI

BI

OUT

Page 31: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

LOWER MIC1

DOCK FLEX CONNECTOR

TRISTAR

AUDIO JACKANTENNA

SPEAKER

DOCK FLEX CONNECTOR THIS ONE ON MLB --->

516S00117 (PLUG)

516S00116 (RCPT)

31 OF 60

VOLTAGE=5.0V

46 OF 49

4.0.0

051-00648

CODEC_TO_HPHONE_HS4_CONN

LOWERMIC1_TO_CODEC_AIN1_CONN_PBB_LAT_GPIO2_CONN

90_TRISTAR_DP2_CONN_PCODEC_TO_HPHONE_HS3_REF_CONN

CODEC_TO_HPHONE_R_CONNCODEC_TO_HPHONE_HS3_CONN

PP3V1_MESA_CONN

SPI_AP_TO_MESA_MOSI_CONN

PP_TRISTAR_ACC2_CONNPP_TRISTAR_ACC1_CONN

TRISTAR_CON_DETECT_CONN_L

90_TRISTAR_DP2_CONN_N90_TRISTAR_DP1_CONN_N90_TRISTAR_DP1_CONN_P

BB_LAT_GPIO1_CONNBB_LAT_GPIO2_CONN

PP3V0_LAT_CONNHPHONE_TO_CODEC_DETECT_CONN

MESA_TO_AP_INT_CONN

BUTTON_MENU_KEY_CONN_LSPI_AP_TO_MESA_SCLK_CONN

MESA_TO_BOOST_EN_CONN

SPI_MESA_TO_AP_MISO_CONN

PP11V3_MESA_CONNSPEAKERAMP_TO_SPEAKER_OUT_NEG

SPEAKERAMP_TO_SPEAKER_OUT_POS

PP1V9_MESA_CONN

CODEC_TO_HPHONE_R

BB_LAT_GPIO2

SPEAKERAMP_TO_SPEAKER_OUT_NEG

PP3V0_LAT_CONN

PP_TRISTAR_ACC2

PP_CODEC_TO_LOWERMIC1_BIAS_CONN

PP_TRISTAR_ACC1_CONN

PP3V0_TRISTAR

CODEC_TO_HPHONE_HS4_REF_CONN

CODEC_TO_HPHONE_HS3_REF_CONN

LOWERMIC1_TO_CODEC_AIN1_CONN_P

TRISTAR_CON_DETECT_L

PP_CODEC_TO_LOWERMIC1_BIAS

LOWERMIC1_TO_CODEC_AIN1_P

LOWERMIC1_TO_CODEC_AIN1_N

TRISTAR_CON_DETECT_CONN_L

PP_TRISTAR_ACC2_CONN

CODEC_TO_HPHONE_HS3_REF

CODEC_TO_HPHONE_HS4_REF

CODEC_TO_HPHONE_L_CONN

CODEC_TO_HPHONE_R_CONN

CODEC_TO_HPHONE_L

CODEC_TO_HPHONE_HS3

CODEC_TO_HPHONE_HS4

CODEC_TO_HPHONE_HS3_CONN

HPHONE_TO_CODEC_DETECT_CONNHPHONE_TO_CODEC_DETECT

CODEC_TO_HPHONE_HS4_CONN

PP_TRISTAR_ACC1

LOWERMIC1_TO_CODEC_AIN1_CONN_N

BB_LAT_GPIO1 BB_LAT_GPIO1_CONN

SPEAKERAMP_TO_SPEAKER_OUT_POS

LOWERMIC1_BIAS_FILT_RETPP_CODEC_TO_LOWERMIC1_BIAS_CONNLOWERMIC1_TO_CODEC_AIN1_CONN_N

CODEC_TO_HPHONE_L_CONNCODEC_TO_HPHONE_HS4_REF_CONN

PP5V0_USB

SYNC_DATE=N/A

I/O:DOCK FLEX B2BSYNC_MASTER=N/A

120-OHM-210MA

01005ROOM=DOCK_B2B

FL462012

ROOM=DOCK_B2B01005

120-OHM-210MAFL4624

1 2

ROOM=DOCK_B2B

6.8V-100PF01005

NO_XNET_CONNECTION=1

DZ46101

2

ROOM=DOCK_B2B

6.8V-100PF01005

NO_XNET_CONNECTION=1

DZ46041

2

FERR-33-OHM-0.8A-0.09-OHM

0201ROOM=DOCK_B2B

FL46051 2

FERR-33-OHM-0.8A-0.09-OHM

0201ROOM=DOCK_B2B

FL46041 2

ROOM=DOCK_B2B

5%56PF16VNP0-C0G01005

C46241

2

X7R-CERM0201

220PF10%25V

ROOM=DOCK_B2B

C4655 1

2

ROOM=DOCK_B2B01005

100PF5%

35VNP0-C0G

C4654 1

2

ROOM=DOCK_B2B

F-ST-SMAA27D-S038VA1

CRITICAL

J4600

3940

4142

1234567891011121314151617181920212223242526272829303132333435363738

0.1UF10%25VX5R

0201ROOM=DOCK_B2B

C4652 1

210%25V

0.1UF

X5R0201

ROOM=DOCK_B2B

C4651 1

2

120-OHM-210MA

01005ROOM=DOCK_B2B

FL46081 2

16V5%56PF

NP0-C0G

ROOM=DOCK_B2B01005

C46011

2

33

16V

100PF5%

ROOM=DOCK_B2B01005NP0-C0G

C46121

2

16V56PF

NP0-C0G01005

5%

ROOM=DOCK_B2B

C46001

2

FERR-33-OHM-0.8A-0.09-OHM

ROOM=DOCK_B2B0201

FL46011 2

FERR-33-OHM-0.8A-0.09-OHM

0201ROOM=DOCK_B2B

FL46001 2

220PF

X7R-CERM10%10V

ROOM=DOCK_B2B01005

C46961

2

01005X7R-CERM10V220PF10%

ROOM=DOCK_B2B

C46971

2

10V10%X7R-CERM

220PF

ROOM=DOCK_B2B01005

C46981

2

220PF

ROOM=DOCK_B2B

X7R-CERM10%10V

01005

C46991

2

600-OHM-25%-0.28A-0.75OHM

0201ROOM=DOCK_B2B

FL46031 2

ROOM=DOCK_B2B0201

600-OHM-25%-0.28A-0.75OHMFL4602

1 2

303

303

303

303

ROOM=DOCK_B2B

10-OHM-1.1A

01005

FL46411 2

10-OHM-1.1A

01005ROOM=DOCK_B2B

FL46421 2

ROOM=DOCK_B2B01005

NP0-C0G-CERM

56PF5%

25V

C4653 1

2X5R10%25V

ROOM=DOCK_B2B0201

0.1UFC4650 1

2

30 3 23

23

23

23

23

23

23

23

23

33

16V

ROOM=DOCK_B2B

NP0-C0G01005

100PF5%

C46421

2

100PF

ROOM=DOCK_B2B

16VNP0-C0G

01005

5%

C46411

2

16V

ROOM=DOCK_B2B

NP0-C0G01005

100PF5%

C46201

2

01005ROOM=DOCK_B2B

5%100PF

NP0-C0G16V

C46351

2

5%

ROOM=DOCK_B2B

100PF

NP0-C0G01005

16V

C46341

2

ROOM=DOCK_B2B010051.00K

1/32W

MF5%

R464012

ROOM=DOCK_B2B

27PF16VNP0-C0G01005

5%

C46401

2

01005ROOM=DOCK_B2B

NO_XNET_CONNECTION=1

6.8V-100PFDZ46031

2

ROOM=DOCK_B2B010056.8V-100PF

NO_XNET_CONNECTION=1

DZ46021

2

ROOM=DOCK_B2B

6.8V-100PF01005

NO_XNET_CONNECTION=1

DZ46011

2

1/32WMF

3.3K

ROOM=DOCK_B2B01005

5%

R46001 2

NO_XNET_CONNECTION=1ROOM=DOCK_B2B

6.8V-100PF01005

DZ46001

2

120-OHM-210MA

ROOM=DOCK_B2B01005

FL461212

ROOM=DOCK_B2B01005

120-OHM-210MAFL4611

12

ROOM=DOCK_B2B

56PF16VNP0-C0G01005

5%

C46111

2

ROOM=DOCK_B2B

16VNP0-C0G01005

5%56PFC46101

2

ROOM=DOCK_B2B01005

120-OHM-210MAFL4610

12

31

31 31

31

31

31

27

27

31

31

31

31

31

31

31

27

27

27

27

27

27

31 25

31 25

27

31 25

31

30 3

31

31

33 30 26 15

31

31

31

24

31

31

31

31

31

31

31

30 3

31

31

31 25

24

31

31

31

31

30 17 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NCNC

IN

BI

BI

BI

BI

OUTIN

IN

OUT

OUT

BI

BI

OUT

OUT

OUT

IN

Page 32: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

STROBE:

MODULE NTC

ANC REF MIC

HOLDRINGER

WARM LEDCOOL LED

VOL UP/DOWN

BUTTONS:

MIC2

BUTTON FLEX

THIS ONE ON MLB --->

BUTTON FLEX CONNECTOR

516S1041 (RCPT)

516S1040 (PLUG)

32 OF 60

47 OF 49

4.0.0

051-00648

PP_LED_DRIVER_COOL_LED

BUTTON_VOL_UP_CONN_LVIBE_RETURN

REARMIC2_TO_CODEC_AIN3_CONN_NREARMIC2_TO_CODEC_AIN3_CONN_PPP_CODEC_TO_REARMIC2_BIAS_CONN

LED_MODULE_NTC_CONN

BUTTON_VOL_DOWN_CONN_LBUTTON_RINGER_A_CONN

PP3V1_VIBE

BUTTON_HOLD_KEY_CONN_L

PP_LED_DRIVER_WARM_LED

PP_CODEC_TO_REARMIC2_BIAS_CONN

REARMIC2_TO_CODEC_AIN3_CONN_PREARMIC2_TO_CODEC_AIN3_P

REARMIC2_TO_CODEC_AIN3_CONN_N

BUTTON_HOLD_KEY_L

BUTTON_RINGER_A BUTTON_RINGER_A_CONN

BUTTON_HOLD_KEY_CONN_L

BUTTON_VOL_DOWN_L

BUTTON_VOL_UP_L

REARMIC2_TO_CODEC_AIN3_N

BUTTON_VOL_UP_CONN_L

PP_LED_DRIVER_COOL_LED

LED_MODULE_NTC

BUTTON_VOL_DOWN_CONN_L

PP_CODEC_TO_REARMIC2_BIAS

LED_MODULE_NTC_CONN

VIBE_PWM_G

PP_LED_DRIVER_WARM_LED

AP_TO_VIBE_TRIG

I/O:BUTTON FLEX B2BSYNC_MASTER=N/A SYNC_DATE=N/A

BUTTON_B2BCRITICAL

F-ST-SM205847-018

J4700

1920

2122

123456789101112131415161718

BUTTON_B2B

20%6.3V

402X5R-CERM1

4.7UFC47161

2

BUTTON_B2B01005

16VNP0-C0G

100PF5%

C47151

2

BUTTON_B2B

100PF5%16VNP0-C0G01005

C47141

2

100PF5%16VNP0-C0G01005BUTTON_B2B

C47031

2

1%10K

01005MF1/32W

BUTTON_B2B

R47011

2

SMXW4701

1 2 DMN3730UFB4DFN1006H4-3

BUTTON_B2B

Q4701

3

1

2

BAS40LPLLP-DFN1006-2

BUTTON_B2B

D4701A

K

ROOM=BUTTON_B2B

5%100PF

NP0-C0G16V

01005

C47201

2

ROOM=BUTTON_B2B

5%100PF

NP0-C0G16V

01005

C47001

2

22

16 8

ROOM=BUTTON_B2B02015.5V-6.2PFDZ4711

1

2

ROOM=BUTTON_B2B

5.5V-6.2PF0201

DZ47101

2

23

23

5%6.3V

NP0-C0G

ROOM=BUTTON_B2B0201

27PFC4710 1

2

8

16 8

16 8

5%6.3V

0201ROOM=BUTTON_B2B

NP0-C0G

27PFC4711 1

2

01005ROOM=BUTTON_B2B

51.1K

MF

1%1/32W

R47201

2

5%100PF

01005NP0-C0G

16V

ROOM=BUTTON_B2B

C4721 1

2

01005ROOM=BUTTON_B2B

120-OHM-210MAFL4720

1 2

5%

01005NP0-C0G

ROOM=BUTTON_B2B

27PF16V

C47221

2

5%100PF

01005NP0-C0G

16V

ROOM=BUTTON_B2B

C4723 1

25%

01005NP0-C0G

ROOM=BUTTON_B2B

16V27PFC47241

2

120-OHM-210MA

01005ROOM=BUTTON_B2B

FL470212

01005ROOM=BUTTON_B2B

120-OHM-210MAFL4701

12

5%NP0-C0G16V

ROOM=BUTTON_B2B01005

56PFC47021

2

ROOM=BUTTON_B2B

5%

01005NP0-C0G

56PF16V

C47011

2

120-OHM-210MA

01005ROOM=BUTTON_B2B

FL470012

5%100PF

01005

16VNP0-C0G

ROOM=BUTTON_B2B

C4713 1

2

ROOM=BUTTON_B2B01005

120-OHM-210MAFL4713

1 2

5%

01005

16V

ROOM=BUTTON_B2B

NP0-C0G

100PFC4712 1

2

01005

120-OHM-210MA

ROOM=BUTTON_B2B

FL47121 2

ROOM=BUTTON_B2B01005

120-OHM-210MAFL4711

1 2

ROOM=BUTTON_B2B

12V-33PF01005-1

DZ47131

2

12V-33PF01005-1

ROOM=BUTTON_B2B

DZ47121

2

01005

1/32W0%

MF

0.00

ROOM=BUTTON_B2B

R47101 2

32 22

32

32

32

32

32

32

32

15

32

32 22

32

32

32

32

32

32

32 22

32

24

32

32 22

8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

S

D

SYM_VER_1

G

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Page 33: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

BASEBAND, WLAN, BT & STOCKHOLM

33 OF 60

49 OF 49

4.0.0

051-00648

PP3V0_TRISTARPP1V8_SDRAMPMU_TO_BB_USB_VBUS_DETECT

UART_AP_TO_STOCKHOLM_TXDUART_STOCKHOLM_TO_AP_CTS_L

UART_AP_TO_STOCKHOLM_RTS_L

PMU_TO_STOCKHOLM_ENAP_TO_STOCKHOLM_DWLD_REQUEST

STOCKHOLM_TO_PMU_HOST_WAKE

UART_BB_TO_AP_CTS_L

UART_AP_TO_BB_TXDUART_BB_TO_AP_RXD

UART_AP_TO_WLAN_TXD

PMU_TO_WLAN_REG_ON

90_PCIE_AP_TO_WLAN_REFCLK_P90_PCIE_AP_TO_WLAN_TXD_N

UART_AP_TO_WLAN_RTS_LUART_WLAN_TO_AP_CTS_L

UART_WLAN_TO_AP_RXD

LCM_TO_AP_HIFA_BSYNC

I2S_BB_TO_AP_DIN

PMU_TO_BB_PMIC_RESET_L

BB_TO_AP_RESET_DETECT_L

UART_OWL_TO_BB_TXD

I2S_AP_TO_BB_DOUTI2S_AP_TO_BB_LRCLK

AP_TO_BB_RADIO_ON_L

PMU_TO_BT_REG_ON

90_USB_BB_DATA_P

BB_TO_PMU_HOST_WAKE_L

AP_TO_BB_HSIC_HOST_RDYBB_TO_AP_HSIC_DEVICE_RDY

45_I2S_AP_TO_BB_BCLK

45_PMU_TO_WLAN_CLK32K

OWL_TO_WLAN_CONTEXT_BOWL_TO_WLAN_CONTEXT_A

90_PCIE_WLAN_TO_AP_RXD_P90_PCIE_WLAN_TO_AP_RXD_N90_PCIE_AP_TO_WLAN_TXD_P

90_PCIE_AP_TO_WLAN_REFCLK_N

PCIE_WLAN_TO_AP_CLKREQ_L

PCIE_AP_TO_WLAN_DEV_WAKE

UART_BT_TO_AP_RXD

90_USB_BB_DATA_N

BB_TO_PMU_AMUX_SMPS4

BB_TO_PMU_AMUX_LDO11BB_TO_PMU_AMUX_LDO5

I2S_BT_TO_AP_DIN

UART_AP_TO_BT_RTS_LUART_BT_TO_AP_CTS_L

UART_AP_TO_BT_TXD

BT_TO_PMU_HOST_WAKEAP_TO_BT_WAKE

45_I2S_AP_TO_BT_BCLKI2S_AP_TO_BT_LRCLK

WLAN_TO_PMU_HOST_WAKE

PCIE_AP_TO_WLAN_RESET_LWLAN_TO_PMU_PCIE_WAKE_L

AP_TO_BB_WAKE_MODEM

AP_TO_BB_RESET_L

50_AP_BI_BB_HSIC0_STB

I2S_AP_TO_BT_DOUT

AP_TO_STOCKHOLM_DEV_WAKE

BB_LAT_GPIO1

BB_LAT_GPIO2

AP_TO_BB_COREDUMP

BB_TO_LED_DRIVER_GSM_BURST_IND

AP_TO_BB_MESA_ONBB_TO_AP_IPC_GPIO

UART_BB_TO_OWL_RXD

SWD_AP_BI_BB_SWDIOSWD_AP_PERIPHERAL_SWCLK

UART_AP_TO_BB_RTS_L

BB_TO_AP_GPS_TIME_MARK

PP_BATT_VCC

PP_VCC_MAIN BB_TO_PMU_AMUX_SMPS1PP1V8_SDRAM

UART_STOCKHOLM_TO_AP_RXD

50_AP_BI_BB_HSIC0_DATA

BASEBAND:RADIO SYMBOLSYNC_DATE=N/ASYNC_MASTER=N/A

RFI566

56 31 30 26 15

36 8

36 8

36 8

36 8

40 13 9

36 9

36 29 28 9 8

41 31

41 31

36 16

57 16

36 8

36 8

36 8

41 8

57 8

58 57 56 33 30 26 24 17 16 15 14 12 8

36 16

58 57 56 33 30 26 24 17 16 15 14 12 8

36 8

36 8

57 6

57 6

36 6

36 6

36 6

36 6

57 6

57 6

36 8

36 8

58 26 25 24 22 21 17 15 14

51 18 17 3

36 8

36 16

36 8

36 8

36 16

36 8

36 9

36 9

36 16

36 8

36 8

36 8

36 16

36 8

36 8

36 8

36 9

36 8

36 8

36 8

36 8

36 7

36 16

58 8

36 5

36 8

41 26 22

36 16

36 8

36 16

36 16

36 16

36 30

36 30

36 9

36 8

36 16

36 5

36 8

36 16

36 8

36 8

36 8

36 16

36 8

41 8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SHARED POWER

ANTENNA STOCKHOLM

RADIO_MLB

BASEBAND WLAN

N69 CELLULAR/WLAN/BT/STOCKHOLM SUBDESIGN SYMBOL

BLUETOOTH

50_BB_HSIC_DATA

PAC_VDD_3V0

PP_STOCKHOLM_1V8_S2RBB_USB_VBUSRFFE_VIO_S2RPP_WL_BT_VDDIO_AP

STOCKHOLM_UART_TXD

STOCKHOLM_UART_RXD

STOCKHOLM_UART_RTS

STOCKHOLM_UART_CTS

AP_TO_STOCKHOLM_EN

AP_TO_STOCKHOLM_FW_DWLD_REQSTOCKHOLM_TO_PMU_HOST_WAKE

BB_UART_RTS_L

BB_UART_RXDBB_UART_TXD

WLAN_UART_RXD

WLAN_REG_ON

90_WLAN_PCIE_REFCLK_P90_WLAN_PCIE_RDN

WLAN_UART_CTS_LWLAN_UART_RTS_L

WLAN_UART_TXD

BB_FORCE_PWM

BB_I2S_TXD

RF_PMIC_RESET_L

BB_RESET_DET_L

BB_OTHER_RXD

BB_I2S_RXDBB_I2S_WS

RADIO_ON_L

BT_REG_ON

90_BB_USB_P

BB_WAKE_HOST_L

BB_HOST_RDYBB_DEVICE_RDY

BB_I2S_CLK

CLK32K_AP

OSCAR_CONTEXT_BOSCAR_CONTEXT_A

90_WLAN_PCIE_TDP90_WLAN_PCIE_TDN

90_WLAN_PCIE_RDP

90_WLAN_PCIE_REFCLK_N

WLAN_PCIE_CLKREQ_L

PCIE_DEV_WAKE

BT_UART_TXD

90_BB_USB_N

ADC_SMPS4

ADC_PP_LDO11ADC_PP_LDO5

ADC_SMPS1

BT_PCM_OUT

BT_UART_CTS_LBT_UART_RTS_L

BT_UART_RXD

HOST_WAKE_BT

WAKE_BT

BT_PCM_CLKBT_PCM_SYNC

HOST_WAKE_WLAN

WLAN_PCIE_PERST_LWLAN_PCIE_WAKE_L

AP_WAKE_MODEM

BB_RST_L

50_BB_HSIC_STROBE

BT_PCM_IN

AP_TO_STOCKHOLM_DEV_WAKE

BB_LAT_GPIO1

BB_LAT_GPIO2

BB_CORE_DUMP

GSM_TXBURST_IND

AP_TO_BB_MESA_ON

BB_IPC_GPIO1

BB_OTHER_TXD

BB_JTAG_TMSBB_JTAG_TCK

BB_UART_CTS_L

BB_GPS_SYNC

PP_BATT_VCC

PP_VCC_MAIN

IN

IN

IN

OUT

OUT

IN

BI

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT

ININ

IN

IN

OUT

IN

BI

OUT

OUTIN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Page 34: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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8/19/2015N69 RADIO_MLB SUBDESIGN - EVT

34 OF 60

BASEBAND (1 OF 2)BASEBAND (1 OF 2)MOBILE DATA MODEM (2 OF 2)

STOCKHOLM

1

LAST_MODIFICATION=Wed Aug 19 10:34:24 2015

ANTENNA SWITCHHIGH BAND PAD

HIGH BAND SWITCH

BASEBAND PMU (2 OF 2)

RF TRANSCEIVER (2 OF 3)

page1

2G PA

MID BAND PAD

RX DIVERSITYRX DIVERSITY (2)GPSANTENNA FEEDSWIFI/BT: MODULE AND FRONT END

OMIT_TABLE_RFRadio Subdesign Ports

34353637383940414243

45464748495051525354555657585960

3

4

6

7

8

9

10

11

12

13

15

20

21

22

23

24

30

31

32

33

35

36

37

40

41

42

43

45

VERY LOW BAND PADLOW BAND PAD

44

5BASEBAND PMU (1 0F 2)

AP INTERFACE & DEBUG CONNECTORSCELL:ALIASES

RF TRANSCEIVER (3 OF 3)QFE DCDC

RF TRANSCEIVER (1 0F 3)

SCH,MLB,N69

051-00648

2015-08-2400047524174 ENGINEERING RELEASED

1 OF 55

4.0.0

?

SYNCCONTENTSPAGE DATE<CSA>

PROPRIETARY PROPERTY OF APPLE INC.

REVISION

ECNREV DESCRIPTION OF REVISION

DRAWING TITLE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

CKAPPD

2 1

1245678

B

D

6 5 4 3

C

A

PAGE

C

A

D

DATE

R

SHEET

DSIZEDRAWING NUMBER

BRANCH

7

B

3

II NOT TO REPRODUCE OR COPY IT

IV ALL RIGHTS RESERVED

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

NOTICE OF PROPRIETARY PROPERTY:

Apple Inc.

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

Page 35: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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. c h

i n a

f i x

. c o

m

BLANK PAGE

35 OF 60

30 OF 55

4.0.0

051-00648

CELL:ALIASES

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Page 36: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

mCORONA PCIE RX/TX TP

OPTIONAL

SIM CARD CONNECTOR

UNDER THE SIM

SIM CARD ESD PROTECTION

NOT UNDER SIMAP INTERFACE & DEBUG CONNECTORS

36 OF 60

PP3132_RFPP3131_RF

PP3140_RFPP3139_RF

PP3138_RF

PP3104_RF

PP3112_RF

PP3111_RF

PP3116_RF

PP3115_RF

PP3173_RF

PP3124_RF

PP3123_RF

PP3122_RF

PP3121_RF

PP3128_RF

PP3127_RF

PP3102_RF

PP3101_RF

PP3199_RF

PP3198_RF

PP3197_RF

PP3196_RF

PP3195_RF

PP3194_RF

PP3193_RF

PP3192_RF

PP3172_RF

PP3171_RF

PP3170_RF

PP3191_RF

PP3190_RF

C3102_RF

VR3101_RF

PP3158_RF

PP3157_RF

J3100_RF

PP3186_RF

PP3185_RF

PP3162_RF

PP3163_RF

PP3129_RF

PP3174_RF

PP3155_RF

PP3154_RF

PP3153_RF

PP3152_RF

PP3120_RF

PP3119_RF

PP3105_RF

36 41

DZ3102_RF

33 60

33 60

33 60

33 60

R3104_RFR3103_RFR3102_RF

C3101_RF

36 58

XW3104_RF

XW3103_RF

XW3102_RF

XW3101_RF36 41

36 41

36 41

R3101_RF

J3101_RF

31 OF 55

4.0.0

051-00648

11

11

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

21

4

3

2

1

5

1

1

50 4948 4746 4544 4342 4140 3938 3736 3534 3332 3130 2928 2726 2524 2322 2120 1918 1716 1514 1312 1110 9

8 76 54 32 1

54

53

52

51

1

1

1

1

1

1

1

1

1

1

1

1

1

21

2

1

2

1

2

1

2

1

21

21

21

21

2

1

1

6

2 7

513111098

123

WIFI_BT

WIFI_BT

WIFI_BT

WIFI_BT

BB_UART_RTS_LSM

P2MM-NSM

BB_COEX_UART_TXD

BB_DEBUG_ERROR

SM

P4MM-NSM

AXE650124

STOCKHOLM_TO_BBPMU_CLK_REQ

SM

STOCKHOLM

P2MM-NSM

SMP2MM-NSM

P4MM-NSM

BB_DEBUG_STATUS

P4MM-NSMSM

P4MM-NSMSM

P4MM-NSM

BB_JTAG_TMSSM

BB_JTAG_TCK_INSM

P4MM-NSMSM

BB_USB_VBUS

90_BB_USB_N

90_BB_USB_P

P4MM-NSM

P4MM-NSMMDM_CLKSM

SPMI_CLKSMP4MM-NSM

SPMI_DATASMP4MM-NSM

50_BB_HSIC_DATASM

50_BB_HSIC_STROBE

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSM

WIFI_BT

SM

P2MM-NSMSM

WIFI_BT

P2MM-NSM

STOCKHOLM

SM

P2MM-NSM

STOCKHOLM

SM

WIFI_BT

P2MM-NSM

WIFI_BT

P2MM-NSMSM

P2MM-NSMSM

P2MM-NSMSM

WIFI_BT

WLAN_UART_RXD

WLAN_UART_CTS_L

WLAN_UART_RTS_L

SM

P2MM-NSMSM

WIFI_BT

SM

P2MM-NSMSM

P2MM-NSMSM

WIFI_BT

P2MM-NSM

P2MM-NSMSM

WIFI_BT

P2MM-NSM

WIFI_BT

SM

P2MM-NSMSM

WIFI_BT

P2MM-NSMSM

WIFI_BT

P2MM-NSM

WIFI_BT

SM

P2MM-NSMSM

WIFI_BT

P2MM-NSMSM

STOCKHOLM

P2MM-NSMSM

STOCKHOLM

P2MM-NSM

WIFI_BT

SM

P2MM-NSM

WIFI_BT

SM

P2MM-NSM

WIFI_BT

SM

P2MM-NSMSM

P2MM-NSMSM

WIFI_BT

BT_PCM_CLK

BT_PCM_SYNC

BB_UART_RXD

90_WLAN_PCIE_TDP

AP_TO_BB_MESA_ON

BB_FORCE_PWM

PP_LDO5

VREG_SMPS4_2V075 ADC_SMPS4

ADC_SMPS1

ADC_PP_LDO11

PP_LDO5

PP_LDO11

VREG_SMPS1_0V90

WATCHDOG_DISABLEBOOT_HSIC_USBBOOT_HSIC

PP_LDO11

BB_SIM_RESET

BB_SIM_CLK BB_SIM_DETECT

90_WLAN_PCIE_RDN

BB_SIM_RESET

SYNC_MASTER=N/A SYNC_DATE=N/A

AP INTERFACE & DEBUG CONNECTORS

5%10V01005

100PF

NP0-C0G

5.5V-6.2PF

0201

MF1/32W

RADIO_BB

1%

01005

10K10K1%

1/32W

RADIO_BB

01005MF

01005

1%10K

1/32WMF

RADIO_BB

6.3V

0201

2.2UF20%

SHORT-10L-0.1MM-SM

SHORT-10L-0.1MM-SM

SHORT-10L-0.1MM-SM

SHORT-10L-0.1MM-SM

1%MF1/32W

F-ST-SMSIM-CARD-N48

377S0163 ALTERNATE VR3101 ESD ALTERNATIVE371S00044

BB_UART_CTS_L

BB_UART_TXD

01005

BB_SIM_CLK

STOCKHOLM_TO_SIM_SWP

STOCKHOLM_TO_SIM_SWP

M-ST-SM

NOSTUFF

BB_RST_L

BB_RESET_DET_L

BB_WAKE_HOST_L

BB_DEVICE_RDY

BB_I2S_WSBB_I2S_RXD

BB_SIM_RESET

BB_SIM_CLK

PP_LDO5PP_LDO11

BB_I2S_TXD

AP_TO_STOCKHOLM_FW_DWLD_REQAP_TO_STOCKHOLM_ENBB_OTHER_TXD

BB_OTHER_RXDBB_COEX_UART_RXD

RF_PMIC_RESET_L

PS_HOLD_PMIC

STOCKHOLM_UART_TXD

STOCKHOLM_UART_CTS

STOCKHOLM_UART_RTSSTOCKHOLM_TO_PMU_HOST_WAKE

BB_CORE_DUMP

BB_SIM_DETECT

BB_JTAG_RST_L

BB_JTAG_TDO

BB_HOST_RDY

WLAN_JTAG_SWDCLK

15.00K

BB_SIM_DATA

X5R-CERM

ESD5004LGA-1

BB_SIM_DATA

90_WLAN_PCIE_RDP

WLAN_REG_ON

HOST_WAKE_WLAN

WLAN_UART_TXD

RFFE1_CLK

RFFE2_CLK

BT_UART_CTS_L

BT_UART_RTS_L

WLAN_JTAG_SWDIO

BB_SIM_DATA BB_GPS_SYNC

PMIC_RESOUT_LBT_PCM_OUT

RADIO_ON_L

BB_I2S_CLK

90_WLAN_PCIE_TDN

RFFE1_DATA

BB_SIM_DETECT

CLK32K_AP

ADC_PP_LDO5

45_BBPMU_TO_STOCKHOLM_19P2M_CLK

STOCKHOLM_TO_SIM_SWP

OSCAR_CONTEXT_B

BB_JTAG_TDI

BB_JTAG_TRST_L

OSCAR_CONTEXT_A

STOCKHOLM_UART_RXD

BT_UART_TXD

BT_UART_RXD

BT_REG_ON

HOST_WAKE_BT

BT_PCM_IN

WAKE_BT

27 8

27

8

7

27 7

27

27 8

7 5

7 5

5 7

27 7

27 7

12

27 8

27 8

24

25

27 8

27 5

25 6 4 3

4

25 6 4 3

12 11 10 8 7 6 4 3

6 4

8

8

8

11 10 8 7 6 4 3

24

27

8 3

8 3

8 3

3

24

8

27

27

24

7

8 3

25

7

7

7

8

25 3

25 27 3

25 27 3

27 25 3

25 27 3

7 5

5

27 5

8

8 24

8 27

27 8

27 25

27

5

12 11 10 8 7 6 4 3

25 6 4 3

8 3

8 3

8 3

8 27

8 27

8

27 8

27 8

8

5

8

27 8

3 5

24

5 25

27

19 18 8

17 16 15 14 13 12 8

21

17 16 14 13 12 8

24 27

24 27

24

27 24

24

27

24

24

27

27

27 24

27

27

27

24

24

27

27

8 24

27 27

27

24 24

27

15

24

27

24

8 27

27

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

TABLE_ALT_ITEM

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

PP

BI

OUT

OUT

OUT

OUT

BI

IN

IN

OUT

I/O

DETECT

GND SWP

VCC

RST

CLK

Page 37: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

1235MA

FOOTPRINT SAME AS 138S0716

SWITCHERS BULK CAPS

VREG_RX

VREG_TX

VREG_IO

VREG_SIM

1100MA

550MA

1350MA

SWITCHERS OUTPUT CAPS

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.BASEBAND PMU (1 OF 2)

FOOTPRINT SAME AS 138S0716

051-006484.0.0

32 OF 5537 OF 60

C3221_RFC3216_RF

C3220_RF

C3219_RF

C3218_RF

C3217_RF

C3222_RFC3223_RFC3224_RF

C3232_RFC3230_RF C3240_RFC3238_RF

C3239_RFC3237_RFC3231_RFC3229_RF

L3204_RF

L3203_RF

L3201_RF

C3213_RFC3211_RFC3210_RFC3209_RFC3202_RF

C3270_RF

U_PMICRF_RF

40

33 37 46

57

58

60

3337 46 57 58

60

3337 46 57 58

60

3337 46 57 58

60

3337 46 57 58

60

47 48 56

39 56

39

36 39 40 41 43 44 45 58

39

39

43 44

39 41

36 39

39

38 39

39

39 43 44

L3202_RF

36 37

37

37

36 37 39

C3215_RFC3214_RFC3212_RFC3208_RFC3206_RFC3205_RFC3204_RFC3203_RFC3201_RF

C3228_RF

C3226_RFC3227_RF

VOLTAGE=4.50V

VOLTAGE=2.95V

VOLTAGE=1.80V

VOLTAGE=4.50V

VOLTAGE=0.95V

VOLTAGE=1.80V

VOLTAGE=5.0V

VOLTAGE=4.50V

VOLTAGE=1.80V

VOLTAGE=1.20V

VOLTAGE=2.05V

VOLTAGE=1.90V

VOLTAGE=1.225V

VOLTAGE=1.80V

VOLTAGE=3.075V

VOLTAGE=0.90V

VOLTAGE=4.50V

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

21

21

21

2

1

2

1

2

1

2

1

2

1

2

1

126

5853

93

1611

74

23

62

82

27

91

28

34

33

9

83

71

3

10

48

59

68

8

7

86

52

54

43

85

1

47

9488

22

38

72

77

4

2

92

262115

49

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

0402-1

PP_VCC_MAIN

6.3V20%

X5R

15UF6.3V20%

X5R

15UF

0402-1

RADIO_PMIC

1.0UFVREG_XO_PMIC

VBATT_S2

VBATT_S1

PP_VCC_MAINMAKE_BASE=TRUE

VBATT_S2

VREG_SMPS1_0V90

VREG_SMPS3_0V95

PP_VCC_MAIN

PP_VSW_S2

PP_LDO13

PP_LDO5

VREG_SMPS4_2V075

VREG_SMPS4_2V075

VREG_SMPS4_2V075

VREG_SMPS2_1V25

PP_VCC_MAINMAKE_BASE=TRUE

MDM_VREF_LPDDR2

MAKE_BASE=TRUEPP_VCC_MAIN

VBATT_S1

VREG_SMPS2_1V25

PP_VSW_S1

REF_BYP

AVDD_BYP

VBATT_S3

VBATT_S2

VBATT_S1

VREG_RF_CLK_BYP

VREG_SMPS2_1V25

VREG_SMPS3_0V95 VREG_SMPS4_2V075

MAKE_BASE=TRUEPP_VCC_MAIN VBATT_S3

VBATT_S3

VBATT_S4

VBATT_S4

PP_VSW_S3

PP_LDO12

PP_LDO11

PP_LDO14_RFSW

VREG_SMPS4_2V075

VREG_SMPS3_0V95

PP_VSW_S4

PP_LDO3

PP_LDO9

PP_LDO8

PP_LDO7

PP_LDO1

PP_LDO2

PP_LDO4

PP_LDO10

VREG_SMPS1_0V90

VBATT_S4

BASEBAND PMU (1 0F 2)

0402-1

20%6.3VX5R

15UF

0402-1

15UF6.3V20%

X5R

0402-1

15UF20%

X5R6.3V

0402-1

15UF20%

X5R6.3V

0201

2.2UFX5R-CERM

RADIO_PMIC

6.3V20%

2.2UF20%6.3VX5R-CERM0201

RADIO_PMICRADIO_PMIC

2.2UFX5R-CERM6.3V0201

20%

20%6.3V

RADIO_PMIC

20UFCERM-X5R0402

20%6.3V20UFCERM-X5R0402 0402

CERM-X5R20%6.3V

RADIO_PMIC

20UF

0402

20%6.3V

RADIO_PMIC

20UFCERM-X5R

0402

20%6.3V

RADIO_PMIC

20UFCERM-X5R

20UFCERM-X5R0402

20%6.3V

RADIO_PMIC

0402CERM-X5R20%6.3V

RADIO_PMIC

20UFCERM-X5R6.3V0402

20UF

RADIO_PMIC

20%

MAKK2016-SM2.2UH-20%-1.5A-0.16OHM

MAKK2016-SM2.2UH-20%-1.5A-0.16OHM

MAKK2016-SM2.2UH-20%-1.5A-0.16OHM

RADIO_PMIC

CERM-X5R0402-9

20%10UF6.3V

CERM-X5R0402-9

RADIO_PMIC

20%10UF6.3V

0402-9CERM-X5R

RADIO_PMIC

20%10UF6.3V

CERM-X5R0402-9

RADIO_PMIC

20%10UF6.3V

RADIO_PMIC

CERM-X5R

20%10UF

0402-9

6.3V

NP0-C0G16V5%100PF

RADIO_PMIC

01005

BGAPM8019

25

0806

2.2UH-20%-1.2A-0.15OHMRADIO_PMIC

0201-1X5R-CERM

20%1.0UF

RADIO_PMIC

10V0201-1

RADIO_PMIC

X5R-CERM

20%1.0UF10V

0201-1

RADIO_PMIC

X5R-CERM

20%1.0UF10V

0201-1

RADIO_PMIC

X5R-CERM

20%1.0UF10V

0201-1

RADIO_PMIC

X5R-CERM

20%1.0UF10V

0201-1

RADIO_PMIC

20%X5R-CERM

1.0UF10V

0201-1X5R-CERM

20%

RADIO_PMIC

1.0UF10V

RADIO_PMIC

20%X5R-CERM

1.0UF

0201-1

10V20%

RADIO_PMIC

1.0UF

X5R-CERM0201-1

10V

10VX5R-CERM

RADIO_PMIC

20%1.0UF

0201-1

0201-1

20%10V

RADIO_PMIC

X5R-CERM

0.1UF

01005X5R

20%4V

RADIO_PMIC

27 25 24 13 4

4

4

4

6 4

3

4

4 3

4 3

4 3

4

4

4

4

4

4

4

43

4

4

4

4

4

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

REG

SYM 5 OF 5

VDD_XO_RFC

VREG_L9

VREG_RFCLK

VREF_DDR2

GND

GND_REF

VDD_INT_BYP

VDD_S2VDD_S2

VDD_S4

VDD_S3

VDD_S1

VDD_L12

VDD_L10

VDD_L9

VDD_L7_8_11

VDD_L2_3

VDD_L1

VIN_VPH2

VIN_VPH1

REF_BYP

VREG_L14

VREG_L13

VREG_L12

VREG_L11

VREG_L10

VREG_L8

VREG_L7

VREG_L6

VREG_L5

VREG_L4

VREG_L2

VREG_L3

VREG_L1

VSW_S4_2VSW_S4_1

VREG_S4

VSW_S3_1VSW_S3_2

VREG_S3

VSW_S2VREG_S2

VSW_S1_2VSW_S1_1

VREG_S1

VREG_XO

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Page 38: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

IN PARALLEL

WITH 10M

N69/69H PRE-PROTO

U404L400

C401R411

XW <2.0MM FROM XTAL GROUND PATCH

REVISIONREVISION0.5V N69

SPARE

SKU_ID

SPARE

0.70V

BOARD_ID0.00V0.50V

N69/69H EVT1

N69/69H PROTO1

N69/69H EVT2

N69H1.1V

BASEBAND PMU (2 OF 2)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

N69/69H DVT

N69/69H PROTO2

TO GND

0.90V

CALCULATE

1.30V

SPAREN69/69H PVT

1.40V1.50V1.60V

1.10V

BB_GPS_ENABLE

1.70V

1.10V(EVT)

4.0.0051-00648

38 OF 6033 OF 55

R3305_RF

R3306_RF 33 36 60

R3312_RF

XW3301_RF

U_PMICRF_RF

U_PMICRF_RF

U_PMICRF_RF

U_PMICRF_RF

C3303_RF

R3311_RF

Y3301_RF

41

36 58

37 38 39

41

39

33 36 60

R3301_RF

36 40

R3309_RF

40 40

37 38 39

R3308_RF

C3301_RF

40

R3307_RF

3336 60

36 40

36 40

3336 60

36 40

21

21

21

21

176387

5

6961605150414036

8490

57

7978

67

64

80

3242

46

73

37243544182939

251419553013

7681

20

65

31

75

66

4556

89

70

21

2

1

4

3

2

1

21

21

21

2

1

21

STOCKHOLM_TO_BBPMU_CLK_REQ

150K

MF01005

1%1/32W

90.9K MF01005

1%1/32W

PP_LDO3

SKU_ID

BOARD_ID

45_BBPMU_TO_STOCKHOLM_19P2M_CLK

01005

1000PF

RADIO_PMIC

1/32W

20.0K

5% MF01005

RADIO_PMIC

010056.3V10%X5R-CERM

RADIO_PMIC01005MF

1/32W

100KRADIO_PMIC

1%

1%

RADIO_PMIC

1/32W

100MF

01005

1/32W1% MF

01005

1.00K

RADIO_PMIC

RADIO_PMIC

2.0X1.6-SM19.2MHZ-10PPM-7PF-80OHM

RADIO_PMIC

MF1%1/32W01005

100K

1000PF

RADIO_PMIC

X5R-CERM6.3V10%

BGAPM8019

BGAPM8019

BGAPM8019

BGAPM8019

NOSTUFF

SHORT-10L-0.25MM-SM

01005

162K MF1%1/32W

BASEBAND PMU (2 OF 2)

Y3301_RF XTAL 19MHZ

Y3301_RF XTAL 19MHZ

PP_LDO3

BOARD_ID

BB_FORCE_PWMBB_BUA_SIM

XO_GND

XO_THERM_Y1

BB_RST_L

PS_HOLD PS_HOLD_PMIC

PMIC_RESOUT_L

RF_PMIC_RESET_L

SPMI_DATASPMI_CLK

RADIO_ON_L

PP_LDO3

XO_OUT_D0_EN

XTAL19M_OUT

XTAL19M_IN

SLEEP_CLK_32K

MDM_CLK

PA_CTL_QFE

50_A0_PMCLK50_PMIC_RF_CLK

50_RF_CLK

ALTERNATE

ALTERNATE197S0598

197S0593

197S0593

197S0565

OMIT

_TAB

LE

VREF_DAC_BIAS

SKU_IDVDDPX_BIAS

4 6

5

5

5

3

12

5

5

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER

TABLE_ALT_ITEM

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

INPUT_PWR

SYM 3 OF 5

GNDGNDGNDGNDGNDGNDGNDGND

GND_S4GND_S3GND_S2GND_S1

SYM 2 OF 5

CLOCKXO_OUT_A0

XO_OUT_D0_ENXO_OUT_D0

GND_XOADC

XTAL_19M_OUTXTAL_19M_IN

BATT_ID_THERM

GND_XO

XO_THERM

SLEEP_CLK

PA_THERM1PA_THERM2

XO_OUT_A1

MPP_GPIO

SYM 4 OF 5

MPP_06MPP_05MPP_04MPP_03MPP_02MPP_01

GPIO_06GPIO_05GPIO_04GPIO_03GPIO_02GPIO_01

CONTROL

SYM 1 OF 5

PS_HOLD

CBL_PWR*PON_TRIG

PON_RST*

RESIN*

SPMI_CLK

GND

GND

OPT

GND

SPMI_DATA

NC

NC

NCNCNC

NC

NCIN

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

OUTIN

IN

IN

IN

BI

BI

IN

OUT

Page 39: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

BASEBAND (1 OF 3)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

(SDC1 PAD)

(MSM CORE)

(MSM MEMORY)

(EBI1 PAD)

(HSIC PAD)

(UIM2 PAD)

(MODEM SUB SYSTEM)

(UIM1 PAD)

(USB CORE)

(QFUSE PROGRAMMING)

(EBI1 PAD)

(LPDDR2)

(LPDDR2_CORE)

(GENIO PAD)

(SDC/UIM)

(USB 1.8V)

(LPDDR2 CORE)

(LPDDR2)(GPS ADC)

(PLL)

(PLL)(BBRX)

(SDC1 PAD)

(GENIO PAD)

(MSM CORE)

C538R500L500U502

(MSM MEMORY)

(QFUSE)(MODEM SUB SYSTEM)

(COMBO DAC/BBRX)

(HSIC PAD)

39 OF 6034 OF 55

4.0.0051-00648

U_BB_RF

U_BB_RF

C3423_RF

C3430_RF

C3425_RF C3438_RF

37 38 39

C3437_RF

C3436_RF

36 37 39 40 41 43 44 45 58

37 39

C3435_RF

37 38 39

C3434_RF

37 39

C3433_RF

37 39 43 44

C3432_RF

37 39 43 44

C3429_RF

37 39 41

C3428_RF

37 39

C3426_RF

37 39

C3427_RF

38 39

37 39

C3424_RF

C3421_RF

36 37 39 40 41 43 44 45 58

37 39 56

C3420_RF

37 39

C3419_RF C3422_RF

37 39

C3401_RF C3404_RF C3407_RF C3410_RF C3413_RF C3416_RF

37 39

C3402_RF C3405_RF C3408_RF C3411_RF C3414_RF C3417_RF

C3418_RFC3415_RFC3412_RFC3409_RFC3406_RFC3403_RF

37 38 39

37 39

36 37 39 40 41 43 44 45 58

37 38 39

37 39

37 39 43 44

37 39 43 44

37 39 41

37

37 39

37 39

38 39

37 39

36 37

36 37 39 40 41 43 44 45 58

37 39 56

37 39

36 37 39

37 39

37 39

36 37 39

A15

R14R13P13B17C17A17E6A9E9E12A6A12W12W20W9W5W1V20T20R20P12P9P8P6N14N13N10N9N6N1M20M15M14M11M10

M7M6

L15L12L11

L8L7L1

K20K19K13K12

K9K8

J14J13J10

J9J6J1

H15H14H11H10

H7H6

G12G11

G7F20F14F13F12E14C20C14A20

A2

U20A19

V13

V10

U11

W8

D17R12U13

E16

V9

U19

R19

V19V5V2K2J19B2

B20

T19M1L20L19F19

L6K11

K7K6

J12J11

J8J7

H13H12

H9H8

G15G14G13G10

G9G6

F11F10

F7F6

E5

R8R7

P15P14N15L10

L9K10G8

F15F9F8

E15

K1J20

P20P1H1E20

P11P10

P7N12N11

N8N7

M13M12

M9M8

L14L13K15K14J15

T17

C9

C6

C12

B12B9

B6

B15

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

RADIO_BB PP_LDO12RADIO_BB RADIO_BB

RADIO_BB

ASIC-MDM9625M-2

X5R-CERM

WLBGA

WLBGA

RADIO_BB

ASIC-MDM9625M-2

PP_LDO11

PP_LDO5

PP_LDO12

PP_LDO2

PP_LDO4

PP_LDO9

PP_LDO1

PP_LDO3

PP_LDO13

PP_LDO3

PP_LDO9

PP_LDO1PP_LDO2PP_LDO9 RADIO_BB

VDDPX_BIAS

PP_LDO11

PP_LDO9

PP_LDO10

PP_LDO1

PP_LDO7

VDDPX_BIAS PP_LDO9

PP_LDO12

PP_LDO11

PP_LDO3PP_LDO3

PP_LDO7

PP_LDO1

PP_LDO9

VREG_SMPS1_0V90

PP_LDO10

PP_LDO10

PP_LDO13

VREG_SMPS1_0V90

PP_LDO10

PP_LDO12

PP_LDO11

BASEBAND (1 OF 2)

RADIO_BB

4VX5R-CERM0201

2.2UF20%

0.1UF

01005NOSTUFF

RADIO_BB

4VX5R

20%

RADIO_BB

01005

0.1UF

NOSTUFF

4VX5R

20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

NOSTUFF

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

NOSTUFF

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

20%

RADIO_BB

2.2UF

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

20%

RADIO_BB

2.2UF

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

RADIO_BB

NOSTUFF

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4V

0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

4VX5R-CERM0201

20%2.2UF

RADIO_BB

4VX5R-CERM0201

2.2UF20%

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

RADIO_BB

4VX5R-CERM0201

2.2UF20%

25

RADIO_BB

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 6 OF 6

GND

GND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

SYM 5 OF 6

PWR

VDD_MEM

VDD_MEMVDD_MEMVDD_MEMVDD_MEMVDD_MEM

VDD_MEM

VDD_MEM

VDD_MEM

VDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEM

VDD_MODEMVDD_MODEM

VDD_USB_CORE

VDD_USB_1P8

VDD_USB_3P3

VDD_A2

VDD_A1VDD_A2

VDD_P6

VDD_A1

VDD_A1VDD_A2

VDD_A2

VDD_PLL

VDD_DDR_CORE_1P8VDD_DDR_CORE_1P8

VDD_ALWAYS_ON

VDD_PLLVDD_PLL

VREF_UIMVREF_SDC

VDD_QFPROM_PRG

VDD_DDR_CORE_1P2

VDD_P1

VDD_P2

VDD_P3VDD_P3

VDD_MODEM

VDD_MODEM

VDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEM

VDD_PLL2

VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2

VDD_COREVDD_COREVDD_CORE

VDD_CORE

VDD_CORE

VDD_COREVDD_CORE

VDD_COREVDD_CORE

VDD_CORE

VDD_MEMVDD_MEM

VDD_MEMVDD_MEMVDD_MEM

VDD_P1VDD_P1VDD_P1VDD_P1

VDD_P3VDD_P3VDD_P3VDD_P3

VDD_P4

VDD_P5VDD_CORE

VDD_CORE

VDD_CORE

VDD_CORE

VDD_MODEMVDD_MODEM

VDD_MODEM

VDD_CORE

VDD_CORE

NC

NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

ININ

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Page 40: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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BASEBAND (2 OF 3)U602

R606L600

C600

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

40 OF 6035 OF 55

051-006484.0.0

U3501_RF

U_BB_RF

U_BB_RF

33 60

36

C3501_RF

R3507_RF R3508_RFU_EEP_RF

38

37 40

33 36 60

33 36 60

33 36 60

33 36 60

36 38

36 38

36

33 36 60

38

36 38 40

33 36 60

36

38

36

36 38

R3502_RF

R3501_RF

R3506_RF

R3505_RF

4

51

2

G19G18

F18F16

G16

G20

H20H19H18H16J18K18J16K16

G1

N20M5R16

R1

U12

W13W10

V12 V11W11

M19

N19P19N18

T4P2

P5

P3R2

N2W17

B18A18D20D19

B19C19

V17W14W18

W15V15

R9R11

R10U10U9

V18W19

2

1

2

1

2

1

A2A1

B2B1

2

1

2

1

21

21

PP_LDO11

BB_JTAG_TCKSOT122674AUP1G34GX

SPMI_DATA

RADIO_BB

XO_OUT_D0_EN

BB_JTAG_TCK_IN

1/32W

BB_JTAG_RST_L

BB_JTAG_TDI

SLEEP_CLK_32K

PMIC_RESOUT_L

BB_JTAG_TRST_L

MDM_CLK

PS_HOLD

MDM_VREF_LPDDR2

ASIC-MDM9625M-2

WLBGA

WLBGA

RADIO_BB

PP_LDO11

EBI1_CAL

BDM_ZQ

RADIO_BB

ASIC-MDM9625M-2

1/32W

BB_USB_TRXTUNEMDM_CLK

50_BB_HSIC_STROBE

90_BB_USB_P90_BB_USB_N

BB_HSIC_CAL50_BB_HSIC_DATA

SPMI_CLK

BB_JTAG_TDO

BB_USB_VBUS

BB_JTAG_TMS

RADIO_BB

PP_LDO11

BB_EEPROM_SDA

BB_EEPROM_SDA

BB_EEPROM_SCL

BB_EEPROM_SCL

MDM_VREF_LPDDR2

BASEBAND (1 OF 2)

6.3V20%1.0UF

X5R0201-1

01005MF1%1/32W10K 10K

1%MF01005

WLCSPCAT24C08C4A

1/32W1%

01005

240MF

RADIO_BB

1%2001/32W01005MF

240

1%01005MF

MF

240

1%010051/32W

RADIO_BB

26 11 9 7

7 5 3

12 11 10 8 7 6 4 3

8 7

12 11 10 8 7 6 4 3

8 7

8 7

8 7

7 4

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NC

NC

SYM 2 OF 6

EBI1_EBI2

EBI1_CAL

EBI1_ZQ

EBI2_CS*EBI2_CLE*EBI2_ALE*

EBI2_AD_6EBI2_AD_7

EBI1_VREF

EBI2_AD_5EBI2_AD_4EBI2_AD_3EBI2_AD_2EBI2_AD_1EBI2_AD_0

EBI2_WE*EBI2_OE*EBI2_BUSY*

EBI1_VREFEBI1_VREF

DIGITAL

SYM 1 OF 6

USB_HS_REXTUSB_HS_SYSCLK

UIM1_DETECT

HSIC_STROBE

RESIN*

SLEEP_CLK

TCK

RESOUT*

TRST*

USB_HS_ID

SRST*

USB_HS_DPUSB_HS_DM

SDC1_DATA_0

SDC1_DATA_2SDC1_DATA_1

SDC1_DATA_3

UIM1_RESETUIM1_CLK

UIM1_DATA

HSIC_CALHSIC_DATA

PMIC_SPMI_DATAPMIC_SPMI_CLK

TDO

USB_HS_VBUS

CXOCXO_EN

TMS

PS_HOLD

TDI

SDC1_CMDSDC1_CLK

MODE_1MODE_0

IN

IN

NCNCNC

NC

NCNCNCNCNCNCNCNC

NCNCNCNCNCNC

NCNCNCNC

NC

NC

NCNC

NCNC

VCC

VSS

SDASCL

OUT

IN

BI

BI

BI

BI

BI

BI

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

Page 41: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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BB_LAT_GPIO3

BB_SWD_ENABLE

BB_UAT_GPIO3

RFFE

UAT_SELECT

LAT_SELECT

BB_UAT_GPIO0

CTRL_FWD_REV

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

BLSP2

SSBI

C704

U702L700R700

BLSP6

GRFC

BLSP3

BB_LAT_GPIO5

BB_LAT_GPIO4

BB_LAT_GPIO2

BB_LAT_GPIO1

BB_UAT_GPIO1

BLSP4

BLSP5

BLSP1

GRFC

BB_DEBUG_SYNC (DEV)

BASEBAND (3 OF 3)

BB_LAT_GPIO0

WLAN_TX_BLANK

36 OF 5541 OF 60

4.0.0051-00648

U_BB_RF

U_BB_RF

56

56

U_BUFFER_RF

33 36 60

33 36 60

33 36 60

33 36 60

33 60

C3602_RF

R3601_RF

36

36

36 41

36

33 36 60

33 36 60

33 36 60

36

36

38

33 36 60

33 36 60

33 36 60

33 36 60

33 36 60

36

36

36

33 60

33 60

33 36 60

40

40

33 36 60

33 60 36

33 36 60

33 36 60

36 57

36 57

33 60

44

41 42

36 45 46 47 48 49 50

36 45 46 47 48 49 50

36 41 51 52 54

41 51 52 54

42

42

42

42

33 60

45

45

42

42

42

42

42

42

42

42

44

44

44

44

44

44

44

44

42

42

42

42

42

42

42

42

C3604_RFC3603_RFC3601_RF

VOLTAGE=1.80V

R5U1U5U2W6V1U17V4R15T2U6W3W4V8U7R3R6T1E1D2D1E2T3N3N5F5E3F3G5C1D3F2F1G2G3H3H2H5

J2J3L2J5C2B1K5M2L3K3M3L5

L18P16E18E19C18D18L16N16M16M18

U8W7V6V7V3W2U4U3

U16V14U14U15P18T18U18R18

E8

A7B7

C8

A8B8

E13

B13A13

C13

A14B14

B16A16

C15C16

E7C7

C3D4W16V16

B3

B4

B10

E10

A3

A4

A10

C10

C4

B5

B11

E11

C5

A5

A11

C11

4

63

52

81

7

2

1

2

1

2

1

2

1

2

1

BB_LAT_GPIO2BB_LAT_GPIO1

RF1352WLCSP

WTR_BB_TX_Q_P

RFFE2_DATA_BUFFER

RFFE2_CLK_BUFFER

MOBILE DATA MODEM (2 OF 2)

0201

BB_UART_CTS_L

BB_SIM_CLKBB_SIM_RESET

BB_UART_TXD

BB_RESET_DET_L BB_DEBUG_STATUS

GSM_TX_PHASE_D0

BOOT_HSICBOOT_HSIC_USB

WATCHDOG_DISABLE

AP_WAKE_MODEM

BB_EEPROM_SCLBB_EEPROM_SDA

BB_OTHER_TXDBB_OTHER_RXD

BB_I2S_CLKBB_I2S_TXD

BB_UART_RXD

RFFE1_CLK

RFFE2_CLKRFFE1_DATA

BB_GPS_SYNC

RFFE2_DATA

BB_DEVICE_RDYBB_BUA_SIM

AP_TO_BB_MESA_ON

BB_WAKE_HOST_LBB_HOST_RDY

BB_DEBUG_ERROR

BB_CORE_DUMP

GSM_TX_PHASE_D1

WFR_SSBI

WTR_SSBI_PRX_DRX

BB_COEX_UART_TXDBB_COEX_UART_RXDWTR_SSBI_TX_GPS

UAT_SELECT

BB_SIM_DETECTBB_SIM_DATA

BB_IPC_GPIO1

GSM_TXBURST_IND

BB_I2S_RXDBB_I2S_WS

BB_UART_RTS_L

RADIO_BB

WLBGAASIC-MDM9625M-2

WTR_BB_TX_I_N

WTR_BB_PRX_I_N

WTR_BB_DRX_I_N

WFR_BB_PRX_I_N

WFR_BB_DRX_I_N

WTR_BB_PRX_I_P

WTR_BB_DRX_I_P

WFR_BB_PRX_I_P

WFR_BB_DRX_I_P

WTR_BB_PRX_Q_N

WTR_BB_DRX_Q_N

WFR_BB_PRX_Q_N

WFR_BB_DRX_Q_N

WTR_BB_PRX_Q_P

WTR_BB_DRX_Q_P

WFR_BB_PRX_Q_P

WFR_BB_DRX_Q_P

ET_DAC_NET_DAC_P

WTR_BB_GPS_I_PWTR_BB_GPS_I_NWTR_BB_GPS_Q_PWTR_BB_GPS_Q_N

WTR_BB_TX_I_P

WTR_TX_IDAC

WTR_BB_TX_Q_N

PP_LDO7

WLBGA

RADIO_BB

ASIC-MDM9625M-2

VREF_DAC_BIAS

RFFE2_CLK

RFFE_VIO

RFFE2_DATA

BB_SIM_DETECT

MAKE_BASE=TRUEPP_LDO11

RFFE2_DATA

WTR_TX_IDAC VREF_DAC_BIAS

PP_LDO11

PP_LDO7

RFFE_VIO

22PF

CERM01005

5%16V

1/32W01005

1%10K

RADIO_BB

MF

01005X5R-CERM6.3V10%2200PF

RADIO_BB

2200PF

01005

6.3V10%

RADIO_BB

X5R-CERM

0.1UF

NOSTUFF

6.3V10%

X7R

RADIO_BB

18 17

23

8 6 4

19

21 19 18 8 3

21 16 14 13 8

21 19 18 8

8 3

8 5

12 11 10 8 7 6 4 3

9 8 8 5

12 11 10 8 7 6 4 3

8 6 4

21 19 18 17 16 14 13 8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SYM 3 OF 6

GPIO

GPIO_43

GPIO_45

GPIO_47GPIO_48

GPIO_9

GPIO_28

GPIO_3GPIO_2

GPIO_4

GPIO_6

GPIO_16

GPIO_24 GPIO_62

GPIO_60

GPIO_37

GPIO_35GPIO_36

GPIO_32

GPIO_34GPIO_33

GPIO_30GPIO_31

GPIO_29

GPIO_27

GPIO_25GPIO_26

GPIO_23GPIO_22

GPIO_20GPIO_21

GPIO_19GPIO_18GPIO_17

GPIO_15GPIO_14

GPIO_5

GPIO_75

GPIO_73GPIO_74

GPIO_71GPIO_70

GPIO_72

GPIO_68GPIO_69

GPIO_65

GPIO_67GPIO_66

GPIO_63GPIO_64

GPIO_61

GPIO_58GPIO_59

GPIO_57

GPIO_55GPIO_56

GPIO_52GPIO_53GPIO_54

GPIO_51GPIO_50GPIO_49

GPIO_46

GPIO_42

GPIO_44

GPIO_41

GPIO_1GPIO_0

GPIO_40GPIO_39GPIO_38

GPIO_13GPIO_12GPIO_11GPIO_10

GPIO_8GPIO_7

SYM 4 OF 6

ANALOGBBRX_IM_CH0

BBRX_IM_CH1

BBRX_IM_CH2

BBRX_IM_CH3

BBRX_IP_CH0

BBRX_IP_CH1

BBRX_IP_CH2

BBRX_IP_CH3

BBRX_QM_CH0

BBRX_QM_CH1

BBRX_QM_CH2

BBRX_QM_CH3

BBRX_QP_CH0

BBRX_QP_CH1

BBRX_QP_CH2

BBRX_QP_CH3

TX_DAC0_VREF

TX_DAC1_VREF

ET_DAC_MET_DAC_P

GNSS_BB_IPGNSS_BB_IMGNSS_BB_QPGNSS_BB_QM

TX_DAC0_IMTX_DAC0_IP

TX_DAC0_IREF

TX_DAC0_QMTX_DAC0_QP

TX_DAC1_IMTX_DAC1_IP

TX_DAC1_IREF

TX_DAC1_QMTX_DAC1_QP

DNCDNC

DNCDNC

OUT

OUT

SDATA

SCLK_A

SDATA_A

GPO2

GND

VIO

SCLK

GPO1

OUT

IN

IN

OUT

NC

NC

NC

NCNC

NC

NCNCNCNC

OUT

NC

NCNCNC

OUT

IN

IN

OUT

NC

NC

NC

NCNC

NCNCNC

NC

NC

NC

NCNCNC

NCNCNCNC

NCNCNCNC

IN

OUT

IN

OUT

OUT

IN

BI

OUT

IN

OUT

OUT

IN

IN

IN

OUT

IN

OUT

BI

BI

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

BI

BI

BI

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Page 42: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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RF_CLK IS SHARED BETWEEN WTR AND WFR. LENGTH DIFFERENCE BETWEEN THE TWO SHOULD BE < 5MM.

WTR TRANSCEIVER (1 OF 2)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

C802R802L800U803

NO DC

DC

DC

DC

LB3

LB2

DC

DC

DC

LB4

MB1

MB2

MB3

HB1

HB2

HB3

HBMB4 NO DC

NO DC

DC

DC

LB1

DC

NO DC

DC

DC

DC

DCLB1

LB2

LB3

LB4

MB1

MB2

NO DC

DC

DC

NO DC

HB1

HBMB4

HB3

HB2

MB3 DC

37 OF 5542 OF 60

051-006484.0.0

41 41

41

41

41

U_WTR_RF

U_WTR_RFU_WTR_RF

44

44

44

44

R3702_RF

41

131

155139138146

154163153162

121

130

152161

151160

10595

71

117

104123

122

156

11855

140

94

141

127

109

3644

6785

6053

29

1

20

28

32

7

16

15

5

2

30

13

12

4

6168

7686

37

50

27

43

51

91

65

73

92

102

19

33

18

17

9

10797

99108

21

50_FWD_OR_REV_RF

50_B1_B25_B34_B39_WTR_TX_OUT50_HB_2G_WTR_TX_OUT

WTR_TX_IDAC

WTR_BB_TX_I_NWTR_BB_TX_I_P

WTR_BB_TX_Q_NWTR_BB_TX_Q_P

WTR_SSBI_PRX_DRXWTR_SSBI_TX_GPS

GSM_TX_PHASE_D0GSM_TX_PHASE_D1

50_B7_WTR_TX_OUT

50_B40_B38_B41_WTR_TX_OUT

50_LB_2G_WTR_TX_OUT50_B8_B26_B20_WTR_TX_OUT50_B13_B17_B28_WTR_TX_OUT

50_B3_B4_WTR_TX_OUT

WTR_RTUNE

WTR_BB_GPS_I_NWTR_BB_GPS_I_P

WTR_BB_GPS_Q_NWTR_BB_GPS_Q_P

100_GPS_WTR_IN_N100_GPS_WTR_IN_P

WTR_BB_DRX_I_NWTR_BB_DRX_I_P

WTR_BB_DRX_Q_NWTR_BB_DRX_Q_P

50_B38X_DRX_WTR_IN

50_B41A_DRX_WTR_IN

50_B7_DRX_WTR_IN

50_B40_DRX_WTR_IN

50_B8_B28B_DRX_WTR_IN

50_B13_B17_DRX_WTR_IN

50_B26_B28A_DRX_WTR_IN

50_B20_B29_DRX_WTR_IN

50_WFR_DRX_LB_CA_IN

50_B34_DRX_WTR_IN

50_B39_DRX_WTR_IN

50_WFR_DRX_MB_CA_OUT

WTR_BB_PRX_I_NWTR_BB_PRX_I_P

WTR_BB_PRX_Q_NWTR_BB_PRX_Q_P

50_B40B_B38X_PRX_WTR_IN

50_B41A_PRX_WTR_IN

50_B7_PRX_WTR_IN

50_B40A_PRX_WTR_IN

50_B8_PRX_WTR_IN

50_B20_PRX_WTR_IN

50_B26_PRX_WTR_IN

50_B13_B17_B28_B29_PRX_WTR_IN

50_WFR_PRX_LB_CA_IN

50_B34_B39_PRX_WTR_IN

50_DCS_WTR_IN

50_PCS_WTR_IN

50_WFR_PRX_MB_CA_OUT

50_RF_CLK

RF TRANSCEIVER (1 0F 3)

RADIO_WTR

RADIO_WTRRADIO_WTRRADIO_WTRRADIO_WTR

WTR1625BGA

BGAWTR1625WTR1625

BGA

4.75K

MF1/32W01005

1%

RADIO_WTR

RADIO_WTRRADIO_WTRRADIO_WTR

18

16

13

8

8

8

8

8

8

8

8

8

17

17

13

15

14

16

22

22

20

20

20

20

20

20

20

20

20

20

19

19

17

19

15

15

15

14

18

20

20

11 5

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SYM 3 OF 5

GND

GND

GNDGND

GND

GND

GND

XO_IN

RTUNE

PDET_RFFB

TX_MB4_OUTTX_MB3_OUTTX_MB2_OUTTX_MB1_OUT

TX_LB4_OUTTX_LB3_OUTTX_LB2_OUTTX_LB1_OUT

TX_HB2_OUT

TX_HB1_OUT

GP_DATA1GP_DATA0

SSBI_TX_GNSSSSBI_PRX_DRX

TX_BB_QPTX_BB_QM

TX_BB_IPTX_BB_IM

DAC_REF

ADC_IN

SYM 2 OF 5

DRX_MB_CA_IN

DRX_MB3_IN

DRX_MB2_IN

DRX_MB1_IN

DRX_LB_CA_OUT

DRX_LB4_IN

DRX_LB3_IN

DRX_LB2_IN

DRX_LB1_IN

DRX_HB_CA_OUT

DRX_HMB4_IN

DRX_HB3_IN

DRX_HB2_IN

DRX_HB1_IN

DRX_BB_QPDRX_BB_QM

DRX_BB_IPDRX_BB_IM

GNSS_RF_INPGNSS_RF_INM

DNC

GNSS_BB_QPGNSS_BB_QM

GNSS_BB_IPGNSS_BB_IM

SYM 1 OF 5

PRX_MB_CA_IN

PRX_MB3_IN

PRX_MB2_IN

PRX_MB1_IN

PRX_LB_CA_OUT

PRX_LB4_IN

PRX_LB3_IN

PRX_LB2_IN

PRX_LB1_IN

PRX_HB_CA_OUT

PRX_HMB4_IN

PRX_HB3_IN

PRX_HB2_IN

PRX_HB1_IN

PRX_BB_QPPRX_BB_QM

PRX_BB_IPPRX_BB_IM

NC

NC

NC

NC

NC

NC

OUT

IN

OUT

INOUT

OUT

OUT

Page 43: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

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CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

WTR DECOUPLING SHARED WITH C3808_RF

WTR TRANSCEIVER (2 OF 2) C934R926

U902

DELETED C3805 PR REVIEW FEEDBACK

L3802_RF

WTR DECOUPLING CAPS

051-006484.0.0

38 OF 5543 OF 60

C3833_RF

C3830_RF

C3813_RF

C3825_RF

C3824_RF

C3823_RF

C3821_RF

XW3803_RF

XW3802_RF

XW3801_RF

U_WTR_RF

U_WTR_RF

L3802_RF

L3801_RF

C3811_RF

C3809_RF

C3807_RF

C3806_RF

C3818_RF

C3803_RF

C3808_RFC3801_RF

C3829_RF

C3826_RF

C3816_RF

C3828_RF

C3817_RF

C3815_RF

164

75846645

132112133158148124125142159

134150106119120128143144145

110

101

111

96778747

406370886949

4623

310

3924

621

8141426426

835

5882835689

147

157

114

129

126

62

80

100

98

116

54

149

136

115

135

137

48

78

90

79

72

57

34

25

74

93

52

59

11

38

14

31

22

103

113

21

21

2

1

2

1

2

1

2

1

2

1

2

1

2

12

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

VDD_DRX_BB_2V

PP_LDO8MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP_LDO1

VDD_GPSMAKE_BASE=TRUE

VDD_MSM_1P8VMAKE_BASE=TRUEPP_LDO11

VREG_1P3V_WTR MAKE_BASE=TRUE

VREG_1P3V_WTR

VREG_2V_WTR

VDD_PRX_HBMB_1P3V

VDD_GPS_BB_1P3VVDD_FBRX_2V

VDD_PRX_LO_HBMB_1P3V

VDD_TX_UPC_1P3V

VDD_PRX_2V

VDD_DRX_LB_1P3V

VDD_DRX_HB_1P3V

VDD_DRX_MB_1P3V

VDD_PRX_LO_HB_1P3V

VDD_DRX_LO1_1P3V

VDD_DRX_LO2_1P3V

VDD_TX_SYNTH_1P3V

VDD_PRX_VCO_1P3V

VDD_TX_LO_1P3V

VDD_PRX_LB_1P3V

VDD_SHDR_VCO_1P3V

VDD_PRX_BB_2V

VDD_TX_DA_2V

VDD_XO_2V

VDD_TX_VCO_2V

VDD_TX_VCO_1P3V

VDD_TX_UPC_1P3V

VDD_TX_SYNTH_1P3V

VDD_TX_PLL_2V

VDD_TX_LO_1P3V

VDD_TX_DA_2V

VDD_TX_DA_1P3V

VDD_TX_BBF_2V

VDD_SHDR_VCO_2V

VDD_SHDR_VCO_1P3V

VDD_SHDR_PLL_1P3V

VDD_PRX_VCO_2V

VDD_PRX_VCO_1P3V

VDD_PRX_PLL_1P3V

VDD_PRX_LO_HBMB_1P3V

VDD_PRX_LO_HB_1P3V

VDD_PRX_LB_1P3V

VDD_PRX_HBMB_1P3V

VDD_PRX_BB_2V

VDD_PRX_2V

VDD_MSM_1P8V

VDD_FBRX_2V

VDD_DRX_MB_1P3V

VDD_DRX_LO2_1P3V

VDD_DRX_LO1_1P3V

VDD_DRX_LB_1P3V

VDD_DRX_HB_1P3V

VDD_DRX_BB_2V

VDD_GPS_VCO_1P3V

VDD_GPS_PLL_1P3V

VDD_GPS_LNA_1P3V

VDD_GPS_BB_1P3V

VDD_GPS_PLL_1P3VMAKE_BASE=TRUE

VDD_SHDR_PLL_1P3V

VDD_TX_DA_1P3V

VDD_PRX_PLL_1P3V

VDD_GPS_VCO_1P3V

MAKE_BASE=TRUE

VDD_GPS_LNA_1P3V

VDD_TX_VCO_2V

VDD_TX_PLL_2V

VDD_XO_2V

VDD_SHDR_VCO_2V

VDD_PRX_VCO_2V

VDD_TX_VCO_1P3V

MAKE_BASE=TRUEVREG_1P3V_WTR

VDD_TX_BBF_2VMAKE_BASE=TRUE

MAKE_BASE=TRUEVREG_2V_WTR

RF TRANSCEIVER (2 OF 3)

RADIO_WTR

01005X5R4V20%0.1UF

20%0.1UF

01005

RADIO_WTR

X5R4V

01005NP0-C0G10V5%100PF

RADIO_WTR

20%

RADIO_WTR

4V0.1UF

01005X5R

0.1UFX5R20%4V01005

RADIO_WTR

4V01005

20%X5R

0.1UF

RADIO_WTR

RADIO_WTR

4VX5R01005

0.1UF20%

RADIO_WTRRADIO_WTR

RADIO_WTR

I188

BGAWTR1625

BGAWTR1625

01005

8.2NH-3%-0.19A-1.6OHM

0201RADIO_WTR

22NH-3%-0.25A

I175

1.0UF

0201-1X5R-CERM6.3V10%

RADIO_WTR

0.1UFX5R20%4V01005

RADIO_WTR

RADIO_WTR

0.1UF20%

01005X5R4V

RADIO_WTR

20%

01005

0.1UFX5R4V

RADIO_WTR

4VX5R20%

01005

0.1UF

RADIO_WTR

X5R-CERM10%0.1UF

020110V

10UF

CERM-X5R6.3V20%

RADIO_WTR

0402-9

10UF

CERM-X5R

20%6.3V

RADIO_WTR

0402-9

RADIO_WTR4V20%X5R01005

0.1UF

RADIO_WTR5%10V100PF

RADIO_WTR

NP0-C0G01005

01005

20%4V0.1UF

RADIO_WTR

X5R

RADIO_WTR

01005

0.1UF20%4VX5R

RADIO_WTR

X5R01005

0.1UF4V20%

X5R01005

20%4V0.1UF

RADIO_WTR

10

11 4

116 4

10 12 11 8 7 6 4 3

10

10

10

10 10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10 10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

NBC

SYM 5 OF 5

GNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGND

GND

GND

GND

GNDGNDGNDGND

GNDGNDGNDGNDGNDGND

GNDGNDGNDGND

GNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGND

GND

SYM 4 OF 5

GND

VDD_RF2_XO

VDD_RF2_T_VCO

VDD_RF1_T_VCO

VDD_RF1_T_UPC

VDD_RF1_T_SYN

VDD_RF2_T_PLL

VDD_RF1_T_LO

VDD_RF2_T_DA

VDD_RF1_T_DA

VDD_RF2_T_BB

VDD_RF2_S_VCO

VDD_RF1_S_VCO

VDD_RF1_S_PLL

VDD_RF2_P_VCO

VDD_RF1_P_VCO

VDD_RF1_P_PLL

VDD_RF1_P_HMB_LO

VDD_RF1_P_HB_LO

VDD_RF1_P_LB

VDD_RF1_P_HMB

VDD_RF2_P_BB

VDD_RF2_P_RX

VDD_DIO

VDD_RF2_FBRX

VDD_RF1_D_MB

VDD_RF1_D_LOM

VDD_RF1_D_LB_LO

VDD_RF1_D_LB

VDD_RF1_D_HB

VDD_RF2_D_BB

VDD_RF1_G_VCO

VDD_RF1_G_PLL

VDD_RF1_G_LNA

VDD_RF1_G_BB

Page 44: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

MB2

U1002L1000R1016C1019

DC

MB1

NO DC

MB3

MB2

MB1 DC

DC

DC

MB3

NO DC

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.WFR TRANSCEIVER

50_WFR_PRX_HB_CA_IN

44 OF 6039 OF 55

4.0.0051-00648

C3902_RF

42

42

42 42

C3903_RFC3901_RF

R3901_RF

C3917_RF

C3904_RF

C3916_RF

C3915_RF

C3913_RF

C3912_RF

C3911_RF

C3910_RF

XW3901_RF

XW3902_RF

C3905_RF

XW3900_RF

U_WFR_RF

U_WFR_RF

17

37

23

56

33

44

10

31

15

24

59

47

39

2

60

58

55

53

51

50

48

46

45

42

41

40

38

35

32

26

21

20

18

14

12

11

9

8

4

7

13

19

5

61622

3

27

2530

2928

61

52

34

1

65

665449

36

43

5764

6263

2

1

2

1

2

1

21

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1RADIO_WFR

RADIO_WFR

4.75K WFR_BB_DRX_Q_N

50_B25_PRX_WFR_IN

50_B3_PRX_WFR_IN

50_B25_DRX_WFR_IN

VDD_PRX_VCO_WFR_2V

VDD_XO_WFR_2V

WFR_BB_PRX_Q_NWFR_BB_PRX_Q_P

50_B1_B4_PRX_WFR_IN

50_B1_B4_DRX_WFR_IN50_B3_DRX_WFR_IN

WFR_BB_PRX_I_P

WFR_RTUNE

50_WFR_DRX_MB_CA_OUT

WFR_BB_PRX_I_N

50_WFR_PRX_LB_CA_IN

WFR_BB_DRX_I_PWFR_BB_DRX_I_NWFR_BB_DRX_Q_P

WFR_SSBI

50_WFR_PRX_MB_CA_OUT

VDD_XO_WFR_2V

VDD1_1P8V

VDD1_DRX_BB_2V

VDD1_PRX_BB_2V

VDD1_DRX_BB_2V

VDD1_PRX_BB_2V

50_WFR_DRX_LB_CA_IN

50_RF_CLK

VDD1_1P8VPP_LDO11MAKE_BASE=TRUE

VREG_2V_WFRPP_LDO8MAKE_BASE=TRUE

PP_LDO1MAKE_BASE=TRUE

VDD_DIG_1P3V

VDD_PRX_VCO_WFR_1P3V

VDD_PRX_VCO_WFR_1P3V

VDD_PRX_PLL_WFR_1P3V

VDD_PRX_PLL_WFR_1P3V

VDD_PRX_MBHB_FE_1P3V

VDD_PRX_MBHB_FE_1P3V

VDD_PRX_LO_WFR_1P3V

VDD_PRX_LO_WFR_1P3V

VDD_PRX_LB_FE_1P3V

VDD_PRX_LB_FE_1P3V

VDD_DRX_MB_HB_FE_1P3V

VDD_DRX_MB_HB_FE_1P3V

VDD_DRX_LO_1P3V

VDD_DRX_LO_1P3V

VDD_DRX_LB_WFR_1P3V

VDD_DRX_LB_WFR_1P3V

VDD_DIG_1P3V VREG_2V_WFR MAKE_BASE=TRUE VDD_PRX_VCO_WFR_2VMAKE_BASE=TRUE

PPLDO1_WFR

RF TRANSCEIVER (3 OF 3)

0.1UF

RADIO_WFR

01005

20%4VX5R

CERM-X5R

10UF20%6.3V

RADIO_WFR

0402-96.3V20%10UF

CERM-X5R

RADIO_WFR

0402-9

1%

RADIO_WFR

1/32W01005MF

01005

RADIO_WFR

0.1UF4VX5R20%

RADIO_WFR

X5R20%0.1UF4V01005

01005

0.1UFX5R20%4V

RADIO_WFR

01005

0.1UF

RADIO_WFR

20%4VX5R

RADIO_WFR

4V0.1UF20%X5R01005

0.1UF20%X5R4V01005

RADIO_WFR

0.1UF

01005X5R4V20%

RADIO_WFR

4VX5R

0.1UF20%

01005

01005

0.1UFX5R4V20%

RADIO_WFR

I114

I113

BGAWFR1620

WFR1620BGA

20

16

16

11

11

8

8

16

20

20

8

8

8

8

8

8

8

11

11

11

11

11

11

9 5

11 12 10 8 7 6 4 3

11 10 4

10 6 4

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11 11 11

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

OUT

OUTIN

SYM 2 OF 2

PWR_GND

VDD_RF1_P_LO

VDD_RF2_P_VCO

VDD_RF1_P_PLL

GND

GND

VDD_RF1_D_MHB_FE

VDD_RF1_D_LB_FE

VDD_RF2_D_BB

VDD_RF1_D_LO

VDD_RF2_XO

VDD_RF1_P_MHB_FE

VDD_RF1_P_VCO

VDD_RF2_P_BB

VDD_RF1_P_LB_FE

VDD_DIO

VDD_RF1_DIG

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

RX_OTHER

SYM 1 OF 2

GND

GND

GND

GND

PRX_BB_QMPRX_BB_QP

PRX_MB2_IN

DRX_MB1_INDRX_MB2_INDRX_MB3_IN

DRX_HB_CA_IN

DRX_LB_CA_IN

PRX_BB_IP

R_TUNE

XO_IN

DRX_MB_CA_OUT

PRX_BB_IM

PRX_LB_CA_IN

PRX_MB3_IN

PRX_MB1_IN

PRX_HB_CA_IN

DRX_BB_IPDRX_BB_IM

DRX_BB_QPDRX_BB_QM

SSBI_PRX_DRX

PRX_MB_CA_OUTNC

NC

Page 45: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

> 1.0MM

SHOULD BE PLACEDFROM QPOET

U1101L1104R1102C1110

QPOET TIMING

(CAN BE CHANGED TO 20UF)

(USID)

INDUCTANCE

I/O @ 1.8V

CRITICAL TO STAY@ 4.7UF TO MEET

IN VLB (B13)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

MAX 0.25MM AWAY

QFE DCDC

BOOST FILTER

MITIGATE RX1 DESENSE

BOTH XW'STO CREATE

45 OF 6040 OF 55

4.0.0051-00648

C4006_RF

C4010_RF

U_QPOET_RFL4002_RF

L4004_RF

XW4004_RF

XW4002_RF

XW4001_RF

C4001_RF

L4001_RF

C4003_RFC4002_RF

C4005_RF

L4003_RF41

41

36 41 46 47 48 49 50

36 41 46 47 48 49 50

R4001_RF

C4008_RFC4007_RF

2

1

2

1

23

20

25

28

1615

5

17

19

26

21

18

13

27

24

3

22

1

98

6

1211

1014

4

72

21

21

2

1

21

21

2

1

21

2

1

2

1

2

1

21

2

1

2

1

2

1

VPA_ET

VPA_ET

APT_VINPUT

VOUT_BOOST_GND

VOUT_BOOST

QPOET_BATT

VBATT_SW

SW_GROUND

ET_DAC_P

APT_VINPUT

PP_LDO11

VPA_APT

ET_DAC_N

GSM_CAP

VPA_BATT

QPOET_VSW

BST_L

VPA_APT

PP_LDO11

GSM_CAPVPA_ET_FILTER

VPA_ET

PP_BATT_VCC

PP_BATT_VCC

PP_BATT_VCC

PP_BATT_VCC

VBATT_SW

PA_CTL_QFE

PP_BATT_VCC

RFFE1_DATA

RFFE1_CLK

SW_GROUND

VOUT_BOOST

VOUT_BOOST_GND

QFE DCDC

0402-9

10UF

CERM-X5R6.3V20%

RADIO_QPOET

10%10V

RADIO_QPOET

470PFX5R01005

BGAQFE110022-OHM-25%-1800MA

0201

22-OHM-25%-1800MA

0201

NOSTUFFSHORT-10L-0.25MM-SM

NOSTUFF

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

NOSTUFF

0402-9

10UF20%6.3VCERM-X5R

RADIO_QPOET

RADIO_QPOET

08052.2UH-20%-0.7A-0.23OHM

0402-9CERM-X5R6.3V

RADIO_QPOET

10UF20%

0402-9

RADIO_QPOET

CERM-X5R6.3V10UF20%

0402CERM-X5R

20%6.3V

RADIO_QPOET

20UF

PSB25201T-SMRADIO_QPOET

1.5UH-1.95A-0.111OHM

RADIO_QPOET

RADIO_QPOET

5%2.2

MF1/32W01005

10V470PF10%

RADIO_QPOET

X5R01005

0402

RADIO_QPOET

20%10VX5R-CERM

4.7UF

17 16 15 14 12

17 16 15 14 12

12

12

12

12

12

12

12 11 10 8 7 6 4 3

1713 12

12

1716 15 14

12 11 10 8 7 6 4 3

17 1615 14 12

2721 19 18 12

27 21 19 18 12

27 21 19 18 12

27 21 19 18 12

12

5

27 21 19 18 12

12

12

12

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

GND

USID_LSB

VSW_BOOST

VSW_BUCK

VOUT_BOOST

VDD_BUCK

AMP_OUT

PA_VBAT

MPP1

C_GSM

GND_BUCK

GND_BOOST

AMP_INPAMP_INM

C_SW_BUCKC_SW_BUCK

C_BUCKC_BUCK

SCLK

SDATA

BYP_LOADBYP_BATT VDD_BATT

VDD_BATT

VDD_1P8

VDD_AMP

GND_AMP

IN

IN

BI

BI

Page 46: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

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2G PACONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

U1201L1204R1200C1208

46 OF 6041 OF 55

4.0.0051-00648

U_2GPA_RF

C4118_RF

R4100_RF

C4113_RF

C4112_RF L4101_RF

L4102_RF

C4108_RF C4109_RF

C4104_RF

C4103_RF

C4107_RF

2

1

21

2

1

2

1

21

21

2

1

2

1

21

21

2

1

SKY77357LGA

01005

50_LB_2G_PA_OUT

50_HB_2G_PA_OUT

2G_PA_VBATT_10UAPP_VCC_MAIN

50_LB_2G_WTR_TX_OUT

50_HB_2G_WTR_TX_OUT

50_LB_2G_ASM_IN

VPA_APT

50_LB_2G_PA_IN

50_HB_2G_PA_INRFFE_VIORFFE1_DATARFFE1_CLK

50_HB_2G_ASM_IN

2G PA

+/-0.05PF0.5PF

01005C0G-CERM16V

0201-1

600-OHM-25%-0.1A

NOSTUFF01005

RADIO_2G

+/-0.1PFNP0-C0G16V0.8PF

100PF

01005NP0-C0G16V5%

4.7NH+/-0.3%-0.4A

0201

1.5NH+/-0.1NH-1.0A

0201

20%2.2UF6.3V

RADIO_2G

X5R-CERM0201

20%2.2UF6.3V

RADIO_2G

X5R-CERM0201

RADIO_2G

01005NP0-C0G16V5%

100PF

100PF

RADIO_2G

5%16V

NP0-C0G

56PFNP0-C0G5%

RADIO_2G

16V01005

16

27 25 24 4

9

9

18

17 12

21 19 18 17 14 8

17 16 15 14 12 8 3

17 16 15 14 12 8 3

18

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

VCCVBATT

LBRFIN

HBRFIN

LBRFOUT

HBRFOUT

VIOSDATASCLK

GNDEPAD

Page 47: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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PLACE INDUCTOR CLOSE TO PA

01

OUT V2

VERY LOW BAND PAD (B13, B17, B28)

B28

B12B17BAND

RF2RF3

RF4

01

1

1

L4215_RFR1300C1332

U1304CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

PLACE INDUCTOR CLOSE TO PA

V1

B13

PLACE INDUCTOR CLOSE TO PA

P2 DOE

USE OMIT TABLE TO SELECT SKU VARIANT.

47 OF 6042 OF 55

4.0.0051-00648

C4206_RF

C4201_RF

C4207_RF

C4223_RF

XW4200_RF

L4211_RF

U_VLB_SW_RF

U_VLBPAD_RF

C4208_RF

C4231_RFC4230_RF

L4224_RF

L4217_RF

C4211_RF

L4216_RF

L4222_RF

L4223_RF

L4221_RF

C4227_RF

C4213_RF

C4224_RF

C4221_RF

FL_B17LP_RF

C4219_RF

2

1

21

2

1

2

1

2

1

21

21

2

1

21

21

21

21

2

1

2

1

21

24

31

2

1

2

1

2

1

NOSTUFF

+/-0.1PFNP0-C0G

RFFE1_DATA

3.3PF16V01005

50_B28_PAD_IN

50_B12B17_PAD_IN

7.5NH+/-3%-0.2A

2.2PF

01005-1

+/-0.1PF16VNP0-C0G

OMIT_TABLE

01005

OMIT_TABLE

CTRL_VLB_BAND_SELECT_1

NP0-C0G

50_B13_B17_B28_WTR_TX_OUT

SHORT-10L-0.1MM-SM

CERM5%16V01005

47PF

50_B13_B17_B28_B29_PRX_WTR_IN

CTRL_VLB_BAND_SELECT_2

50_B12B17_PAD_IN

CTRL_VLB_BAND_SELECT_2CTRL_VLB_BAND_SELECT_1

22-OHM-25%-0.2A-0.9DCR

50_B13_PAD_ANT

+/-0.1PF2.5PF

NP0-C0G

OMIT_TABLE

16V

01005

10NH-3%-0.170A

OMIT_TABLE

01005

50_B28A_ASM_TRX

50_B13_PAD_IN

CXA2973GC

NOSTUFF

+/-0.1PF1.0PF

01005NP0-C0G16V

LFL15710MTCTD717BAND17

0402

100PF

16V5%

01005NP0-C0G

100PF5%10V

01005

2.7PF

01005-1NP0-C0G

+/-0.1PF16V

01005

2.4NH+/-0.1NH-0.370A

5.1NH-3%-0.250A

OMIT_TABLE

01005

01005

7.5NH+/-3%-0.2A

01005

5%

01005

15PF16VNP0-C0G-CERM +/-0.05PF

1.5PF

NP0-C0G-CERM16V

01005

OMIT_TABLE

16V5%

01005NP0-C0G

68PF

LGA

OMIT_TABLE

SKY77802-23

22NH-5%-0.1A

01005

RADIO_VLB_PAD

1.0UF20%10V0201-1X5R-CERM

100PF

NP0-C0G

5%10V

01005

OMIT_TABLE

VERY LOW BAND PAD

50_B29_PAD_ANT

50_B13_ASM_TRX

50_B28B_PAD_ANT50_B17_PAD_ANT

50_B28A_PAD_ANT

VPA_ET

50_B13_B17_B28_B29_MCH_RX

VCC_VLB_SW

50_B28_PAD_IN

RFFE_VIO

50_B17_ASM_TRX50_B17_PAD_LPF_IN

LB_VLB_VIO

RFFE1_CLK

50_B13_PAD_IN

VPA_BATT

50_B29_ASM_TRX

50_B28B_ASM_TRX

PP_LDO14_RFSW

50_B13_B17_B28_B29_PAD_RX

BGA9

14

15

14

18

12 15 16 17

4 23

14

14

9

14

8 13 16 17 18 1921

18

18

15

3 8 12 13 15 16 17

14

14

12 15 16 17

18

18

14

14

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

RF3

RF1RF2

RF4

V1

VDD

V2

PAD

RX_OUT

GND

SW1SW2

B13_ANT

B28B_ANT

B29_RX_IN

B28A_ANT

B17_ANT

VIO

SDATASCLK

B13_INB17_INB28_IN

THRM

VCCVBAT

GND

OUTIN

Page 48: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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11

BE A CAPACITOR.FIRST SHUNT MUSTWTR OUTPUT HAS DC

CAPACITOR THAT'S SUPPOSED TO GO HERE IS LOCATED ON

LOW BAND PAD (B8, B26, B20)

B20

V201 B26

C4318_RF

L4322_RFR1400

U1402

BANDV11 B80

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

VERY LOW BAND PAD. THE 2 PAD'S NEED TO SHARE DECOUPLING

051-00648

43 OF 5548 OF 60

4.0.0

C4311_RF

C4314_RF

C4309_RF

C4304_RF

C4303_RF

C4301_RF

C4305_RF

XW4300_RF

C4300_RF

C4320_RF

L4301_RF

U_LBPAD_RF

L4313_RF

L4312_RF

L4322_RF

C4313_RF

L4315_RF

L4316_RF

C4317_RF

C4318_RF

L4321_RF

L4320_RF

C4321_RF

L4306_RFU_LB_SW_RF

21

2

1

21

2

1

2

1

21

2

1

21

21

2

1

2

1

21

21

2

1

1

23

4756

98

21

21

21

21

21

50_B8_PAD_IN

PP_LDO14_RFSWSHORT-10L-0.1MM-SM

50_B8_PAD_IN

50_B26_WTR_TX_OUT50_B20_WTR_TX_OUT

50_B26_WTR_TX_OUT18PF

CERM

VCC_LB_SW

CTRL_LB_BAND_SELECT_1

50_B8_B26_B20_WTR_TX_OUT6.8NH-140MA

01005

2.7PF

NP0-C0G

+/-0.1PF16V

01005

+/-0.1PF

50_B20_PAD_IN

01005

16VNP0-C0G

0.7PF

50_B26_PAD_IN

50_LB_SW_MCH_IN50_LB_SW_T_MCH

CERM16V5%

01005

10VNP0-C0G

CTRL_LB_BAND_SELECT_2

50_B8_ASM_TRX

50_B26_PAD_ANT

VPA_ET

50_B20_PRX_WTR_IN50_B20_MATCH_1

50_LB_SW_MCH_IN

50_B26_ASM_TRX

50_B8_MATCH_1 50_B8_PRX_WTR_IN

50_B20_ASM_TRX

CTRL_LB_BAND_SELECT_1 50_B20_PAD_RX

50_B8_PAD_RX

LB_VLB_VIORFFE1_CLK

VPA_BATT

50_B26_PRX_WTR_IN

50_B8_PAD_ANT

50_B20_WTR_TX_OUT

50_B26_PAD_RX

RFFE1_DATA

CTRL_LB_BAND_SELECT_2

50_B26_MATCH

50_B20_PAD_ANT

LOW BAND PAD

100PF

NP0-C0G16V5%

01005

5%16VCERM01005

47PF

01005NP0-C0G

5%16V

100PF

01005NP0-C0G10V5%

100PF

100PF

01005

5%

01005

16V5%47PF

47PF5%

16VCERM

01005

LGATQF6410

8.2NH-3%-0.19A-1.6OHM01005

01005

7.5NH+/-3%-0.2A

01005-1

18NH-3%-0.140A

+/-0.05PF16V

0.9PF

CERM01005

01005

15NH-3%-0.140A

01005

5.1NH-3%-0.250A

01005

16V

1.0PF

NP0-C0G

+/-0.1PF

1.5PF

NP0-C0G

+/-0.1PF16V

01005

01005

3.3NH+/-0.1NH-290MA

5.6NH-3%-0.23A-1.3OHM

01005

18NH-3%-140MA

NOSTUFF

01005

BGA

RADIO_LB_PAD

CXA2973GC

15

15

15

15

18

17 16 14 12

9

15

15

18

9

18

9

15

14

17 16 14 13 12 8 3

17 16 14 12

15

15

15

17 16 14 13 12 8 3

15

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PADTHRM

VCC1

B20IN

SW1SW2

B20RX

B20ANT

B26RX

B26ANTB8ANT

B8RX

VCC2

GND

VIO

SDATASCLK

B8INB26IN

VBATT

GND

RF3

RF1RF2

RF4

V1

VDD

V2

Page 49: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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MID BAND PAD (B1, B25, B3, B4, B34, B39)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. L4409_RF

U1501

R1500C4426_RF

051-00648

44 OF 5549 OF 60

4.0.0

C4425_RF

FL_B39LP_RF

C4423_RF

C4408_RF

C4407_RF

L4401_RF

L4402_RF

L4405_RF

C4413_RF

L4408_RF

L4421_RF

L4403_RF

L4404_RF

L4407_RF

C4418_RF

L4409_RF

L4406_RF

U_MBPAD_RF

2 1

2

1

21

2

1

21

21

21

21

2

1

21

21

21

24

31

21

2

1

2

1

1

262736

484746454443424140393837

32

33323130292825232221201918171514 13119764

24

5

8

1235

34

10

16

2.2NH+/-0.1NH-200MA01005

1.2NH+/-0.1NH-220MA

01005

3.6NH+/-0.1NH-180MA

01005

2.5NH+/-0.1NH-0.2A

01005

01005

16VNP0-C0G

50_B25_ASM_MATCH

1.4PF+/-0.1PF

50_B1_B25_B34_B39_WTR_TX_OUT

VPA_BATT

RFFE_VIO

50_B25_PRX_WFR_IN

50_B25_PRX_MATCH

50_B34_B39_HB_SWITCH_IN

VPA_ET

50_B3_PAD_RX

50_B3_PRX_WFR_IN50_B3_PRX_MATCH

50_B3_B4_WTR_TX_OUT

50_B25_ASM_TRX

50_B34_B39_PAD_ANT50_B34_B39_LPF_IN

50_B1_B4_PAD_RX50_B25_PAD_RX

RFFE1_CLKRFFE1_DATA

50_B1_B3_B4_ASM_TRX

50_B1_B3_B4_PAD_ANT50_B25_PAD_ANT

50_B1_B4_PRX_WFR_IN

MID BAND PAD

33PF

01005NP0-C0G-CERM

16V5%

RADIO_WFR

0402

OMIT_TABLE

LFL151G95TCSD734BAND34-39

16V

33PF

01005NP0-C0G-CERM

5%

RADIO_WFR

47PFCERM16V5%

01005

RADIO_MB_PAD

X5R-CERM10V1.0UF20%

0201-1

RADIO_MB_PAD

1.5NH+/-0.1NH-0.400A

01005

0.8NH+/-0.1NH-0.630A

OMIT_TABLE

01005

01005

3.6NH+/-0.1NH-0.280A

2.2NH+/-0.1NH-0.380A

01005

01005

1.3NH+/-0.1NH-0.400A

+/-0.1PF16V

01005NOSTUFF

0.2PF

NP0-C0G

2.7NH+/-0.1NH-0.370A

RADIO_WFR01005

LGA

RADIO_MB_PAD

AFEM-8020-AP1

9

17 15 14 12

21 19 18 1714 13 8

11

19

17 15 14 12

11

9

18

17 15 14 1312 8 3

17 15 14 1312 8 3

18

11

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

OUTIN

VBAT

T

VCC1

B34_39_OUT

B25RXB1/4RX

B3RXVCC2

VIO

B25ANTB1/3/4ANT

SCLKSDATA

GND

GND

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

EPAD

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

B3/4IN

B1/25/34/39IN

Page 50: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

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C4533_RF

L1616R1600

U1601

HIGH BAND PAD (B7, B38, B40, B41, XGP)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

051-006484.0.0

50 OF 6045 OF 55

FT_41BC_RF

C4502_RF

U_HBPAD_RF

C4503_RF

C4522_RF

C4505_RF

C4500_RF

C4521_RF

L4516_RFL4517_RF

FTB40A41A_RF

C4506_RF

C4507_RF

L4528_RF

L4525_RF

L4515_RF

C4532_RF

L4522_RF

C4520_RF

L4526_RF

R4509_RF

C4533_RF

L4524_RF

L4523_RFL4527_RF

L4520_RF

L4507_RF

R4531_RF

L4506_RFC4528_RF

FT_B40_RF

C4501_RF

L4512_RF

21

2

1

21

2

1

2

1

21

2

1

2

1

10 9 6 5 2 3

14

87

2

1

2

1

2

1

2

1

2

1

2121

21

2

1

2

1

21

2

1

2

1

41

532

21

21

6 49 1

10 8 7 5 3 2

2

1

2

1

2

1

OMIT_TABLE

16V

01005NP0-C0G

+/-0.1PF0.7PF

50_B7_ASM_TRXOMIT_TABLE

0%

0.00

01005

1/32WMF

OMIT_TABLE0.3PF+/-0.1PF16VNP0-C0G01005

OMIT_TABLE

3.1NH-+/-0.1NH-0.29A

2.7NH+/-0.1NH-0.6A

50_B40B_TX_PAD50_B41C_TX_PAD50_B40A_B41A_TX_PAD

RFFE_VIORFFE1_CLK

50_B41C_FILTER_IN

50_B40A_B41A_FILTER_IN50_B41A_TX_HB_SWITCH_IN

OMIT_TABLE

50_B40A_TX_HB_SWITCH_IN

7.5NH-5NH%-140MA

4.3NH-3%-0.270A

+/-0.1PF

NP0-C0G

50_B40A_TX_HB_SWITCH_MCH

OMIT_TABLE

1/32WMF

0.00

0%

01005

OMIT_TABLE

1PF

01005

OMIT_TABLE

OMIT_TABLE

16V

SAW-BAND-40A-41A-TDD-LX

9.1NH-3%-0.17A-1.7OHM

01005

OMIT_TABLE

0201

+/-0.5PF0.3PF

CERM

OMIT_TABLE

01005

16V

OMIT_TABLE

50_B41C_FILTER_IN50_B41B_FILTER_IN 50_B41B_TX_HB_SWITCH_MCH

50_B7_PRX_WTR_IN

50_B40B_TX_FILTER_OUT 50_B40B_TX_HB_SWITCH_IN

50_B41B_TX_HB_SWITCH_IN

50_B7_WTR_TX_OUT

50_B7_PAD_IN

50_B41C_TX_HB_SWITCH_MCH 50_B41C_TX_HB_SWITCH_IN

VPA_BATT

50_B40B_TX_FILTER_IN50_B40_B38_B41_WTR_TX_OUT

50_B38_B40_B41_PAD_IN

VPA_ET

VPA_APT

50_B40A_B41A_FILTER_IN

50_B41B_FILTER_IN

RFFE1_DATA

50_B7_RX_PAD

50_B41B_TX_PAD

50_B7_ANT_PAD

HIGH BAND PADSAWEN2G58QA0F57

OMIT_TABLE

SAW-BAND-41B-41C-TDD-TX

LGA

RADIO_HB_PAD

RADIO_HB_PAD

LGA

OMIT_TABLE

RADIO_HB_PAD

TQF6430

OMIT_TABLE

1.0PF

01005NP0-C0G16V+/-0.1PF

RADIO_HB_PAD

OMIT_TABLE

RADIO_WTR

1.8PF

01005NP0-C0G16V+/-0.1PF

1.0UF20%

OMIT_TABLE

RADIO_HB_PAD

10VX5R-CERM0201-1

3.0PF

01005NP0-C0G

16V+/-0.1PF

01005

OMIT_TABLE

OMIT_TABLE

010051.5NH+/-0.1NH-0.400A

LGA

OMIT_TABLE

885058

0201-1X5R-CERM

OMIT_TABLE

20%1.0UF10V

RADIO_HB_PAD

OMIT_TABLE16V5%68PF

01005NP0-C0G

OMIT_TABLE

1.4NH+/-0.1NH-1.1A

0201

OMIT_TABLE

68PF

NP0-C0G-CERM01005

25V5%

0201

OMIT_TABLE

2.7NH+/-0.1NH-0.6A

OMIT_TABLE

2.2NH+/-0.1NH-0.380A

01005

01005NP0-C0G

OMIT_TABLE

RADIO_HB_PAD

5%16V

100PF

OMIT_TABLE

1.8NH+/-0.1%-0.380A

01005

OMIT_TABLE

010059.1NH-3%-0.17A-1.7OHM

OMIT_TABLE

01005

1.3NH+/-0.1NH-0.400A

OMIT_TABLE

01005

010057.5NH+/-3%-0.2A

01005

LGASAFFU2G35MA0F57TX-BAND40-LTE

OMIT_TABLE18PF

RADIO_HB_PAD

16VCERM

2%

01005

OMIT_TABLE

01005

3.3NH+/-0.1NH-290MA

18

14

17

14

19

17

17

9

9

16 15 14 12

9

16 15 14 12

13 12

17

17

161513

12 8 3

161514 13

12 8 3

21

1918 16 13 8

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

B41COUT

B41BOUT

B41CIN

B41BINRF3/

RF1/RF2/

RF4/

GND

GND

GND

GND

GND

GND

VAPT

VCC2

VCC1

VBAT

T

B7IN

B38_40_41

EPAD

GND

GND

GND

GND

GND

GND

GND

GND

GND

SDATA

VIOSCLK

B41CB40A/B41A

B7RXB7ANT

B41B

GND

GND

GND

GND

B40B

B41A_PORTB40A_PORT

GND

GND

GND

GND

GND

GND

ANT_B41AANT_B40A

UNBAL_PRT1 UNBAL_PRT4

GND

GND

GND

Page 51: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

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TO DIVERSITY MODULE

U1702

C1702R1700L4608_RFANTENNA SWITCH

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

TO DIVERSITY MODULE

46 OF 5551 OF 60

051-006484.0.0

L4601_RFFRX34B39_RF U_ASM_RF_RF

C4602_RF

L4603_RF L4604_RF

R4607_RF

C4606_RF

L4602_RF

21

2

1

2

1

21

6

91

10875432

26

29

11

242322

1716

188

109

2728

7

4

321

14

19

12

20

3331630251513

32

21

5

2

1

2

1

2

1

50_HB_SWITCH_TX

50_HB_SWITCH_RX

VCC_ASM_FILTERED

50_B20_ASM_TRX

50_HB_DIVERSITY_ASM

50_B1_B3_B4_ASM_TRX

50_B34_RX_ASM_OUT

50_B39_RX_ASM_OUT

50_B7_ASM_TRX

50_B25_ASM_TRX

50_FWD_OR_REV_RF

50_ANT2_CONN

50_ANT1_CONN

RFFE_VIO

RFFE2_DATA

RFFE2_CLK

50_HB_2G_ASM_IN

50_B17_ASM_TRX

50_B8_ASM_TRX

50_B28A_ASM_TRX

50_B28B_ASM_TRX

50_B26_ASM_TRX

50_B13_ASM_TRX

50_B29_ASM_TRX

50_LB_DIVERSITY_ASM

50_LB_2G_ASM_IN

RF5159LGA2.4NH+/-0.1NH-200MA

PP_BATT_VCC

50_B34_B39_FILT_RX50_B34_B39_PRX_WTR_IN

ANTENNA SWITCH

OMIT_TABLE

01005

BAND34-39

LGASAWFD1G90LC0F57

OMIT_TABLE

47PF

01005CERM5%16V

1.0NH+/-0.1NH-0.22A-0.9OHM01005

NOSTUFF

1.0NH+/-0.1NH-0.22A-0.9OHM

NOSTUFF01005

0.00

MF

0%1/32W

01005

22PF5%16V

01005CERM

OMIT_TABLE

3.3NH+/-0.1NH-180MA01005

19

19

21

14

14

15

14

14

15

14

13

3 8 19 21

8 19 21

8 13 14 16 17 19 21

23

23

9

16

17

16

21

15

27 21 19 12

9

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

OUT_FIL2

OUT_FIL1INPUT

VDD

TRX11

HBRF2

TRX7TRX6RX1

RF7

TRX8

FWD/REV

A2

A1

VIO

SDATASCLK

GND

RF1RF3

HBTX

TRX2TRX3TRX0TRX1TRX4TRX5

RX2

LBRF2

LBTX

Page 52: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.HIGH BAND SWITCH

52 OF 60

C4703_RF

L4713_RF

L4704_RF L4708_RFL4712_RF

L4706_RF

L4705_RF

U_HBS_RF

L4710_RF

L4709_RF

C4720_RF

C4701_RFFR38X40B_RF

FR40A41A_RF

R4700_RF

XW4700_RF

C4710_RF

47 OF 55

4.0.0

051-00648

21

21

21

2

1

2

1

2

1

2

1

2

1

4

1

5

10987

1211

17

23

16151314

6

2

1

2

1

21

21962

10875431

69

10 8 7 5 4 3 1

22

1

50_HB_SWITCH_RX

50_HB_SWITCH_TX

OMIT_TABLE

50_B40B_RX

50_B40B_B38X_PRX_FILTER

2.2NH+/-0.1NH-200MA01005

OMIT_TABLE

SAW-BAND-40A-41A-TDD-RX

50_B40B_TX_HB_SWITCH_IN

50_B41B_TX_HB_SWITCH_IN

50_B34_B39_HB_SWITCH_IN

50_B40A_TX_HB_SWITCH_IN

50_B41C_TX_HB_SWITCH_IN

50_B41A_TX_HB_SWITCH_IN

50_B41A_PRX_WTR_IN 50_B41A_PRX_MATCH 50_B41A_PRX_FILTER

RFFE2_CLK

RFFE2_DATA

50_B40B_B38X_PRX_MATCH2

0.00

OMIT_TABLE

0%

01005

1/32WMF

1.4NH+/-0.1NH-0.4A

OMIT_TABLE

01005

OMIT_TABLE

01005

5%

100PF

CERM6.3V

2.7NH+/-0.1NH-0.370A

2.7NH+/-0.1NH-0.370A

16V5%CERM

47PF

01005

SHORT-10L-0.1MM-SM

LGA

885055

OMIT_TABLE

OMIT_TABLE

LGA

885056SAW-BAND-40B-38X-TDD-RX

RADIO_HBSWITCH

OMIT_TABLE

NP0-C0G

100PF

10V

01005

5%

OMIT_TABLE

12NH-3%-0.140A01005

CXM3652URUQFN

OMIT_TABLE

OMIT_TABLE

010052.0NH+/-0.1NH-0.380A

OMIT_TABLE01005

OMIT_TABLE

2.9NH-+/-0.1NH-0.36A01005

OMIT_TABLE

3.7NH-+/-0.1NH-0.27A01005

OMIT_TABLE

01005

OMIT_TABLE

5%

18PF

CERM16V

01005

HIGH BAND SWITCH

VCC_HBS PP_BATT_VCC

50_B40A_PRX_FILTER

50_B40A_B41A_RX

50_B40B_B38X_PRX_WTR_IN50_B38X_RX

50_B40A_PRX_WTR_IN

50_B40B_RX

RFFE_VIO

50_B40A_B41A_RX

50_B38X_RX

18

12

17

9

18

18 21 27

19

3 8 18 21

9 19

9

19

8 13 14 16 17 18 21

8 21

19

19

19

17

17

17

16

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PAD

VBATT

GNDTHRM

SDATASCLKVIO

TX RF1TX3TX4TX5TX6

TX1TX2

RX2RX1

RX3RX RF1

RF3/RX_B40BRF2/RX_B38X

RF1/ANT

GND

GND

GND

GND

GND

GND

GND

RX_B40ARX_B41A

ANT

GND

GND

GND

GND

GND

GND

GND

Page 53: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

LOWBAND DIVERSITY - WTR

PLACE AT WTR END OF TRACE

R1800L1829U1801

C4826_RF

MIDBAND DIVERSITY - WTR

PLACE AT WTR END OF TRACE

MIDBANDMIDBAND DIVERSITY - WFR

RX DIVERSITY (1)HIGHBAND DIVERSITY - WTR

051-006484.0.0

48 OF 5553 OF 60

C4818_RF

C4817_RF

C4808_RF

C4816_RF

L4808_RF

C4804_RF

C4805_RF

L4817_RF

L4816_RF

C4827_RF

L4827_RF

L4825_RF

L4821_RF

L4822_RF

L4820_RF

L4813_RF

L4810_RF

L4802_RF

L4804_RF

L4801_RF

L4805_RF

C4803_RF

L4806_RF

L4829_RF

C4820_RF

R4815_RF

L4814_RF

L4830_RF

C4831_RF

C4832_RF

L4826_RF

C4826_RF

L4819_RF

L4823_RF

L4809_RF

L4807_RF

C4809_RF

21

2

1

21

21

21

2

1

21

21

21

21

21

21

21

21

21

21

21

21

2

1

21

21

2

1

2

1

21

21

21

21

21

21

21

21

21

21

21

21

21

21

NOSTUFF

0.3PF16V+/-0.05PF

C0G-CERM01005

22NH-5%-0.1A

01005

0100516V

2.0NH+/-0.1NH-0.380A

01005

2.4NH+/-0.1NH-0.370A01005

2.2NH+/-0.1NH-0.380A

16V

100PF

NP0-C0G5%

01005

0.8PF+/-0.05PF

01005

C0G-CERM01005

0.4NH+/-0.1NH-0.990A

01005

0.00

0%

MF1/32W

01005

8.2NH-3%-0.19A-1.6OHM

01005

16VNP0-C0G01005-1

2.2PF+/-0.1PF

1.8NH+/-0.1%-0.380A

2.4NH+/-0.1NH-0.370A

01005

1.6NH+/-0.1NH-0.390A

01005

2.3NH+/-0.1NH-0.370A

01005

01005

2.2NH+/-0.1NH-0.380A

2.7NH+/-0.1NH-0.370A

01005

2.2NH+/-0.1NH-0.380A

01005

5.6NH-3%-0.23A-1.3OHM

01005

10NH-3%-0.170A01005

10V5%

100PF

2.4NH+/-0.1NH-200MA

01005

1.3NH+/-0.1NH-0.400A

01005

100PF

01005

16V5%

NP0-C0G

01005

5%16V

NP0-C0G

100PF

3.6NH+/-0.1NH-180MA

NOSTUFF01005

100PF

NP0-C0G

5%

01005

16V

5%16V

NP0-C0G01005

100PF 16VNP0-C0G01005

100PF

5%

5%16V

NP0-C0G01005

100PF

RX DIVERSITY

50_B41A_DRX_FILTER50_B41A_DRX_WTR_IN50_B41A_DRX_WTR_MCH

50_B1_B4_DRX_DSM

50_B40_DRX_FILTER

50_B3_DRX_MATCH

50_B7_DRX_DSM

50_B26_B28A_DRX_WTR_MCH

50_B39_DRX_MATCH

50_B39_DRX_WTR_IN

50_PCS_WTR_IN

50_B3_DRX_WFR_IN

50_B25_DRX_DSM

50_B13_B17_DRX_DSM

50_B8_B28B_DRX_DSM

50_B34_DRX_DSM

50_B26_B28A_DRX_DSM

50_B34_DRX_WTR_IN

50_B26_B28A_DRX_WTR_IN

50_B7_DRX_WTR_IN

50_B25_DRX_WFR_IN50_B20_B29_DRX_DSM

50_B38X_DRX_WTR_IN

50_PCS_DRX_MATCH

50_DCS_DSM_OUT50_DCS_WTR_IN

50_DCS_DRX_MATCH

50_PCS_DSM_OUT

50_B38X_DRX_DSM

50_B25_DRX_MATCH

50_B3_DRX_DSM

50_B39_DRX_DSM

01005

50_B40_DRX_WTR_IN

01005

3.3NH+/-0.1NH-290MA

01005

NP0-C0G+/-0.1PF

1.1PF

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLEOMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

OMIT_TABLE

01005

1.8NH+/-0.1%-0.380A

01005

C0G-CERM16V

01005

22NH-5%-0.1A

NP0-C0G

50_B13_B17_DRX_WTR_IN 01005

22NH-5%-0.1A

16V+/-0.05PF0.8PF

50_B8_B28B_DRX_WTR_IN01005

1.1NH+/-0.1NH-220MA50_B1_B4_DRX_WFR_IN

50_B20_B29_DRX_WTR_IN9

21 9

21

21

21

21

9 21

9

11

21

21

21

21

21

9

9

9

9

11 21

9

21 9

21

9

21

11

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Page 54: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

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RX DIVERSITY (2) C1900R1900L1900U1901

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

54 OF 6049 OF 55

4.0.0051-00648

U_DSM_RF

C4901_RF

L4905_RF

L4902_RF L4904_RFL4901_RF L4903_RF

FD40B41A_RF

21

2519

3

2

403938373635

4

5

1514

1317

12

34

23

163332

29

31282726242220181110861

30

7

9

2

1

21

2

1

2

1

2

1

2

1

10 8 7 5 3 2

9 16 4

VCC_DSM PP_BATT_VCC

50_B41A_DRX_FILTER

50_B13_B17_DRX_DSM

50_B20_B29_DRX_DSM50_DCS_DSM_OUT

50_B8_B28B_DRX_DSM

50_B34_DRX_DSM

50_B38X_DRX_DSM50_B39_DRX_DSM

50_B41A_DRX_DSM

50_B7_DRX_DSM

50_B25_DRX_DSM 50_HB_DIVERSITY_ASM

50_LB_DIVERSITY_ASM

RFFE2_DATA

RFFE_VIO

RFFE2_CLK50_B3_DRX_DSM50_B1_B4_DRX_DSM

50_B40_DRX_DSM

50_PCS_DSM_OUT50_B26_B28A_DRX_DSM

50_B40_DRX_FILTER

RX DIVERSITY (2)

LGA

OMIT_TABLE

M472B

NP0-C0G-CERM01005

15PF16V5%

01005

22-OHM-25%-0.2A-0.9DCR

5.6NH-3%-0.23A-1.3OHM

OMIT_TABLE

01005

OMIT_TABLE

5.1NH-3%-0.250A01005

01005

OMIT_TABLE

15NH-3%-0.140A01005

OMIT_TABLE

5.6NH-3%-140MA

OMIT_TABLE

SAW-2-1-BAND-40-41A-DRX

LGA

B39252B9920P810

27 19 18 12

20

20

20

20

20

20

20

20

20

20 18

18

19 18 8

19 18 17 16 14 13 8

19 18 8 3

20

20

20 20

20

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

PAD

RX_BAND_1_4RX_BAND_3

SCLK

VDD

VIO

SDATA

ANT_LB

ANT_HB

GND

GND THRM

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

RX_BAND_25

RX_BAND_7

RX_BAND_40RX_BAND_41A

RX_BAND_39RX_BAND_38X

RX_BAND_34

PCS

DCSRX_BAND_20

RX_BAND_8+28B

RX_BAND_26+28A

RX_BAND_12+13

B40IN

B41AINB41AOUT

B40OUT

GND

GND

GND

GND

GND

GND

Page 55: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

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CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

C1900R1900L1900U1901

GPS

55 OF 6050 OF 55

4.0.0051-00648

FL_GPSRF_RF

L5003_RF

L5002_RF

C5001_RF1

52

43

21

21

2

1

100_GPS_WTR_IN_P

50_GPS_DSM_IN

100_GPS_FIL_OUT_P

100_GPS_FIL_OUT_N 100_GPS_WTR_IN_N

GPS

LNA-GNSS-BALB8821LGA

10NH-3%-0.170A

01005

10NH-3%-0.170A

01005

RADIO_GPS

0100516V+/-0.1PF1.0PFNP0-C0G

9

23

9

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

GND

BAL_PORTBAL_PORT

GND

UNBAL_PORT

Page 56: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

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f i x

. c o

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BYPASS CAPS FOR ALTERNATE ANTENNA WITHOUT U_ASWNT

MODULE INCLUDES INTERNAL DECOUPLING

ANTENNA FEEDS

1=UPPER_HB_ANT

ANT & COAX CONNECTOR FOR LOWER & UPPER SECTION OF MLB

GPS FEED

0=UPPER_LBMB_ANT

P2 DOE

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

TO THE PAC FOR LBMB

56 OF 60

4.0.0

51 OF 55

051-00648

LOW_COAX_RF

L5111_RFC5110_RF

L5109_RF

R510

2_RF

C5101_RF

C5102_RF

L5102_RF

UPPER_HB_ANT_RF

XW5100_RF

57

FLWIFDIP_RF

L5135_RF

UPPER_LBMB_ANT_RF

C5139_RF

C513

8_RF

L5123_RF

C5109_RF

SP3_RF

R5101_RF

R5137_RF

C5136_RF LOW_ANT_RF

C5104_RFC5103_RF

L5103_RF

U_ANTPAC_RF

R5135_RFGPS_SP1_RF

UP_COAX_RF

FL5146_RFC5107_RF

C5105_RF

L5108_RF

C5106_RF

L5107_RF

L5101_RF

R5105_RF

R5104_RF

L5106_RF

L5121_RF

L5120_RF

R5136_RF

L5129_RF

C5128_RF

C5130_RF

L5122_RFFLCELWIF_RF

C5129_RF

U_GPSLNA_RF

57

U_SWUANT_RF

VOLTAGE=2.95V

2

1

2121

2

1

21

2

1

2

1

1

432

6

4

5 3 1

2

2

1

1

2

1

21

1

21

211

4 3 2

2

1

2

1

211

3

2

1

2

1

2

1

2

1

21

21

2

1

2

1

21

2

1

2

1

7

6

1

4

9

10 8 5 3 2

2

1

7.5NH-+/-0.2NH-440MA03015

2.5NH+/-0.1NH-500MA

NOSTUFF1%

201

XFLGA

50_UAT_CELL_F

50_UAT_CELL_LPF

2.5NH+/-0.1NH-500MA

0201

1.1PF25VC0G-CERM0201

+/-0.05PF

CXA4011GC50_UAT_CELL

0201

50_UAT_CELL_F

X5R

0.00

5.6NH-3%-0.23A-1.3OHM

50_WICE_CELL2_IN

49.9

1/20W

50_WIFI_2G_NOTCHPLEXER_IN2

885072

1.7NH-+/-0.1NH-0.8A-0.07OHM

1/20WMF

1%1/20W

RADIO_LOW_ANT

50_ANT2_UPPER_COAX_CONN

RFFE2_PAC_CLK_FILT

50_WICE_ANT2_GND

01005

12NH-3%-0.140ANOSTUFF

LGA

DIPLEXER-CELL-WIFI

50_WIFI_2G_DIPLEXER_IN

2.4NH+/-0.2NH-0.57A-0.07OHM

50_NTCH_FILT_OUT

OMIT_TABLE

22PF

CERM

5%16V

NOSTUFF01005

01005

NOSTUFF

20%6.3VX5R

2.2UF

0201-2

NOSTUFF

+/-0.05PF25VC0G-CERM0201

0.3PF

1.4NH+/-0.1NH-1.1A

0201

0201

0.00

MF1/20W1%

3.0NH+/-0.1NH-0.6A

0201

MF1/32W

01005

0.00

0%

MF01005

0.00

03015

20NH-3%-.14A-2.9OHM

01005

16V

01005

5%

NP0-C0G-CERM

33PF

16V

0.8PF

01005

+/-0.05PF

C0G-CERM

01005

10%6.3V

FLTR-GPS-0603LFE18832MHC1D449

F-ST-SM1MM5829-2700

SM-NSP1.6X1.21MM

1/20W1%

0201MF

RF1346WLCSP

20NH-3%-.14A-2.9OHM

01005

0.01UF

X5R

10%6.3V

01005

33PF

NP0-C0G-CERM

5%

01005

16V

F-ST-SM1MM5829-27001.8PF

25VC0G-CERM0201

+/-0.05PF

OMIT_TABLE0.00

MF

MF0201

1%

SPRING-OVERPASS-GND-NORTH-X145

CLIP-SM

0201

SM-NSP1.6X1.21MM

22NH-100MA0201

NOSTUFFI248

SM

F-ST-SM1MM5829-2700

ANTENNA FEEDS50_ANT1_CONN_R

50_WIFI_2G_NOTCHPLEXER_IN

50_UPPER_HB_CELL

PP_LDO13_GPS

50_ANT2_CONN50_UAT_PAC50_UPPER_LBMB

50_GPS_DSM_IN

PP_LDO13

50_WIFI_5G_IN_OUT

UAT_SELECT

VIO_FILT

50_GPS_ANT50_ANT1_CONN

VIO_FILT

RFFE2_PAC_DATA_FILT

RFFE_VIO_S2R

50_GPS_ANT_FEED 50_GPS_ANT_MATCH

25V

0201COG-CERM

+/-0.05PF0.2PF

+/-0.1PF

8.2PF

25V

CER

0201

RADIO_LOW_ANT

MM5829-2700

50_UPPER_HB_ANT_FEED

F-ST-SM1

SKY65736LGA

1.2NH-+/-0.05NH-1.1A-0.04OHM50_UPPER_HB_ANT_FEED2 50_UPPER_HB_ANT_FEED1

0201NOSTUFF

DPX165950DT-8030D1

1/32W0%

RFFE2_CLK_BUFFER

50_WIFI_2G_DIPLEXER_IN2 0.00

RFFE2_PAC_DATA_FILT

10V10%120PF

01005

RFFE2_PAC_CLK_FILT10V10%120PF

01005CER-X7R

RFFE2_DATA_BUFFER

PAC_VDD_3V0

0.01UF

PAC_VDD_3V0_IN

4.3NH+/-3%-0.5A

0201

RADIO_LOW_ANT

CER-X7R

0201

SHORT-10L-0.1MM-SM

47PF

01005CERM16V

VCC_SWANT5%

PP_LDO14_RFSW

23

23

18

22

4 6

23

8

8

8

23

18

23

23

27

4 14 15 23

23

23 15 14 4

23

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

BI

GND

COMMON

HIGH_BAND

LOW_BAND

NC

NCNCNC

GNDNC

RF2

VBAT

NC

VIO

SCLK

SDATA

NC

RF1OUTIN

NC

RF1 RF3

RF2

SMD1_RF2GND

SMD2_RF1/SMD4_GND

RFIN

GND THRM_PAD

RFOUT

VCC

BI

GND

VC1

RF

RF2

RF1

VDD

Page 57: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

MODULE BOOT-STRAPPED TO PCIE INTERNALLYMODULE BOOT-STRAPPED TO HSIC BY GPIO6/SDIO2/SDIO1=110

SWIZZLE DATA LANE ON TOP-LEVELDC BLOCKS LOCATED ON AP SIDE

32K INTERFACE TO AP

WLAN/BT

57 OF 60

L5216_RF

33 60

C5222_RFC5220_RFC5221_RF56

56

R5214_RF

C5211_RF

33 36 60

FL5201_RF

C5213_RF

C5212_RFL5208_RF

33 36 60

R5210_RF

33 36 60

33 60

33 60 36

33 36 60

33 36 60

33 36 60

33 36 60

R5205_RF

R5206_RF

33 60 36

33 36 60

33 60 36

33 60 36

33 60 36

33 36 60

33 36 60

33 36 60

33 36 60

U5201_RF

33 36 60

C5203_RF

C5205_RF

C5202_RF

C5204_RF

R5208_RF

R5201_RF

33 37 46 58 60

33 60

33 36 60

33 36 60

33 36 60

L5201_RF

C5215_RF

36

36

R5202_RF

33 60 36

33 60 36

33 36 60

33 60

33 57 60

33 60

33 60

C5201_RF

VOLTAGE=1.80V

52 OF 55

4.0.0

051-00648

2

1

21

2

1

24

31

2

1

2

1

2

1

2

1

21

21

9

26

22 55542423

23

564

98979695949392919089888786858483828180797877767574737271706968676665646362616059

28

657

12

1918

1716

2120

1413

33

34

3532

3111

8

30

5753525146443729272515136

40413938

10

50

4748

49

4342

5845

2

1

2

1

2

1

2

1

21

21

2

1

4

3

2

1

2

1

2

1

BT_UART_RXD

BT_UART_CTS_L

BT_UART_RTS_L

BT_UART_TXD

PP_WLAN_VDDIO_1V8

4.7UF

WIFI_BTWIFI_BT

0.01UF

0%

WIFI_BT

PP_WL_BT_VDDIO_AP

1/32W01005 27PF

BT_REG_ON

90_WLAN_PCIE_RDN

90_WLAN_PCIE_REFCLK_N

WLAN_PCIE_CLKREQ_L

CERM

90_WLAN_PCIE_TDP

OSCAR_CONTEXT_A

OSCAR_CONTEXT_B

WLAN_JTAG_SWDIO

WLAN_PCIE_PERST_L

5%

01005

16V

100PF

NP0-C0G

PP_WLAN_VDDIO_1V8

NOSTUFF

25V0.2PF

WIFI_BT

NP0-C0G

50_WIFI_5G_BPF_RADIO

1.3NH+/-0.1NH-1.1A

0201

2.7NH+/-0.1NH-0.50A

50_WIFI_5G_IN_OUT

NOSTUFF

WIFI_BT

+/-0.05PFCOG-CERM0201

SMLFH185G53RG1D868

50_WLAN_G_ANT

NP0-C0G

20%

WLAN_SR_LC

90_WLAN_PCIE_TDN

90_WLAN_PCIE_REFCLK_P

90_WLAN_PCIE_RDP

WLAN_PCIE_WAKE_L

HOST_WAKE_WLAN

JTAG_SEL

WLAN_JTAG_SWDCLK

CLK32K_AP

WLAN_REG_ON

WLAN_UART_TXD

WLAN_UART_RXD

WLAN_COEX_RXD

WLAN_UART_RTS_L

WLAN_UART_CTS_L

BT_PCM_OUT

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_IN

PCIE_DEV_WAKE

WLAN_COEX_TXD

BB_COEX_UART_TXD

BB_COEX_UART_RXD

50_WIFI_2G_NOTCHPLEXER_IN

JTAG_SEL

WAKE_BT

WLAN_BUCK_OUT

WLAN_PCIE_PERST_L

WLAN_SR_VLX

50_WLAN_A_ANT

HOST_WAKE_BT

PP_VCC_MAIN

SYNC_MASTER=N/A

WIFI/BT: MODULE AND FRONT ENDSYNC_DATE=N/A

27PFWIFI_BT

16V01005

5%NP0-C0G

4.7UF

CER-X5R6.3V

0402

20%

X5R-CERM6.3V

0201

2.2UF

WIFI_BT

MF1/20W5%

201

0

+/-0.1PF16V

WIFI_BT

0.2PF

01005NOSTUFFNOSTUFF

+/-0.1PF16V

WIFI_BT

0.2PF

01005

0201

WIFI_BT

WIFI_BT

100K

01005MF1/32W5%

0.000%

1/32W01005

WIFI_BT

MF

0%1/32W

0.00

01005MF

WIFI_BT

LBEE5U8ZKC-646LGA

WIFI_BT

01005NP0-C0G16V5%

WIFI_BT

27PF

16V5%NP0-C0G01005

6.3V20%CER-X5R0402

WIFI_BT

10%

010056.3VX5R

0.00

MF

MF5%10K

01005NOSTUFF

WIFI_BT

1/32W

WIFI_BT

WIFI_BT

WIFI_BT

2.2UH-20%-0.3A-0.38OHM

0603

10K1/32W5%MF01005

WIFI_BT

7.5UF20%

WIFI_BT

4V

0402

24

24 27

24

8 3

8 3

24

24

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

IN

BI

BI

IN

IN

GND

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

BI

OUT

BI

IN

OUT

OUT

IN

IN

OUT

PCIE_REFCLK_PPCIE_REFCLK_N

GPIO_0PCIE_WAKE*

PCIE_CLKREQ*

PCIE_RDN

RF_SW_CTRL_8

BT_PCM_CLKBT_PCM_SYNC

BT_PCM_OUT

BT_UART_TXDBT_UART_RXDBT_UART_RTS*BT_UART_CTS*

BT_DEV_WAKEBT_HOST_WAKE

5G_ANT

BT_PCM_IN

GND THRM_PAD

CLK32K

VIN_LDOSR_VLX

WL_REG_ONBT_REG_ON

PCIE_PRST*

JTAG_SELJTAG_TCK(GPIO_2)

PCIE_TDPPCIE_TDNPCIE_RDP

JTAG_TMS(GPIO_3)

JTAG_TRST(GPIO_6)JTAG_TDO(GPIO_5)JTAG_TDI(GPIO_4)

VBAT

T_RF

_VCC

VBAT

T_RF

_VCC

VBAT

TVB

ATT

VDDI

O_1

P8V

GPIO_1

2G_ANT

SECI_RX(GPIO_14)SECI_TX(GPIO_13)

UART_TX(GPIO_10)UART_RX(GPIO_9)

UART_CTS(GPIO_8)UART_RTS(GPIO_7)

NC

OUT

IN

IN

IN

IN

IN

NC

IN

BI

IN

IN

OUT

OUT

IN

BI

IN

Page 58: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

PU FOR MAUI IO WAKE GLITCH

USE FIDUCIAL FOR SH ANTENNA GND

USE LDO11 TO MATCH IMPLEMENTATION OF N71/66

R2100C2101

L2102U2100

STOCKHOLMCONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

53 OF 5558 OF 60

051-006484.0.0

C5319_RF

C5323_RFC5322_RF

U5302_RF

3336 60

58

L5303_RFC5321_RF

C5315_RF

C5312_RF

33 36 60

R5303_RF

T530

1_RF

C5314_RF

R5304_RF

C5310_RF

C5308_RF

3336 60

58

C5311_RF

C5309_RF

L5302_RF

R5309_RF

R5301_RF

R5302_RF

R5305_RF

33 36 60

33 36 58 60

33 36 58 60

33 58 60

C5304_RF

C5303_RF

36

33 58 60

C5330_RF

R5310_RF

C5317_RF

3336 58 60

C5324_RF

C5302_RF

33 36 58 60

R5307_RF

33 36 58 60

R5306_RF

U5301_RF

PP5304_RF

33 36 60

R5316_RF

PP5303_RF

PP5302_RF

R5313_RF

3336 58 60

TP5301_RF

36 38

L5301_RF

C5318_RFC5316_RFC5313_RF

TP5303_RF

36 38

VOLTAGE=1.80V

VOLTAGE=1.80V

2

1

2

1

C3

E5

G2

E2

F7

E1

C6 C7

D5

G5G3

B1

G4

E7

A5

B7

E6

A6

B3B4

F1

E3E4

A4

B5

G1F2

F6F5

C1

A1

C2

D3

A3

D1A7

C5

F4

G6G7

B2

C4B6

D2

A2

F3D6D4

D7

1

21

1

1

21

1

21

21

21

21

1

2

1

2

1

2

1

A2A1A3

B2B1

C2C1

B3

C3

21

2

1

2

1

21

21

41

32

21

21

2

1

21

2

1

21

21

21

2

1

2

1

2

1

2

1

2

1

2

1

21

2

1

2

1

2

1

P2MM-NSMSTOCKHOLM

SM

P2MM-NSMSM

STOCKHOLM

P2MM-NSMSM

STOCKHOLM

RADIO_STOCKHOLM

STOCKHOLM_RXN

AP_TO_STOCKHOLM_DEV_WAKE

RADIO_STOCKHOLM

PP_STOCKHOLM_1V8_S2R

RADIO_STOCKHOLM

STOCKHOLM_UART_RXD

NOSTUFF

STOCKHOLM_UART_CTS

PP_STOCKHOLM_1V8_S2R

1/32W

100K

01005MF

5%

1/32W

100K

01005MF

5%

AP_TO_STOCKHOLM_DEV_WAKE

AP_TO_STOCKHOLM_EN

AP_TO_STOCKHOLM_FW_DWLD_REQ

PP_STOCKHOLM_1V8_S2R

5%

01005

1/32W

RADIO_STOCKHOLM

MF

100K

MF1/32W

100K

01005

5%

RADIO_STOCKHOLM

1/32W

100K

01005MF

5%

RADIO_STOCKHOLM

1/32W

X5R-CERM

25V

STOCKHOLM_UART_CTS

STOCKHOLM_UART_RTS

STOCKHOLM_UART_RXD

STOCKHOLM_UART_TXD

AP_TO_STOCKHOLM_EN

PP_STOCKHOLM_ESE

0.1UF

01005

330PF2%25VNPO-COG0201

C0G-NP0

ATB201206E-20011

0402

160NH-10%-0.48A-0.33OHM

560PF

NPO-C0G25V

0201

2%

NOSTUFF

2%50V

NP0-C0G

STOCKHOLM_ANT_MATCH

01005

0201

NOSTUFF

1000PF

0201

25V2%

82PF

0201

560PF

NPO-C0G25V

0201

2%

NPO-C0G

560PF2%25V

0201

NOSTUFF

22PF

C0G0201

5%50V

STOCKHOLM_VMID

0.00

STOCKHOLM_TO_PMU_HOST_WAKE

45_BBPMU_TO_STOCKHOLM_19P2M_CLK

STOCKHOLM_TO_SIM_SWP

STOCKHOLM_DC_BOOST

STOCKHOLM_SIM_PRES

PN66VEU3-A101D003

STOCKHOLM_TO_BBPMU_CLK_REQ

AP_TO_STOCKHOLM_FW_DWLD_REQ

STOCKHOLM_TX2

STOCKHOLM_TX1

STOCKHOLM_RXP

SH_DWP_M

SH_DWP_S

SE2_SVDD_IN

SE2_PWR_REQ

STOCKHOLM_TVDD

UFLGA

10V

RADIO_STOCKHOLM

1/32WMF

STOCKHOLM_DVDD

STOCKHOLM_DC_BOOST_EN

TP-P55

PP_STOCKHOLM_ESERADIO_STOCKHOLM

0.1UF

STOCKHOLM_SVDD_IN

X5R-CERM

STOCKHOLM_5V

10V

PP_PN66_SIM_PMU

PP_LDO11

0.00

01005MF

1/32W0%

0201

RADIO_STOCKHOLM

RADIO_STOCKHOLM

10V

RADIO_STOCKHOLM

STOCKHOLM_SIM_PRES

0.00

PP_STOCKHOLM_1V8_S2R

0%1/32WMF

PP_STOCKHOLM_1V8_S2R

PP_VCC_MAIN

6.3V

01005

TP-P55

STOCKHOLM_ANT

STOCKHOLM_RXP_CAP

STOCKHOLM_RXN_CAP

STOCKHOLM_BOOST_SW

STOCKHOLM_BAL0

STOCKHOLM_BAL1

STOCKHOLM_5VPP_VCC_MAIN

SYNC_MASTER=N/A SYNC_DATE=N/A

STOCKHOLM

2%50VC0G

100PF

0201

0402-1

20%15UF6.3VX5R

0402-1

20%15UF6.3VX5R

WLCSP

FAN4

8614

BUC5

0X

1.8UH-0.7A

060315UF

0402-1X5R6.3V20%

0201

25VC0G-NP0

1000PF2%

201

1/20W

560

5%

MF

0805

560

MF201

5%1/20W

1000PF

2%

0201

25VC0G-NP0

2%

C0G-NP00201

1000PF

0402

160NH-10%-0.48A-0.33OHM

01005MF

0%

0.00

1UF20%10VX5R0201

10%

20%1UF

X5R

0%

20%

20%

X5R10V

0201

1UF

0201

1UF

X5R

20%

27

25 27

25 27

25 27

25

25

25

25

25

25 27

25

25

25 27

25

4 13 24 25 27

25 27 25 24 13 4

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SW

PGND

PGND

VIN

SW

VOUT

AGND

EN

VOUT

IN

OUT

UNBA

LBA

L0G

NDBA

L1

IN

OUT

IN

IN

IN

BI

IN

IN

NC

NCNC

NC

IN

IN

PVDD

SVDD

SIM

_PM

U_VC

C

AVDD

CLK_REQ

SPIM_SCKSPIM_MISOSPIM_MOSI

XTAL2

ESE_IO1

NFC_CLK_XTAL1

SMX_RST*

RTS

SMX_CLK

VEN

TXCTS

RX

SVDD_REQDWL

IRQ

AVSS

AVSS

AVSS

DVSS

VSS

DVSS

TVSS

PVSS

VMID

TX2

RXN

TX1

RXP

GPIO0SIM_SWIOSPIM_IRQ

ESE_DWPM_DBGESE_DWPS_DBG

WKUP_REQ

SE2_SVDD_INSE2_PWR_REQ

TX_PWR_REQSPIM_NSS

VUP

TVDD

ESE_

VDD

VBAT

VDD

PP

OUT

NC

PP

PP

IN

A

NC

NCOUT

NCNC

A

IN

Page 59: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

N69N69HN69 SKU BOM OPTION TABLE

N69H TDD

59 OF 60

54 OF 55

4.0.0

051-00648

118S0652

152S1851

1

162K 1% 01005

2.2PF 0.1PF 01005 COG131S0387

7.5NH 3% 01005 200MA

10NH 01005 170MA

2.5PF 0.1PF 01005 COG

C4211_RF

C4211_RF

152S1853

R4509_RF

R4509_RF

C4500_RF

0R 01005

152S1983

152S1623

CRITICAL

1 CRITICAL117S0161 0R 01005 N69H

117S0161

N69H

1PF 01005 16V

68PF 01005 25V

N69HCRITICAL

CRITICAL

C4520_RF

131S0244

152S00036

152S1989

117S0161

100PF 01005

FILTER SAW BAND 40A B41A

CRITICAL

3.3NH 01005

353S00374

152S1998

1

1

N691 CRITICAL117S0161 0R 01005

01005 49.9R

01005 49.9R

1.1PF 01005

1.0PF 01005 16V

68PF 01005 16V

3.3NH 01005 +/-0.1NH 131S0599

118S0652

2.9NH 01005 360MA

1

L4223_RF CRITICAL

C4213_RF

152S1996

152S1571

152S2061

1

SAW FILTER B40A B41A

1

5.6NH 01005

N69H

4.3NH 01005 3%

131S00042

N69H

CRITICAL

L4517_RF

131S0307

1 0.3PF +-0.05PF 01005 16V

N69H

1UF 0201 10V

N69H

R4531_RF

100PF 01005 16V

155S0906

152S1988 CRITICAL

1 CRITICAL N6901005 49.9R

N69CRITICAL118S0652

N69C4231_RF CRITICAL01005 1.5PF1

N69CRITICAL1

1 N695.1NH 0.1NH 01005 250MA152S1993

N69HCRITICAL

CRITICAL01005 49.9R C4231_RF118S0652

CRITICAL

CRITICAL

CRITICAL

CRITICAL

C4521_RF

L4516_RF

L4515_RF

L4526_RF

L4520_RF

C4532_RF

C4533_RF

L4507_RF

FTB40A41A_RF

L4602_RF

FD40B41A_RF

CRITICAL

N69H

39K 1% 01005

118S0724

N69H

CRITICAL

CRITICAL

L4902_RF

L4901_RF

100PF 01005

N69H

L4830_RF

CRITICAL

N69H

N69H

N69H

CRITICAL

2.2NH 01005 200MA152S1619

C4528_RF

L4506_RF

L4528_RF

C4502_RF

C4506_RF

1.5NH 01005 +/-0.1NH

117S0161 1

152S1977

131S0390

1

2.7NH 0201 +/-0.1NH152S2002

7.5NH 01005 5%152S1408

0.3PF 01005 16V131S00042

L5121_RF

C4213_RF

CRITICAL

N69H

L5120_RF

5.6NH 01005

3.0NH 0201

SWTICH SPDT 1.1X1.1

CRITICAL

1

2.7NH 01005 370MA

CRITICALC4710_RF

L4421_RF

U_DSM_RF

CRITICAL

N69HCRITICAL

1.8NH 01005 380MA

3.1NH 01005 +/-0.1NH

1

0OHM 01005 R4700_RF

131S0307

1

C4720_RF

FR40A41A_RF

N69HCRITICAL1

1 CRITICAL N69H1.4NH 01005 220MA152S1946 L4706_RF

155S0881

18PF 01005 C4703_RF

FL_B39LP_RF

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

2.4NH 01005 370MA

C4701_RF

N69H

N69H

N69HCRITICAL

L4709_RF

152S1917

1

N69HC4827_RF131S0307 1 CRITICAL

L4817_RF

1

131S0214

353S4167

FILTER SAW B40B 38X

CRITICALL4705_RF

CRITICAL

L4704_RF

CRITICAL

R4815_RF

C4816_RF

L4816_RF

152S1720

2.4NH 01005

0R 01005

L4904_RF

L4903_RF

152S1900

3.3NH 01005 290MA1

152S1571

5.1NH 01005L4813_RF

131S0376

CRITICAL

TDK MODULE M472A NO B12/B13/B17

1

CRITICAL N69H

CRITICAL

U_SWUANT_RF CRITICAL

CRITICAL

N69H

SAW DRX B40B41A

CRITICAL353S00390

152S1567

C4809_RF N69H1

1 N69H

IND 0.8NH 630MA 01005

L4217_RF

152S1564

152S1544

131S0307

1.3NH 01005

100PF 01005

0.4NH 01005

1.8NH 01005 L4814_RF

CRITICAL

1 CRITICAL

N69H1

N69H1

N69H1

N69H1 CRITICAL

N69H1

RADIO HIGH BAND PAD

15NH 01005

152S2045

0R 0201

1

353S00331

1 5.6NH 01005

N69HCRITICAL

CRITICAL1155S0908

N69HCRITICAL152S1907

N69HCRITICAL1

1

1 L4601_RF

FLTR SAW DUAL FILTER B34B39 CRITICAL155S0981 FRX34B39_RF1

OMIT_TABLE_RF

N69H

N69H152S2040

N69H1 1.3NH 01005 +/-0.1NH152S1982

1

N69R3312_RF CRITICAL118S0729

N69R5137_RF1 CRITICAL

N69SKY77826 CRITICALU_VLBPAD_RF1

N691 U_DSM_RFDSM M471A NO B7 CRITICAL353S00373

N69HCRITICAL1 FILTER LOW PASS B39

N69HCRITICAL1155S0903 FR38X40B_RF

1

N69H9.1NH 01005 3% L4523_RF152S1853 1

N69H1

N69HCRITICAL3.7NH 01005 270MA

N69HCRITICAL152S1989 2.7NH 01005 370MA L4712_RF1

N69HL4708_RF1152S00034

12NH 01005 140MA L4710_RF1152S1576

47PF 010051131S0216

N69HCRITICAL1152S1853 L4527_RF9.1NH 01005 3%

N69HCRITICAL155S0900 1 FILTER SAW BAND 41B 41C FT_41BC_RF

N69HCRITICAL152S1965 L4524_RF1

N69H152S2024 1.4NH 0201 1.1A L4525_RF1

N69H2.0NH 01005 380MA

N69HCRITICALL4713_RF1

131S0214 18PF 010051

N69H1

N69HCRITICAL155S0902

N69H1152S00035

N69HCRITICAL1

N69HSWITCH IC LGA161 U_HBS_RF

N69HCRITICAL1131S0395 3.0PF 01005 +/-0.1PF

N69H1

N69H1138S0706

1

N69H1

N69H7.5NH 01005 3%1

N69H2.2NH 01005 +/-0.1NH1152S1986

N69H1 FILTER B40155S0982 FT_B40_RF

N69H152S2002 L4522_RF2.7NH 0201 +/-0.1NH

1

N69H1 CRITICAL131S0644

N69H

SKY77827 U_VLBPAD_RF N69H1

CRITICAL1353S4180 U_HBPAD_RF

N69H1 CRITICAL131S0417 18PF 01005 16V C4501_RF

N69HCRITICAL1131S0375 C4503_RF

N69H1 CRITICAL131S0635 C4507_RF

N69H1UF 0201 10V138S0706 1 CRITICALC4505_RF

N69HCRITICAL1152S1907 L4512_RF

CRITICAL N69H1.8PF 01005 16V131S0247 C4522_RF

CRITICAL N69H1

CRITICAL1 N69H

N69H1 CRITICAL

N69H1 L4216_RF CRITICAL

353S3876 1

N69HCRITICAL

1 R3312_RF118S0726 N69H

CRITICAL1

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II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

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REVISION

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DR

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NOTICE OF PROPRIETARY PROPERTY:

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B

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8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

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REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

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REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

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Page 60: APPD ECN DESCRIPTION OF REVISION 2. ALL CAPACITANCE …asc.kh.ua/files/iphone-se-schematic-.pdf · pmu/soc bom options w w w . c h i n a f i x . c o m soc alternates schematic & pcb

w w w

. c h

i n a

f i x

. c o

m

STOCKHOLM INTERFACES

BB DEBUG INTERFACES

WLAN/BT HOUSE KEEPING

RADIO SYMBOL(HEIARCHY)CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

FCT TESTING

HSIC IPC

AUDIO I2S

WLAN PCIE IPC

WLAN/BT UART

ANTENNA CONTROL

WLAN/OWL UART

OSCAR UART

CELLULAR HOUSE KEEPING

BT AUDIO PCM

BB UART

60 OF 60

57 33

57 36 33

57 36 33

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57 33

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57 36 33

57 33

38 36 33

60 57 36 33

58 36 33

58 36 33

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58 36 33

58 36 33

58 36 33

58 36 33

58 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

60 57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

57 36 33

36 33

36 33

36 33

36 33

40 36 33

40 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

41 36 33

40 36 33

40 36 33

41 33

41 33

41 36 33

41 36 33

41 33

38 36 33

41 36 33

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41 36 33

38 36 33

40 36 33

40 33

38 36 33

41 33

41 33

57 33

57 36 33

57 36 33

41 36 33

55 OF 55

4.0.0

051-00648

PAC_VDD_3V0

RFFE_VIO_S2R

PP_STOCKHOLM_1V8_S2R

AP_TO_STOCKHOLM_EN

STOCKHOLM_TO_PMU_HOST_WAKE

AP_TO_STOCKHOLM_DEV_WAKE

AP_TO_STOCKHOLM_FW_DWLD_REQ

WLAN_PCIE_CLKREQ_L

90_WLAN_PCIE_RDP

90_WLAN_PCIE_RDN

90_WLAN_PCIE_REFCLK_P

90_WLAN_PCIE_REFCLK_N

WLAN_PCIE_PERST_L

90_WLAN_PCIE_TDP

90_WLAN_PCIE_TDN

WLAN_PCIE_WAKE_L

RADIO_ON_L

HOST_WAKE_WLAN

PP_VCC_MAIN

OSCAR_CONTEXT_B

OSCAR_CONTEXT_A

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

BT_PCM_CLK

BT_UART_CTS_L

BT_UART_RTS_L

BT_UART_RXD

WLAN_UART_RXD

WLAN_UART_TXD

HOST_WAKE_WLAN

HOST_WAKE_BT

WAKE_BT

BT_REG_ON

WLAN_REG_ON

CLK32K_AP

PP_WL_BT_VDDIO_AP

ADC_SMPS4

ADC_PP_LDO5

ADC_PP_LDO11

ADC_SMPS1

BB_USB_VBUS

90_BB_USB_P

90_BB_USB_N

BB_CORE_DUMP

BB_OTHER_TXD

BB_OTHER_RXD

BB_I2S_WS

PP_BATT_VCC

BB_I2S_CLK

BB_I2S_RXD

BB_I2S_TXD

BB_GPS_SYNC

BB_DEVICE_RDY

BB_HOST_RDY

50_BB_HSIC_STROBE

50_BB_HSIC_DATA

BB_IPC_GPIO1

GSM_TXBURST_IND

AP_TO_BB_MESA_ON

BB_WAKE_HOST_L

AP_WAKE_MODEM

BB_RST_L

BB_UART_RTS_LBB_UART_CTS_LBB_UART_RXD

BB_UART_TXD

RF_PMIC_RESET_L

BB_JTAG_TMS

BB_JTAG_TCK

BB_FORCE_PWM

BB_LAT_GPIO2BB_LAT_GPIO1

PCIE_DEV_WAKE

WLAN_UART_RTS_L

WLAN_UART_CTS_L

BB_RESET_DET_L

BT_UART_TXD

STOCKHOLM_UART_CTS

STOCKHOLM_UART_RTS

STOCKHOLM_UART_TXD

STOCKHOLM_UART_RXD

Radio Subdesign Ports

25

23

23 15 14 4

24

25 3

25 3

25

25 3

24

24 3

24 3

24

24

24

24 3

24 3

24

5 3

27 24 3

25 24 13 4

24

24

24

24

24

24

24 3

24 3

24 3

24 3

24 3

27 24 3

24

24 3

24 3

24 3

24 3

3

3

3

3

7 3

7 3

7 3

8 3

8 3

8 3

8 3

21 19 18 12

8

8 3

8 3

8 3

8 3

8 3

7 3

7 3

8

8

8 3

8 3

8

5 3

8 3

8 3

8 3

8 3

5 3

7 3

7 3

5 3

8

8

24

24 3

24 3

8 3

24 3

25 3

25 3

25 3

25 3

II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

DR

IV ALL RIGHTS RESERVED

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

IN

OUT

OUT

IO

IN

IN

IN

IN

OUT

IN

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IO

IO

IO

OUT

OUT

OUT

OUT

IO

OUT

OUT

IN

OUT

IN

IN

IO

IN

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IO

OUT

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

IN

OUT

IN

OUT