App_II_CH2_OPAmp_Basic.pdf

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Chapter 2: Op-Amp Basic Stages

2.1IntroductionAn integrated circuit IC is a circuit where an entire circuit is constructed on a single piece of

semiconductor material. One of the commonly used types of IC is the operational amplifier.

The schematic diagram of the 741-type OP-Amp and its symbol is shown below.

Inverting Input

Non InvertingInput

Vee

Vcc

Output

+

-

Operational Amplifier is a high gain dc differential amplifier capable of performing a wide

range of functions by using external feedback. It is the most flexible linear device. By

controlling the feedback network properties, we can manipulate the overall forward transfer

function of the device and its application.

The majority of commercially available operational amplifiers employ the structure shownbelow.

Bias Network Differential Amp Gain Stage Level Shifter Output Stage


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Diff-Amp Additional GainBuffer & Level

ShifterOutput Deriver

V1

V2

VO

The differential amplifier is used as the input stage to provide the inverting and the non

inverting inputs and the high input resistance as well as voltage gain. The low output

resistance of the op-amp is achieved by the emitter follower output stage. The level shifter

adjusts the dc voltages so that the output voltage signal is referenced to ground. The

adjustment of dc level is required because the gain stages are direct coupled. The input and

output stages are required to match the op-amp with the external world.

2.2Differential AmplifiersPreviously in Applied electronics I, we have discussed single stage amplifiers of one input

and one output terminal with limited gain, input resistance and output resistance. Here,

another basic transistor circuit configuration called differential amplifier is introduced,

which can give us high gain and specified input and output resistance values. It is the inputstage for most operational amplifiers and is widely used amplifier building block in analogue

integrated circuit. Unlike the other amplifiers we have discussed so far, it has two input

terminals and one output terminal, where the output signal is the difference of the two input

signals as shown in the difference amplifier block diagram below.

Difference

Amplifier

V2

V1

VO

Figure 2.1: Difference amplifier block diagram

Where the output voltage VO

There are two different modes of operation of the differential pair:

is given by: = (1 2)

1. The differential pair with a common-mode input signal CM: = 1 + 2

2

2. The differential pair with a differential (mode) input signal: = 1 2

Thus, the total output voltage is given by

=

(

1

2) +

1 + 22

Where and respectively are the differential gain and the common mode gain.


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The above equations shows that ifV1 = V2, the differential mode input signal is zero and the

common mode input signal is Vcm = V1 = V2

The differential amplifier can be implemented with BJTs and FETs. We focus on differential

amplifiers implemented using BJT transistors.

.

2.2.1. Response for differential inputsDifferential mode: This mode of operation exists when the differential amplifier has one

source connected to each input and the two sources are out of phase with each other and of

the same amplitude.

Common mode: This exists if the sources are equal in amplitude and in phase, the two

opposing forces will balance each other, so that they cancel.

Consider the following basic BJT differential pair configuration

VB1 VB2

I

Q1 Q2

iC1 iC2

VC1 VC2

VCC

RC1 RC2

iE2iE1

Vout

- +

VEE

Figure 2.2: Basic BJT differential pair configuration

Following the polarity shown in figure 2.2, the ac output voltage can be expressed as:

= 2 1The output voltage Vout

Common mode response

is called a differential output since it combines the two ac collector

voltages into one voltage.

First let us consider a circuit in which the two base terminals are connected together and a

common mode voltage Vcm

The voltage at the common emitters is given by KVL in one of the transistor input circuit:

is applied as shown in figure 2.3 below.


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= () 2.1If the transistors Q1 and Q2 are identical, the current IQ

If base currents are negligible then, 1 1 2 2,

splits evenly between the two

transistors and is given by:

1 = 2 = 2 2.2

Therefore, the collector voltages are given by:

1 = 2 = 2 2.3

Q1 Q2

VCC

RC1 RC2

+

-

Vcm

2

QI

2

QI

QI

112

C

Q

CCC RI

VV = 222

C

Q

CCCR

IVV =

2

QI

2

QI

VE

VEE

Figure 2.3: Basic diff-amp with applied common mode voltage

From this we conclude that, for an applied common mode voltage, splits equally betweenQ1 andQ2 and the difference between VC1 andVC2

By varying V

is zero.

cm

Differential response

in figure 2.3 above by a small amount and determining the circuit response,

will not result any change in the above equations. Thus, suggesting that both the collector

current and voltages of the transistor will remain unchanged. Hence, we say the circuit does

not respond to changes in the input common mode level; or the circuit rejects input CM

variations.

Let us now increase the base voltage VB1, in figure 2.2, by a small voltage Vd/2 and decrease

VB2 by the same amount. I.e. let

1 = 2 2 = 2 2.4


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This show the voltages at the bases ofQ1 andQ2 are no longer equal. Since the emitters are

common, the base to emitter voltages ofQ1 andQ2 are not the same. We have increasedVB1

and decreasedVB2, giving us VBE1>VBE2, as a result iC1 increases by Iabove its quiescent

value andiC2

Q1 Q2

VCC

RC1 RC2

II

Q +2

II

Q 2

QI

+= 11

2C

Q

CCCRI

IVV

= 22

2C

Q

CCCRI

IVV

II

Q +2

II

Q

2

VE

VEE

2

dv

2

dv

++

--1BEV 2BEV

decreases by I below its quiescent value. This is shown in figure 2.4 below.

Figure 2.4: Basic differential amplifier with applied differential mode

Hence, there exists a potential difference between the two collector terminals which is given asfollows:

2 1 = 22

2+ 1

= 2 + 1 , 1 = 2 = 2 1 = 2 2.5

This proves that a voltage difference is created between the two collector terminals (VC2 and

VC1

2.2.2. Small signal analysis) by applying a differential mode input voltages.

Consider the following small signal circuit configuration.


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VB1 VB2

Ri1 Ri2V1 V2

RC1 RC2

gm1V1 gm2V2

E

+

-

+

-

Figure 2.5: Small signal model of bipolar pair

Take the requirement that the input signals do not affect the bias currents of transistors Q1

and Q2

For differential operation V

significantly. I.e. both transistors must exhibit approximately equal trans-

conductance. And for small differential inputs the tail node maintains constant voltage (which

results in a state called virtual ground).

B1 andVB2 represent small changes in each input and they should

satisfy VB1= - VB2

Note: The emitter current sourceI

.

Q

To analyse the small signal operation let us take KVL around the input network and KCL at

node E.

is replaced with an open circuit.

1 1 = = 2 2 2.1111 + 11 + 22 + 22 = 0 2.12

LetRi1 = Ri2 andgm1 = gm2

Since V

, then equation 2.12 yields:

1 = 2B1 = - VB2

This would result in:

=

1 1= 0

, equation 2.11 will become:

21 = 21

Thus, for small signal analysis of the circuit the emitter voltage remains constant if the two

inputs vary differentially and by a small amount.

With the assumption taken to analyse the above circuit and the result obtained, node E can be

shorted to ac ground reducing the differential pair of figure 2.5 to two half circuits, with each

half resembling common emitter stage as shown in figure 2.6 below.


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VB1 VB2

Ri1 Ri2V1 V2

RC1 RC2

gm1V1 gm2V2

+

-

+

-

Figure 2.6: Simplified small signal model

With this simplified model, we can write:

1 = 111 2.13Substituting forV1 = VB1, gm1=gm2=gmandRC1 = RC2 = RC

Then, the differential voltage gain of the differential pair is:

= 1 21 2 =1 (2)1 2

= 2.15

,

1 = 1 2.14() 2 = 2 2.14()

Common mode gain (AC

The small signal equivalent model for the common mode signal is:

)

Ri1 Ri2V1 V2

RC RC

gm1V1 gm2V2

E

+

-

+

-

VO1+

-

Vcm

VO2+

-

Figure 2.7: Small signal pair of common mode circuit

The common mode gainAc of transistorQ1 in the above common mode circuit is given by:

= 1 = 11 , 1 = 2 = 2.16


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This results to:

= 11 2.17By symmetry of the two transistors the total gain of common mode pair is zero.

Vcm

Ri1 V1

RC1

gm1V1

+

-

2RE

Figure 2.8: Small signal model for the common mode circuit when Re is added

But if an emitter resistor is connected to the emitter node E of the above figure 2.8, the one sided gain

AC

For large values of and dividing byR

is simply given by:

= 1 =1111 + 2(1 + )(1 )

=1

2(1 + ) + 1 2.18

Because the same signal is applied forQ

i1

= 12 + 1 12 , 2 1 2.19

1 andQ2both Vo1andVo2are out of phase with Vcm

2.2.3. Common mode rejection ratio (CMRR).

It is defined as the ratio between the differential gain and the common mode gain, indicates

the ability of the amplifier to accurately cancel voltages that are common to both inputs.

= For an ideal diff-ampAc

For the differential amplifier shown in figure 2.2 the one sided differential and common

mode gains are given by:

is zero andCMRR goes to infinite.

, = 20 log


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= 2

And

= 12(1 + ) + 1Using these equations the CMRR can be expressed as:

= =1

22(1 + )1 + 1 2.20

The common mode gain decreases as increases. Therefore, as equation 2.20 shows CMRRincreases as increases.Hence, the higher the differential gain with respect to the common mode gain, the better the

performance of the diff-amp in terms of the rejection of the common mode signals.

Example 1:

Determine the differential and common mode gains of the diff-amp for the figure 2.2, with

parameters = 10, = 10, = 0.8, = 12. The transistorparameters are: = 100. Assume the output resistance looking into the constant currentsource is

= 25

, and again take the assumption that the source resistance of each

transistor is zero.

Solution:

From equation 2.15, the differential mode gain for the one sided output is

= 112

, 1 = 11 , 1 = 11, 1 =1

Therefore,

= 1

1

2 , 1 = 1 = 11

2 , 1 =2

= 14

Substituting the values of 1 and and taking = 26, we get

= 0.8

12

4 0.026 = 92.3


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From equation 2.18, the common mode gain is

= 12(1 + ) + 1

Rewriting the above equation and using = = 1

2(1 + ) + 2

= 100 0.8 122(1 +1 0 0)25 + 2 100 26mV = 0.237

As it is seen in the above result, the common mode gain is significantly less than the

differential-mode gain, but it is not zero because our current source is not ideal.

And the CMRR is given by

= =92.3

0.237= 389

Expressing this in decibel,

= 20 log10 389 = 51.8The CMRR of diff-amp can be improved by increasing the current source output resistance.

Input and output impedances

For the differential pair configuration and its equivalent model shown in figure 2.9 below, we

can write the input impedance as follows:

11 = = 22

And also we have from KVL loop between V1, node E andV2

From this it follows that

= 21

:

= 1 2 , 1 = 2 = 21 ,

This implies that as if the two base emitter junctions appear in series. And hence, the result is

called the differential input impedance of the circuit.


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Q

1

Q

2

VCC

RC RC

QI

VE

IX

VX

Ri1 Ri2V1 V2

RC RC

gm1V1 gm2V2

E

+

-

+

-

VX

IX

IX

Figure 2.9: Method for calculation of differential input impedance and its equivalent model.

The output impedance for the differential mode is 2RC. But ifRC is derived from an active

load, the output resistance ro

of the BJT cannot be ignored rather it must be included as given

below:

= 2(//)

Example 2:

The differential amplifier of figure example 2, shown below uses transistors with B=100.

Evaluate the following:

a. The input differential resistance b. The overall differential gain (neglect the effect ofroc. The worst case Common mode gain if the two collector resistances are accurate to

within 1%.

).

d. The CMRR, in dB


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I

Q1 Q2

VCC=15V

RC= 10K

- +

VO

+

-

VS/2

+

-

VS/2

RC= 10K

Rid

5K 5K

RE= 150 RE= 150

1mAREE= 200K

Figure: Example 2

Solution:

a. Each transistor is biased at an emitter current of 0.5mA. Thus,

1 = 2 = =25

0.5 = 50The input differential resistance can now be found as:

= 2( + 1)( + ) = 2(101)(50 + 150) = 40

b. The voltage gain from the signal source to the bases ofQ1andQ2

=

+ =40

4 0 + 5 + 5 = 0.8

is:

The voltage gain from the bases to the output is

=

=2

2( + ) =2 10

2(50 + 150)= 50

The overall differential voltage gain can now be found as


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= =

= 0.8 50 = 40c. Assuming perfect symmetry, except mismatch in the collector resistances, the

common mode gain is given by:

= 2

Where = 0.02 in the worst case. Then

= 102 200 0.02 = 5104

d. = 20 log10

= 20 log10

40

5

104 = 98

Input Offset voltage of the differential pair

Consider the basic BJT differential pair with both input grounded, as shown in figure 2.10

below.

I

Q1 Q2

iC1 iC2

VCC

RC1 RC2

iE2iE1

- +VO

I

Q1 Q2

iC1 iC2

VCC

RC1 RC2

iE2iE1

- +0V

+

-

-VOS

(a) (b)

Figure 2.10: (a) The BJT differential pair with both input grounded, (b) Application of the

input offset voltage VOS

As we have seen until now, if the two sides of the differential pair were perfectly matched,

the current Iwould split evenly in both sides andV

.

O would be zero. But practical circuits

exhibit mismatches that result in a dc output voltage VOS, even with both inputs grounded.

We call VO

To obtain the input offset voltage V

the output dc offset voltage.

OS we divide VO by the differential gainAd

=


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If we apply a voltage - VOS

The factors which contribute to the dc offset voltage of bipolar differential amplifier are

mismatches in load resistors (R

between the input terminals of the differential amplifier, then the

output voltage will be reduced to zero as shown in figure 2.10(b).

C1 andRC2), from junction area, and other mismatches in Q1

andQ2

2.3. Constant Current Sources.

Frequently in practice, Re is replaced by a transistor circuit. They are widely used as emitter

sources for differential amplifiers and also to bias transistors. Now lets consider the circuit

shown below.

Q1 Q2

VCC

RC RC

3I

IB1

VB1 VB2

-VEE

R1

R3 R2

IE2IE1

IO

D

Q3

RS1 RS2

IC1 IC2

+

-1BEV

+

-

2BEV

IB2

VO1 VO2

+

-

+

-

VS2VS1

Figure 2.13: Differential amplifier with constant current stage in the emitter circuit

On figure 2.13 Q3

Now applying KVL to the base ofQ

acts as a constant current source.

3

is the diode voltage. Hence, 3 = 13

21 + 2 +11 + 2 3

:

33 + 3 = + ( ) 21 + 2

If the circuit parameters are chosen so that


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11 + 2 = 3 =23 (1 + 2)

Since this current is independent of the signal voltages, then Q3 acts to supply the diff-amp

consisting ofQ1 andQ2 with the constant currentIO

2.4. Current Mirror.

The principle of a current mirror is that a current fed in at the input of the current mirror

circuit will produce an identical value of current in the second.

Lets consider the following current mirror circuit.

VO

Q3 Q4

I

IC

+

11CI

CI2

CI CI

+

11CI

IO=IC

+

-VBE

Figure 2.14: BJT current mirror

If is sufficiently high, so that we can neglect the base currents, the reference current I ispassed through the diode connected transistor Q3 and thus establishes a corresponding

voltage VBE, which in turn is applied between base and emitter of Q4. Hence, if Q3 is

matched with Q4, the collector current ofQ4 will be equal to that ofQ3

However, for finite transistor, if transistors Q; i.e. =

3 andQ4 are matched and have the same VBE

Then, a node equation at the collector ofQ

,

their collector currents will be equal i.e = 3

Since = , the ratio betweenI

yields:

= + 2 = 1 + 2

O

Now, consider the following circuit which employs a symmetrical differential pairQ

and the reference currentIis given by:

=

1 + 2=

1

1 + 2

1 andQ2

along with a current mirror loadQ3 andQ4.


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Q1 Q2

VCC

I

Q3 Q4

VB1 VB2

Vout

+

-

-VEE

2

dmvg 2

dm

vg

2

dm

vg

Figure 2.15: Differential pair with active load

The current mirror active load is a way to accomplish high gain for a single stage differential

amplifier. The NPN transistors Q1 and Q2 shown in figure 2.15 above make up the

differential amplifier andQ3 andQ4

Darlington Connection

(PNP) make up the current mirror. The current mirror

acts as the collector load and provide a high effective collector load resistance, increasing the

gain.

If we connect two transistors together as shown below then it is called Darlington pair. Itbehaves like a single transistor with an effective current gain approximately equal to the

product of the current gains of the two transistors. The base emitter on voltage of the pair is

twice the base emitter on voltage of a single transistor and the saturation voltage is greater

than that of a single transistor by an amount equal to the base emitter on voltage. If a small

signal Ii is input to the base, the collector current of transistor Q1 is 1 and the emittercurrent is( + 1) . The latter becomes the base current of transistor Q2 and hence thecollector current of Q2 is 2(1 + 1) . Thus the total collector current of the Darlington pairis

2(1 + 1) + 1 12 Therefore, this circuit can be very useful in high current stages where a large gain is required.


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B

C

E

Q1

Q2

Figure 2.16: Darlington circuit

2.5. Level Shifter and Buffer CircuitsIn integrated circuits the use of coupling capacitors is always avoided and to offset any direct

voltage level present between say, two amplifier stages, different methods are employed. One

of these methods is to use an emitter follower that can serve as a voltage shifter as shown in

the following figures.

Vi

R1

R2

VO

VCC

(a)

Vi

R1

VO

VCC

(b)

IO

Vi

R2

VO

VCC

(c)

+

-

VZ

Figure 2.14: Level shifter circuits

If the output is taken at the emitter then the change in levels is = 0.7. Ifthis shift is not sufficient, the output may be taken at the junction of two resistors in the

emitter leg (a). The voltage shift is then increased by the drop across R1. The disadvantage

with this arrangement is that the signal voltage suffers attenuation 21+2. This difficulty isavoided by replacing R2by a current source IO

An avalanche diode can also be used to translate a voltage (c). Then the shift will be

=

(

+

). A number of forward biased p-n diodes may also be used in place

of the zener diode.

(b). The level shift is = ( + 1)and there is no ac attenuation for a very high resistance current source.


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2.6. Output Driver CircuitsAn output voltage must be capable of supplying the load current and must have a low output

resistance. A common configuration for the output stage of an op amp is the emitter follower

with complementary transistors. If the input signal Vi goes positive the n-p-n transistor Q1

acts as a source to supply current to the loadRL and the p-n-p transistorQ2 is cutoff. On the

other hand, ifVi becomes negative, Q1 is cutoff andQ2 acts as a sink to remove current from

the load, that is to decreaseIL

RL

Q1

Q2

+VCC

n-p-n

p-n-p

IL

-VCC

Vi VO

.

Figure 2.15: Complementary class B emitter follower output stage

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App_II_CH2_OPAmp_Basic.pdf