Application of MOS Technologyto Silicon Carbide Devices

Mrinal K. Das, Ph.D.Device Scientist

Power R&DCree, Inc.

Research Triangle Park, North Carolina

Outline

• Introduction

• MOS Fundamentals

• Kinetics

• Process Technology

• Characterization

• Historical Progress

• Future Prospects

• Summary and Discussion

What is MOS?

Semiconductorp-Si

OxideSiO2

Metal

EC

EF

Ei

EV

EF

FV = 4.7 eV

FC = 3.15 eV

Why is MOS Important?

SemiconductorSi

OxideSiO2

Metal

EC

EF

Ei

EV

EF

Field Effect Switching; Charge Storage

+VG

VG

Si Devices Enabled

• Switching Devices

NMOSFET

PMOSFET

CMOS

LDMOS

Power MOSFET

IGBT

• Charge Storage/Transfer

DRAM

CCD

MOS Structures can be madeon SiC thereby enabling all ofthese devices on SiC as well

Kinetics of Oxide Growth

Si + O2 Ë SiO2 (Dry)Si + H2O Ë SiO2 + 2H2 (Wet)

Si

T = 1000oC, Dry O2

EA = 46.6 kcal/mol (Si-Si)

EA = 28.5 kcal/mol

TOX = 500Å (t=1 hr)

2SiC + 3O2 Ë 2SiO2 + 2COSiC + 3H2O Ë SiO2 + 3H2 + CO

T = 1200oC, Dry O2

TOX = 500Å (t=2.5 hr)

SiC

EA = 58 kcal/mol (Si-C)

EA = 34 kcal/mol

TOX = (B/A)(t + t)

TOX = (Bt)1/2

Transition to SiO2

Crystalline Si

SiOX x < 2, tint < 30 Å

Amorphous SiO2

SiC

SiCYOX, tint ~ 50 Å

Amorphous SiO2

4H-SiC

SiO2

MOS Process Flow

• Incoming clean

Solvent Clean

Piranha Clean

• Pre-Oxidation clean

Organic Clean (DI:NH4OH:H2O2)

Metal Clean (DI:HCl:H2O2)

Oxide Etch (DI:HF)

• Immediately load into furnace

Low temperature push

Oxidation/Anneal at high temp

Low temperature slow pull

• Immediately metallize

Blanket Al evaporation

Photolithography

Etch

• Clean backside

Frontside PR protect

Oxide Etch (DI:HF)

PR Strip

• Forming Gas anneal

450oC 30 min

H2 containing ambient

Fabrication of Si MOS Capacitor

MOS Process Flow

Major Differences for SiC

• Ozone clean prior to pre-oxidation clean

• Furnace push occurs with Dry O2 flowing

• Low temperature Wet O2 prior to ramp up

• Oxide growth at T > 1100oC

• Low temperature Wet O2 after oxide growth

• High temperature nitridation needed as final step

• Forming Gas anneal not as effective

Characterization of MOS Structures

Semiconductorp-Si (1E16 cm-3)

OxideSiO2

Al

EC

EF

Ei

EV

EF

Non-Idealities: FMS

VacuumLevel

FM = 4.1eVcSi = 4.05eV

EG/2 = 0.56eV

FF=0.35eV

FS = cSi + EG/2 + FF

= 4.96eV

FMS = FM – FS

= -0.86eV

Characterization of MOS Structures

Semiconductorp-Si (1E16 cm-3)

OxideSiO2

Al

EC

EF

Ei

EV

EF

Non-Idealities: FMS

FMS = FM – FS

= -0.86eVNet Effect:

Constant Shift in Voltage

EC

EF

Ei

EV

EF

Non-Idealities: QOX

Characterization of MOS Structures

Semiconductorp-Si

OxideSiO2

Metal

Net Effect:Constant Shift in Voltage

Mobility Reduction + QOX is balancedby ionized acceptors

++++++++

EC

EF

Ei

EV

EF

Non-Idealities: DIT

Characterization of MOS Structures

Semiconductorp-Si

OxideSiO2

Metal

Net Positive Charge

Acceptor

Donor

- charge if filled,neutral if empty

+ charge if empty,neutral if filled

EC

EF

Ei

EVEF

Non-Idealities: DIT

Characterization of MOS Structures

Semiconductorp-Si

OxideSiO2

Metal

Net Negative Charge

Acceptor

Donor

- charge if filled,neutral if empty

+ charge if empty,neutral if filled

Net Effect:Variable Shift in Voltage

Mobility Reduction

RT Photo C-V

P-SiC MOS-C, HP4284 100kHz

0

25

50

75

100

-15 -10 -5 0 5 10 15

Cap

acit

ance

(p

F)

light on/off

deep depletion

interface state ledge

Voltage (V)

inversion

accumulation

ACC

OXOX C

AT

e=

qA

VCQ FBMSOX

OX

)( -F=

flatband

dVCd

AqN

SiC

A )/1(2

22e

=

G

OXIT qAE

VCD

D=

C

V

IdealFMS

QOX

QIT

CFB

Simultaneous NMOS-PMOS CVs

NMOS-PMOS CV Yields Interface Quality

0.0E+00

2.0E-11

4.0E-11

6.0E-11

8.0E-11

1.0E-10

1.2E-10

1.4E-10

1.6E-10

-5 -4 -3 -2 -1 0 1 2 3

Gate Voltage (V)

Cap

acit

ance

(F

)

NMOS-Capacitor

PMOS-Capacitor

V = FFN+FFP+VIT

VFB = VOX+VIT

High-Low C-V

N-SiC MOS-C, Keithley 590, 595, 5951

qAC

CC

CCD D

LFOX

LFOXIT

1˜̃¯

ˆÁÁË

Ê-

-=

DOX

DOXHF CC

CCC

+=

0

50

100

150

200

250

-6.0 -4.0 -2.0 0.0 2.0 4.0 6.0

ChfClf

Cap

acit

ance

(p

F)

Gate Voltage (V)

COX

CD

RS

CIT GIT

CHF

CLF

qACC

CC

CC

CCD

HFOX

HFOX

LFOX

LFOXIT

1˜̃¯

ˆÁÁË

Ê

--

-=

High-Low C-V

Energy Calculation

D

SiCD C

AW

e=

SiC

DAS

WqN

ef

2

2

=

SFG

V

EEE ff +-=-

2

0

2

4

6

8

10

0.4 0.6 0.8 1.0 1.2

reverse sweepforward sweep

DIT

(x

101

1 cm

-2eV

-1)

E – EV (eV)

EC

Ei

EV

EF

fF

fS

˜̃¯

ˆÁÁË

Ê=

i

AF n

NkT lnf

WD

Conductance Technique

P-SiC MOS-C, HP4284

1. Bias MOS-Capacitor into strong accumulation

a. Measure C and R in series mode (COX and RS)

b. Sweep frequency (100 Hz to 1 MHz)

2. Bias MOS-Capacitor into flatband

a. Measure C and R in parallel mode (CM and GM)

b. Sweep frequency (100 Hz to 1 MHz)

3. Bias MOS-Capacitor toward depletion

a. Measure C and R in parallel mode (CM and GM)

b. Sweep frequency (100 Hz to 1 MHz)

Conductance Technique

222

222 )(

M

MMC

Ca

CGaG

w

w

+

+=

a

CGC MC

C =

COX

CD

RS

CIT GIT

P-SiC MOS-C, HP4284

0

1

2

3

4

5

6

7

8

10 3 10 4 10 5 10 6

Gp

/

(pF

)

(rad/s)w

w

22

2

)( COXC

COXP

CCG

GCG

-+=

ww

w

)( 222MMSM CGRGa w+-=

( )Ú•

•-

D-

D-

D-

D+

= S

U

U

U

US

ITP Udee

eqDGUS

S

S

S 2

2

2

2

2 2

]1ln[

2

s

wtwt

psw

• Nicollian and Brews, MOS Physics & Technology, New York: John Wiley & Sons (1982)

Cap

acit

ance

(p

F)

Conductance Technique

Energy Calculation

22

22

)(

)(

COXC

OXCCOXCOXP CCG

CGCCCCC

-+

--=

ww

ITPD CCC -=

( )Ú•

•-

D-

D-

D-

D= S

U

U

U

US

ITIT Ude

e

eqDC US

S

S

S 2

2

2

2

arctan

2

s

wtwt

ps

0

50

100

150

200

250

300

103 104 105 106

Angular Frequency (rad/s)

CIT

CD

CP

COX

CD

RS

CIT GIT

Comparison of Results

High-Low and Conductance

0

2

4

6

8

10

0.50 0.70 0.90 1.10 1.30 1.50

DIT

( x

1011

cm

-2eV

-1 )

E - EV (eV)

Conductance

High-Low CV

• DIT measurementscan only be made inthe majority carrierhalf of the bandgap

• High-Low is easierfor analysis and allowsdeeper probe ofbandagap

• Conductance iseasier to implement,has greater sensitivity,and yields data on trapdynamics

Simple Lateral NMOSFET Fabrication

400 mm x 400 mm Channel

P- Epilayer

Al

B-doped Poly-Si

N+ N+

500 Å SiO2

P+ 4H-SiC Substrate

Backside Contact

Ni Ni

+VG

+VD

Inverted Channel

Simple Lateral NMOSFET CharacterizationCG – VG with Source, Drain, Body Grounded

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20

Gate Voltage (V)

Gat

e C

apac

itan

ce (

C/C

OX)

FM

S

QF +

QIT

+ Q

MIAccumulation

Depletion

Flat Band

Inversion Turn On

Fully On

Filling Traps

Simple Lateral NMOSFET CharacterizationField Effect Mobility Measurement

VTH = 2.5 V

( ) ˙˚

˘ÍÎ

È--˜

¯

ˆÁË

ʘ¯

ˆÁË

Ê=2

2D

DTHGOXn

D

VVVV

A

C

L

WI

m˜̃¯

ˆÁÁË

Ê

∂

∂˜̃¯

ˆÁÁË

ʘ¯

ˆÁË

Ê=G

D

DOXFE V

I

VC

A

W

Lm

Reliability Concerns in the DMOSFETRelevant Oxide Fields

N-Type Drift Layer

P-Well P-Well

N+Source

N+SourceP+ P+

Gate MetalNi NiGate Oxide

N-Type Substrate

Ni

ON State~NMOS

VG

EC

EV

EOX

VG ↑

VG

EC

EV

OFF State~PMOSEOX

VD ↑

Reliability Method

Time Dependent Dielectric Breakdown

• Simultaneously stress capacitors (each 200 mm in

diameter) into strong accumulation at a desired

operating temperature

– N-type : Positive stress; P-type : Negative stress

• Record failure times for all capacitors

• Determine time at which half the distribution has failed

(MTTF) for a given oxide field

• Plot MTTF vs. Field and extrapolate back to lower

fields to determine reliability

Reliability Method

Constant Voltage Stress

• Large enough accumulation bias to collect data

in reasonable amounts of time

• Constantly monitor current until failure

criterion is attained.

• Computer collects failure statistics

Reliability Method

Dielectric Strength Measurement

Gate Oxide Field (MV/cm)

Log

Gat

e Le

akag

e (A

)

10

Fowler-N

ordhei

m

Tunnelin

g

Die

lect

ric

Str

eng

th

SiO2 SiC

EC

Reliability Method

Bimodal Failure Distribution

Failure Time (sec)

Cum

ulat

ive

Fai

lure

(%

)

100

Intr

insi

c

Extrinsic

7.17.68.1Field (MV/cm)

Reliability Method

Weibull Plot of Intrinsic Failures

Failure Time (sec)

Cum

ulat

ive

Fai

lure

(%

) Field (MV/cm)

50

7.17.68.1

1.8E62.1E52.5E4t50

Reliability Method

Extrapolation for Low Field MTTF

Oxide Field (MV/cm)

Mea

n T

ime

to F

ailu

re (

hr)

10-2

100

102

104

106

108

4 5 6 7 8 9

Power DMOSFET Cross SectionRelevant Internal Resistances

N-Type Drift Layer

P-Well P-Well

N+Source

N+SourceP+ P+

Gate MetalNi NiGate Oxide

RDrift

RJFET

RChannel ËIncrease Mobility

N-Type Substrate

Ni

DnDrift Nq

dR

m=

Ë Reduce DIT

Historical Progress of SiC MOS

Improved Clean and Unload

DIT

( x

1011

cm

-2eV

-1 )

E - EV (eV)

• PMOS-C measuredwith High-Low Methodat 350oC

• DIT < 2E11 cm-2eV-1

with RCA clean andgentle unloading

0

2

4

6

8

10

0.4

0.6 0.8 1.0

1.2 1.4 1.6 1.8

PiranhaFast Pull

RCAFast Pull

RCASlow Pull

• Shenoy, et al., J. Electron. Mater. 24, 303 (1995)

Historical Progress of SiC MOS

• PMOS-C measuredwith High-Low andConductance at 300oC

• DIT < 1E11 cm-2eV-1

near midgap with950oC Reox Anneal

0.50.60.70.80.9

1

2

3

4

0.0 0.5 1.0 1.5

1150 °C Wet Oxidation (3 hr.)

1150 °C Wet Oxidation (3 hr.)with 950 °C Reox Anneal (3 hr.)

DIT

( x

1011

cm

-2eV

-1 )

E - EV (eV)

950oC Re-Oxidation Anneal

• Lipkin, et al., J. Electron. Mater. 25, 909 (1996)

Historical Progress of SiC MOS

• PMOS-C measured atroom temperature

• Qox = 5E11 cm-2 with950oC Reox Anneal(50% reduction)

Reduced QOX in Reoxidized Samples

20

40

60

80

100

120

140

-8 -6 -4 -2 0 2 4

Cap

acit

ance

(p

F)

Voltage (V)

Flatband Capacitance

1150oC Wet O2

1150oC Wet O2950oC Reox

• Das, et al., J. Electron. Mater. 27, 353 (1998)

Historical Progress of SiC MOS

MOSFET Turn-On Remains Poor!

Non-Idealities in the SiC MOS System

Surface Morphology

<5 Å100 Å

1600oC ImplantActivation Anneal

Increased surface roughness decreases thechannel mobility at high fields

Large magnitude of surface roughness maycause discontinuity in the inversion layer

Non-Idealities in the SiC MOS System

Surface Potential Fluctuations

P-SiC

N+ N+

OXIDE

Isolated pools of electrons

+ ++ + + +

++

+

++

1011

1012

1013

00.511.522.53

4H-SiC DIT

Comparison

Purdue Hilo (P)

Purdue CT (N)

Afanasev (N)

Afanasev (P)

Inte

rfac

e S

tate

Den

sity

(cm

-2eV

-1)

Bandgap Energy (eV)EC EV

But the True Culprit Is…

Despite all of the

interface improvement

in the lower half of the

bandgap, the upper

half of the bandgap

remains relatively

unaffected.

DIT

• Afanas’ev, et al., Phys. Stat. Sol., 162, 321 (1997)

Schörner, et al., IEEE Electron

Dev. Lett., 20, 241 (1999)

Arnold, IEEE Trans. Electron

Dev., 46, 497 (1999)

Which Interface Traps Matter?

Ec

Ei

Metal Ox Semiconductor

Inversion

EFEv

Ff

FfDIT in the upper

halfof the band gap iscritical to n-channel

MOSFET turn-on.

First Major Breakthrough

Post Oxidation NO Anneal

Order of magnitude DITreduction with POA inNO at 1175oC

• Li, et al., J. Appl. Phys., 86, 4316 (1999) • Chung, et al., Appl. Phys. Lett., 76, 1713 (2000)

Reduced Stretch Out of NMOS C-V

Post Oxidation NO Anneal

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-5 -4 -3 -2 -1 0 1 2 3 4 5

Gate Voltage (V)

No

rmal

ized

Cap

acit

ance

(C

/CO

X)

Measured

Theoretical

NO

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-5 -4 -3 -2 -1 0 1 2 3 4 5

Gate Voltage (V)

No

rmal

ized

Cap

acit

ance

(C

/CO

X)

Measured

Theoretical

ReOx

Significant stretch-out of CVdue to interface traps

Minimal stretch-out of CVdue to reduced trapping

Improved NMOSFET C-V with NO AnnealCG – VG with Source, Drain, Body Grounded

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

-10 -8 -6 -4 -2 0 2 4

Gate Voltage (V)

Gat

e C

apac

itan

ce (

C/C

OX)

Flat Band @ -6 V

Turn On @ -1 V

Fully On @ 2 V

Improved MOSFET Turn-On

Post Oxidation NO Anneal

Gate Oxide Leakage Characteristic

Dielectric Strength > 10 MV/cm

>90% Yield

Time Dependent Dielectric Breakdown

NMOS-C,175 oC

NMOS-C, 300 oC

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

0 1 2 3 4 5 6 7 8 9 10 11 12

Oxide Field (MV/cm)

Mea

n T

ime

To

Fai

lure

(h

r)

NMOS-C 175C

MOSFET 175C

PMOS-C 175 C

NMOS-C 300C

Acceptable MTTF:100 years

Op

erating

Field

PMO

S-C, 175°C

Improved 1800V MOSFET Performance

Post Oxidation NO Anneal

Ron,sp = 8.1 mW·cm2 (at Vgs = 15 V)

10 A at 0.86 V(Vgs = 15 V)

BV = 1800 V (at Vgs = 0 V)

• Ryu, et al., Mater.Sci. Forum, 527-529, 1261 (2006)

Improved 10 kV MOSFET Performance

Post Oxidation NO Anneal

• Ryu, et al., International Symposium on Power Semiconductor Devices (2006)

0 2000 4000 6000 8000 10000

0.0

2.0x10-6

4.0x10-6

6.0x10-6

8.0x10-6

1.0x10-5

1.2x10-5

JD (

A/c

m2

)

VDS

(V)

10 kV @ 11 mA/cm2

0 2 4 6 8 10-1

0

1

2

3

4

5

6

7

8

9

Vg= 5 V, Vg=0 V

Vg= 10 V

Vg= 15 V

ID (

A)

VDS

(V)

Ron,sp = 111 mW-cm2

VF @ 5A = 3.9 VBV > 10 kVVG = 0 V

Cooper Plot Perspective for SiC MOS Switches

Silicon Unipolar Limit

4H-SiC Unipolar Limit1998UMOS

1999DMOS

2001UMOS

2001SIAFET

2001SEMOS

2002UMOS

2003DMOS

2004DMOS

2006IGBT

Future MOS Prospects for SiC

Dealing with the Sub-Oxide Issue

• Sub-Oxide formed by the conventional thermal

oxidation of SiC

– Competition between Si and underlying C to oxidize

• The Sub-Oxide may give rise to 2 major non-idealities in

SiC MOS

– Interface states (DIT) – affects (1) mobility and (2) threshold

– Fixed oxide charge (QOX) – affects (1) threshold and (2) mobility

• Sub-Oxide formation may limit the effectiveness of

conventional nitridation (NO and N2O) due to in-situ

oxidation

Future MOS Prospects for SiC

Minimizing the Sub-Oxide Formation

• Ammonia (NH3) annealed oxide

– No in-situ oxidation caused by NO or N2O

• Deposited oxides

– No consumption/incorporation of the SiC into the

sub-oxide layer

• Metal Enhanced Oxides (MEO)

– Faster oxidation precludes the sub-oxide formed by

the competition between Si and C to oxidize

Conductance of Dry Oxide + NO Anneal

0.0E+00

1.0E-11

2.0E-11

3.0E-11

4.0E-11

5.0E-11

6.0E-11

1.0E+03 1.0E+04 1.0E+05 1.0E+06

Frequency (Hz)

GP(w

)/w

(F

)

VG = VFBDIT=5E11 eV-1cm-2

EC-E= 0.2 eV

sUS = 3.5 kT

Large, Broad Conductance Curves

Conductance of Dry Oxide + NO Anneal

0.0E+00

1.0E-11

2.0E-11

3.0E-11

4.0E-11

5.0E-11

6.0E-11

1.0E+03 1.0E+04 1.0E+05 1.0E+06

Frequency (Hz)

GP(w

)/w

(F

)

VG = VFB to Vdepl

Stationary Conductance Peaks

Conductance of Dry Oxide + NH3 AnnealSmaller, Narrower, Mobile Conductance Peaks

0.0E+00

5.0E-13

1.0E-12

1.5E-12

2.0E-12

2.5E-12

3.0E-12

1.0E+03 1.0E+04 1.0E+05 1.0E+06

Frequency (Hz)

GP

(w)/w

(F

)

Increasing|VG|

sUS = 1 – 1.5 kT

DIT < 1E11 eV-1cm-2

Improved Channel MobilityNH3 Anneal Results in Better MOSFET Performance

0

10

20

30

40

50

60

70

80

-5 0 5 10 15 20

Gate Voltage (V)

Fie

ld E

ffec

t C

han

nel

Mo

bili

ty (

cm2 /V

-s)

LPCVD A

Thermal A

N2O

Dry

Dry O2 + Wet Re-Ox

Dry O2 + Wet Re-Ox + N2O

Dry O2 + Wet Re-Ox + NH3

Deposited LTO + NH3

Limitations of Deposited/NH3 Oxides

• Poor gate yield

– Most likely due to the NH3 etching the exposed gate

oxide

– Majority of devices have gate leakage problems

• Poor reliability

– Non-leaky devices exhibit significantly reduced

dielectric strength (~5 MV/cm)

– MTTF is very low

Metal Enhanced Oxidation (MEO)

SiC Boat SiC Boat

Alu

min

a

SiC

Waf

er

SiC

Waf

er

Oxidation in the Presence of Alumina

1054 803 716 650 632 558 311 199

1172 1076 941 856 825 819 809 793 696 280

1233 1129 1023 952 883 847 834 824 764 810 798 553

1267 1175 1086 990 921 790 857 825 830 839 806 789 763 556

1303 1235 1134 1083 989 907 741 684 541 757 808 828 795 774 714 417

1823 1239 1169 1080 1016 961 821 340 325 543 643 682 821 806 780 735

1488 1210 1149 1084 1001 901 367 317 309 343 593 874 859 823 816 782

1932 1177 1122 1055 973 881 390 319 328 404 552 863 895 883 878 904

2343 1136 1090 1024 958 918 466 390 416 533 710 935 939 938 949 1000

2180 1115 1055 988 915 849 914 589 645 818 914 1018 1005 1000 1009 1099

1963 1018 956 903 875 818 720 885 962 979 1021 1036 1048 1079

1210 955 917 890 957 907 928 974 1004 1031 1061 1091

1155 943 918 916 923 951 1000 1048 1100 1123

1480 1004 966 963 978 1036 1086 1161

0 to 500 500 to 1000 1000 to 1500 1500 to 2000 2000 to 2500

1000oC Dry O2 1 hr

• Olafsson, et al., Electron. Lett., 40, 508 (2004)

0

10

20

30

40

50

60

-5 -4 -3 -2 -1 0 1 2 3 4 5

Voltage (V)

Cap

acit

ance

(p

F)

Ideal CV

Best Fit to Data

Exp. Data

C-V of SiC NO Anealed NMOS-CapacitorSlight Stretch-Out and Flatband Shift

C-V of SiC MEO NMOS-CapacitorAlmost Ideal C-V is obtained

0

10

20

30

40

50

60

70

-5 -4 -3 -2 -1 0 1 2 3 4 5

Voltage (V)

Cap

acit

ance

(p

F)

Ideal CV

Best Fit to Data

Exp. Data

Well-Behaved GP/w Curves

Conductance of SiC MEO NMOS-Capacitor

Improved Channel MobilityMEO Results in Better MOSFET Performance

0

10

20

30

40

50

60

70

80

-4 0 4 8 12 16

Gate Voltage (V)

Fie

ld E

ffec

t M

ob

ility

(cm

2/V

s)

ReOx

NO

MEO

0

10

20

30

40

50

60

-4 0 4 8 12 16 20

Gate Voltage (V)

Fie

ld E

ffec

t M

ob

ility

(cm

2/V

s)

ReOx

NO

MEO

5 mm Epitaxy

Al: 5E15 cm-3 Epi: 5 mm, Al:5E15 cm-3

Al1E18 cm-3, 0.5 mm

Limitations of MEO Oxides

• Sodium contamination

– Sodium manifests itself as a positive mobile ion in

the gate oxide

– Several volts of threshold shift occur

• Incompatible with DMOSFET processing

– The quality of the interface degrades with any post

metallization processes at elevated temperature

– Forming an ohmic contact to SiC becomes difficult

• Sveinbjornsson, et al., European Conference on SiC and Related Materials (2006)

Summary

SiC MOS technology has matured dramatically within the past decade

Thermal Dry-Wet Oxides:

•Charge Coupled Devices (Sheppard, Purdue U.)

•CMOS Circuits (Ryu, Purdue U.)

•9 kV Power IGBT (Zhang, Cree Inc.)

Nitrided Oxides:

•1200 V Power MOSFET (to be commercialized in 1 year)

•10 kV Power MOSFET (20 kHz SSPS, Navy)

•DRAM Non-Volatile Memory (Dimitrijev, Griffiths U.)

Next Generation Oxides:

•600 V Power MOSFET (Cree, Inc.)

•RF Power LDMOSFET (Alok, Philips)

Acknowledgements

Prof. Jim CooperProf. Mike MellochProf. Mike Capano

Dr. Jay Shenoy

WithGenerousSupportFrom: ONR

Dr. John ZolperDARPA/MTO

Dr. Harry DietrichAFRL

Dr. Jim ScofieldARL

Dr. Skip Scozzie

Dr. John PalmourDr. Anant Agarwal

Dr. Lori LipkinDr. Sei-Hyung Ryu

Dr. Jon ZhangDr. Brett Hull

Dr. S. KrishnaswamiMr. Len Hall

Mr. H. HagleitnerMs. Sarah Haney

Ms. Charlotte Jonas

Mr. Jim RichmondMr. Khiem LamMs. Fatima HusnaMr. Jim Vencl