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ARM Cortex-M0 August 22, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. CORTEX-M0 Structure Discussion

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  • ARM Cortex-M0August 22, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com

    CORTEX-M0 Structure Discussion 2 Core Peripherals

  • Cortex-M0 StructureDiscussion 2 Core PeripheralsTopics TodayCORTEX-M0 SYSTICK Core PeripheralCORTEX-M0 NVIC Core PeripheralCORTEX-M0 SCB Core Peripheral

  • Cortex-M0 Core PeripheralsCortex-M0 32 Bit CPUSYSTICKNVICSCBCore Peripherals are Common to All Cortex Devices

  • Core Peripheral Memory Map

    Memory Region UsageMemory AttributeXNMemory Region Start Memory Region StopDevice AccessDeviceXN0xE01000000xFFFFFFFFPrivate PeripheralStrongly OrderedXN0xE00000000xE00FFFFFExternal DeviceDeviceXN0xA00000000xDFFFFFFFExternal MemoryNormal--0x600000000x9FFFFFFFInternal PeripheralDeviceXN0x400000000x5FFFFFFFInternal SRAMNormal--0x200000000x3FFFFFFFInternal Code ExecuteNormal--0x000000000x1FFFFFFF

  • Core Peripheral Memory Map

    Core PeripheralMemory Region Start Memory Region StopNested Vector Controller (NVIC)0xE000EF000xE000EF03System Control Block (SCB)0xE000ED000xE000ED3FNested Vector Controller (NVIC)0xE000E1000xE000E4EFSysTick Timer (STK)0xE000E0100xE000E01FSystem Control Block (SCB)0xE000E0080xE000E00F

  • SYSTICK Core Peripheral24-Bit Reload Register24-Bit Down CounterIRQ Control RegisterCortex-M0 CPUSysTick InterruptSystem Clock

  • SYSTICK Core PeripheraltimeTime interval = Reload Count / Clock FrequencyP e r i o d i c I n t e r r u p t s

  • SYSTICK Core PeripheralSimple Periodic Interval TimerIdentical Structure in Cortex-M0, M3, M4Settable Interrupt Priority24-Bit Counter WidthCount Enable ControlInterrupt Enable Control

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is an Interrupt Controller?INSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONNormal Program Flow Instruction Proceed in Sequence

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is an Interrupt Controller?INSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONNormal Program FlowInterrupt Service Program FlowInterrupt EventInterrupt Return

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralAn Interrupt Controller manages the process of interrupting normal program flow upon receipt of an interrupt eventInterrupt Entry: Push Stack FrameFetch Interrupt VectorInterrupt Exit: Pop Stack FrameResume normal program executionWhat is an Interrupt Controller?

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Vectored Interrupt Controller?VECTOR 0VECTOR 1VECTOR 2VECTOR 3VECTOR 4VECTOR 5VECTOR 6VECTOR 7VECTOR 8VECTOR NInterrupt Service Routine 2 Interrupt Service Routine 6 Interrupt Service Routine 4 Interrupt Service Routine 8 Vector Table contains Start Address of Interrupt Service RoutineInterrupt ControllerIndividual InterruptsVector Table

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralAn Interrupt Vector is a unique 32-Bit value which is set to the Start Address of an Interrupt Service RoutineInterrupt Vectors are Stored in a Sequential Table of VectorsVectored Interrupts have low latency

    What is a Vectored Interrupt Controller?

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Vectored Interrupt Controller?

    Exception NumberIRQ NumberVectorOffsetInitial Stack Value0x001Reset Vector0x042-14NMI Vector0x083-13Hard Fault Vector0x0C4RESERVED5RESERVED6RESERVED7RESERVED8RESERVED9RESERVED10RESERVED11-5SVCall Vector0x2C12RESERVED13RESERVED14-2PendSV Vector0x3815-1SYSTICK Vector0x3C160IRQ0 Vector0x40171IRQ1 Vector0x44182IRQ2 Vector0x48 4731IRQ31 Vector0xBC

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Vectored Interrupt Controller?Receive InterruptBranch to Global Service RoutineDetermine Unique InterruptService Unique InterruptNormal Program FlowReturn to Normal Program FlowReceive InterruptNormal Program FlowService Unique InterruptReturn to Normal Program FlowVECTOREDNOT VECTOREDHas extra steps longer latencyOlder ARM7 StyleNew CORTEX Style

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?INSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONNormal Program FlowInterrupt Service Program FlowInterrupt EventInterrupt ReturnINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONINSTRUCTIONInterrupt Service Program FlowInterrupt EventInterrupt ReturnLow PriorityHigh Priority

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?Nested Interrupt SupportIndividual Interrupts have PriorityHigher Priority Interrupt will Preempt LowerLower or Equal Priority Interrupt will WaitInterrupt Tail Chaining to Reduce LatencyInterrupt Late Arriving to Reduce Latency

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?

    Interrupt TypesInterrupt PriorityResetHighest Priority -3Non Maskable Interrupt (NMI)Priority -2Hard FaultPriority -1SVCallConfigurable PriorityPendSVConfigurable PrioritySysTickConfigurable PriorityInterrupt (IRQ0 - 31)Configurable Priority

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?

    Interrupt PreemptionHigher Priority Interrupt preempts lower priority interruptInterrupt Tail ChainingAt completion of interrupt, it another interrupt event has occurred, then stack pop is skipped and new interrupt service startsInterrupt Late ArrivingIf low priority interrupt begins and while saving the stack frame a higher priority interrupt occurs, then higher priority interrupt will execute first.

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?Normal program flowNormal program flowPush Stack FramePop Stack FrameService InterruptNormal program flowNormal program flowPush Stack Frame 1Pop Stack Frame 2Service Interrupt 1Service Interrupt 2Int 1Int 2IntPush Stack Frame 2Service Interrupt 1Pop Stack Frame 1Interrupt Preemption Int 2 Higher Priority Than Int 1

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?Normal program flowNormal program flowPush Stack FramePop Stack FrameService InterruptNormal program flowNormal program flowPush Stack FramePop Stack FrameService Interrupt 1Service Interrupt 2Int 1Int 2IntInterrupt Tail Chaining Int 1 Higher or Equal Priority Than Int 2

  • Nested-Vectored Interrupt ControllerNVIC Core PeripheralWhat is a Nested Vectored Interrupt Controller?Normal program flowNormal program flowPush Stack FramePop Stack FrameService InterruptNormal program flowNormal program flowPush Stack FramePop Stack FrameService Interrupt 2Service Interrupt 1Int 1Int 2IntInterrupt Late Arriving Int 2 Higher Priority Than Int 1

  • SCB Core PeripheralRegister Set which provides system implementation and system control functionsCPU ID RegisterInterrupt Control and State RegisterApplication Interrupt and Reset Control RegisterSystem Control RegisterConfiguration Control RegisterSystem Handler Priority Registers

  • Cortex-M0+ PeripheralMPC Core PeripheralMemory Protection UnitCORTEX-M0+ Eight Separate RegionsCORTEX-M0+ Overlapping RegionsCORTEX-M0+ Background Regions

  • Meaning and ImplicationsProcessor Architecture 8 Bit World to 32 Bit WorldProcessing Capability8 Bit Architecture32 Bit CORTEX-M0Sophisticated NVIC Interrupt ControlLow Latency Interrupt FeaturesVectoring, Preemption, Chaining, Late ArrivalCore Control FeaturesMemory Protection Unit