ARM PrimeCell Technical Reference Manualinfocenter.arm.com/help/topic/com.arm.doc.ddi0142b/DDI... · ARM PrimeCell Technical Reference Manual Preface About this document ... † a

ARM PrimeCell™

General Purpose Input/Output (PL060)

Technical Reference Manual

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI0142B

ARM PrimeCellTechnical Reference Manual

Copyright © 1999 ARM Limited. All rights reserved.

Release Information

The following changes have been made to this book.

Proprietary Notice

Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

Change history

Description Issue Change

November 1998 A First release

February 1999 B Second release

ii Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

ContentsARM PrimeCell Technical Reference Manual

PrefaceAbout this document ...................................................................................... viFurther reading ............................................................................................ viiiFeedback ....................................................................................................... ix

Chapter 1 Introduction1.1 About the ARM PrimeCell General Purpose Input/Output (PL060) ............ 1-21.2 AMBA compatibility ..................................................................................... 1-4

Chapter 2 Functional Overview2.1 ARM PrimeCell General Purpose Input/Output (PL060) overview .............. 2-22.2 PrimeCell GPIO functional description ........................................................ 2-32.3 PrimeCell GPIO operation ........................................................................... 2-5

Chapter 3 Programmer’s Model3.1 About the programmer’s model ................................................................... 3-23.2 Summary of PrimeCell GPIO registers ....................................................... 3-33.3 Register descriptions .................................................................................. 3-4

Chapter 4 Programmer’s Model for Test4.1 PrimeCell General Purpose Input/Output test harness overview ................ 4-24.2 Scan testing ................................................................................................ 4-3

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. iii

Contents

4.3 Test registers .............................................................................................. 4-4

Appendix A ARM PrimeCell General Purpose Input/Output (PL060) Signal DescriptionsA.1 AMBA APB signals ..................................................................................... A-2A.2 On-chip signals ........................................................................................... A-3A.3 Signals to pads ........................................................................................... A-4

iv Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Preface

This preface introduces the ARM PrimeCell General Purpose Input/Output (PL060) and its reference documentation. It contains the following sections:

• About this document on page vi

• Further reading on page viii

• Feedback on page ix.

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. v

Preface

About this document

This document is the technical reference manual for the ARM PrimeCell General Purpose Input/Output (PL060).

Intended audience

This document has been written for experienced hardware engineers who may or may not have experience of ARM products.

Organization

This document is organized as follows:

Chapter 1 Introduction

Read this chapter for an introduction on the PrimeCell General Purpose Input/Output (GPIO) and its features.

Chapter 2 Functional Overview

Read this chapter for a description of the major functional blocks of the PrimeCell GPIO.

Chapter 3 Programmer’s Model Read this chapter for a description of the registers and signals of the PrimeCell GPIO.

Chapter 4 Programmer’s Model for Test Read this chapter for a description of the test registers and programming details of the PrimeCell GPIO.

Appendix A ARM PrimeCell General Purpose Input/Output (PL060) Signal Descriptions Read this appendix for a description of the PrimeCell GPIO signals.

Typographical conventions

The following typographical conventions are used in this document:

bold Highlights signal names within text, and interface elements such as menu names. May also be used for emphasis in descriptive lists where appropriate.

italic Highlights special terminology, cross references and citations.

typewriter Denotes text that may be entered at the keyboard, such as commands, file names and program names, and source code.

vi Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Preface

typewriter Denotes a permitted abbreviation for a command or option. The underlined text may be entered instead of the full command or option name.

typewriter italic Denotes arguments to commands or functions where the argument is to be replaced by a specific value.

typewriter bold Denotes language keywords when used outside example code.

Timing diagram conventions

This manual contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.

Key to timing diagram conventions

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Clock

HIGH to LOW

Transient

HIGH/LOW to HIGH

Bus stable

Bus to high impedance

Bus change

High impedance to stable bus

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. vii

Preface

Further reading

This section lists publications by ARM Limited that are related to this product.

ARM publications

AMBA Specification (Rev 2.0) (ARM IHI 0011).

PrimeCell General Purpose Input/Output (PL060) Integration Manual (PL060 INTM 0000).

PrimeCell General Purpose Input/Output (PL060) Design Manual (PL060 DDES 0000).

viii Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Preface

Feedback

ARM Limited welcomes feedback on both the ARM PrimeCell General Purpose Input/Output (PL060), and the documentation.

Feedback on this document

If you have any comments on this document, please send an email to [email protected] giving:

• the document title

• the document number

• the page number(s) to which your comments refer

• a concise explanation of your comments.

General suggestions for additions and improvements are also welcome.

Feedback on the ARM PrimeCell General Purpose Input/Output (PL060)

If you have any comments or suggestions about this product, please contact your supplier giving:

• the product name

• a concise explanation of your comments.

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. ix

Preface

x Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Chapter 1 Introduction

This chapter introduces the ARM PrimeCell General Purpose Input/Output (PL060) and contains the following sections:

• About the ARM PrimeCell General Purpose Input/Output (PL060) on page 1-2

• AMBA compatibility on page 1-4.

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. 1-1

Introduction

1.1 About the ARM PrimeCell General Purpose Input/Output (PL060)

The PrimeCell General Purpose Input/Output (GPIO) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip peripheral that is developed, tested and licensed by ARM.

The PrimeCell GPIO is an AMBA slave module that connects to the Advanced Peripheral Bus (APB).

The PrimeCell GPIO has 16 bits of programmable input/output organized as two 8-bit ports, port A and port B. Pins of both ports can be configured as either inputs or outputs. At system reset, port A defaults to inputs, and port B defaults to outputs. The PrimeCell GPIO interfaces with input/output pad cells using a data input, data output and output enable line per pad. Figure 1-1 illustrates the PrimeCell GPIO interfaces.

Figure 1-1 GPIO block diagram and PADS connections

1.1.1 Features of the PrimeCell GPIO

The PrimeCell GPIO offers:

• compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into System-on-a-Chip (SoC) implementation

Connection of GPIO linesto the external I/O PADS

PBOE[7:0]

EPA[7:0]

PORTB[7:0]

EPB[7:0]

PORTA[7:0]

PAOE[7:0] nPAOE[7:0]

XPB[7:0]

AMBAAPB

SCANMODE

AMBAAPB

I/f

PORTA

DIR.REG.

PORTA

DATAREG.

PORTB

DIR.REG.

PORTB

DATAREG.

I/O PADSGPIO

PAOE[7:0]

PORTA[7:0]

EPA[7:0]

PBOE[7:0]

PORTB[7:0]

EPB[7:0]

Active HIGH

Active LOW

XPA[7:0]

1-2 Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Introduction

• 16 individually programmable input/output pins

• control word read-back capability

• port A defaults to eight inputs at reset

• port B defaults to eight outputs at reset.

The direction registers for port A and port B are programmable.

Additional test registers and modes are implemented for functional verification and manufacturing test.


Introduction

1.2 AMBA compatibility

The PrimeCell GPIO complies with AMBA Specification (Rev 2.0) onwards. The fundamental differences from the AMBA Specification Revision D are:

• the timing of the strobe signal PSTB compared with the enable signal PENABLE

• the time at which read data is sampled

• a separate unidirectional read data bus PRDATA, and unidirectional write data bus PWDATA (instead of the bidirectional data bus PD)

• the address bus is named PADDR (instead of PA).

This document assumes little-endian memory organization, where bytes of increasing significance are stored in increasing addresses in memory, and hence low-order bytes are transferred on the low-order bits of the data bus. This block can also be used in a system with a big-endian memory organization, and several methods of achieving this are described in the PrimeCell General Purpose Input/Output (PL060) Integration Manual.


Chapter 2 Functional Overview

This chapter describes the major functional blocks of the ARM PrimeCell General Purpose Input/Output (PL060) and contains the following sections:

• ARM PrimeCell General Purpose Input/Output (PL060) overview on page 2-2

• PrimeCell GPIO functional description on page 2-3

• PrimeCell GPIO operation on page 2-5.


Functional Overview

2.1 ARM PrimeCell General Purpose Input/Output (PL060) overview

The PrimeCell GPIO is an Advanced Microcontroller Bus Architecture (AMBA) bus slave that connects to the AMBA Advanced Peripheral Bus (APB). It provides 16 inputs/outputs organized as two 8-bit groups, port A and port B.

The CPU reads and writes data and control/status information to and from the PrimeCell GPIO via the AMBA APB interface.

Each port has an associated:

• Data direction register

• Data register.

2.1.1 Data direction register

The data direction register, is 8 bits wide, and is programmed to select whether each individual input/output pin is configured as an input or an output.

2.1.2 Data register

The data register, is 8 bits wide, and is used to:

• read the value input on those PrimeCell GPIO lines that are configured as inputs

• program the value output on those PrimeCell GPIO lines that are configured as outputs.


Functional Overview

2.2 PrimeCell GPIO functional description

A diagrammatic view of the PrimeCell GPIO is shown in Figure 2-1. Note that for clarity test logic is not shown.

Figure 2-1 PrimeCell GPIO block diagram

The functions of the PrimeCell GPIO are described in the following sections:

• AMBA APB interface

• Register block on page 2-4

• Interface reset on page 2-5

• GPIO operation on page 2-5.

2.2.1 AMBA APB interface

The AMBA APB interface generates read and write decodes for accesses to the control register and data register for each input/output port.

The AMBA APB is a local secondary bus which provides a low-power extension to the higher bandwidth AMBA Advanced High-Performance Bus (AHB), or AMBA Advanced System Bus (ASB), within the AMBA system hierarchy. The AMBA APB groups narrow-bus peripherals to avoid loading the system bus, and provides an interface using memory-mapped registers which are accessed under programmed control.

Port AData direction

Register

Port AData

register

Port BData direction

Register

Port BData

register

AMBAAPB

Interface

PRDATA [7:0]

PWDATA [7:0]

PADDRL [3:2]

PADDRH [7:6]

PWRITE

PENABLE

PSEL

PCLK

BnRES

PAOE [7:0]

PORTA [7:0]

EPA [7:0]

PBOE [7:0]

PORTB [7:0]

EPB [7:0]

Register block


Functional Overview

2.2.2 Register block

The register block implements the storage element for the data registers and data direction register for both input/output ports. Test registers are also implemented in this block for functional verification and manufacturing test.


Functional Overview

2.3 PrimeCell GPIO operation

The operation of the PrimeCell GPIO is described in the following sections:

• Interface reset

• GPIO operation.

2.3.1 Interface reset

All block registers are cleared during power on reset (BnRES LOW). This disables the output drivers for port A (input as default) and enables the drivers for port B (output as default).

2.3.2 GPIO operation

For each port, there is a data register and a data direction register. On reads, the data register contains the current status of corresponding port pins, whether they are configured as input or output. Writing to a data register only affects the pins that are configured as outputs.

Data direction registers

The data direction registers operate in a different manner on each port:

For Port A 0 (zero) indicates the port is defined as an input (default), and 1 in the data direction register indicates the port is defined as an output.

For Port B 0 (zero) in the data direction register indicates the port is defined as an output (default), 1 in the data direction register indicates the port is defined as an input.

Figure 2-2 on page 2-6 illustrates a write to a port data register or data direction register.


Functional Overview

Figure 2-2 Write operation

Figure 2-3 on page 2-7 illustrates a read from a port data register or data direction register

.

`


Functional Overview

Figure 2-3 Read operation

The read data will actually be sampled at the APB bridge on the rising edge of PCLK when PENABLE is HIGH.

`


Functional Overview


Chapter 3 Programmer’s Model

This chapter describes the ARM PrimeCell General Purpose Input/Output (PL060) registers and provides details needed when programming the microcontroller. It contains the following sections:

• About the programmer’s model on page 3-2

• Summary of PrimeCell GPIO registers on page 3-3

• Register descriptions on page 3-4.


Programmer’s Model

3.1 About the programmer’s model

The base address of the PrimeCell GPIO is not fixed, and may be different for any particular system implementation. The offset of any particular register from the base address, however, is fixed.

The following locations are reserved, and must not be used during normal operation:

• locations at offsets 0x10–0x3c and 0x8c–0xff are reserved for possible future extensions

• locations at offsets +0x40 through +0x88 are reserved for test purposes.



3.2 Summary of PrimeCell GPIO registers

The PrimeCell GPIO registers are shown in Table 3-1.

Table 3-1 PrimeCell GPIO register summary

Address Type WidthReset value

Name Description

GPIO Base + 0x00 Read/write

8 0x00 GPIOPADR Port A data register.


8 0x00 GPIOPBDR Port B data register.


8 0x00 GPIOPADDR Port A data direction register.

GPIO Base + 0x0c Read/write

8 0x00 GPIOPBDDR Port B data direction register.

GPIO Base + 0x10–0x3c - - - - Reserved.

GPIO Base + 0x40–0x88 - - - - Reserved (for test purposes).

GPIO Base + 0x8c–0xff - - - - Reserved.



3.3 Register descriptions

The following registers are described in this section:

• GPIOPADR: [8] (+ 0x00)

• GPIOPBDR: [8] (+ 0x04)

• GPIOPADDR: [8] (+ 0x08) on page 3-5

• GPIOPBDDR: [8] (+ 0x0c) on page 3-5.

For each of the following register descriptions, the format of the title is:

Register name: [bit width] (Offset from Base).

3.3.1 GPIOPADR: [8] (+ 0x00)

GPIOPADR is the port A data register. Values written to GPIOPADR will be output on the PORTA pins if the corresponding GPIOPADDR data direction bits are set HIGH (port output). The values read from this register are determined, for each bit, by the value of the corresponding bit in the data direction register GPIOPADDR. A read from this register will return the last bit value written when the bit is configured as an output, or it will return the current value on the corresponding port input bit EPA if the bit is configured as an input. All bits are cleared by a reset. Table 3-2 shows the bit assignments for the GPIOPADR.

3.3.2 GPIOPBDR: [8] (+ 0x04)

GPIOPBDR is the port B data register. Values written to GPIOPBDR will be output on the PORTB pins if the corresponding GPIOPBDDR data direction bits are set LOW (port output). The values read from this register are determined, for each bit, by the value of the corresponding bit in the data direction register GPIOPBDDR. A read from this register will return the last bit value written when the bit is configured as an output,

Table 3-2 GPIOPADR register

Bits Name Type Function

7:0 Port A data register

Read/ write

Port A input data. Port A output data.



or it will return the current value on the corresponding port input bit EPB if the bit is configured as an input. All bits are cleared by a reset. Table 3-3 shows the bit assignments for the GPIOPBDR.

3.3.3 GPIOPADDR: [8] (+ 0x08)

GPIOPADDR is the port A data direction register. Bits set in GPIOPADDR will set the corresponding pin in PORTA to be an output. Clearing a bit configures the pin to be an input. All bits are cleared by a reset. Table 3-4 shows the bit assignments for the GPIOPADDR.

3.3.4 GPIOPBDDR: [8] (+ 0x0c)

GPIOPBDDR is the port B data direction register. Bits cleared in the GPIOPBDDR will set the corresponding pin in PORTB to be an output. Setting a bit configures the pin to be an input. All bits are cleared by a reset. Table 3-5 shows the bit assignments for the GPIOPBDDR.

Table 3-3 GPIOPBDR register


7:0 Port B data register

Read/ write

Port B input data. Port B output data.

Table 3-4 GPIOPADDR register


7:0 Port A data direction register

Read/ write

Bits set, Port A output. Bits cleared, Port A input.

Table 3-5 GPIOPBDDR register


7:0 Port B data direction register

Read/ write

Bits set, Port B input.

Bits cleared, Port B output.




Chapter 4 Programmer’s Model for Test

This chapter describes the additional logic for functional verification and production testing. It contains the following sections:

• PrimeCell General Purpose Input/Output test harness overview on page 4-2

• Scan testing on page 4-3

• Test registers on page 4-4.


Programmer’s Model for Test

4.1 PrimeCell General Purpose Input/Output test harness overview

The additional logic for functional verification and production testing allows:

• stimulation of input signals to the block

• generation of a special test clock enable signal to propagate test vectors.

Off-chip test vectors are supplied via a 32-bit parallel External Bus Interface (EBI) and converted to internal AMBA bus transfers. The application of test vectors is controlled via the Test Interface Controller (TIC) AMBA bus master module. Figure 4-1 shows a blow diagram of the PrimeCell GPIO.

Figure 4-1 PrimeCell GPIO test harness

PrimeCell

AMBA APB interface

Non-

APBinputs

Test stimulus Test resultscapture

GPIOAMBA

Non-

APBoutputs

AMBA



4.2 Scan testing

The PrimeCell GPIO has been designed to simplify the insertion of scan test cells and the use of Automatic Test Pattern Generation (ATPG) for an alternative method of manufacturing test.

During scan testing, the SCANMODE input must be driven HIGH to ensure that all internal data storage elements can be asynchronously reset. For normal use and application of manufacturing test vectors via the TIC, SCANMODE must be negated LOW.



4.3 Test registers

The PrimeCell GPIO test registers are memory-mapped as shown in Table 4-1.

Each register shown in Table 4-1 is described below.

4.3.1 GPIOTCER [0] (+0x40–0x7c)

GPIOTCER is the test clock enable register. This is a virtual register. Accesses to it will result in the creation of an internal test clock enable. Table 4-2 shows the bit assignments for the GPIOTCER.

GPIOTCER has a multiple word space in the register address map to allow for the generation of multiple test clock enable pulses.

Table 4-1 Test registers memory map

Address Type Width Reset value Name Description

GPIO Base + 0x40–0x7c Read/write

0 - GPIOTCER Test clock enable register.


5 0x00 GPIOTCR Test control register.


8 0x00 GPIOTISRA Test input stimulus register for port A.


8 0x00 GPIOTISRB Test input stimulus register for port B.

Table 4-2 GPIOTCER register

Bit Name Description

7:0 - When in registered clock mode (refer to GPIOTCR [5] (+0x80) on page 4-5), a test clock enable is produced only when this register is accessed (read or write).



4.3.2 GPIOTCR [5] (+0x80)

GPIOTCR is he test control register. This register controls the clocking mode and the input pin multiplexing during test mode. Table 4-3 shows the bit assignments for the GPIOTCR.

Table 4-3 GPIOTCR register


7:5 - Reserved, read unpredictable, should be written as 0.

4 Test Input Select (TESTINPSEL)

By default, this bit is cleared to 0 for normal operation. This bit selects the source for the primary inputs.

When this bit is cleared to 0, the primary inputs are taken from the external pads (normal operation).

When this bit is set to 1, the values programmed in GPIOTISRA and GPIOTISRB are used as the inputs to Port A and Port B.

3 Test Reset (TESTRST)

By default, this bit is cleared to 0 for normal operation when reset by BnRES.

When this bit is set to 1, a reset is asserted throughout the module, EXCEPT for the test registers (this simulates reset by BnRES being asserted to 0).

2 Registered Clock Mode (REGCLK)

This bit selects the internal test clock mode:

0 = Strobe clock mode is selected which generates a test clock enable on every AMBA APB access (read or write) to the block. Use of strobe clock mode allows testing with less test vectors when testing functions such as counters. The Test Clock Enable is generated from PENABLE ANDed with PSEL.

1 = Registered clock mode is selected which only generates a test clock enable on an AMBA APB access to the GPIOTCER (GPIO Test Clock Enable register) location.

This bit has no effect unless bit 0 and bit 1 are both set to 1.

This bit is cleared to 0 by default on reset by BnRES.



4.3.3 GPIOTISRA [8] (+0x84)

GPIOTISRA is the test input stimulus register for port A. This register provides direct stimulus control of the non-AMBA primary inputs to port A of the device. Table 4-4 shows the bit assignments for the GPIOTISRA.

4.3.4 GPIOTISRB [8] (+0x88)

GPIOTISRB is the test input stimulus register for port B. This register provides direct stimulus control of the non-AMBA primary inputs to port B of the device. Table 4-5 shows the bit assignments for the GPIOTISRB.

1 Test Clock Enable (TESTCLKEN)

This bit selects the source of the test clock:

0 = The internal clock enable is continuously HIGH.

1 = The internal test clock enable is selected, so that the test clocks are enabled for only one period of the input clock per AMBA APB access. The internal clock enable mode depends on the setting of bit 2.

This bit has no effect unless bit 0 is set to 1.


0 Test Mode Enable (TESTEN)

0 = Normal operating mode is selected.

1 = Test mode is selected.

Bits 1 and 2 have no effect unless bit 0 is set to 1.


Table 4-3 GPIOTCR register (continued)


Table 4-4 GPIOTISRA register


7:0 Port A Programmable test stimulus to primary input EPA.

Table 4-5 GPIOTISRB register


7:0 Port B Programmable test stimulus to primary input EPB.


Appendix A ARM PrimeCell General Purpose Input/Output (PL060) Signal Descriptions

This appendix describes the signals that interface with the ARM PrimeCell General Purpose Input/Output (PL060). It contains the following sections:

• AMBA APB signals on page A-2

• AMBA APB signals on page A-2

• Signals to pads on page A-4.

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. A-1

ARM PrimeCell General Purpose Input/Output (PL060) Signal Descriptions

A.1 AMBA APB signals

The PrimeCell General Purpose Input/Output (GPIO) module is connected to the AMBA APB bus as a bus slave. With the exception of the BnRES signal, the AMBA APB signals have a P prefix and are active HIGH. Active LOW signals contain a lower case n. The AMBA APB signals are described in Table A-1.

.

Table A-1 AMBA APB signal descriptions

Name TypeSource/destination

Description

BnRES Input Reset controller Bus reset signal, active LOW.

PADDRH[7:6] Input APB bridge Subset of AMBA APB address bus.

PADDRL[3:2] Input APB bridge Subset of AMBA APB address bus.

PCLK Input Clock generator AMBA APB clock, used to time all bus transfers.

PENABLE Input APB bridge AMBA APB enable signal. PENABLE is asserted HIGH for one cycle of PCLK to enable a bus transfer.

PRDATA [7:0] Output APB bridge Subset of unidirectional AMBA APB read data bus.

PSEL Input APB bridge PrimeCell GPIO select signal from decoder. When set to 1 this signal indicates the slave device is selected by the AMBA APB bridge, and that a data transfer is required.

PWDATA [7:0] Input APB bridge Subset of unidirectional AMBA APB write data bus.

PWRITE Input APB bridge AMBA APB transfer direction signal, indicates a write access when HIGH, read access when LOW.

A-2 Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B


A.2 On-chip signals

Table A-2 shows the non-AMBA on-chip signals from the block.

Table A-2 On-chip signals


Description

SCANMODE Input Test controller PrimeCell GPIO scan test hold input.

This signal must be asserted HIGH during scan testing to ensure that internal data storage elements can be reset asynchronously.

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. A-3


A.3 Signals to pads

Table A-3 describes the signals from the GPIO to input/output pads of the chip. It is the responsibility of the user to make proper use of the peripheral pins to meet the exact interface requirements.

Table A-3 Signals to pads


Description

PORTA[7:0] Output Pads Port A output driver. Values written into the GPIOPADR register are put onto these lines and driven out to the port A pins if the corresponding data direction bits are set HIGH (GPIOPADDR register).

EPA[7:0] Input Pads Port A input. Values present on these pins are reflected within the GPIOPADR register if the corresponding GPIOPADDR data direction bits are LOW.

PAOE[7:0] Output Pads Port A output enable (active HIGH). Values written into the GPIOPADDR register are put onto these lines.

PORTB[7:0] Output Pads Port B output driver. Values written into the GPIOPBDR register are put onto these lines and driven out to the port B pins if the corresponding data direction bits are LOW (GPIOPBDDR register).

EPB[7:0] Input Pads Port B input. Values present on these pins are reflected within the GPIOPBDR register if the corresponding GPIOPBDDR data direction bits are HIGH.

PBOE[7:0] Output Pads Port B output enable (active LOW). Values written into the GPIOPBDDR register are put onto these lines.

A-4 Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

Index

AAddress, base 3-2AMBA

APB bus A-2APB interface 2-3APB signals A-2

AMBA compatibility 1-4ATPG 4-3Automatic test pattern generation 4-3

BBase address 3-2Big-endian 1-4Block diagram, PrimeCell GPIO 2-3BnRES A-2

CClocking mode 4-5

Compatibility,AMBA 1-4

DData register 2-2

EEPA A-4EPB A-4External bus interface 4-2

FFunctional description, PrimeCell GPIO

2-3

GGPIO test harness 4-2GPIOADDR 3-5GPIOPADR 3-4GPIOPBDDR 3-5GPIOPBDR 3-4GPIOTCER 4-4GPIOTCR 4-5GPIOTISRA 4-6GPIOTISRB 4-6

IInput pin multiplexing 4-5Interface reset 2-5

LLittle- endian 1-4

ARM DDI0142B Copyright © 1999 ARM Limited. All rights reserved. Index-1

Index

MMultiplexing input pins 4-5

OOperation, PrimeCell GPIO 2-5

PPADDRH A-2PADDRL A-2Pads A-4PAOE A-4PBOE A-4PCLK A-2PENABLE A-2Port A 2-5

data direction register 3-5data register 3-4input A-4Output driver A-4output enable A-4

Port B 2-5data direction register 3-5data register 3-4input A-4output driver A-4output enable A-4

PORTA A-4PORTB A-4PRDATA A-2PrimeCell GPIO

block diagram 2-3functional description 2-3Integration Manual 1-4operation 2-5overview 2-2

Production testing 4-2Programmer’s model 3-1

for test 4-1PSEL A-2PWDATA A-2PWRITE A-2

RRead operation 2-7Register

data 2-2descriptions 3-4port A data 3-4port A data direction 3-5port B data 3-4port B data direction 3-5summary 3-3test 4-4test clock enable 4-4test control 4-5test input stimulus 4-6

Register block 2-4Reset, interface 2-5

SScan testing 4-3SCANMODE A-3Signals A-4Summary of registers 3-3

TTest clock enable 4-4Test clock enable register 4-4Test control register 4-5Test harness 4-2Test input stimulus register 4-6Test interface controller 4-2Test registers 4-4Testing 4-2

VVerification 4-2Virtual register 4-4

WWrite operation 2-6

Index-2 Copyright © 1999 ARM Limited. All rights reserved. ARM DDI0142B

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ARM PrimeCell Technical Reference Manualinfocenter.arm.com/help/topic/com.arm.doc.ddi0142b/DDI... · ARM PrimeCell Technical Reference Manual Preface About this document ... † a