ARM Processor Organization - Presentation

7/27/2019 ARM Processor Organization - Presentation

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ARM processorARM processor

organizationorganization

P. BakowskiP. Bakowski

[email protected]@ieee.org


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ARM register bankARM register bank

TheThe register bankregister bank, which stores the, which stores the processorprocessor

statestate..

r00r00

r01r01

r14r14r15r15


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It hasIt has two read portstwo read ports and oneand one write port whichwrite port which

can each be used to access any register, plus ancan each be used to access any register, plus anadditional read port and an additional write portadditional read port and an additional write port

that give special access to r15, the programthat give special access to r15, the program

counter.counter.

r00r00

r01r01

r14r14

r15r15


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It hasIt has two read portstwo read ports andand oneone write portwrite port whichwhich

can each be used to access any register, plus ancan each be used to access any register, plus anadditional read port and an additional write portadditional read port and an additional write port


counter.counter.

r00r00

r01r01

r14r14

r15r15


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can each be used to access any register, plus ancan each be used to access any register, plus anadditional read portadditional read port and anand an additional write portadditional write port


counter.counter.

r00r00

r01r01

r14r14

r15r15


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can each be used to access any register, plus ancan each be used to access any register, plus anadditional read portadditional read port and anand an additional write portadditional write port

that give special access to r15, thethat give special access to r15, the programprogram

countercounter..

r00r00

r01r01

r14r14

r15r15


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ARM barrel shifterARM barrel shifter

TheThe barrel shifterbarrel shifter, which can, which can shift or rotateshift or rotate oneone

operandoperand byby any number of bitsany number of bits..

number of bitsnumber of bits


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ARM ALUARM ALU

The ALU, which performs theThe ALU, which performs the arithmeticarithmetic andand logiclogic

functionsfunctions required by therequired by the instructioninstruction set.set.

functionsfunctions

operandsoperands


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ARM 3ARM 3--stage pipelinestage pipeline

TheThe address registeraddress register andand incrementerincrementer, which select, which select

and hold addresses and generate sequentialand hold addresses and generate sequentialaddresses when required.addresses when required.

address registeraddress register

incrementerincrementer


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ARM 3ARM 3--stage pipelinestage pipelineThe data registers, which hold data passing to andThe data registers, which hold data passing to and

from memory.from memory.

data out registerdata out register data in registerdata in register

d[31:0]d[31:0]to/from memoryto/from memory

datadata instructionsinstructions


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ARM 3ARM 3--stage pipelinestage pipeline

The instruction decoder and associated control logic.The instruction decoder and associated control logic.

control pathcontrol path

da

ta

in

regi s

ter

da

ta

in

regi s

ter

instructionsinstructions

data pathdata path

control signalscontrol signals


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Three stage pipeline : ARM 1,2,3Three stage pipeline : ARM 1,2,3

FETCHFETCH; the instruction is fetched from memory and; the instruction is fetched from memory and

placed in the instruction pipeline.placed in the instruction pipeline.

fetchfetch

memorymemoryaddress registeraddress register

data in registerdata in registerto instructionto instructionregisterregister

clock cycleclock cycle


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Three stage pipeline : ARM 1,2,3Three stage pipeline : ARM 1,2,3DECODEDECODE; the instruction is decoded and the; the instruction is decoded and the

datapath control signals prepared for the next cycle.datapath control signals prepared for the next cycle.

fetchfetch decodedecode

instruction registerinstruction register



fetchfetch


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EXECUTEEXECUTE; the instruction; the instruction controls the datapathcontrols the datapath; the; the

register bank is read, an operand shifted the ALUregister bank is read, an operand shifted the ALUresult generated and written back into a destinationresult generated and written back into a destination

register.register.


fetchfetch

executeexecute

decodedecode

data pathdata pathcontrol signalscontrol signals


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fetchfetch

executeexecute

decodedecode executeexecutefetchfetch decodedecode executeexecute

instruction throughputinstruction throughput : 1 instruction per clock cycle: 1 instruction per clock cycle

instruction latency : 3 clock cyclesinstruction latency : 3 clock cycles

clock cycleclock cycle


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fetchfetch

executeexecute

decodedecode executeexecutefetchfetch decodedecode executeexecute

instruction throughput : 1 instruction per clock cycleinstruction throughput : 1 instruction per clock cycle

instruction latencyinstruction latency : 3 clock cycles: 3 clock cycles


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ARM 1,2,3 architectureARM 1,2,3 architecture

addr

ess

register

addr

ess

register

data

in

register

data

in

register

incrementer

incrementer

data

out

register

data

out

register



registerregister

bankbank

MM

ALUALU

BSBS


a[31:0]a[31:0]

d[31:0]d[31:0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

MM multiplier, BSmultiplier, BS barrel shifterbarrel shifter


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Multi cycle executionMulti cycle execution

fetchfetch decodedecodeSTRSTR

STRSTR store instructionstore instruction needs two execution cycles:needs two execution cycles:

address calculation cycle andaddress calculation cycle and

data transfer cycledata transfer cycle

fetchfetch


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executeexecutedecodedecode addressaddress

fetchfetch

fetchfetch

address calculationaddress calculation cycle andcycle and

data transfer cycledata transfer cycle


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fetchfetch decodedecode executeexecute


transfertransfer


data transferdata transfer cyclecycle

4 clock cycles4 clock cycles


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fetchfetch decodedecode executeexecute


transfertransfer


data transferdata transfer cyclecycle

4 clock cycles4 clock cycles

Attention: onlyAttention: only oneonememory transfermemory transfer

per clock cycleper clock cycle


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Processor performanceProcessor performance

The timeThe time TT, required to execute a given program, required to execute a given programis given by:is given by:

T=(NT=(Ninstinst*CPI)/f*CPI)/fclkclk

NNinstinst--number of instructions in the programnumber of instructions in the program

CPICPI --clock cycles per instructionclock cycles per instruction

ffclkclk --clock frequencyclock frequency


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NNinstinst--number of instructionsnumber of instructionsin the programin the program




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CPICPI --clockclock cycles per instruction (throughput)cycles per instruction (throughput)



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SinceSince NNinsiinsi is constantis constant for a given program there arefor a given program there areonlyonly two waystwo ways to increase performance:to increase performance:

increase the clock rate,increase the clock rate, ffclkclk.. reduce the average number of clock cycles perreduce the average number of clock cycles per

instruction,instruction, CPI.CPI.


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Clock rate increaseClock rate increaseIncrease the clock rateIncrease the clock rate,, ffclkclk. This requires the logic in. This requires the logic ineach pipeline stage to be simplified and, therefore,each pipeline stage to be simplified and, therefore,

thethe number of pipeline stages to be increasednumber of pipeline stages to be increased..

stage1stage1 stage2stage2 stage3stage3

clock cycleclock cycle 3 stages3 stages


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Clock rate increaseClock rate increaseIncrease the clock rateIncrease the clock rate,, ffclkclk. This requires the logic in. This requires the logic ineach pipeline stage to be simplified and, therefore,each pipeline stage to be simplified and, therefore,

thethe number of pipeline stages to be increasednumber of pipeline stages to be increased..

stage1stage1 stage2stage2 stage3stage3 stage4stage4 stage5stage5

stage1stage1 stage2stage2 stage3stage3




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Clock rate increaseClock rate increaseNote that theNote that the clock rateclock rate to be used depends heavilyto be used depends heavily

on theon the implementation technologyimplementation technology..

stage1stage1 stage2stage2 stage3stage3clock cycleclock cycle 3 stages3 stages

new implementation technologynew implementation technology

stage1stage1 stage2stage2 stage3stage3clock cycleclock cycle 3 stages3 stages


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More hardware resourcesMore hardware resourcesReduceReduce the average number ofthe average number of clock cycles perclock cycles per

instructioninstruction,, CPI.CPI. This requires the introduction of moreThis requires the introduction of more

parallelismparallelism that means more hardware resources to bethat means more hardware resources to beused in a given clock cycle.used in a given clock cycle.

data readdata read oror

instruction fetchinstruction fetchdata readdata read andand

instruction fetchinstruction fetch

D/I MD/I M DMDM IMIM


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55--stage pipeline organizationstage pipeline organizationHigher performance ARM cores employ a 5Higher performance ARM cores employ a 5--stagestage

pipeline and havepipeline and have separate instruction and dataseparate instruction and data

memoriesmemories..

Breaking instruction execution down into five stagesBreaking instruction execution down into five stages

rather than three reduces the maximum work whichrather than three reduces the maximum work which

must be completed in a clock cycle, and hence allowsmust be completed in a clock cycle, and hence allowsa higher clock frequency to be used.a higher clock frequency to be used.

The separate instruction and data memories seen asThe separate instruction and data memories seen as

separate caches connected to a unified instruction andseparate caches connected to a unified instruction anddata main memory allow a significant reduction in thedata main memory allow a significant reduction in the

core's CPI.core's CPI.


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memoriesmemories..

BreakingBreaking instruction executioninstruction execution down intodown into five stagesfive stages


must be completed in a clock cycle, and hence allowsmust be completed in a clock cycle, and hence allowsaa higher clock frequencyhigher clock frequency to be used.to be used.

The separate instruction and data memories seen asThe separate instruction and data memories seen as

separate caches connected to a unified instruction andseparate caches connected to a unified instruction anddata main memory allow a significant reduction in thedata main memory allow a significant reduction in the



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memoriesmemories..

Breaking instruction execution down into five stagesBreaking instruction execution down into five stages


must be completed in a clock cycle, and hence allowsmust be completed in a clock cycle, and hence allowsa higher clock frequency to be used.a higher clock frequency to be used.

TheThe separate instruction and data memoriesseparate instruction and data memories seen asseen as

separate cachesseparate caches connected to a unified instruction andconnected to a unified instruction anddata main memory allow a significant reduction in thedata main memory allow a significant reduction in the



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Fetch stageFetch stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

FETCHFETCH -- the instruction is fetched from memory andthe instruction is fetched from memory and

placed in theplaced in the instruction cacheinstruction cache..

incrementer

incrementer

I cacheI cachenext PCnext PC

to decoderto decoder


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Decode stageDecode stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

DECODEDECODE -- the instruction isthe instruction is decodeddecoded andand registerregister

operands readoperands read from the register file.from the register file.

II--decode

decode


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Decode stageDecode stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

There areThere are three operand read portsthree operand read ports in the register file,in the register file,

so most instructions can obtain all their operands inso most instructions can obtain all their operands in

one cycle.one cycle.

II--decode

decode registerregister

filefile


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Execute stageExecute stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

EXECUTEEXECUTE -- anan operand isoperand is shiftedshifted and the ALU resultand the ALU resultgenerated.generated.

registerregisterfilefile

MMALUALU

BSBS

+4+4

ALUbusALUbus


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EXECUTEEXECUTE -- an operand is shifted and thean operand is shifted and theALU resultALU resultgeneratedgenerated..


MMALUALU

BSBS

+4+4

ALUbusALUbus


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If the instruction is aIf the instruction is a load or storeload or store the memorythe memoryaddress is computedaddress is computed in the ALU.in the ALU.


MMALUALU

BSBS

+4+4

ALUbusALUbus


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Buffer stageBuffer stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

BUFFERBUFFERdatadata -- data memory is accessed if required.data memory is accessed if required.

Otherwise the ALU result is simply buffered for one clockOtherwise the ALU result is simply buffered for one clock

cycle to give the same pipeline flow for all instructions.cycle to give the same pipeline flow for all instructions.

+4+4

D cacheD cache

byte replicationbyte replication

rotation/signrotation/signextensionextension


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Write back stageWrite back stagefetchfetch decodedecode executeexecute bufferbuffer writewrite

WRITEWRITE--back; the results generated by the instructionback; the results generated by the instruction

are written back to the register file, including any dataare written back to the register file, including any data

loaded from memory.loaded from memory.

registerregister

filefile

ALUALU

ALUbusALUbus

D cacheD cacherotation/signrotation/sign

extensionextension


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Data forwardingData forwardingIn the 5In the 5--stage pipeline instructionstage pipeline instruction execution is spreadexecution is spread

across three pipeline stagesacross three pipeline stages, the only way to resolve, the only way to resolve

data dependencies without stalling the pipeline is todata dependencies without stalling the pipeline is tointroduceintroduce forwardingforwarding pathspaths..

fetchfetch

decodedecode

executeexecute

bufferbuffer

writewrite


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Data forwardingData forwarding

fetchfetch decodedecode executeexecute bufferbuffer writewrite


Data dependenciesData dependencies arise when an instructionarise when an instruction

needs to use theneeds to use the result of one of its predecessorsresult of one of its predecessorsbefore that result has returned to thebefore that result has returned to the register fileregister file..

to register fileto register file


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Data forwardingData forwardingForwarding pathsForwarding paths (by(by--pass) allow the intermediatepass) allow the intermediate

results to be passed between stages as soon as they areresults to be passed between stages as soon as they are

available, in the 5available, in the 5

--stage ARM pipeline each of the threestage ARM pipeline each of the three

source operands can be forwarded from any of threesource operands can be forwarded from any of three

intermediate result registersintermediate result registers



to register fileto register file

byby--pass pathspass paths


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PC organizationPC organization -- compatibilitycompatibility

TheThe programming behaviorprogramming behavior of the PC implementedof the PC implemented

through r15 is based on thethrough r15 is based on the operational characteristicsoperational characteristicsof the 3of the 3--stage ARM pipeline.stage ARM pipeline.

Basically the 5Basically the 5--stage pipeline reads the instructionstage pipeline reads the instruction

operandsoperands one stage earlierone stage earlier and that is incompatible withand that is incompatible with33--stage design.stage design.


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PC organizationPC organization -- compatibilitycompatibility

The programming behavior of the PC implementedThe programming behavior of the PC implemented

through r15 is based on the operational characteristicsthrough r15 is based on the operational characteristicsof the 3of the 3--stage ARM pipeline.stage ARM pipeline.

Basically the 5Basically the 5--stage pipeline reads the instructionstage pipeline reads the instruction

operandsoperands one stage earlierone stage earlier and that is incompatible withand that is incompatible with33--stage design.stage design.


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PC organisationPC organisation -- solutionsolutionThis problem is resolved by theThis problem is resolved by the incrementationincrementation of the PCof the PC

value from the fetch stage in thevalue from the fetch stage in the decode stagedecode stage,,

bypassing the pipeline register between the two stages.bypassing the pipeline register between the two stages.

PC+4 for the next instruction is equal to PC+8 for thePC+4 for the next instruction is equal to PC+8 for the

current instruction (4 bytes farther), so the correct r15current instruction (4 bytes farther), so the correct r15

value is obtained without additional hardware.value is obtained without additional hardware.


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PC organisationPC organisation -- solutionsolutionPC+4 for the next instruction is equal to PC+8 for thePC+4 for the next instruction is equal to PC+8 for the

current instruction (4 bytes farther), so the correct r15current instruction (4 bytes farther), so the correct r15

value is obtained without additional hardware.value is obtained without additional hardware.

incrementer

incre

menter

I cacheI cache

nextnext

PC+4PC+4

to decoderto decoder

next PC+8next PC+8

registerregister

filefile

r15r15


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ARM programming modelARM programming modelTheThe Instruction Set ArchitectureInstruction Set Architecture (ISA) defines the(ISA) defines the

operations that the programmer can use to change theoperations that the programmer can use to change the

statestate of the system incorporating the processor.of the system incorporating the processor.

This state usually comprises the values of the data itemsThis state usually comprises the values of the data items

in the visible registers and the memory.in the visible registers and the memory.

Each instruction performs a defined transformation fromEach instruction performs a defined transformation from

the state before the instruction is executed to the statethe state before the instruction is executed to the state

after it has completed.after it has completed.


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ARM programming modelARM programming modelThe Instruction Set Architecture (ISA) defines theThe Instruction Set Architecture (ISA) defines the


state of the system incorporating the processor.state of the system incorporating the processor.

ThisThis statestate usually comprises the values of theusually comprises the values of the data itemsdata items

inin thethe visiblevisible registersregisters and theand the memorymemory..

Each instruction performs a defined transformation fromEach instruction performs a defined transformation from

the state before the instruction is executed to the statethe state before the instruction is executed to the state

after it has completed.after it has completed.


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ARM programming modelARM programming modelThe Instruction Set Architecture (ISA) defines theThe Instruction Set Architecture (ISA) defines the


state of the system incorporating the processor.state of the system incorporating the processor.

This state usually comprises the values of the data itemsThis state usually comprises the values of the data items

in the visible registers and the memory.in the visible registers and the memory.

Each instructionEach instruction performsperforms a defineda defined transformationtransformation fromfrom

thethe state beforestate before the instruction is executed to thethe instruction is executed to the statestate

afterafter it has completed.it has completed.


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ARM memory subsystemARM memory subsystem

ARM memoryARM memory may be viewed as amay be viewed as a linear array oflinear array of

bytesbytes numbered fromnumbered from zero up to 2zero up to 2

3232

--11..

00

223232--11

linear arraylinear array

of bytesof bytes


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ARM memory subsystemARM memory subsystemDataData items may be 8items may be 8--bitbit bytesbytes, 16, 16--bitbit halfhalf--wordswords oror

3232--bitbit wordswords..

223232--11

wordswordsbytesbytes

00112233


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ARM memory subsystemARM memory subsystemWordsWords are alwaysare always alignedaligned onon 44--byte boundariesbyte boundaries (the(the

two leasttwo least significantsignificant address bitsaddress bits areare zerozero) and half) and half--

words are aligned on even byte boundaries.words are aligned on even byte boundaries.

00112233

223232--11

0000

word addressword address

byte numberbyte number


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ARM memory subsystemARM memory subsystemWordsWords are alwaysare always alignedaligned onon 44--byte boundariesbyte boundaries (the(the

two leasttwo least significantsignificant address bitsaddress bits areare zerozero) and half) and half--

words are aligned on even byte boundaries.words are aligned on even byte boundaries.

00112233

223232--11

little endianlittle endian organizationorganization


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ARM loadARM load--store architecturestore architecture

TheThe processing instructionprocessing instruction (add, subtract, and so on)(add, subtract, and so on)

take the valuestake the values from the registersfrom the registers and always placeand always placethe results into a register.the results into a register.


MMALUALU

BSBS

+4+4

ALUbusALUbus


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ARM loadARM load--store architecturestore architecture

TheThe processing instructionprocessing instruction (add, subtract, and so on)(add, subtract, and so on)

take the values from the registers and always placetake the values from the registers and always placethethe results into a registerresults into a register..


MMALUALU

BSBS

+4+4

ALUbusALUbus


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ARMARM loadload--store architecturestore architectureThe only instructions which apply to memory state are onesThe only instructions which apply to memory state are ones

which copy memorywhich copy memory values into registervalues into register ((load instructionsload instructions))

or copy register values into memory (store instructions).or copy register values into memory (store instructions).


DD --cachecache memorymemory


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ARM loadARM load--storestore architecturearchitectureThe only instructions which apply to memory state are onesThe only instructions which apply to memory state are ones

which copy memory values into register (load instructions)which copy memory values into register (load instructions)

or copy registeror copy register values into memoryvalues into memory ((store instructionsstore instructions).).


DD --cachecache memorymemory


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ARM instructionsARM instructions

In general the ARM instructions fall into one of theIn general the ARM instructions fall into one of the

followingfollowing three categoriesthree categories:: data processing instructionsdata processing instructions

data transfer instructionsdata transfer instructions

control flow instructionscontrol flow instructions


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followingfollowing three categoriesthree categories:: data processingdata processing instructionsinstructions




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data transferdata transfer instructionsinstructions



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control flowcontrol flow instructionsinstructions


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ARM data processingARM data processing

Data processing instructions:Data processing instructions:

these use andthese use and change only register valueschange only register values;;


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ARM data processingARM data processingFor example, an instruction can addFor example, an instruction can add two registerstwo registers andand

place the result in aplace the result in a registerregister..

registerregister

filefile MMALUALU

BSBS

+4+4

ALUbusALUbus


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ARM data transferARM data transfer

Data transfer instructions copy memory values intoData transfer instructions copy memory values into

registers (registers (loadload instructions) or copy register valuesinstructions) or copy register valuesinto memory (into memory (storestore instructions);instructions);

An additional form, useful only in systems code,An additional form, useful only in systems code,exchanges a memory value with a register value.exchanges a memory value with a register value.


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ARM data transferARM data transfer

Data transfer instructions copy memory values intoData transfer instructions copy memory values into

registers (load instructions) or copy register valuesregisters (load instructions) or copy register valuesinto memory (store instructions);into memory (store instructions);

An additional form, useful only in systems code,An additional form, useful only in systems code,exchangesexchanges a memory value with a register value.a memory value with a register value.


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ARM data transferARM data transferData transfer instructions copy memory values intoData transfer instructions copy memory values into

registers (load instructions) or copy register valuesregisters (load instructions) or copy register values

into memory (store instructions);into memory (store instructions);

An additional form, useful only in systems code,An additional form, useful only in systems code,

exchangesexchanges a memory value with a register value.a memory value with a register value.

e.g.e.g. test and settest and set instructioninstruction


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ARM control flowARM control flowControl flow instructions cause execution toControl flow instructions cause execution to switch toswitch to

a different addressa different address, either, either permanentlypermanently ((branchbranch

instructionsinstructions) or saving a return address to resume the) or saving a return address to resume theoriginal sequence (branch and link instructions) ororiginal sequence (branch and link instructions) or

trapping into system code (supervisor calls).trapping into system code (supervisor calls).


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ARM control flowARM control flowControl flow instructions cause execution to switch toControl flow instructions cause execution to switch to

a different address, either permanently (brancha different address, either permanently (branch

instructions) orinstructions) or saving a return address to resume thesaving a return address to resume theoriginal sequenceoriginal sequence ((branch and linkbranch and link instructions) orinstructions) or

trapping into system code (supervisor calls).trapping into system code (supervisor calls).

link addresslink address


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ARM control flowARM control flowControl flow instructions cause execution to switch toControl flow instructions cause execution to switch to

a different address, either permanently (brancha different address, either permanently (branch

instructions) or saving a return address to resume theinstructions) or saving a return address to resume theoriginal sequence (branch and link instructions) ororiginal sequence (branch and link instructions) or

trapping into system codetrapping into system code ((supervisor callssupervisor calls).).

system codesystem code

link addresslink address


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ARM supervisor modeARM supervisor modeThe ARM processor supports aThe ARM processor supports a protected supervisorprotected supervisor

modemode. The protection mechanism ensures that user. The protection mechanism ensures that user

code cannot gaincode cannot gain supervisor privilegessupervisor privileges withoutwithoutappropriate checks being carried out to ensure that theappropriate checks being carried out to ensure that the

code is not attemptingcode is not attempting illegal operationsillegal operations..

user codeuser code

I/O driverI/O driver

illegal operation ?illegal operation ?


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ARM supervisor modeARM supervisor modeThe upshot of this for the userThe upshot of this for the user--level programmer is thatlevel programmer is that

systemsystem--level functionslevel functions can only be accessed throughcan only be accessed through

specifiedspecified supervisor callsupervisor call..

system codesystem code

user codeuser code

I/O driverI/O driver

system/supervisorsystem/supervisor callcall

ARM I/O programming


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ARM I/O programmingARM I/O programming

The ARM handles I/0The ARM handles I/0 (input/output) peripherals (such(input/output) peripherals (such

as disk controllers, network interfaces, and so on) asas disk controllers, network interfaces, and so on) as

memorymemory--mapped devicesmapped devices with interrupt support.with interrupt support.

memorymemory--mapped devicesmapped devices

ARM I/O programming


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ARM I/O programmingARM I/O programming

TheThe internal registersinternal registers in these devices appear asin these devices appear as

addressable locationsaddressable locations within the ARM's memory mapwithin the ARM's memory map

and may be read and written using the same (and may be read and written using the same (loadload--storestore) instructions as any other memory locations.) instructions as any other memory locations.

memory locationsmemory locations

storestore

loadload

ARM I/O interruptions


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ARM I/O interruptionsARM I/O interruptions

Peripherals may attract the processor's attention byPeripherals may attract the processor's attention by

making anmaking an interrupt requestinterrupt request using either theusing either the normalnormal

interruptinterrupt ((IRQIRQ) or the) or the fast interruptfast interrupt ((FIQFIQ)) inputinput..

to CPUto CPU --

IRQIRQ

to CPUto CPU -- FIQFIQ



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Both interrupt inputs are levelBoth interrupt inputs are level--sensitive and maskable.sensitive and maskable.

Normally most interrupt sources share theNormally most interrupt sources share the IRQ inputIRQ input,,

with just one or twowith just one or two timetime--critical sourcescritical sources connected toconnected tothethe higherhigher--priority FIQ inputpriority FIQ input..

IRQIRQ

FIQFIQ



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Some systems may includeSome systems may include direct memory accessdirect memory access

(DMA) hardware external to the processor to handle(DMA) hardware external to the processor to handle

highhigh--bandwidth trafficbandwidth traffic..

system bussystem bus

DMA trafficDMA traffic

ARM exceptions


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ARM exceptionse cept o s

The ARM architecture supports a range of :The ARM architecture supports a range of :

interruptsinterrupts

trapstraps

supervisor callssupervisor calls

all grouped under the general heading ofall grouped under the general heading of exceptionsexceptions..

ARM exceptionsARM exceptions


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e cept o sp



trapstraps





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pp



trapstraps





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pp



trapstraps





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pp



trapstraps





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p

TheThe general waygeneral way of exception handling is the same in allof exception handling is the same in all

cases:cases:

the current state is saved by copying the PC intothe current state is saved by copying the PC into

rl4_exc and the CPSR into SPSR_exc (whererl4_exc and the CPSR into SPSR_exc (where excexc standsstands

for the exception type);for the exception type);

the processor operating mode is changed to thethe processor operating mode is changed to theappropriate exception mode;appropriate exception mode;

the PC is forced to a value between 00the PC is forced to a value between 001616 and 1Cand 1C1616, the, the

particular value depending on the type of exception.particular value depending on the type of exception.



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The general way of exception handling is the same in allThe general way of exception handling is the same in all

cases:cases:

thethe current statecurrent state isis savedsaved by copying theby copying the PCPC intointo

rl4_excrl4_exc and theand the CPSRCPSRintointo SPSR_excSPSR_exc (where(where excexc standsstands

for thefor the exception typeexception type););






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cases:cases:




thethe processor operating modeprocessor operating mode is changed to theis changed to theappropriateappropriate exception modeexception mode;;





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cases:cases:





the PC is forced to a value betweenthe PC is forced to a value between 00001616 andand 1C1C1616, the, the


ARM instruction executionARM instruction execution


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address

register

address

register

datain

register

datain

register

incremen

ter

incremen

ter

data

out

register

data

out

register



registerregister

bankbank

MM

ALUALU

BSBS


a[31:0]a[31:0]

d[31:0]d[31:0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

MM multiplier, BSmultiplier, BS barrel shifterbarrel shifter

Data processing instructionData processing instruction


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address

register

address

register

datain

register

datain

register

incremen

ter

incremen

ter

data

out

register

data

out

register

registerregister

bankbank

MM

ALUALU

BSBS

a

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

registerregister registerregister operationsoperations

Data processing instructionData processing instructionrrr


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address

register

address

register

datain

register

datain

register

incremen

ter

incremen

ter

data

out

register

data

out

regist

er

registerregister

bankbank

MM

ALUALU

BSBS

a

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

registerregister immediateimmediate operationsoperations

ir

register

ir

register

Store instructionStore instructionrrrr


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P. Bakowski 91

address

register

ad

dress

register

datain

register

datain

register

incremen

ter

incremen

ter

data

out

register

data

out

regist

er

registerregister

bankbank

MM

ALUALU

BSBS

a

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

compute address operationcompute address operation

ir

register

ir

register

new addressnew address

Store instructionStore instructionrrrr


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address

register

ad

dress

register

datain

register

datai

n

register

incremen

ter

incremen

ter

data

out

register

data

out

regist

er

registerregister

bankbank

MM

ALUALU

BSBS

a

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

store datastore data autoauto--indexindex

ir

register

ir

register

autoauto

--indexindex

Branch instructionBranch instructionrrrr


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address

register

ad

dress

register

datain

register

datai

n

register

incremen

ter

incremen

ter

data

out

register

data

out

regist

er

registerregister

bankbank

MM

ALUALU

BSBSa

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

compute branch addresscompute branch address

ir

register

ir

register

branch addressbranch address

Branch instructionBranch instructionrr

erer


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P. Bakowski 94

ad

dress

register

ad

dress

regi

ster

datain

register

datai

n

register

incremen

ter

incremen

ter

data

out

regist

er

data

out

regist

er

registerregister

bankbank

MM

ALUALU

BSBSa

[31

:0]

a

[31

:0]

d[31:

0]

d[31:

0]

AbusAbus

BbusBbus

ALUbusALUbus

PCPC

store return addressstore return address

ir

register

ir

register

return addressreturn address

R14R14

SummarySummary


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P. Bakowski 95

ARMARM register bankregister bank

ARM barrel shifter and ALUARM barrel shifter and ALU

ARM 3ARM 3--stage and 5stage and 5--stage pipelinesstage pipelines

ARM programming modelARM programming modelARM instructionsARM instructions

SummarySummary


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P. Bakowski 96


ARMARM barrel shifterbarrel shifter andandALUALU



SummarySummary


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ARMARM 33--stagestage andand 55--stage pipelinesstage pipelines


SummarySummary


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ARMARM programming modelprogramming modelARM instructionsARM instructions

SummarySummary


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ARM programming modelARM programming modelARMARM instructionsinstructions

Documents

ARM Processor Organization - Presentation