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Arquitetura 8051

Microcontroladores

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Indice

• Características del Microcontrolador 8051• Arquitetura 8051• Memória interna• Área de RAM• Clock y Reset• Temporización

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Características del 8051• 8051 Introducido en el mercado por Intel al

início de década de 80 (1981)• Atualmente producido por várias compañias

en muchas variantes• Microcontrolador de 8 bits

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Microcontroladores y Fabricantes

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•Atmel •ARM •Intel

•8-bit •8XC42 •MCS48 •MCS51 •8xC251

•16-bit •MCS96 •MXS296

•National Semiconductor •COP8

•Microchip •12-bit instruction PIC •14-bit instruction PIC

•PIC16F84 •16-bit instruction PIC

•NEC

•Motorola •8-bit

•68HC05 •68HC08 •68HC11

•16-bit •68HC12 •68HC16

•32-bit •683xx

•Texas Instruments •TMS370 •MSP430

•Zilog •Z8 •Z86E02

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8051

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Part Number Fabricante ROM RAM Pinos I/O Timers Interrupciones Vcc Package

8051 Intel 4K 128 32 2 5 5v 40

8031 Intel - 128 32 2 5 5v 40

8751 Intel 4K 128 32 2 5 5v 40

8052 Intel 8K 256 32 3 8 5v 40

AT89C51 Atmel 4K 128 32 2 6 5v 40

AT89C1051 Atmel 1K 64 15 1 3 3v 20

AT89C2051 Atmel 2K 128 15 2 6 3v 20

DS5000-8 Dallas 8K 128 32 2 6 3v 40

DS5000T-8 Dallas 32K 128 32 2 6 3v 40

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Arquitetura 8051 Standard• CPU CISC de 8 bits (8 bit Data bus, 16 bit Address bus)

– ULA 8 bits– Registradores 8 bits

• 4Kbytes de ROM de programa– ROM => 8051– EPROM => 8751– ROMLESS => 8031– FLASH => AT89C51 (Atmel)

• 256 bytes de SRAM– 128 bytes de SFRs– 128 bytes de usuário+pilha

• 64 kbytes de ROM externa• 64 kbytes de RAM externa

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Arquitetura 8051 Standard• Periféricos

– 2 Timers de 16 bits com 4 modos funcionamiento– 4 puertos paralelos– 1 Canal de comunicación serial– 5 fuentes de interrupción independentes

• 2 externas• 2 timers• 1 canal serial

• Set de instrucciones– 112 instrucciones básicas

• Instruciones aritméticas;• Instrucciones lógicas• Instrucciones moviminto• Instrucciones saltos y desvios• Instrucciones de controe interno

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Pines 8051

8

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

805180318751

AT89C51

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Pines 8051

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P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7

P2.0P2.0P2.0P2.0P2.0P2.0P2.0P2.0

P1.0P1.0P1.0P1.0P1.0P1.0P1.0P1.0

P3.0P3.1P3.2P3.3P3.4P3.5P3.6P3.7

RST

XTAL1XTAL2

Vcc

GND

PSEN

EA/VPP

AD0AD1AD2AD3AD4AD5AD6AD7

A8A9A10A11A12A13A14A15

RXDTXDINT0INT1T0T1WRRD

ALE/PRG

PORT 0

PORT 2

PORT 1

PORT 3

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CPU

On-chip RAM

On-chip ROM for program code

4 I/O Ports

Timer 0

Serial PortOSC

Interrupt Control

External interrupts

Timer 1

Timer/Counter

Bus Control

TxD RxDP0 P1 P2 P3

Counter Inputs

Arquitectura Microcontrolador 8051

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ACC

B

IP

IE

SBUF

SCON

TH1

TL1

TH0

TL0

TMOD

TCON

DPH

DPL

SP

BYTE ENDEREÇÁVEL

BIT e BYTE ENDEREÇÁVEL

BANCO REGISTRADORES

DRIVERS

RA

M D

EC

OD

ER

SFR

’s D

EC

OD

ER

CY

ROTATE CONTROL

INTERRUPT

CONTROL

SERIAL

PORT

TIMER

CONTROL

PARITY

P

CY, AC, OV

ULA

PROGRAM CONTROL

PCH

PCL

CONTROL PLA

CONTROL ENGINE

INSTRUCTION DECODER

CONTROL

OSC & TIMING CIRCUITRY P3P1

PR

OG

RA

M M

EM

OR

Y A

DD

RE

SS

DE

CO

DE

R

DRIVERS

P2 P0

XTAL1 XTAL2 EA ALE PSEN P1.0 – P1.7 P3.0 – P3.7 P2.0 – P2.7 P0.0 – P0.7 RST VCC GND

4K x 8

EPROM (8751)

ROM MASK (8051)

ROMLESS (8031)

FLASH (AT89C51)

AC F0 RS1 RS0 OV - P

ACC

B

IP

IE

SBUF

SCON

TH1

TL1

TH0

TL0

TMOD

TCON

DPH

DPL

SP

BYTE ENDEREÇÁVEL

BIT e BYTE ENDEREÇÁVEL

BANCO REGISTRADORES

DRIVERS

RA

M D

EC

OD

ER

SFR

’s D

EC

OD

ER

CY

ROTATE CONTROL

INTERRUPT

CONTROL

SERIAL

PORT

TIMER

CONTROL

PARITY

P

CY, AC, OV

ULA

PROGRAM CONTROL

PCH

PCL

CONTROL PLA

CONTROL ENGINE

INSTRUCTION DECODER

CONTROL

OSC & TIMING CIRCUITRY P3P1

PR

OG

RA

M M

EM

OR

Y A

DD

RE

SS

DE

CO

DE

R

DRIVERS

P2 P0

XTAL1 XTAL2 EA ALE PSEN P1.0 – P1.7 P3.0 – P3.7 P2.0 – P2.7 P0.0 – P0.7 RST VCC GND

4K x 8

EPROM (8751)

ROM MASK (8051)

ROMLESS (8031)

FLASH (AT89C51)

AC F0 RS1 RS0 OV - P

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Demux Barramentos 8051

12

8051‘373

ALE

AD7-0

Ahigh

Alow

Data

PSEN

A13-A15

‘LS138

27C128

A0-A13

E

G’

Y0’

Y1’

Q0-Q7

LE

Di Qi

LE

‘LS02

PSEN

ALE

A0-15

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Memória en 8051

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Memória de programa

OU

FFFF

0000

FFFF

0000

10000FFF

EA = 1 EA = 0

64 K External

60 K External

4 K Internal

07

70

Memória de Dados

SFRs

RAM80

FF

00

7F E

DirectDirect , Register,Reg. Indirect

FFFF

0000

64 K External

Internal

PSEN

PSEN

RD

WR

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RAM Interna 8051

14

7F

00

08

10

18

20

30

Scratch Pad Area

RAM

Bit Addressable RAM

Bank 3

Bank 2

Bank 1

Bank 0 R0R7R0

R7R0R7

R0R7

Select Bank withPSW.4 , .3 = RS1, RS0

Bit #00 7F OR20.0 2F.7

* = Bit endereçável

Port 0Stack pointerData pointer DPTR

Power Controltimer/counter controltimer/counter Modetimer 0 Lowtimer 1 Lowtimer 0 Hightimer 1 High

Port 1

Serial ControlSerial Data Buffer

Port 2

Interrupt Enable Ctr 1* IE

* P2

SBUF* SCON

* P1

TH1TH0TL1TL0TMOD

* TCONPCON

DPHDPLSP* P080

818283

8788898A8B8C8D

90

98

A0

99

A8

* P3

* IP

* PSW

* ACC

* BF0

FF

E0

D0

B8

B0

SFRsSFRsUser & Stack

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Bancos de Registradores

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0706050403020100

R7R6R5R4R3R2R1R0

0F

08

17

10

1F

18

Bank 3

Bank 2

Bank 1

Bank 0

Cuatro bancos de registrosCada banco con registros R0-R7

8052

8051

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Área de Bit e Byte

16

7F 78

1A

10

0F 08

07 06 05 04 03 02 01 00

27

26

25

24

23

22

21

20

2F

2E

2D

2C

2B

2A

29

28

20h – 2Fh (16 locations X 8-bits = 128 bits)

Bit addressing:mov C, 1Ahormov C, 23h.2

8052

8051

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Reset y Clock en 8051

17

EA/VPPX1

X2RST

Vcc

10 uF

8.2 K

30 pF

9

31

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Reset y Clock en el 8051

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0000DPTR0007SP0000PSW0000B0000ACC0000PCValorRegister

RAM ????

Estado após Reset:

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Ciclo de Máquina en el 8051

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Ejemplo.: Encontrar el ciclo de máquina para:(a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz.

Solución:

(a) 11.0592 MHz / 12 = 921.6 kHz; Ciclo de máquina = 1 / 921.6 kHz = 1.085 s

(b) 16 MHz / 12 = 1.333 MHz; Ciclo de máquina = 1 / 1.333 MHz = 0.75 s

Ciclo de Máquina = 1/ (fext / 12)

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Temporización del 8051

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Señal de reloj: S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Señal de ALE:

1- Un ciclo de instrucción de un byte. Ex: INC A. Lê Opcode Lê o próx. Lê o próx. Opcode (descarta) Opcode novamente

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 2- Un ciclo de instrución de dos bytes. Ex: ADD A,#data. Lê Opcode Lê segundo Lê prox. Byte Opcode

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 3- Dois ciclos de instrução de um byte. Ex: INC DPTR. Lê Opcode Lê prox. Lê prox. Lê prox. Opcode (descata) Opcode (descarta) Opcode (descarta)

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 Abajo las señales y tiempos involucrados en la busqueda en la memória de programa externa de la instrucción MOVX. S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

Señal de ALE:

PSEN\ :

RD\: P2: PCH Out PCH Out PCH Out PCH Out PCH Out P0:

Inst. in

PCL Out Inst. in PCL Out Inst.

in PCL Out Inst.

in PCL Out