ASIC Design: CMOS Logic Latches

GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS 1

Discussion and CMOS Design of Logic LatchesMuhammad Fahd Waseem, Member, IEEE

Abstract—This assignment answers questions about the designand physical CMOS layout of electronic logic latches. It clearlyindicates their operation using block diagrams and relatedfunctions, and demonstrates functionality in gate & transistorschematics and physical level layouts.

Note that flip-flops are expressly removed from this paper, asthey are non-transparent, while latches are transparent.

Index Terms—Latches, Flip-Flops, ASIC, VLSI, MicroWind,Switch Level, Physical Level

I. INTRODUCTION

IN electronics, a latch is a kind of bistable multivibrator, anelectronic circuit that has two stable states and therefore can

store one bit of information. Today the word is mainly usedfor simple transparent storage elements, while slightly moreadvanced non-transparent (or clocked) devices are describedas flip-flops.

While gates have to be built directly from transistors, latchescan be built from gates, and flip-flops can be built from latches.Both latches and flip-flops are circuit elements whose outputdepends not only on the current inputs, but also on previousinputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas aflip-flop always does [1]. Generally defined, a clock is an edgetriggering mechanism, while an enable (or a gate) is a leveltriggering mechanism.

In other words, a true latch is always asynchronous whilea flip-flop is always synchronous. Because the distinctionbetween a flip-flop and a latch is clear, this paper will adhereto the correct technical definitions as per the title, and describeproper latches only.

Latches may be gated, or non-gated, depending on whetherthey have an enable input.

II. LATCH TYPES

A. SR Latches

When using static gates as building blocks, the most fun-damental latch is the simple SR latch, where S and R standfor set and reset. It can be constructed from a pair of cross-coupled logic gates. The stored bit is present on the outputmarked Q. See Fig. 1 & 2.

Normally, in storage mode, the S and R inputs are both low,and feedback maintains the Q and Q outputs in a constantstate, with Q the complement of Q. If S is pulsed high whileR is held low, then the Q output is forced high, and stays highwhen S returns to low; similarly, if R is pulsed high while S

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Fig. 1: (a) SR Latch, and (b) D Latch

Fig. 2: Blocks for (a) SR Latch, and (b) D Latch

is held low, then the Q output is forced low, and stays lowwhen R returns to low. See Table I.

The NOR gates in the SR latch can also be replaced byNAND gates, to gain an SR latch i.e. an SR latch with activelow inputs.

B. Sub latch types based on the SR Latch

The R = S = 1 combination is called a restricted combi-nation or a forbidden state because, as both NOR gates thenoutput zeros, it breaks the logical equation Q = not Q. Thecombination is also inappropriate in circuits where both inputsmay go low simultaneously (i.e. a transition from restrictedto keep). The output would lock at either 1 or 0 dependingon the propagation time relations between the gates (a racecondition). In certain implementations, it could also lead tolonger ringings (damped oscillations) before the output settles,and thereby result in undetermined values (errors) in high-frequency digital circuits. Although this condition is usuallyavoided, it can be useful in some applications.

To overcome the restricted combination, one can add gatesto the inputs that would convert (S,R) = (1,1) to one of thenon-restricted combinations. That can be:

• Q = 1 (1,0) – referred to as an S-latch• Q = 0 (0,1) – referred to as an R-latch• Keep state (0,0) – referred to as an E-latch• Toggle the output – referred to as a JK-latch

TABLE I: State Table for SR Latch

S R Output

0 0 Keep State

0 1 Q=0

1 0 Q=1

1 1 Restricted Combination

2 GIKI INTERNAL COMPILATION FOR CS465 ASIC DESIGN PROJECTS

TABLE II: State Table for D Latch

D Output

1 Q=1

0 Q=0

Fig. 3: Gated, (a) SR Latch, and (b) D Latch

C. D Latches

This latch exploits the fact that in the two active inputcombinations (01 and 10) of the SR latch, R is the complementof S. The NOT gate converts the two D input states (0 and1) to these two input combinations for the SR latch. Thus aD-latch may be considered as a one-input asynchronous SRlatch. This configuration prevents from applying the restrictedcombination to the inputs. It is also known as transparent latch,or data latch. The word transparent comes from the fact thatthe signal propagates directly through the circuit, from theinput D to the output Q. See Fig. 1 & 2 and Table II.

Transparent latches are typically used as I/O ports or inasynchronous systems. They are available as integrated cir-cuits, usually with multiple latches per circuit.

D. Gated SR Latch

A gated SR latch can be made by adding a second levelof NAND gates to the inverted SR latch (or a second levelof AND gates to the direct SR latch). The extra gates furtherinvert the inputs so the simple SR latch becomes a gated SRlatch (and a simple SR latch would transform into a gated SRlatch with inverted enable). See Fig. 3 & 4.

With E high (enable true), the signals can pass through theinput gates to the encapsulated latch; all signal combinationsexcept for (0,0) = hold then immediately reproduce on the(Q,Q) output, i.e. the latch is transparent.

With E low (enable false) the latch is closed (opaque) andremains in the state it was left the last time E was high. SeeTable III.

Fig. 4: Blocks for Gated (a) SR Latch, and (b) D Latch

TABLE III: State Table for Gated SR and D Latches

E/C State

0 No Change / Keep State

1 Same as Regular Latch

E. Gated D LatchesThe gated D latch works in the same way as the D latch

with the SR latch. The two non-gate inputs to the gated SRlatch are bound by a NOT gate. With E low (enable false) thelatch is closed (opaque) and remains in the state it was leftthe last time E was high. See Fig. 3 & 4 and Table III. Thereare no invalid states.

III. SPECIFICATIONS

We are required to design optimized D latches as definedby the project guidelines for the CS465 Asic Design courseproject [2]. These requirements are drawn from the coursetextbook (Introduction to VLSI Circuits and Systems, by JohnP. Uyemura).

Standard design rules and methodologies must be appliedto design the stated latches. Verilog must be used as the HDL,block diagrams must be displayed and simulations must all becomplete.

IV. DESIGN METHODOLOGY

It is our requirement to design for, and test, the givenobjectives, but not produce fabricatable packages. So ourdesign methodology shall follow the standard CMOS-VLSIdesign flow for digital circuits,

1) System Specification: What is the application / systemwe need to design, and with what parameters.

2) System Design and Verification: To be done on a highlevel schematic simulator, Verilog HDL (behavioral),or an equivalent high level model extractor. For lesscomplicated specifications, this step may be skipped.

3) Logic Synthesis: Reducing the system design to gatelevel descriptions, and subsequent verification. This usu-ally entails a simulation or test in Verilog at the gate /RTL level, or a dedicated logic level simulator.

4) Circuit Design: For CMOS design, this entails reducingthe gate level design into an optimized transistor levelcircuit, and subsequent testing.

5) Physical Design: The circuit design is converted intooptimized silicon layouts. Layouts at this level aregenerally optimized according to a set of design rules,and tested using extended SPICE models.

V. DESIGN ENVIRONMENT

The design environment is defined as the ecosystem ofsoftware tools and kits available during the design phase ofthe project [3].

A. Software Tools

• GNU CC: The GNU C Compiler. Used in a Linuxenvironment for testing SystemC code.

• ModelSim™: The industry standard HDL & system levelsynthesis and simulation suite.

• DSCH: A digital schematic editor and simulator, writtenfor academic purposes by Dr. Etienne Sicard, based inToulouse, France [4].

• µWind (MicroWind): A physical layout design tool andsimulator for CMOS circuits, also written by Dr. EtienneSicard.

M.F. WASEEM, M.D. ZARRAR, AND I. AZIZ: DISCUSSION AND CMOS DESIGN OF LOGIC LATCHES 3

B. BSIM4: Berkeley MOSFET SPICE Simulator

MicroWind integrates BSIM4 (Berkeley MOSFET SPICESimulator) into the simulations it performs.

BSIM4, as an extension of BSIM model, addresses theMOSFET physical effects into sub-100nm regime. It isa physics-based, accurate, scalable, robustic and predictiveMOSFET SPICE model for circuit simulation and CMOStechnology development. It is developed by the BSIM Re-search Group in the Department of Electrical Engineering andComputer Sciences (EECS) at the University of California,Berkeley. BSIM is charted by the Compact Model Council(CMC) [5]. It is a consortium of semiconductor companiesand simulator vendors world-wide promoting BSIM3v3 devel-opment as the industry standard compact model. The councilis affiliated with Electronic Industries Alliance (EIA).

BSIM4 is handled from within the MicroWind interfaceusing a series of parameters. As such, it is among the mostaccurate SPICE simulators for CMOS available in the market.While commercial EDA tool vendors have models furtheradvanced in accuracy, BSIM4 is perfectly sufficient for ourrequirements.

C. Restrictions of the Used Software Tools

Our selection of software tools imposes some restrictionsof the kind of design that can be implemented.

ModelSim is the least restricting of those, because of itspervasive commercial background. Its standard method forHDL simulations is a slightly old technique, whereby thetestbench must be created from HDL itself.

DSCH and MicroWind suffer from a limit on the size of thenetlist. Extremely large circuits cannot be simulated on them.The macros for collective operations are poor: undo is limitedto one operation, collective resizing does not follow polygonrules, attributes cannot be changed by multiple selection, andso on. Moreover, DSCH tends to fixate the orientation ofthe symbols for transistors, making the re-orienting of theseparticularly painstaking.

MicroWind also does not support cell methods. This maybe a major problem when designing large circuits that rely onmultiple repeating units.

Despite these restrictions, the design environment is suffi-cient for our requirements. Our specifications do not call forlarge complex designs, but highly optimized small designs. Wedo not require the use of cells in our design, and by issuingsoftware commands carefully (and taking repeated backups),we can avoid the pitfalls of the lack of GUI macros in DSCHand MicroWind.

VI. HIGH LEVEL BEHAVIORAL MODELING IN SYSTEMC

SystemC is a language built in C++ that spans from con-cept to implementation in hardware and software. The IEEEStandards Association approved the standard for the SystemClibrary as IEEE Std. 1666™ 2005 [6].

We used SystemC to design a basic D latch, just to testthe highest level of abstraction available. The advantage ofusing SystemC lay in the true high-level abstraction it offers,

as opposed to the pseudo behavioral abstraction offered byVerilog in the always blocks it uses.

Appendix A shows the code we used to implement the latch.The text results immediately follow it. It may be noted that thetesting was extremely rudimentary, and not very exhaustive ineither scope or optimization. The purpose was just to get ataste of the language. In our case, the Mint 6 distribution ofLinux was used for the compilation.

VII. NOTES ON THE LAYOUTS IMPLEMENTED

Throughout our layout designs, it should be noted that weimplemented our design rules based on the CMOS 90nm,6 Metal Copper, Strained SiGe LowK fabrication process.For this process, some of the design rules pertinent to ourrequirements are given in Appendix B. It may be noted thatthe design rules file specifies many other rules, and manyspecifications for use by the SPICE engine in MicroWind, butto specify them here is beyond the scope of this paper.

We used λ design rules, with 1λ = 0.050µm. 2λ is thesmallest possible channel length, according to the design rules.

Electrical symmetry was maintained wherever possible. Wedecided to use a baseline NFET size, and then resize thePFETs accordingly to achieve the symmetry. The aspect ratioof the baseline NFET was chosen to be 5, i.e. 10λ/2λ dueto the channel length sizing restriction. The channel length isalways kept at λ = 2, for both PFETs and NFETs. In resizing,only the channel width was changed for the PFETs.

The mobility ratio r (of P-channel FETs to N-channel FETs)depends on the manufacturing process. However, it is rarethat exact mobilities are provided. In that case, it is possibleto use the IDS to VDS curves of tranistors to find r becausemobility (µ) ∝ (current carried). So,

r =µN

µP=

∣∣∣∣ IDS, N

IDS, P

∣∣∣∣All other variables constant

To process the given equation, we generated I–V curves forone NFET and one PFET, with channel dimensions for bothbeing sized at 10λ × 2λ. The curves are shown in Fig. 5.Choosing the values for VDS = VGS = ±1.20V, we find,

r =IDS, N

IDS, P≈ 650µA

350µA= 1.86 ≈ d1.86e = 2

Thus, we shall use the value of r = 2 where needed.The unusual shapes and sizes of interlayer contacts will

be noted: these are to optimize contact resistances whilecomplying with the design rules. These lead to higher signalfidelity.

The physical layouts were almost entirely made in levelsMetal 1 and below. Only in the case of a capacitance require-ment were we forced to move to Metal 2. N-wells were allrooted to the highest potential, and the substrate was groundedto the lowest potential in all cases.

Circuit setup times in the SPICE / BSIM4 / MicroWindsimulations were ignored - these are typically within the first200ps.

For logic values, VDD was considered 1.20V and VSS 0.00V.The colour and sketchmark legend given in Fig. 6 is

followed throughout this paper for physical CMOS layouts.


Fig. 5: I–V Curves for Similarly Sized NFETs and PFETs, for increasing biasing

Fig. 6: Physical CMOS Layout Legend

VIII. BASIC D LATCH

The basic D latch logic on a transistor level was imple-mented in DSCH. Fig. 7 shows the created schematic. Thiswas also simulated in Verilog, shown in Fig. 8. The code forthe simulation can be found in Appendix C. It can be seenthat the output Q immediately follows D.

This was then converted to a CMOS layout, as shown inFig. 9. For creating electrical signal symmetry, PFETs wereincreased in size. Note the inconsistent sizing of the PFETs(the PFETs for the main circuit are larger than the PFET forthe inverter). This is because the 2 PFETs are connected inseries the P half of the circuit for any given signal route, which

Fig. 7: Transistor Level Schematic of Basic D Latch

means the signal propagates half as fast. Using the mobilityconstant ratio of 2, the PFETs thus needed to be 4 times aslarge as the NFET (which were baseline-sized) for electricalsymmetry.

The simulation results are shown in Fig. 10. The MicroWinddefault simulation parameters for BSIM4 were used. As canbe seen, the output Q immediately takes the logic of the input,showing the overall success of the design.


Fig. 8: Verilog Simulation for Basic D Latch at Transistor Level

Fig. 9: CMOS Layout of Basic D Latch

Fig. 10: SPICE Simulation of Basic D Latch Layout

IX. D LATCH WITH ENABLE CONTROL

The schematic created in DSCH (Fig. 11) at gate level isidentical to the D latch shown in Fig. 3. The Verilog code forthis can be found in Appendix D, and the simulation is shownin Fig. 12. Q follows D only when En is high. Else, the ANDgates are disabled and D does not flow through the latch.

Fig. 11: D Latch w/Enable Logic Schematic

Fig. 13: D Latch w/Enable Transistor AOI Schematic

A. D Latch at Transistor Level

The D latch (with enable) at transistor level is an AOI (And-Or-Invert) conversion of the logic schematic shown in Fig. 11.The transistor level schematic is shown in Fig. 13. The Verilogcode for this schematic is given in Appendix E, while thesimulation is shown in Fig. 14.

B. D Latch with Enable, Physical Layout

Converting the transistor level schematic into a physicallayout, while maintaining optimum circuit characteristics,turned out to be a bit of a challenge. Fig. 15 shows theconverted layout. Note how the metal lines arc around thepolylines to avoid the involvement of an extra metal layer forinterconnection. By optimizing the placement of the ‘fingers’in the PFETs and NFETs and intelligent connection in paralleland series, the size of the circuit was kept to a minimum whilealso keeping signal delays at a minimum. Electrical symmetrytoo, was maintained.

Fig. 16 shows the SPICE simulation results from Mi-croWind. The circuit characteristics are optimal: Q follows


Fig. 12: Verilog Simulation for D Latch w/Enable Gate Logic

Fig. 14: D Latch w/Enable Transistor Verilog Simulation

Fig. 15: D Latch w/Enable Physical Layout

D as long as Enabled. Else, it keeps the value it had beforebeing unEnabled.

X. BISTABLE CIRCUITS AS LATCHES

Bistables are circuits with two stable states. Bistable circuitscan be also be used as latches. The advantage of using bistablesas latches is that their sizes are reduced, but the disadvantage isthat they are slow and can have ‘glitches’ during input changesdue to the feedback mechanism they rely on.

Fig. 16: D Latch w/Enable Physical Layout Simulation

A. Basic Bistable D Latch

The Verilog code for a basic bistable D latch is given inAppendix F, and the simulation is shown in Fig. 17. Thetransistor level schematic is shown Fig. 18.

One important thing to note is that bistables need to be‘forced’ to change state by a ‘strong’ voltage source. Thestable output needs a current influx to change polarity, soa high impedance signal will not change the output. A lowimpedance voltage source / signal is thus necessary. This isthe reason bistables are slower than the AOI latches.

Converting this to physical layout was easy as it was simplyconnection of two CMOS inverters in feedback loop. Thelayout is shown in Fig. 19 and the SPICE simulation result inFig. 20. As can be seen, Q follows D, thus the implementationis successful.

B. Bistable D Latch with Controlled Loading

One way to make the bistable latch faster and performwithout the current influxes is to add to gating switches.Transmission gates are often used for this, but using simply


Fig. 17: Basic D Latch Bistable Verilog Simulation

Fig. 18: Basic D Latch Bistable Transistor Level Schematic

NFETs if usually better, to avoid routing difficulties and toprevent the circuit from gaining undue size (which was theadvantage of the bistables).

Appendix G shows the Verilog code for such a configura-tion, and Fig. 21 shows the simulation results from the Verilog.Fig. 22 shows a transistor level schematic. When the control,C, is high, the feedback loop is broken and the input gatefrom D is opened. This allows the value of D to be takenup by the circuit. When C goes low, the feedback loop is re-established and the input from D is turned off. The simulationshows exactly such a thing happening.

XI. C2MOS LATCHES

This is category of latches that are slightly mis-named,because though C2MOS stands for Clocked CMOS, they arenot edge triggered devices, but level triggered (i.e. gated).Their symmetricity in latch construction makes them compactand highly useful in VLSI applications.

A. C2MOS Static D Latch

These are so called because they use a feedback mechanism,not much unlike the bistable with load control, to hold a valueof Q as long as necessary.

Appendix H shows the Verilog code for such a config-uration, and Fig. 23 shows the simulation results from the

Fig. 19: Basic D Latch Bistable Physical Layout

Fig. 20: Basic D Latch Bistable Physical Layout SPICESimulation


Fig. 21: D Latch Bistable with Loading Control, Verilog Simulation

Fig. 22: D Latch Bistable with Loading Control, TransistorLevel Schematic

Verilog. ModelSim Verilog had problems simulating the circuitbecause the feedback loop in this particular latch had morethan one element to accept feedback from. Thus, we had to addtransistor. These allow Verilog to consider discretized feedbackduring a time-based simulation and effectively simulate thecircuit.

Fig. 24 shows a transistor level schematic. Fig. 25 showsthe converted physical layout in CMOS, and finally, Fig. 26shows the SPICE simulation results. The Verilog results, thenthe SPICE results confirm that when the clk is low, the logic ofD flows through and is latched. When clk is high, the first levelof transistors is shut off, and the second layer of transistorshold the value in feedback mode.

B. C2MOS Dynamic D Latch

Fig. 27 shows the schematic for a dynamic D latch. They arecalled dynamic because of the presence of the capacitance asa holding mechanism for the ‘current’ value of Q. There is nofeedback. If the input from the first level of gates is turned off,the capacitor – which was charged, or empty, depending upongD – holds the required voltage. But as the FET inputs arenot perfect insulators, and there is current leakage otherwiseas well, the voltage level at the capacitor changes till it nolonger reliably holds the value of Q. The value of D needs tobe fed in at repeated intervals or ‘refreshed’, thus the word

Fig. 24: C2MOS Static D Latch Transistor Level Schematic

Fig. 25: C2MOS Static D Latch Physical Layout


Fig. 23: C2MOS Static D Latch Verilog Simulation

Fig. 26: C2MOS Static D Latch Layout SPICE Simulation

dynamic. Often, the capacitor is not expressly made but relieson the relatively low parasitic capacitance, making the repeatedrefreshing even more necessary.

Due to the compactness of the circuit, however, such latcheswere used extensively in RAM for computers until betterNAND type cells or static RAMs replaced them.

We wrote out the required Verilog for the circuit (Ap-pendix I), but were unable to simulate it. The reason turnedout to be that only a special kind of Verilog called Ver-ilogAMS™ can simulate the capacitance necessary for such asimulation.

The physical layout, on the other hand (Fig. 28) was easilysimulated by the BSIM4 engine in MicroWind, as can be seenin Fig. 29. Note the presence of the large metal layers: theseact as capacitor pads to complement the parasitic capacitance,hence improving the characteristics of the circuit.

The dimensions of the pads are,

3.85µm× 4.55µm = 17.52(µm)2

Using the surface capacitance parameters of the process spec-ifications,

CS,Metal1 = 28aF/(µm)2

CS,Metal2 = 25aF/(µm)2

We get the available capacitance as,

CAvailable = (28aF/(µm)2 + 25aF/(µm)2)

× 17.52(µm)2

' 930aF

Fig. 27: C2MOS Dynamic D Latch Transistor Level Schematic

Fig. 29: C2MOS Dynamic D Latch Layout SPICE Simulation

Thus, about 930aF of extra capacitance is available inaddition to the parasitic capacitance.

It can be seen that the voltage tends to veer away from thepreviously held value towards an AC average of 0.60V as timepasses. But as the value of Q is refreshed, the capacitor onceagain holds the value anew.

XII. CONCLUSION

CMOS latches were designed in a variety of ways, alwaysfollowing the standard VLSI top-down design methodology.The different designs had tradeoffs between performance, size,and glitch states. For gated designs, the smallest design in


Fig. 28: C2MOS Dynamic D Latch Physical Layout

terms of area was the bistable with controlled loading. Thefastest design with best signal transferrance characteristics wasthe AOI latch. The C2MOS latch characteristics were in themiddle.

APPENDIX ASYSTEMC CODE FOR A BASIC D LATCH

#include "systemc.h"

SC_MODULE(d_ff) {sc_in<bool> din;sc_out<bool> dout;

void doit() {dout = din;

};

SC_CTOR(d_ff) {SC_METHOD(doit);sensitive << din;

}};

SC_MODULE_EXPORT(d_ff);

* SystemC 2.1.1 --- Dec 20 2010 23:17:37* Copyright (c) 1996-2010 by all Contributors* ALL RIGHTS RESERVED

*Executing new

@5 ns :: Setting din -> dout SET 0@10 ns :: Unsetting din -> dout UNSET 1@15 ns :: Setting din -> dout SET 2@20 ns :: Unsetting din -> dout UNSET 3

*Terminating simulation

APPENDIX BDESIGN RULES FOR THE CMOS 90NM, 6 METAL COPPER

STRAINED SIGE LOWK PROCESS

NAME CMOS 90nm, 6 Metal Copper - strained SiGe- LowK

*lambda = 0.05 // Lambda is set to half the

gate sizemetalLayers = 6 // Number of metal layerslowK = 3.1 // inter-metal oxidesalicide = 1 // salicide optionedram = 1 // embedded DRAM processefram = 1 // embedded FRAM processmimcapa = 1 // enable mim capastrain = 1 // Strain material** Design rules associated to each layer** Wellr101 = 10 (well width)r102 = 11 (well spacing)*


* Diffusion N+, P+*r201 = 4 (diffusion width)r202 = 4 (diffusion spacing)r203 = 6 (border of nwell on diffp)r204 = 6 (nwell to next diffn)r210 = 16 (minimum diff surface lambda2)** Poly*r301 = 2 (poly width)r302 = 2 (gate length)r303 = 4 (high voltage gate length)r304 = 3 (poly spacing)r305 = 1 (spacing poly and unrelated diff)r306 = 4 (width of drain and source diff)r307 = 3 (extra gate poly)r310 = 16 (Minimum poly surface lambda2)** Contactr401 = 2 (contact width)r402 = 4 (contact spacing)r403 = 1 (metal border for contact)r404 = 1 (poly border for contact)r405 = 1 (diff border for contact)r406 = 2 (contact to gate)r407 = 1 (poly2 border for contact)* metalr501 = 3 (metal width)r502 = 4 (metal spacing)r510 = 16 (metal surface lambda2)* viar601 = 2 (Via width)r602 = 4 (Spacing)r604 = 1 (border of metal)r605 = 1 (border of metal2)* metal2r701 = 3 (Metal 2 width)r702 = 4 (spacing)r710 = 16 (Metal2 surface lambda2)

APPENDIX CBASIC D LATCH, CMOS VERILOG

module Q1130( D,Q,Qbar);input D;output Q,Qbar;wire w4,w5,w6;nmos nmos_1(Qbar,vss,Q); // 1.0u 0.12unmos nmos_2(Q,vss,Qbar); // 1.0u 0.12upmos pmos_3(w4,vdd,Q); // 2.0u 0.12upmos pmos_4(Q,w5,w6); // 2.0u 0.12upmos pmos_5(out2,w4,D); // 2.0u 0.12unmos nmos_6(Q,vss,w6); // 1.0u 0.12upmos pmos_7(w5,vdd,Qbar); // 2.0u 0.12unmos nmos_8(Qbar,vss,D); // 1.0u 0.12unot inv_9(w6,D);

endmodule

APPENDIX DGATED D LATCH WITH Enable CONTROL, GATE LEVEL

VERILOG

module Q1131( En,D,Q,Qbar);input En,D;output Q,Qbar;wire w4,w5,w6;and and2_1(w4,En,D);and and2_2(w6,w5,En);

not inv_3(w5,D);nor nor2_4(Q,Qbar,w6);nor nor2_5(Qbar,w4,Q);

endmodule

APPENDIX EGATED D LATCH WITH Enable CONTROL, CMOS VERILOG

module Q1132( D,En,Qbar,Q);input D,En;output Qbar,Q;wire w4,w5,w6,w8,w9;reg vdd=1;reg vss=0;nmos nmos_1(Qbar,vss,Q); // 1.0u 0.12unmos nmos_2(Q,vss,Qbar); // 1.0u 0.12upmos pmos_3(w4,vdd,Q); // 2.0u 0.12upmos pmos_4(Q,w5,w6); // 2.0u 0.12upmos pmos_5(Qbar,w4,D); // 2.0u 0.12unmos nmos_6(Q,w8,w6); // 1.0u 0.12upmos pmos_7(w5,vdd,Qbar); // 2.0u 0.12unmos nmos_8(Qbar,w9,D); // 1.0u 0.12upmos pmos_9(Q,w5,En); // 2.0u 0.12unot inv_10(w6,D);nmos nmos_11(w9,vss,En); // 1.0u 0.12unmos nmos_12(w8,vss,En); // 1.0u 0.12upmos pmos_13(Qbar,w4,En); // 2.0u 0.12u

endmodule

APPENDIX FBISTABLE CIRCUIT, CMOS VERILOG

module Q1134( A,Abar);input A;output Abar;reg vdd=1;reg vss=0;pmos pmos_1(Abar,vdd,A); // 2.0u 0.12unmos nmos_2(A,vss,Abar); // 1.0u 0.12unmos nmos_3(Abar,vss,A); // 1.0u 0.12upmos pmos_4(A,vdd,Abar); // 2.0u 0.12u

endmodule

APPENDIX GBISTABLE CIRCUIT WITH LOADING CONTROL, CMOS

VERILOG

module Q1134m( D,C,Qbar);input D,C;output Qbar;wire w2,w4,w5;reg vdd=1;reg vss=0;pmos pmos_1(Qbar,vdd,w2); // 2.0u 0.12unmos nmos_2(w5,w2,w4); // 1.0u 0.12unmos nmos_3(w5,vss,Qbar); // 1.0u 0.12unmos nmos_4(Qbar,vss,w2); // 1.0u 0.12upmos pmos_5(w5,vdd,Qbar); // 2.0u 0.12unot inv_6(w4,C);nmos nmos_7(w2,D,C); // 1.0u 0.12u

endmodule

APPENDIX HC2MOS STATIC D LATCH, CMOS VERILOG

module Q1138a( clk,D,Q);input clk,D;output Q;reg vdd=1;


reg vss=0;wire w3,w4,w5,w8,w9,w10;not inv_1(w3,clk);nmos #(3.1) nmos_2(w5,w4,w3); // 1.0u 0.12unmos #(1.0) nmos_3(w4,vss,D); // 1.0u 0.12upmos #(1.0) pmos_4(w8,vdd,D); // 2.0u 0.12upmos #(3.1) pmos_5(w5,w8,clk); // 2.0u 0.12unot inv_6(Q,w5);pmos #(1.0) pmos_7(w9,vdd,Q); // 2.0u 0.12unmos #(1.0) nmos_8(w10,vss,Q); // 1.0u 0.12upmos #(3.1) pmos_9(w5,w9,w3); // 2.0u 0.12unmos #(3.1) nmos_10(w5,w10,clk); //1.0u 0.12u

endmodule

APPENDIX IC2MOS DYNAMIC D LATCH, CMOS VERILOG

module Q1138b(D,clk,Q);input D,clk;output Q;wire w2,w3,w7,w8,w9,w10;reg vdd=1;reg vss=0;nmos #(10) nmos_1(w3,vss,w2); // 1.0u 0.12unmos #(17) nmos_2(Q,w3,clk); // 1.0u 0.12unot #(17) inv_3(w7,clk);pmos #(10) pmos_4(w8,vdd,w2); // 2.0u 0.12upmos #(17) pmos_5(Q,w8,w7); // 2.0u 0.12unmos #(31) nmos_6(w2,w9,w7); // 1.0u 0.12upmos #(10) pmos_7(w10,vdd,D); // 2.0u 0.12unmos #(10) nmos_8(w9,vss,D); // 1.0u 0.12upmos #(31) pmos_9(w2,w10,clk); // 2.0u 0.12ucapa #(1) Capa_10(vss,w2); // 1pF

endmodule

ACKNOWLEDGMENT

The authors would like to thank their teachers, instructorsand TAs without whom this work would neither have beenrequired, nor completed. In particular, they would like to thankDr. Bazaz for an invigorating introduction to the world ofVLSI design, and Mr. Kashif Riaz for being his invaluableaide.

REFERENCES

[1] J. P. Uyemura, Introduction to VLSI Circuits and Systems. GeorgiaInstiute of Technology, USA: Wiley, Inc., 2002.

[2] (2010, Dec) [internal giki subsite only] ee424: List of assignedterm projects. GIK Institute, Topi, Pakistan. [Online]. Available:http://192.168.1.32/file.php/13/Term_Projects_ASIC_Design_.pdf

[3] Electronic design. Hayden Pub. Co., 1988, no. v. 36, nos. 23-29. [On-line]. Available: http://books.google.com/books?id=oM4EAQAAIAAJ

[4] (2010, Dec) Microwind - about us. Department of Electricaland Computer Engineering, INSA, Toulouse. [Online]. Available:http://www.microwind.net/about_us.php

[5] (2010, Dec) Bsim homepage - introduction. Universityof California, Berkeley. [Online]. Available: http://www-device.eecs.berkeley.edu/∼bsim3/bsim4_intro.html

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ASIC Design: CMOS Logic Latches