Asic Design Flow%5B1%5D

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CHAPTER TWO

ASIC Design Flow

Application-specific integrated circuit (ASIC) design is based on a designflow that uses hardware description language (HDL). Most electronic designautomation (EDA) tools used for ASIC flow are compatible with both Verilogand very high speed integrated circuit hardware description language (VHDL).

In this flow, the design and implementation of a logic circuit are coded ineither Verilog or VHDL. Simulation is performed to check its functionality.This is followed by synthesis. Synthesis is a process of converting HDL to logicgates. After synthesis, the next step is APR (auto-place-route). APR is ex-plained in more detail in Section 2.6.

Figure 2.1 shows a diagram of an ASIC design flow, beginning with specifi-cation of an ASIC design to register transfer level (RTL) coding and, finally,to tapeout.

2.1 SPECIFICATION

Figure 2.2 indicates the beginning of the ASIC flow: the specification of adesign. This is Step 1 of an ASIC design flow. The design of an ASIC chipbegins here.

Specification is the most important portion of an ASIC design flow. In thisstep, the features and functionalities of an ASIC chip are defined. Chipplanning is also performed in this step.

During this process, architecture and microarchitecture are derived fromthe required features and functionalities. This derivation is especially impor-

3

Verilog Coding for Logic Synthesis, edited by Weng Fook LeeISBN 0-471-429767 Copyright 2003 by John Wiley and Sons, Inc.


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4 ASIC DESIGN FLOW

SpecificationRTL codingTest bench

Simulation

PassNo

Synthesis

Standard celltechnologylibrary

Yes

Timingconstraints

Pre-layout

timing analysispass?

APRNo Yes

Tapeout

Pre-layout

synthesistweaks

Back

annotation

Post-layouttiming analysispass?

Yes

Post-layoutsynthesistweaksand synthesis

Logicverificationpass?

Yes

No

No

FIGURE 2.1. Diagram showing an ASIC design flow. Sections 2.1 to 2.9 explain eachsection of the ASIC flow in detail.

STEP 1

SpecificationRTL CodingTest bench

Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layouttiming analysispass?

APRNo Yes

Tapeout

Pre-layoutsynthesistweaks

Backannotation


Yes


No

LogicVerificationPass?

Yes

No

FIGURE 2.2. Diagram indicating Step 1 of an ASIC design flow: specification.


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tant, as the architecture of a design plays an important role in determining theperformance capabilities and silicon area utilization.Figure 2.3 shows the process involved in defining the architecture and

microarchitecture of a design. Specification contains a list of all features andfunctionalities required in the design. These include power consumption,voltage references, timing restrictions, and performance criteria. From this list,the chip architecture can be drafted. This defined architecture must take intoconsideration all required timing, voltage, and speed/performance of thedesign. Architectural simulations need to be performed on the drafted archi-tecture to ensure that it meets the required specification.

During architecture simulations, the architectural definition will have to be

changed if the simulation result shows it cannot meet any requirements in thespecification. When all the requirements are met, this architecture is said tomeet the required specifications. From here, a microarchitecture is drafted anddefined to allow execution of the architecture from a design standpoint.

The microarchitecture is the key point that enables the design phase.A microarchitecture interfaces the designs architecture and circuit. It alsoallows transformation of an architectural concept into possible designimplementation.

2.2 RTL CODING

Figure 2.4 shows Step 2 of the ASIC design flow. This is the beginning of thedesign phase. The microarchitecture is transformed into a design by convert-ing it into RTL code.

As shown in Section 2.1 (Step 1 of the ASIC design flow), architecture andmicroarchitecture are derived from specification. In Step 2, the micro-architecture, which is the implementation of the design, is coded in synthe-sizable RTL.

RTL CODING 5

Specification

Architecturedefinition

Microarchitecturedefinition

Architecturalsimulation

Simulationpass

YesNo

FIGURE 2.3. Diagram showing the definition of architecture and microarchitecture.


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There are several ways to obtain the RTL code. Some designers use graphi-cal entry tools like Summit Designs Visual HDL or Mentor Graphics HDLDesigner. These graphical entry tools allow designers to use bubble diagrams,flow charts, or truth table to implement the microarchitecture, which subse-

quently generate the RTL code either in Verilog or VHDL. However, somedesigners prefer writing the RTL code rather than using a graphical entry tool.Both approaches end in the same result: synthesizable RTL code thatdescribes logic functionality of the specification.

2.2.1 Types of Verilog Code: RTL, Behavioral, and Structural

Section 2.2 discusses RTL coding. In Verilog language, there are threetypes of Verilog code. For most cases of synthesis, synthesizable RTL code isused. Table 2.1 lists the differences and usage of each of the types of Verilogcode.

2.3 TEST BENCH AND SIMULATION

Figure 2.5 shows Step 3 in the ASIC design flow, which involves creation oftest benches. These are used to simulate the RTL code.

A test bench is basically a wraparound environment surrounding a design,which enables the design to be simulated. It injects a specified set of stimulus

6 ASIC DESIGN FLOW

STEP 2


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout


APRNo Yes

Tapeout


Backannotation

Post-layout


Yes


No


Yes

No

FIGURE 2.4. Diagram indicating Step 2 of an ASIC design flow: RTL coding.


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TEST BENCH AND SIMULATION 7

TABLE 2.1. The three types of Verilog code

RTL Behavioral Structural

RTL coding, or register Behavioral coding is Structural Verilog codingtransfer level, is most used to describe a black has a data type structure

commonly used to describe box design whereby the that defines thethe functionality of a output of the design is different components anddesign for synthesis. It specified for a certain their interconnectsis also descriptive in input pattern. Behavioral present in a design. Itnature, similar to code mimics the represents a netlist of abehavioral Verilog. functionality and design. StructuralHowever, it only uses a behavior of the black Verilog is normally usedsubset of Verilog syntax, box design. It is when passing netlistas not all Verilog syntax normally used for system- information of a designis synthesizable. RTL level testing. between design tools. Forcoding can be viewed as example, upon completionmore descriptive than of synthesis, the netlist

structural Verilog but of a design is passed toless descriptive compared APR (refer to Section 2.6with behavioral Verilog. for explanation of APR)

using structural Verilog.

module RTL (inputA, inputB,inputC, inputD, outputA);

input inputA, inputB, inputC,inputD;

output outputA;

reg outputA;always @ (inputA or inputBor inputC or inputD)begin

if (inputA & inputB& ~inputD)outputA = inputC;

else if (inputA &inputD & ~inputC)outputA = inputB;

elseoutputA = 0;

end

endmodule

module behavior (inputA,inputB, inputC, inputD,outputA);

input inputA, inputB,inputC, inputD;

output outputA;

reg outputA;always @ (inputA or inputBor inputC or inputD)begin

if (inputA & inputB &~inputD)outputA = #5inputC;

else if (inputA &inputD & ~inputC)outputA = #3inputB;

else if ((inputA ==1'bx) | (inputB ==

1'bx) | (inputC ==1'bx) | (inputD ==1'bz))outputA = #7 1'bx;

else if ((inputA ==1'bz) | (inputB ==1'bZ))outputA = #7 1'bZ;

elseoutputA = #3 0;

end

endmodule

module structural (inputA,inputB, inputC, inputD,outputA);

input inputA, inputB,inputC, inputD;

output outputA;

wire n30;AN3 U8 ( .A(inputA),.B(n30), .C(inputB),.Z(outputA) );

EO U9 ( .A(inputD),.B(inputC), .Z(n30) );

endmodule


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into the inputs of the design, check/view the output of the design to ensurethe designs output patterns/waveforms match designers expectations.

RTL code and the test bench are simulated using HDL simulators. If theRTL code is written in Verilog, a Verilog simulator is required. If the RTL codeis written in VHDL, a VHDL simulator is required. Cadences Verilog XL,

8 ASIC DESIGN FLOW

Referring to the Verilog code shown, when simulated or synthesized, both the RTLand structural Verilog will yield the same functionality. Behavioral Verilog, however,

is not synthesizable.

Synthesized logic for RTL Verilog and structural Verilog

inputA

inputD

inputC

inputB

EO AN3

STEP 3


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layouttiming analysispass?

APRNo Yes

Tapeout


Backannotation


Yes


No


Yes

No

FIGURE 2.5. Diagram indicating Step 3 of an ASIC design flow: test bench andsimulation.

TABLE 2.1. (Continued)

RTL Behavioral Structural


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Synopsyss VCS, and Mentor Graphics Modelsim are among some of theVerilog simulators used. Cadences NCSim and Mentor Graphics Modelsimare capable of simulating both Verilog and VHDL. Synopsyss Scirocco is anexample of a VHDL simulator. Apart from these simulators, there are manyother VHDL and Verilog simulators. Whichever simulator is used, the endresult is the verification of the RTL code of the design based on the test benchthat is written.

If the designer finds the output patterns/waveforms during simulation donot match what he or she expects, the design needs to be debugged. A non-matching design output can be caused by a faulty test bench or a bug in theRTL code. The designer needs to identify and fix the error by fixing the testbench (if the test bench is faulty) or making changes to the RTL code (if theerror is caused by a bug in the RTL code).

Upon completion of the change, the designer will rerun the simulation.This is iterated in a loop until the designer is satisfied with the simulation

results. This means that the RTL code correctly describes the required logicalbehavior of the design.

2.4 SYNTHESIS

Figure 2.6 shows Step 4 of the ASIC design flow, which is synthesis. In thisstep, the RTL code is synthesized. This is a process whereby the RTL code isconverted into logic gates.The logic gates synthesized will have the same logicfunctionality as described in the RTL code.

SYNTHESIS 9

STEP 4


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout

timing analysis

pass?

APRNo Yes

Tapeout


Backannotation

Post-layout

timing analysis

pass?

Yes

Post-layoutsynthesistweaks

and synthesis

No


Yes

No

FIGURE 2.6. Diagram indicating Step 4 of an ASIC design flow: synthesis.


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In Step 4, a synthesis tool is required to convert the RTL code to logic gates.More common tools used in the ASIC industry include Synopsyss DesignCompiler and Cadences Ambit.

The synthesis process requires two other input files to make the conversionfrom RTL to logic gates. The first input file that the synthesis tool must havebefore making the conversion is the technology library file. It is a library filethat contains standard cells. During the synthesis process, the logic function-ality of the RTL code is converted to logic gates using the available standardcells in the technology library. The second input file, constraints file, helps todetermine the optimization of the logic being synthesized. This file normallyconsists of information like timing and loading requirements and optimizationalgorithms that the synthesis tool needs to optimize the logic, and even pos-sibly design rule requirements that need to be considered during synthesis.

Step 4 is a very important step in the ASIC design flow. This step ensuresthat synthesis tweaks are performed to obtain the most optimal results

possible, should the design not meet the specified performance or area.If, upon final optimization, the required performance or area utilization isstill not within acceptable boundaries, the designer must reconsider themicroarchitecture as well as architectural definitions of the design. Thedesigner must re-evaluate to ensure the specified architecture and microar-chitecture can meet the required performance and area. If the requirementscannot be met with the current architecture or microarchitecture, the designerwill have to consider changing the definition of the architecture or microar-chitecture. This is undesirable, as changing the architecture or microarchitec-ture can potentially bring the design phase back to the early stages of Step 1of the ASIC design flow (specification). If by changing the architecture and

microarchitecture definition the design is still unable to provide the kind ofperformance or area utilization required, the designer must resort to thepossibility of changing the specification itself.

2.5 PRE-LAYOUT TIMING ANALYSIS

When synthesis is completed in Step 4, the synthesized database along withthe timing information from Step 4 is used to perform a static timing analysis(Step 5). In Step 5, timing analysis is pre-layout, because the database iswithout any layout information (Fig. 2.7).

A timing model is built and its timing analysis is performed on the design.Normally, the timing analysis is performed across all corners with differentvoltages and temperatures. This is to catch any possible timing violations inthe design when used across specified temperature and voltage range.

Any timing violation caught, for example, setup and hold time violations,will have to be fixed by the designer. The most common way of fixing thesetiming violations is to create synthesis tweaks to fix those paths that are failingtiming.

10 ASIC DESIGN FLOW


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A common fix for hold violation is to add delay cells into the path that isfailing hold time check. A common fix for setup violation is to reduce theoverall delay of the path that failed the setup timing check.

These synthesis tweaks are used to resynthesize the design. Another

pre-layout timing analysis is performed.Step 5 in the ASIC flow sometimes varies depending on the design project.

Some design projects will proceed to Step 6, although having timing failuresin pre-layout timing analysis. The reason for this is because it is pre-layouttiming analysis. The interconnect parasitics that are used for timing analysisare estimations and may not be accurate.

A more common method used in Step 5 is to fix timing failures that areabove certain values. The designer can set a value ofx nanoseconds allowedtiming violation.The path that fails more thanx nanoseconds is fixed.The paththat fails less thanx nanoseconds is not fixed. Again, this can be attributed tothe fact that the parasitics used in the timing analysis are not accurate, because

no back annotated information is used during this step (pre-layout timinganalysis).

2.6 APR

Once pre-layout timing analysis of the synthesized database is completed, thesynthesized database together with the timing information from synthesis is

APR 11

STEP 5


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout


APR

No Yes

Tapeout

Pre-layout

synthesistweaks

Back

annotation


Yes


No


Yes

No

FIGURE 2.7. Diagram indicating Step 5 of an ASIC design flow: pre-layout timinganalysis.


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used for APR (Fig. 2.8). In this step, synthesized logic gates are placed androuted. The process of this placement and routing has some degree of flexi-bility whereby the designer can place the logic gates of each submoduleaccording to a predefined floor plan.

Most designs have critical paths that are tight in terms of timing. Thesepaths can be specified by the designer as high-priority paths. The APR toolwill route these high-priority paths first before routing other paths to allowfor the most optimal routing.

APR is also the step involved in clock tree synthesis. Most APR tools canhandle routing of clock tree with built-in special algorithms. This is an espe-cially important portion of the APR flow because it is critical that the clocktree be routed correctly with an acceptable clock skew. Most APR toolsallow a designer to specify a required clock skew and buffers up each branchon the clock tree to the desired clock skew.

2.7 BACK ANNOTATION

Back annotation is the step in the ASIC design flow where the RC parasiticsin layout is extracted (Fig. 2.9). The path delay is calculated from these RCparasitics. For deep submicron design, these parasitics can cause a significantincrease in path delay. Long routing lines can significantly increase the inter-connect delay for a path. This could potentially cause paths that are previously

12 ASIC DESIGN FLOW

STEP 6


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout


APRNo Yes

Tapeout


Backannotation

Post-layout


Yes


No


Yes

No

FIGURE 2.8. Diagram indicating Step 6 of an ASIC design flow: APR.


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(in pre-layout) not critical in timing to be timing critical. It could also causepaths that are meeting the timing requirements to now become critical pathsthat no longer meet the timing requirements.

Back annotation is an important step that bridges the differences between

synthesis and physical layout. During synthesis, design constraints are usedby the synthesis tool to generate the logic that is required. However, thesedesign constraints are only an estimation of constraints that apply to eachmodule. The real physical constraints caused by the RC parasitics may ormay not reflect the estimated constraints accurately. More likely than not,the estimations are not accurate. As a result, these will cause differencesbetween synthesis and physical layout. Back annotation is the step that bridgesthem.

2.8 POST-LAYOUT TIMING ANALYSIS

Post-layout timing analysis is an important step in ASIC design flow thatallows real timing violations such as hold and setup, to be caught (Fig. 2.10).This step is similar to pre-layout timing analysis, but it includes physical layoutinformation.

In this step, the net interconnect delay information from back annotationis fed into a timing analysis tool to perform post-layout timing analysis. Anysetup violations need to be fixed by optimizing the paths that fail the setup

POST-LAYOUT TIMING ANALYSIS 13

STEP 7


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout


APRNo Yes

Tapeout


Backannotation

Post-layout


Yes


No


Yes

No

FIGURE 2.9. Diagram indicating Step 7 of an ASIC design flow: back annotation.


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violations to reduce the path delay. Any hold violation is fixed by addingbuffers to the path to increase the path delay.

Post-layout synthesis tweaks are used to make these timing fixes duringresynthesis. This allows logic optimization of those failing paths.

When post-layout synthesis is completed,APR, back annotation, and timinganalysis are performed again. This will occur in a loop until all the timingviolations are fixed. When there are no longer timing violations in the layoutdatabase, the design is ready for logic verification.

Note: Post-layout timing analysis is the same as pre-layout timing analysis,

except that in post-layout timing analysis, accurate net delay information from

physical layout (net delay information for the design is obtained from the

extracted layout parasitics) is used. In pre-layout timing analysis, net delay infor-

mation is estimated.

2.9 LOGIC VERIFICATION

When post-layout timing analysis is completed, the next step is logic verifica-tion (Fig. 2.11). This step acts as a final sanity check to ensure the design hasthe correct functionality. In this step, the design is resimulated using the exist-ing test benches used in Step 3 but with additional timing information obtainedfrom layout.

14 ASIC DESIGN FLOW

STEP 8


Simulation

PassNo

Synthesis


Yes

Timingconstraints

Pre-layout


APRNo Yes

Tapeout


Backannotation

Post-layout


Yes


No


Yes

No

FIGURE 2.10. Diagram indicating Step 8 of an ASIC design flow: post-layout timinganalysis.


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Although the design has been verified in Step 3, the design may have fail-ures in Step 9. The failures may be caused by timing glitches or race condi-tions due to layout parastics. If there are failures, the designer has to fix thesefailures by either moving back to Step 2 (RTL coding) or Step 8 (post-layout

synthesis tweaks).When the design has finally passed logic verification, it proceeds to tapeout.

LOGIC VERIFICATION 15


Simulation

PassNo

Synthesis

Yes

APR

No Yes

Tapeout

Yes

No

Yes

NoSTEP 9



Back

annotation

Timingconstraints

Pre-layout


Pre-layout

synthesistweaks



FIGURE 2.11. Diagram indicating Step 9 of an ASIC design flow: logic verification.

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