ASIC Methodology. Venkat Kodavati Director of Engineering [email protected]

ASIC Methodology.ASIC Methodology.

Venkat KodavatiDirector of Engineering

[email protected]

Naksha Technologies Inc. (Confidential)Naksha Technologies Inc. (Confidential)

PhilosophyPhilosophy

All that matters is shipping the product It’s all about re-use

re-use of software re-use of IP cores re-use of design flows re-use of verification infrastructure re-use of DVT tools re-use of implementation flows


Philosophy (cont.)Philosophy (cont.)

The key to efficient design is not related to specific choices of CAD tools

It’s much more an issue of mindset

Methodology, organization, and architecture go hand in hand

Delicate balance between stability of the tried and tested and evolutionary improvement


How we thinkHow we think

Learn from experience If you have a better idea, validate it, then use it

everywhere Don’t change things for the sake of it

There are always unexpected consequences Be very careful to asses the impact of s/w visible

changes Improve the process

Make it easier for next time Simplify Automate

Everything is iterative, so put the time into the automation

Repeatable, predictable Fix things up front Consistency

templates chip level block level (shared over projects)

naming conventions


How we think (cont.)How we think (cont.)

Parallelism Ability to work on all stages of the process

simultaneously Early look

Avoid surprises later in the flow Shorten the critical path

A typical tapeout here happens 1 - 2 weeks after the final RTL or netlist change


Vital infrastructureVital infrastructure

Strong source control Reproducibility Traceability Everything under source control Easy to use Scaleable

Compute Servers LSF system 64 bit servers

Bug tracking Absolutely critical to managing the process Use the database for everything

Real bugs Possible bugs New feature requirements


Core Reuse MethodologyCore Reuse Methodology

Common Design blocks: A distributed DMA model:

Encapsulate HW and SW in a block independent of system environment.

Same driver works whether block is on the internal system bus or the an external (PCI) bus. Includes some internal buffering (one or two packets) to

reduce system level latency issues. Bus Master & slave :

AXI, AHB, APB protocols Extremely light weight Parameterizable for Size Unified application interface

RISC processor Standarad MIPS instruction set Simple Instruction and Data memory To Realize complex control sequences

Standardized support for BIST control/status Clock control Core enable/disable


RTL Level AutomationRTL Level Automation

AutoReg HW CSR modules C header files TCL defs Documentation

BIST Insertion Hierarchal Controllers Fuse Box Interfaces Memory re-organization for BIST


DESIGNDESIGN

Micro-Architecture and Design for Optimal Performance Low Power – Clock Gating, Power Islands High Performance – Pipelined, Superscalar Smaller Area – Circuit Re-use

Detailed Design Documentation Follow Standard practices Home grown flexible rules based sanity Auto

Checker. Coding guidelines Lint, Naming Conventions Synthesizability, Clock Gating, DFT

Design with embedded Assertions High Level Languages as needed

C-based Modeling System Verilog Verilog, VHDL


Core versus chip partitioningCore versus chip partitioning

We separate the creation of new IP (e.g. gmac) from the building of chips

Process of continuous improvement at the core level Major changes co-ordinate with chip tapeouts Software team fully participate in architectural

decisions Chip assembly very predictable and streamlined


Chip constructionChip construction Backplane configuration file

Signal Group Creation Module definition file

IO definition file Pad defintion Pinmux specification Multiple Package support Tap controller & Boundary Scan Insertion

Core parameters file Cores have configurable functionality

Top level definition file Chip version IDs Exceptions JTAG register contents Naming exceptions for hard macros


Automation !! Automation !!!Automation !! Automation !!!

Extensive use of Makefiles & Perl Makefiles and Perl scripts to automate every stage

The Repository SVN Version control, ease of remote use &

maintenance Gobal repository of precompiled database

Chip Generators Chipgen: IPXACT based chip toplevel generator Busgen: XML based system backplane generator Padsgen: XLS based chip padring generator Scripts automate Straps, Pinmuxing, Scan support


Chipgen™Chipgen™

IPXACT Based Chip toplevel generator Module specific IPXACT description to specify

ports/interfaces System Level IPXACT description to specify

interconnections Standardized way of describing modules and

system Generated Verilog/VHDL chip toplevel

USAGE:

Chipgen.pl –verilog –chipname <chip_toplevel> -ipxact <system_ipxact> -ipxact <core_ipxact>…


Chipgen™ Cont…Chipgen™ Cont…

IPXACT Example

<spirit:componentInstance> <spirit:instanceName>emac</spirit:instanceName> <spirit:componentRef spirit:vendor=“Naksha" spirit:library="core" spirit:name=“emac"> <spirit:configuration> <spirit:configurableElement spirit:referenceId="NUM_INTERRUPTS"> <spirit:configurableElementValue>8</spirit:configurableElementValue> </spirit:configurableElement> </spirit:configuration> </spirit:componentInstance>

<spirit:interconnection> <spirit:name>emac</spirit:name> <spirit:activeInterface spirit:componentRef=“emac" spirit:busRef="ahbm0"/> <spirit:activeInterface spirit:componentRef=“ahbbus" spirit:busRef=“emac_ahbSlave"/> </spirit:interconnection>


Busgen™Busgen™

XML Based System Backplane Generator Generates AHB 2.0 based Verilog/VHDL XML Conf file to specify Masters/Slaves Crossbar configuration to ease timing Slave interfaces specify select addresses Master interfaces specify Mux controls Ability to specify additional ports

USAGE:

Busgen.pl –conf <conf_file> -busname <busname> -verilog


Busgen™ Contd..Busgen™ Contd..

Busgen.conf

<BUS_DEF> <BUS_NAME>cbus</BUS_NAME> <ARBITER> <MUX_SEL ref_name="MCTRL" sig_name="arb2cbus_hmaster"/> <MUX_SEL ref_name="MDATA" sig_name="arb2cbus_hmaster_r"/> </ARBITER> <ADD_PORTS> <PORT dir="input" name="sys_clk" width="1"/> <PORT dir="input" name="sys_reset_n" width="1"/></ADD_PORTS> <BUSIF_DEF> <SLAVE_AHBDEF> <PORT dir="input" name="hready" from="" mux_sel="" width="1"/> <PORT dir="output" name="hwdata" from="MMUX" mux_sel="MDATA" width="WIDTH"/> <<<<<>>>>> </SLAVE_AHBDEF> <MASTER_AHBDEF> <PORT dir="output" name="hresp" from="SMUX" mux_sel="MADDR" width="2"/> <PORT dir="output" name="hrdata" from="SMUX" mux_sel="MADDR" width="WIDTH"/> <<<<<>>>>> </MASTER_AHBDEF> </BUSIF_DEF>


Busgen™ Contd..Busgen™ Contd..

<MASTERS>

<MASTER> <NAME>EMAC1</NAME> <IN_PREFIX>emac12cbus</IN_PREFIX> <OUT_PREFIX>cbus2emac1</OUT_PREFIX> <CONTROL>4'b0000</CONTROL> </MASTER></MASTERS>

<SLAVES> <SLAVE> <NAME>EMAC1</NAME> <IN_PREFIX>emac12cbus</IN_PREFIX> <OUT_PREFIX>cbus2emac1</OUT_PREFIX> <SEL_ADDR>16'h1920</SEL_ADDR> </SLAVE></SLAVES>


Padsgen™Padsgen™

XLS Based padring generator Operates on tab delimited text files Generates Verilog padring module Automates Boundary Scan Stiching, BSDL

Generation Columns specify pin muxing, test specific muxing Ability to turnoff Boundary scan for

Analog/MixedSignal blocks Package specific support to tie off un-used pins


Structured approachesStructured approaches

Test SCAN BIST JTAG Now adding logic BIST

Clocking Distribution Gating

Reset Synchronizers No tri-states on chip


One Testbench™ Simulation One Testbench™ Simulation StrategyStrategy

RTL is ill-suited to test generation and checking Testbench instantiates just the DUT and Verification

Models Special purpose Testbenches are wasteful Use Generic Testbench with very few modifications Testbench neither creates stimulus nor checks results Directed tests generated by perl scripts or by hand Simulator independent constructs to ease of portability Flash, DRAM, USB host/device, PCI master/slave, etc. Use 3rd-party models where available Stimulated and recorded by C language models through

PLI/FLI Transactions use standard protocols (PCI, SDIO) Portability to emulator and bringup lab


One TestGenerator™One TestGenerator™

Single PERL based test generator Single test generator for all Chips/Cores Ability to specify run time Chip/Core specific arguments Can run existing canned tests Ability to generate constrained random tests Ability to run multiple tests simultaneously Takes run time arguments to specify load sharing

queues Can run in regress mode to keep track of results Ability to generate test reports for regressions Selectively turns on coverage option and generates

reports Can also be used to run gatelevel simulations with SDF Ability to invoke C/TCL based post processors One Script does All !!!


One TestGenerator™ Contd…One TestGenerator™ Contd…

Usage:Testgen.pl -chip <chip_name>

-queue <lsf_queue> -test <test_range>

-seed <initial_seed> -trace <trace_name>

-email <email_id> -<simulator_name> -save -regress

-coverage


Test MethodologyTest Methodology

The Test Plan Random & Constrained random test generators Directed tests to cover corner cases Wacky & Evil tests aimed at design abuse Port all core level tests to system level System level tests to measure

throughput/performance Additional System level bandwidth starvation

tests Protocol checkers to catch runtime errors Compliance suits to guaranty spec compliance Assertions for functional coverage Catch all Bugs !!!


Advanced Tools and LanguagesAdvanced Tools and Languages

Evaluate and use State of art Tools Assertion Based Verification Static and Dynamic checkers Extensive use of Formal tools Clock Domain crossing checkers Linting and policy checkers

Languages System Verilog TCL for Tool Automation PERL/C for Generators & Checkers


FPGA Based VerificationFPGA Based Verification

State of the art FPGA Software Development Platforms

Lower cost solution for smaller volumes Used to evaluate and quantify design trade offs for our

IP Used to get first cut throughput performance numbers Complete Functional coverage at speed Software development and Verification ahead of time

Emulation Axis, Palladium HW & Software Co-verification Mostly TCL based priliminary Software Drivers Ability to run same tests as in Simulation


Backend AutomationBackend Automation

Automated SDC generation Boundary scan/pinmux cell placement Spare cell Insertion Clock gate Insertion Automated CTS scripts for low/useful skew Package co-ordinate extraction


Simplify the backendSimplify the backend

Predictable timing Naming conventions in the padring and top level Formal structure for handoffs

synthesized netlists constraints patches extracted timing

With good automation in place re-running P&R to fit a new floorplan is not a big deal

Think ahead We may be designing this for 90nm today but we can

be certain we’ll want it later in 65nm, 40nm . . .


Our EDA ToolsOur EDA Tools

State of the Art tools Modelsim Finsim Debussy Cadence RC Cadence FE 5.2 Voltage Storm Celtic and PT-SI Tetramax ATPG

Documents

ASIC Methodology. Venkat Kodavati Director of Engineering [email protected]