Atmel-42397-8-bit-AVR-Microcontroller …...– Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change •

8-bit AVR Microcontroller

ATmega328PB

DATASHEET PRELIMINARY

IntroductionThe Atmel® ATmega328PB is a low-power CMOS 8-bit microcontroller basedon the AVR® enhanced RISC architecture. By executing powerfulinstructions in a single clock cycle, the ATmega328PB achieves throughputsclose to 1MIPS per MHz. This empowers system designer to optimize thedevice for power consumption versus processing speed.

FeatureHigh Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family

• Advanced RISC Architecture– 131 Powerful Instructions– Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 20 MIPS Throughput at 20MHz– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments– 32KBytes of In-System Self-Programmable Flash program

memory– 1KBytes EEPROM– 2KBytes Internal SRAM– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM– Data retention: 20 years at 85°C/100 years at 25°C(1)– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program• True Read-While-Write Operation

– Programming Lock for Software Security• Peripheral Touch Controller

– Capacitive touch buttons, sliders and wheels– 24 Self-cap channels and 144 mutual cap channels

• Peripheral Features– Two 8-bit Timer/Counters with Separate Prescaler and Compare

Mode

Atmel- 42397A-8-bit AVR Microcontroller_Datasheet_Preliminary-07/2015

– Three 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode– Real Time Counter with Separate Oscillator– Ten PWM Channels– 8-channel 10-bit ADC in TQFP and QFN/MLF package– Two Programmable Serial USART– Two Master/Slave SPI Serial Interface– Two Byte-oriented 2-wire Serial Interface (Philips I2C compatible)– Programmable Watchdog Timer with Separate On-chip Oscillator– On-chip Analog Comparator– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features– Power-on Reset and Programmable Brown-out Detection– Internal Calibrated Oscillator– External and Internal Interrupt Sources– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and

Extended Standby• I/O and Packages

– 27 Programmable I/O Lines– 32-pin TQFP and 32-pin QFN/MLF

• Operating Voltage:– 1.8 - 5.5V

• Temperature Range:– -40°C to 85°C

• Speed Grade:– 0 - 4MHz @ 1.8 - 5.5V– 0 - 10MHz @ 2.7 - 5.5.V– 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1MHz, 1.8V, 25°C– Active Mode: 0.2mA1

– Power-down Mode: 0.1μA1

– Power-save Mode: 0.75μA (Including 32kHz RTC)1Note:

1. This value corresponds to ATmega328. This value might increase for ATmega328PBdue to feature additions. Exact value will be updated after silicon characterization.

Atmel ATmega328PB [DATASHEET]Atmel- 42397A-8-bit AVR Microcontroller_Datasheet_Preliminary-07/2015

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Table of Contents

Introduction......................................................................................................................1

Feature............................................................................................................................ 1

1. Description.................................................................................................................9

2. Configuration Summary...........................................................................................10

3. Ordering Information................................................................................................ 11

4. Block Diagram......................................................................................................... 12

5. Pin Configurations................................................................................................... 135.1. Pin Descriptions..........................................................................................................................13

6. I/O Multiplexing........................................................................................................15

7. Resources................................................................................................................16

8. Data Retention.........................................................................................................17

9. About Code Examples.............................................................................................18

10. Capacitive Touch Sensing....................................................................................... 1910.1. QTouch Library........................................................................................................................... 1910.2. Peripheral Touch Controller........................................................................................................19

11. AVR CPU Core........................................................................................................ 2011.1. Overview.....................................................................................................................................2011.2. ALU – Arithmetic Logic Unit........................................................................................................2111.3. Status Register...........................................................................................................................2111.4. General Purpose Register File................................................................................................... 2311.5. Stack Pointer.............................................................................................................................. 2411.6. Instruction Execution Timing...................................................................................................... 2511.7. Reset and Interrupt Handling..................................................................................................... 25

12. AVR Memories.........................................................................................................2812.1. Overview.....................................................................................................................................2812.2. In-System Reprogrammable Flash Program Memory................................................................2812.3. SRAM Data Memory...................................................................................................................2912.4. EEPROM Data Memory............................................................................................................. 3012.5. I/O Memory.................................................................................................................................3112.6. Register Description................................................................................................................... 32

13. System Clock and Clock Options............................................................................ 4313.1. Clock Systems and Their Distribution.........................................................................................4313.2. Clock Sources............................................................................................................................ 44

13.3. Low Power Crystal Oscillator......................................................................................................4513.4. Full Swing Crystal Oscillator.......................................................................................................4713.5. Low Frequency Crystal Oscillator...............................................................................................4813.6. Calibrated Internal RC Oscillator................................................................................................4913.7. 128kHz Internal Oscillator.......................................................................................................... 5013.8. External Clock............................................................................................................................ 5113.9. Clock Output Buffer.................................................................................................................... 5213.10. Timer/Counter Oscillator............................................................................................................ 5213.11. System Clock Prescaler............................................................................................................. 5213.12. Register Description...................................................................................................................53

14. CFD - Clock Failure Detection mechanism............................................................. 5714.1. Overview.....................................................................................................................................5714.2. Features..................................................................................................................................... 5714.3. Operations..................................................................................................................................5714.4. Timing Diagram.......................................................................................................................... 5814.5. Register Description................................................................................................................... 59

15. PM - Power Management and Sleep Modes...........................................................6115.1. Sleep Modes...............................................................................................................................6115.2. BOD Disable...............................................................................................................................6215.3. Idle Mode....................................................................................................................................6215.4. ADC Noise Reduction Mode.......................................................................................................6215.5. Power-Down Mode.....................................................................................................................6315.6. Power-save Mode.......................................................................................................................6315.7. Standby Mode............................................................................................................................ 6415.8. Extended Standby Mode............................................................................................................ 6415.9. Power Reduction Register..........................................................................................................6415.10. Minimizing Power Consumption.................................................................................................6415.11. Register Description................................................................................................................... 65

16. SCRST - System Control and Reset....................................................................... 7216.1. Resetting the AVR...................................................................................................................... 7216.2. Reset Sources............................................................................................................................7216.3. Power-on Reset..........................................................................................................................7316.4. External Reset............................................................................................................................7416.5. Brown-out Detection...................................................................................................................7416.6. Watchdog System Reset............................................................................................................ 7516.7. Internal Voltage Reference.........................................................................................................7516.8. Watchdog Timer......................................................................................................................... 7616.9. Register Description................................................................................................................... 78

17. INT- Interrupts..........................................................................................................8217.1. Interrupt Vectors in ATmega328PB............................................................................................ 8217.2. Register Description................................................................................................................... 83

18. EXINT - External Interrupts..................................................................................... 8618.1. Pin Change Interrupt Timing.......................................................................................................8618.2. Register Description................................................................................................................... 87


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19. I/O-Ports.................................................................................................................. 9619.1. Overview.....................................................................................................................................9619.2. Ports as General Digital I/O........................................................................................................9619.3. Alternate Port Functions...........................................................................................................10019.4. Register Description................................................................................................................. 112

20. TC0 - 8-bit Timer/Counter with PWM.....................................................................12220.1. Features................................................................................................................................... 12220.2. Overview...................................................................................................................................12220.3. Timer/Counter Clock Sources.................................................................................................. 12420.4. Counter Unit............................................................................................................................. 12420.5. Output Compare Unit................................................................................................................12420.6. Compare Match Output Unit.....................................................................................................12620.7. Modes of Operation..................................................................................................................12720.8. Timer/Counter Timing Diagrams...............................................................................................13120.9. Register Description................................................................................................................. 132

21. TC1 - 16-bit Timer/Counter with PWM...................................................................14621.1. Features................................................................................................................................... 14621.2. Overview...................................................................................................................................14621.3. Accessing 16-bit Registers.......................................................................................................14821.4. Timer/Counter Clock Sources.................................................................................................. 15121.5. Counter Unit............................................................................................................................. 15121.6. Input Capture Unit.................................................................................................................... 15221.7. Compare Match Output Unit.....................................................................................................15421.8. Output Compare Units..............................................................................................................15521.9. Modes of Operation..................................................................................................................15721.10. Timer/Counter Timing Diagrams.............................................................................................. 16421.11. Register Description................................................................................................................. 165

22. Timer/Counter0 and Timer/Counter1,3,4 Prescalers.............................................18622.1. Internal Clock Source............................................................................................................... 18622.2. Prescaler Reset........................................................................................................................18622.3. External Clock Source..............................................................................................................18622.4. Register Description................................................................................................................. 187

23. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation................... 18923.1. Features................................................................................................................................... 18923.2. Overview...................................................................................................................................18923.3. Timer/Counter Clock Sources.................................................................................................. 19023.4. Counter Unit............................................................................................................................. 19023.5. Output Compare Unit................................................................................................................19123.6. Compare Match Output Unit.....................................................................................................19323.7. Modes of Operation..................................................................................................................19423.8. Timer/Counter Timing Diagrams...............................................................................................19823.9. Asynchronous Operation of Timer/Counter2............................................................................ 19923.10. Timer/Counter Prescaler.......................................................................................................... 20123.11. Register Description................................................................................................................. 201


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24. OCM1C2 - Output Compare Modulator.................................................................21424.1. Overview...................................................................................................................................21424.2. Description................................................................................................................................214

25. SPI – Serial Peripheral Interface........................................................................... 21625.1. Features................................................................................................................................... 21625.2. Overview...................................................................................................................................21625.3. SS Pin Functionality................................................................................................................. 22025.4. Data Modes.............................................................................................................................. 22125.5. Register Description................................................................................................................. 222

26. USART - Universal Synchronous Asynchronous Receiver Transceiver................22726.1. Features................................................................................................................................... 22726.2. Overview...................................................................................................................................22726.3. Clock Generation......................................................................................................................22826.4. Frame Formats.........................................................................................................................23126.5. USART Initialization..................................................................................................................23226.6. Data Transmission – The USART Transmitter......................................................................... 23326.7. Data Reception – The USART Receiver.................................................................................. 23526.8. Asynchronous Data Reception.................................................................................................23926.9. Multi-Processor Communication Mode.....................................................................................24326.10. Examples of Baud Rate Setting............................................................................................... 24426.11. Register Description................................................................................................................. 247

27. USARTSPI - USART in SPI Mode.........................................................................25927.1. Features................................................................................................................................... 25927.2. Overview...................................................................................................................................25927.3. Clock Generation......................................................................................................................25927.4. SPI Data Modes and Timing.....................................................................................................26027.5. Frame Formats.........................................................................................................................26027.6. Data Transfer............................................................................................................................26227.7. AVR USART MSPIM vs. AVR SPI............................................................................................26327.8. Register Description................................................................................................................. 264

28. TWI - 2-wire Serial Interface..................................................................................26528.1. Features................................................................................................................................... 26528.2. Two-Wire Serial Interface Bus Definition..................................................................................26528.3. Data Transfer and Frame Format.............................................................................................26728.4. Multi-master Bus Systems, Arbitration and Synchronization....................................................26928.5. Overview of the TWI Module.................................................................................................... 27128.6. Using the TWI...........................................................................................................................27328.7. Transmission Modes................................................................................................................ 27528.8. Multi-master Systems and Arbitration.......................................................................................29128.9. Register Description................................................................................................................. 293

29. AC - Analog Comparator....................................................................................... 30129.1. Overview...................................................................................................................................30129.2. Analog Comparator Multiplexed Input...................................................................................... 302


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29.3. Register Description................................................................................................................. 302

30. ADC - Analog to Digital Converter......................................................................... 31130.1. Features....................................................................................................................................31130.2. Overview...................................................................................................................................31130.3. Starting a Conversion...............................................................................................................31330.4. Prescaling and Conversion Timing...........................................................................................31430.5. Changing Channel or Reference Selection.............................................................................. 31530.6. ADC Noise Canceler................................................................................................................ 31630.7. ADC Conversion Result............................................................................................................32030.8. Temperature Measurement...................................................................................................... 32030.9. Register Description................................................................................................................. 321

31. PTC - Peripheral Touch Controller.........................................................................34131.1. Overview...................................................................................................................................34131.2. Features................................................................................................................................... 34131.3. Block Diagram.......................................................................................................................... 34231.4. Signal Description.....................................................................................................................34231.5. Product Dependencies............................................................................................................. 34331.6. Functional Description..............................................................................................................344

32. DBG - debugWIRE On-chip Debug System.......................................................... 34532.1. Features................................................................................................................................... 34532.2. Overview...................................................................................................................................34532.3. Physical Interface..................................................................................................................... 34532.4. Software Break Points..............................................................................................................34632.5. Limitations of debugWIRE........................................................................................................34632.6. Register Description................................................................................................................. 346

33. BTLDR - Boot Loader Support – Read-While-Write Self-Programming................ 34833.1. Features................................................................................................................................... 34833.2. Overview...................................................................................................................................34833.3. Application and Boot Loader Flash Sections............................................................................34833.4. Read-While-Write and No Read-While-Write Flash Sections...................................................34933.5. Entering the Boot Loader Program...........................................................................................35133.6. Boot Loader Lock Bits.............................................................................................................. 35233.7. Addressing the Flash During Self-Programming...................................................................... 35333.8. Self-Programming the Flash.....................................................................................................35433.9. Register Description................................................................................................................. 362

34. MEMPROG- Memory Programming......................................................................36534.1. Program And Data Memory Lock Bits...................................................................................... 36534.2. Fuse Bits...................................................................................................................................36634.3. Signature Bytes........................................................................................................................ 36934.4. Calibration Byte........................................................................................................................ 36934.5. Page Size................................................................................................................................. 36934.6. Parallel Programming Parameters, Pin Mapping, and Commands..........................................37034.7. Parallel Programming...............................................................................................................37134.8. Serial Downloading...................................................................................................................379


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35. Electrical Characteristics....................................................................................... 38435.1. Absolute Maximum Ratings......................................................................................................38435.2. DC Characteristics....................................................................................................................38435.3. Speed Grades.......................................................................................................................... 38735.4. Clock Characteristics................................................................................................................38735.5. System and Reset Characteristics........................................................................................... 38835.6. SPI Timing Characteristics....................................................................................................... 39035.7. Two-wire Serial Interface Characteristics................................................................................. 39135.8. ADC Characteristics................................................................................................................. 39335.9. Parallel Programming Characteristics...................................................................................... 394

36. Typical Characteristics...........................................................................................39736.1. Active Supply Current...............................................................................................................39736.2. Idle Supply Current...................................................................................................................39936.3. ATmega328PB Supply Current of IO Modules.........................................................................40136.4. Power-down Supply Current.....................................................................................................40236.5. Pin Pull-Up................................................................................................................................40336.6. Pin Driver Strength................................................................................................................... 40636.7. Pin Threshold and Hysteresis...................................................................................................40836.8. BOD Threshold.........................................................................................................................40936.9. Internal Oscillator Speed.......................................................................................................... 41236.10. Current Consumption in Reset and Reset Pulse Width........................................................... 415

37. Register Summary.................................................................................................416

38. Instruction Set Summary....................................................................................... 421

39. Packaging Information...........................................................................................42539.1. 32A........................................................................................................................................... 42539.2. 32MS1...................................................................................................................................... 426

40. Errata.....................................................................................................................42740.1. Rev. A.......................................................................................................................................427

41. Revision History.....................................................................................................428


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1. DescriptionThe Atmel® ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhancedRISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achievesthroughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for powerconsumption versus processing speed.

The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registersto be accessed in a single instruction executed in one clock cycle. The resulting architecture is more codeefficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega328PB provides the following features: 32Kbytes of In-System Programmable Flash withRead-While-Write capabilities, 1Kbytes EEPROM, 2Kbytes SRAM, 27 general purpose I/O lines, 32general purpose working registers, five flexible Timer/Counters with compare modes, internal andexternal interrupts, two serial programmable USART, two byte-oriented 2-wire Serial Interface (I2C), twoSPI serial port, a 8-channel 10-bit ADC in TQFP and QFN/MLF package, a programmable WatchdogTimer with internal Oscillator, Clock failure detection mechanism and six software selectable power savingmodes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire SerialInterface, SPI port, and interrupt system to continue functioning. PTC with enabling up to 24 self-cap and144 mutual-cap sensors. The Power-down mode saves the register contents but freezes the Oscillator,disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, theasynchronous timer continues to run, allowing the user to maintain a timer base while the rest of thedevice is sleeping. Also ability to run PTC in power-save mode/wake-up on touch and Dynamic on/off ofPTC analog and digital portion. The ADC Noise Reduction mode stops the CPU and all I/O modulesexcept asynchronous timer, PTC, and ADC to minimize switching noise during ADC conversions. InStandby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. Thisallows very fast start-up combined with low power consumption.

Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionalityinto AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing andincludes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®)technology for unambiguous detection of key events. The easy-to-use QTouch Composer allows you toexplore, develop and debug your own touch applications.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISPFlash allows the program memory to be reprogrammed In-System through an SPI serial interface, by aconventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.The Boot program can use any interface to download the application program in the Application Flashmemory. Software in the Boot Flash section will continue to run while the Application Flash section isupdated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-SystemSelf-Programmable Flash on a monolithic chip, the Atmel ATmega328PB is a powerful microcontrollerthat provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega328PB is supported with a full suite of program and system development tools including: CCompilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.


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2. Configuration SummaryFeatures ATmega328PB

Pin count 32

Flash (KB) 32

SRAM (KB) 2

EEPROM (KB) 1

General Purpose I/O pins 27

SPI 2

TWI (I2C) 2

USART 2

ADC 10-bit 15ksps

ADC channels 8

AC propagation delay 400ns (Typical)

8-bit Timer/Counters 2

16-bit Timer/Counters 3

PWM channels 10

PTC Available

Clock Failure Detector (CFD) Available

Output Compare Modulator (OCM1C2) Available

RC Oscillator +/-1.5%

VREF Bandgap +/-2%

Operating voltage 1.8 - 5.5V

Max operating frequency 20MHz

Temperature range -40°C to +105°C


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3. Ordering InformationSpeed [MHz] Power Supply [V] Ordering Code(2) Package(1) Operational Range

20 1.8 - 5.5 ATmega328PB-AUATmega328PB-AUR(3)ATmega328PB-MUATmega328PB-MUR(3)

32A32A32MS132MS1

Industrial(-40°C to 85°C)

ATmega328PB-ANATmega328PB-ANR(3)ATmega328PB-MNATmega328PB-MNR(3)

32A32A32MS132MS1

Industrial(-40°C to 105°C)

Note: 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailedordering information and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHSdirective). Also Halide free and fully Green.

3. Tape & Reel.


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4. Block DiagramFigure 4-1 Block Diagram


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5. Pin ConfigurationsFigure 5-1 Pinout ATmega328PB

12345678

2423222120191817

(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4

(ACO) PE0VCC

GNDPE1

(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT9)PC0 (ADC0/PCINT8)PE3 (ADC7)GNDAREFPE2 (ADC6)AVCCPB5 (SCK/PCINT5)

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

(PCI

NT21

/OC0

B/T1

) PD5

(PCI

NT22

/OC0

A/AI

N0) P

D6(P

CINT

23/A

IN1)

PD7

(PCI

NT0/

CLKO

/ICP1

) PB0

(PCI

NT1/

OC1

A) P

B1(P

CINT

2/SS

/OC1

B) P

B2(P

CINT

3/O

C2A/

MO

SI) P

B3(P

CINT

4/M

ISO

) PB4

PD2

(INT0

/PCI

NT18

)PD

1 (T

XD/P

CINT

17)

PD0

(RXD

/PCI

NT16

)PC

6 (R

ESET

/PCI

NT14

)PC

5 (A

DC5/

SCL/

PCIN

T13)

PC4

(ADC

4/SD

A/PC

INT1

2)PC

3 (A

DC3/

PCIN

T11)

PC2

(ADC

2/PC

INT1

0)

32 TQFP Top View

12345678

2423222120191817

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

32 VFQFN Top View

(PCINT19/OC2B/INT1) PD3(PCINT20/XCK/T0) PD4

(ACO) PE0VCC

GNDPE1

(PCINT6/XTAL1/TOSC1) PB6(PCINT7/XTAL2/TOSC2) PB7

PC1 (ADC1/PCINT9)PC0 (ADC0/PCINT8)PE3 (ADC7)GNDAREFPE2 (ADC6)AVCCPB5 (SCK/PCINT5)

(PCI

NT21

/OC0

B/T1

) PD5

(PCI

NT22

/OC0

A/AI

N0) P

D6(P

CINT

23/A

IN1)

PD7

(PCI

NT0/

CLKO

/ICP1

) PB0

(PCI

NT1/

OC1

A) P

B1(P

CINT

2/SS

/OC1

B) P

B2(P

CINT

3/O

C2A/

MO

SI) P

B3(P

CINT

4/M

ISO

) PB4

PD2

(INT0

/PCI

NT18

)PD

1 (T

XD/P

CINT

17)

PD0

(RXD

/PCI

NT16

)PC

6 (R

ESET

/PCI

NT14

)PC

5 (A

DC5/

SCL/

PCIN

T13)

PC4

(ADC

4/SD

A/PC

INT1

2)PC

3 (A

DC3/

PCIN

T11)

PC2

(ADC

2/PC

INT1

0)

NOTE: Bottom pad should be soldered to ground.

5.1. Pin Descriptions

5.1.1. VCCDigital supply voltage.

5.1.2. GNDGround.

5.1.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Boutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The PortB pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillatoramplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillatoramplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] inputfor the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

5.1.4. Port C (PC[5:0])Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC[5:0]output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The PortC pins are tri-stated when a reset condition becomes active, even if the clock is not running.


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5.1.5. PC6/RESETIf the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristicsof PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longerthan the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses arenot guaranteed to generate a Reset.

The various special features of Port C are elaborated in Alternate Functions of Port C on page 105.

5.1.6. Port D (PD[7:0])Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Doutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The PortD pins are tri-stated when a reset condition becomes active, even if the clock is not running.

5.1.7. Port E (PE[3:0])Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port Eoutput buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The PortE pins are tri-stated when a reset condition becomes active, even if the clock is not running.

5.1.8. AVCCAVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externallyconnected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC througha low-pass filter. Note that PC[6:4] use digital supply voltage, VCC.

5.1.9. AREFAREF is the analog reference pin for the A/D Converter.

5.1.10. ADC[7:6] (TQFP and VFQFN Package Only)In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins arepowered from the analog supply and serve as 10-bit ADC channels.


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6. I/O MultiplexingEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can beassigned to one of the peripheral functions.

The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 6-1 PORT Function Multiplexing

No PAD EXTINT PCINT ADC/AC PTC X PTC Y OSC T/C # 0 T/C # 1 USART I2C SPI MISC

1 PD[3] INT1 PC2-19 X3 Y11 TC2-OCB

2 PD[4] PC2-20 X4 Y12 TC0-CLK U0-XCK SIO

3 PE[0] PC3-24 ACO X8 Y16 TC4-ICP TW1-SDA

4 VCC

5 GND

6 PE[1] PC3-25 X9 Y17 TC4-CLK TW1-SCL

7 PB[6] PC0-06 XTAL1 SCI

8 PB[7] PC0-07 XTAL2

9 PD[5] PC2-21 X5 Y13 TC0-OCB TC1-CLK SII

10 PD[6] PC2-22 AIN0 X6 Y14 TC0-OCA SDO

11 PD[7] PC2-23 AIN1 X7 Y15 SDI

12 PB[0] PC0-00 X10 Y18 CLKOUT TC1-ICP

13 PB[1] PC0-01 X11 Y19 TC1-OCA

14 PB[2] PC0-02 X12 Y20 TC1-OCB S0-SS

15 PB[3] PC0-03 X13 Y21 TC2-OCA U1-TXD S0-MOSI

16 PB[4] PC0-04 X14 Y22 U1-RXD S0-MISO

17 PB[5] PC0-05 X15 Y23 U1-XCK S0-SCK

18 AVCC

19 PE[2] PC3-26 ADC6 Y6 TC3-ICP S1-SS

20 AREF

21 GND

22 PE[3] PC3-27 ADC7 Y7 TC3-CLK S1-MOSI

23 PC[0] PC1-08 ADC0 Y0 S1-MISO

24 PC[1] PC1-09 ADC1 Y1 S1-SCK

25 PC[2] PC1-10 ADC2 Y2

26 PC[3] PC1-11 ADC3 Y3

27 PC[4] PC1-12 ADC4 Y4 TW0-SDA

28 PC[5] PC1-13 ADC5 Y5 TW0-SCL

29 RESET PC1-14 HVRST/dW

30 PD[0] PC2-16 X0 Y8 TC3-OCA U0-RXD

31 PD[1] PC2-17 X1 Y9 0 TC4-OCA U0-TXD

32 PD[2] INT0 PC2-18 X2 Y10 TC3-OCB TC4-OCB


15

7. ResourcesA comprehensive set of development tools, application notes, and datasheets are available for downloadon http://www.atmel.com/avr.


16

http://www.atmel.com/avr

8. Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPMover 20 years at 85°C or 100 years at 25°C.


17

9. About Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of thedevice. These code examples assume that the part specific header file is included before compilation. Beaware that not all C compiler vendors include bit definitions in the header files and interrupt handling in Cis compiler dependent. Confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructionsmust be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.


18

10. Capacitive Touch Sensing

10.1. QTouch LibraryThe Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces onmost Atmel AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and AtmelQMatrix® acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for theAVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,and then calling the touch sensing API’s to retrieve the channel information and determine the touchsensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://www.atmel.com/technologies/touch/. For implementation details and other information, refer to the AtmelQTouch Library User Guide - also available for download from the Atmel website.

10.2. Peripheral Touch ControllerThe purpose of PTC is to acquire signals to detect touch on capacitive sensors. The external capacitivetouch sensor is typically formed on a PCB, and the sensor electrodes are connected to the analog frontend of the PTC through the I/O pins in the device. The PTC supports both self- and mutual-capacitancesensors.

Related LinksPTC - Peripheral Touch Controller on page 341


19

http://www.atmel.com/technologies/touch/http://www.atmel.com/technologies/touch/http://www.atmel.com/dyn/resources/prod_documents/doc8207.pdfhttp://www.atmel.com/dyn/resources/prod_documents/doc8207.pdf

11. AVR CPU Core

11.1. OverviewThis section discusses the AVR core architecture in general. The main function of the CPU core is toensure correct program execution. The CPU must therefore be able to access memories, performcalculations, control peripherals, and handle interrupts.

Figure 11-1 Block Diagram of the AVR Architecture

FlashProgramMemory

InstructionRegister

InstructionDecoder

ProgramCounter

Control Lines

32 x 8GeneralPurpose

Registrers

ALU

Statusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Dire

ct A

ddre

ssin

g

Indi

rect

Add

ress

ing

InterruptUnit

SPIUnit

WatchdogTimer

AnalogComparator

I/O Module 2

I/O Module1

I/O Module n

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separatememories and buses for program and data. Instructions in the program memory are executed with asingle level pipelining. While one instruction is being executed, the next instruction is pre-fetched from theprogram memory. This concept enables instructions to be executed in every clock cycle. The programmemory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 8-bit general purpose working registers with a single clockcycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALUoperation, two operands are output from the Register File, the operation is executed, and the result isstored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Spaceaddressing – enabling efficient address calculations. One of the these address pointers can also be usedas an address pointer for look up tables in Flash program memory. These added function registers arethe 16-bit X-, Y-, and Z-register, described later in this section.


20

The ALU supports arithmetic and logic operations between registers or between a constant and aregister. Single register operations can also be executed in the ALU. After an arithmetic operation, theStatus Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directlyaddress the whole address space. Most AVR instructions have a single 16-bit word format. Everyprogram memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the ApplicationProgram section. Both sections have dedicated Lock bits for write and read/write protection. The SPMinstruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack.The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is onlylimited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in theReset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/writeaccessible in the I/O space. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global InterruptEnable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vectortable. The interrupts have priority in accordance with their Interrupt Vector position. The lower theInterrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI,and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locationsfollowing those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

11.2. ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general purpose workingregisters. Within a single clock cycle, arithmetic operations between general purpose registers or betweena register and an immediate are executed. The ALU operations are divided into three main categories –arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerfulmultiplier supporting both signed/unsigned multiplication and fractional format. See the Instruction SetSummary section for a detailed description.

Related LinksInstruction Set Summary on page 421

11.3. Status RegisterThe Status Register contains information about the result of the most recently executed arithmeticinstruction. This information can be used for altering program flow in order to perform conditionaloperations. The Status Register is updated after all ALU operations, as specified in the Instruction SetReference. This will in many cases remove the need for using the dedicated compare instructions,resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored whenreturning from an interrupt. This must be handled by software.


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11.3.1. Status Register

Name: SREGOffset: 0x3FReset: 0x00Property:

-

Bit 7 6 5 4 3 2 1 0 I T H S V N Z C

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interruptenable control is then performed in separate control registers. If the Global Interrupt Enable Register iscleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enablesubsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLIinstructions, as described in the instruction set reference.

Bit 6 – T: Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination forthe operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, anda bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCDarithmetic. See the Instruction Set Description for detailed information.

Bit 4 – S: S = N ㊉ VThe S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement OverflowFlag V. See the Instruction Set Description for detailed information.

Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the Instruction SetDescription for detailed information.

Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.

Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction SetDescription for detailed information.

Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Descriptionfor detailed information.


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11.4. General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve therequired performance and flexibility, the following input/output schemes are supported by the RegisterFile:

• One 8-bit output operand and one 8-bit result input• Two 8-bit output operands and one 8-bit result input• Two 8-bit output operands and one 16-bit result input• One 16-bit output operand and one 16-bit result input

Figure 11-2 AVR CPU General Purpose Working Registers7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

Genera l R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Regis ters R17 0x11

…

R26 0x1A X-regis te r Low Byte

R27 0x1B X-regis te r High Byte

R28 0x1C Y-regis te r Low Byte

R29 0x1D Y-regis te r High Byte

R30 0x1E Z-regis te r Low Byte

R31 0x1F Z-regis te r High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most ofthem are single cycle instructions. As shown in the figure, each register is also assigned a data memoryaddress, mapping them directly into the first 32 locations of the user Data Space. Although not beingphysically implemented as SRAM locations, this memory organization provides great flexibility in accessof the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

11.4.1. The X-register, Y-register, and Z-registerThe registers R26...R31 have some added functions to their general purpose usage. These registers are16-bit address pointers for indirect addressing of the data space. The three indirect address registers X,Y, and Z are defined as described in the figure.


23

Figure 11-3 The X-, Y-, and Z-registers15 XH XL 0

X-regis te r 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-regis te r 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-regis te r 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement. See the Instruction Set Summary for details.

Related LinksInstruction Set Summary on page 421

11.5. Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storing returnaddresses after interrupts and subroutine calls. The Stack is implemented as growing from higher tolower memory locations. The Stack Pointer Register always points to the top of the Stack.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks arelocated. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must bedefined by the program before any subroutine calls are executed or interrupts are enabled. Initial StackPointer value equals the last address of the internal SRAM and the Stack Pointer must be set to pointabove start of the SRAM. See the table for Stack Pointer details.

Table 11-1 Stack Pointer Instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

ICALL

RCALL

Decremented by 2 Return address is pushed onto the stack with a subroutine call orinterrupt

POP Incremented by 1 Data is popped from the stack

RET

RETI

Incremented by 2 Return address is popped from the stack with return from subroutine orreturn from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actuallyused is implementation dependent. Note that the data space in some implementations of the AVRarchitecture is so small that only SPL is needed. In this case, the SPH Register will not be present.


24

11.5.1. SPH and SPL - Stack Pointer High and Stack Pointer Low RegisterBit 15 14 13 12 11 10 9 8

0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initia l Value0

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

11.6. Instruction Execution TimingThis section describes the general access timing concepts for instruction execution. The AVR CPU isdriven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internalclock division is used. The Figure below shows the parallel instruction fetches and instruction executionsenabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipeliningconcept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,functions per clocks, and functions per power-unit.

Figure 11-4 The Parallel Instruction Fetches and Instruction Executions

clk

1st Instruction Fetch1st Instruction Execute

2nd Instruction Fetch2nd Instruction Execute

3rd Instruction Fetch3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

The following Figure shows the internal timing concept for the Register File. In a single clock cycle anALU operation using two register operands is executed, and the result is stored back to the destinationregister.

Figure 11-5 Single Cycle ALU Operation

Total Execution T ime

Register Operands Fetch

ALU Operation Execute

Result W rite Back

T1 T2 T3 T4

clkCPU

11.7. Reset and Interrupt HandlingThe AVR provides several different interrupt sources. These interrupts and the separate Reset Vectoreach have a separate program vector in the program memory space. All interrupts are assigned individual


25

enable bits which must be written logic one together with the Global Interrupt Enable bit in the StatusRegister in order to enable the interrupt. Depending on the Program Counter value, interrupts may beautomatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improvessoftware security.

The lowest addresses in the program memory space are by default defined as the Reset and InterruptVectors. They have determined priority levels: The lower the address the higher is the priority level.RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectorscan be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register(MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programmingthe BOOTRST Fuse.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. Theuser software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can theninterrupt the current interrupt routine. The I-bit is automatically set when a Return from Interruptinstruction – RETI – is executed.

There are basically two types of interrupts:

The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the ProgramCounter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, andhardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logicone to the flag bit position(s) to be cleared. If an interrupt condition occurs while the correspondinginterrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled,or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the GlobalInterrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until theGlobal Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts donot necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled,the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the mainprogram and execute one more instruction before any pending interrupt is served.

The Status Register is not automatically stored when entering an interrupt routine, nor restored whenreturning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. Nointerrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.The following example shows how this can be used to avoid interrupts during the timed EEPROM writesequence.

Assembly Code Example

in r16, SREG ; store SREG valuecli ; disable interrupts during timed sequencesbi EECR, EEMPE ; start EEPROM writesbi EECR, EEPEout SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1

EECR |= (1

12. AVR Memories

12.1. OverviewThis section describes the different memory types in the device. The AVR architecture has two mainmemory spaces, the Data Memory and the Program Memory space. All memory spaces are linear andregular.

12.2. In-System Reprogrammable Flash Program MemoryThe device contains 32Kbytes On-chip In-System Reprogrammable Flash memory for program storage.Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16K x 16. For softwaresecurity, the Flash Program memory space is divided into two sections - Boot Loader Section andApplication Program Section in the device.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The device Program Counter(PC) is 14 bits wide, thus addressing the 16K program memory locations.

Constant tables can be allocated within the entire program memory address space, using the LoadProgram Memory (LPM) instruction.

Timing diagrams for instruction fetch and execution are presented in Instruction Exectution Timing.

Figure 12-1 Program Memory Map ATmega328PB

0x0000

0x3FFF

Program Memory

Application Flash Section

Boot Flash Section

Related LinksMemory Programming on page 365Instruction Execution Timing on page 25Boot Loader Support – Read-While-Write Self-Programming on page 348


28

Self-Programming the Flash on page 354

12.3. SRAM Data MemoryThe following figure shows how the device SRAM Memory is organized.

The device is a complex microcontroller with more peripheral units than can be supported within the 64locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 2303 data memory locations address both the Register File, the I/O memory, Extended I/Omemory, and the internal data SRAM. The first 32 locations address the Register File, the next 64location the standard I/O memory, then 160 locations of Extended I/O memory, and the next 2048locations address the internal data SRAM.

The five different addressing modes for the data memory cover:• Direct

– The direct addressing reaches the entire data space.• Indirect with Displacement

– The Indirect with Displacement mode reaches 63 address locations from the base addressgiven by the Y- or Z-register.

• Indirect– In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

• Indirect with Pre-decrement– The address registers X, Y, and Z are decremented.

• Indirect with Post-increment– The address registers X, Y, and Z are incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the 2048bytes of internal data SRAM in the device are all accessible through all these addressing modes.

Figure 12-2 Data Memory Map

32 Registers64 I/O Registers

Internal SRAM(2048 x 8)

0x0000 - 0x001F0x0020 - 0x005F

0x08FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.0x0100

12.3.1. Data Memory Access TimesThe internal data SRAM access is performed in two clkCPU cycles as described in the following Figure.


29

Figure 12-3 On-chip Data SRAM Access Cycles

clk

WR

RD

Data

Data

Address Address valid

T1 T2 T3

Compute Address

Read

Writ

e

CPU

Memory Access Instruction Next Instruction

12.4. EEPROM Data MemoryThe device contains 512 bytes of data EEPROM memory. It is organized as a separate data space, inwhich single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying theEEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

See the related links for a detailed description on EEPROM Programming in SPI or Parallel Programmingmode.

Related LinksMemory Programming on page 365

12.4.1. EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 12-2 EEPROM Programming Time on page37. A self-timing function, however, lets the user software detect when the next byte can be written. Ifthe user code contains instructions that write the EEPROM, some precautions must be taken. In heavilyfiltered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device forsome period of time to run at a voltage lower than specified as minimum for the clock frequency used.Please refer to Preventing EEPROM Corruption on page 31 for details on how to avoid problems inthese situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer tothe description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction isexecuted. When the EEPROM is written, the CPU is halted for two clock cycles before the next instructionis executed.



30

12.4.2. Preventing EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low forthe CPU and the EEPROM to operate properly. These issues are the same as for board level systemsusing EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regularwrite sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itselfcan execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be doneby enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does notmatch the needed detection level, an external low VCC reset Protection circuit can be used. If a resetoccurs while a write operation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.


12.5. I/O MemoryThe I/O space definition of the device is shown in the Register Summary.

All device I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by theLD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose workingregisters and the I/O space. I/O Registers within the address range 0x00-0x1F are directly bit-accessibleusing the SBI and CBI instructions. In these registers, the value of single bits can be checked by usingthe SBIS and SBIC instructions.

When using the I/O specific commands IN and OUT, the I/O addresses 0x00-0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to theseaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60..0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/Omemory addresses should never be written.

Some of the Status Flags are cleared by writing a '1' to them; this is described in the flag descriptions.Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, andcan therefore be used on registers containing such Status Flags. The CBI and SBI instructions work withregisters 0x00-0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

Related LinksInstruction Set Summary on page 421Memory Programming on page 365Register Summary on page 416

12.5.1. General Purpose I/O RegistersThe device contains three General Purpose I/O Registers, General Purpose I/O Register 0/1/2 (GPIOR0/1/2). These registers can be used for storing any information, and they are particularly useful for storing


31

global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1Fare directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

Related LinksInstruction Set Summary on page 421Memory Programming on page 365Register Summary on page 416

12.6. Register Description


32

12.6.1. EEPROM Address Register HighWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: EEARHOffset: 0x22Reset: 0x0XProperty:

When addressing I/O Registers as data space the offset address is 0x42

Bit 7 6 5 4 3 2 1 0 EEAR9 EEAR8

Access R R/W Reset 0 x

Bit 1 – EEAR9: EEPROM Address 9Refer to EEARL on page 34.

Bit 0 – EEAR8: EEPROM Address 8Refer to EEARL on page 34.


33

12.6.2. EEPROM Address Register LowWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: EEARLOffset: 0x21Reset: 0xXXProperty:


Bit 7 6 5 4 3 2 1 0 EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x

Bits 7:0 – EEARn: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 BytesEEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The initial value ofEEAR is undefined. A proper value must be written before the EEPROM may be accessed.


34

12.6.3. EEPROM Data RegisterWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: EEDROffset: 0x20Reset: 0x00Property:


Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0

Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0

Bits 7:0 – EEDRn: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM inthe address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the dataread out from the EEPROM at the address given by EEAR.

• EEDR[7] is MSB• EEDR[0] is LSB


35

12.6.4. EEPROM Control RegisterWhen using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. Whenaddressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offsetaddresses. The device is a complex microcontroller with more peripheral units than can be supportedwithin the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O spacefrom 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

Name: EECROffset: 0x1FReset: 0x00Property:

When addressing I/O Registers as data space the offset address is 0x3F

Bit 7 6 5 4 3 2 1 0 EEPM1 EEPM0 EERIE EEMPE EEPE EERE

Access R/W R/W R/W R/W R/W R/W Reset x x 0 0 x x

Bits 5:4 – EEPMn: EEPROM Programming Mode Bits [n = 1:0]The EEPROM Programming mode bit setting defines which programming action that will be triggeredwhen writing EEPE. It is possible to program data in one atomic operation (erase the old value andprogram the new value) or to split the Erase and Write operations in two different operations. TheProgramming times for the different modes are shown in the table below. While EEPE is set, any write toEEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busyprogramming.

Table 12-1 EEPROM Mode Bits

EEPM[1:0] Programming Time Operation

00 3.4ms Erase and Write in one operation (Atomic Operation)

01 1.8ms Erase Only

10 1.8ms Write Only

11 - Reserved for future use

Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE tozero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE iscleared. The interrupt will not be generated during EEPROM write or SPM.

Bit 2 – EEMPE: EEPROM Master Write EnableThe EEMPE bit determines whether writing EEPE to '1' causes the EEPROM to be written.When EEMPE is '1', setting EEPE within four clock cycles will write data to the EEPROM at the selectedaddress.

If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to '1' by software,hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for anEEPROM write procedure.


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Bit 1 – EEPE: EEPROM Write EnableThe EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data arecorrectly set up, the EEPE bit must be written to '1' to write the value into the EEPROM. The EEMPE bitmust be written to '1' before EEPE is written to '1', otherwise no EEPROM write takes place. The followingprocedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.2. Wait until SPMEN in SPMCSR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a '1' to the EEMPE bit while writing a zero to EEPE in EECR.6. Within four clock cycles after setting EEMPE, write a '1' to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software mustcheck that the Flash programming is completed before initiating a new EEPROM write. Step 2 is onlyrelevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash isnever being updated by the CPU, step 2 can be omitted.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM MasterWrite Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting anotherEEPROM access, the EEAR or EEDR Register will be modified, causing the interruptedEEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during allthe steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The usersoftware can poll this bit and wait for a zero before writing the next byte. When EEPE has beenset, the CPU is halted for two cycles before the next instruction is executed.

Bit 0 – EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct addressis set up in the EEAR Register, the EERE bit must be written to a '1' to trigger the EEPROM read. TheEEPROM read access takes one instruction, and the requested data is available immediately. When theEEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, itis neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. See the following table for typicalprogramming times for EEPROM access from the CPU.

Table 12-2 EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ. Programming Time

EEPROM write (from CPU) 26,368 3.3ms

The following code examples show one assembly and one C function for writing to the EEPROM. Theexamples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interruptswill occur during execution of these functions. The examples also assume that no Flash Boot Loader ispresent in the software. If such code is present, the EEPROM write function must also wait for anyongoing SPM command to finish.


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Assembly Code ExampleEEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set

Documents

Atmel-42397-8-bit-AVR-Microcontroller …...– Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change •