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CS222: (a) Activation Record of Merge Sort(a) Activation Record of Merge Sort(b) Architecture Space RISC/CISC
Dr. A. Sahu
Dept of Comp. Sc. & Engg.Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
1
OutlineOutline• Activation Record in Recursion:
– Merge Sort Activation Record
• Features of MIPS ISA
• Other architectural variations
• RISC and CISCRISC and CISC
• Examples
Activation record / frameActivation record / frame
local data
$sp
saveds registerss registers
(if any)
return addr
arguments$fp
Sorting example ‐MainSorting example Mainconst m = 20;
void main(void) {void main(void) {
int N, i; int X[m], Y[m];
t " t th t f i t \ " i Ncout << "enter the count of integers\n"; cin >> N;
cout << "enter the integers\n";
f ( ) [ ]for (i = 0; i < N; i++) cin >> X[i];
sort(X, Y, N);
cout << "sorted values : \n";
for (i = 0; i < N; i++) cout << Y[i] << " "; cout << endl;
}
Recursive merge sort procedurevoid sort (int A[ ], int B[ ], int n) {
int A1[m], A2[m]; int n1, n2;int A1[m], A2[m]; int n1, n2;
if (n == 1) B[0] = A[0];
l {else {
n1 = n / 2; n2 = n ‐ n1;
sort (A, A1, n1);
sort (A+n1, A2, n2);sort (A+n1, A2, n2);
merge (A1, A2, B, n1, n2);
}
}
}
}
Merge procedureMerge procedurevoid merge (int P[ ], int Q[ ], int R[ ], int p, int q) {
kint i, j, k;
i = j = k = 0;
while (i < p && j < q)
if (P[i] < Q[ j]) R[k++] = P[i++];if (P[i] < Q[ j]) R[k++] = P[i++];
else R[k++] = Q[ j++];
hil (i ) [k ] [i ]while (i < p) R[k++] = P[i++];
while (j < q) R[k++] = Q[ j++];
}
Activation record for mergeActivation record for merge
d ( [ ] $sp iijj ca
ls
void merge (int P[ ], int Q[ ], int R[ ],
i t i t )return addrreturn addr
P
k los
int p, int q)
{
k
pRRQQ
ameterint i, j, k;
……..
qqp
para}
Simplifying activation recordSimplifying activation record
dd$sp$sp ii
jj
return addr
$sppp
return addrreturn addrP
k
QPa0
1 QPP
pRRQQ
RQa1
a2 RRQ
qqp
i
kj
t0t1t2
iijjkt2
Activation record for sortActivation record for sort
$$sp
s
A1void sort (int A[ ],
int B[ ], int n)
{A2
n1
locals{
int A1[m], A2[m];
int n1, n2;
return addrreturn addrA
n2n2
ters
………
}
nnBBA
aram
etpa
Part of merge procedurePart of merge procedure
l $t3 4($ )dd…..
while (i < p)
R[k++] = P[i++];
lw $t3, 4($sp)
L: bge $t0, $t3, X
muli $t4, $t0, 4
return addr
qqpp
R[k++] = P[i++];
…… add $t4, $t4, $a0
lw $t6, 0($t4)
addi $t0, $t0, 1QPPa0
1 addi $t0, $t0, 1
muli $t5, $t2, 4
add $t5, $t5, $a2
$t6 0($t5)
RRQa1
a2
sw $t6, 0($t5)
addi $t2, $t2, 1
j L
ii
kjj
t0t1t2
X:kt2
Calling merge
addi $a0, $sp, 0ddi $ 1 $ 80
return addrreturn addr
merge (A1, A2, B, n1, n2);
addi $a1, $sp, 80lw $a2, 176($sp)l $t8 160($ )A1
qqp
lw $t8, 160($sp)sw $t8, ‐8($sp)l $t8 164($ )
A2
A1
QPPa0
1 lw $t8, 164($sp)sw $t8, ‐4($sp)ddi $ $ 12
n2n2n1n1 RR
Qa1a2
addi $sp, $sp, ‐12jal merge
return addr
BAA
ii
kjj
t0t1t2 ….
merge: sw $ra, 0($sp)nn
kt2
Return from mergeReturn from merge
l $ ($ )return addrreturn addr
lw $ra, 0($sp)
addi $sp, $sp, 12A1
qqp
jr $ra
A2
A1
QPPa0
1
n2n2n1n1 RR
Qa1a2
return addr
BAA
ii
kjj
t0t1t2
nnkt2
Calling sortCalling sortsort (A, A1, n1);
A’A’’ sort: sw $ra, 168($sp)
…….
l $t8 172($ )A1
n’n’B’
lw $t8, 172($sp)
sw $t8, ‐12($sp)
addi $t8 $sp 0A2
A1
addi $t8, $sp, 0
sw $t8, ‐8($sp)
lw $t8, 160($sp)n2n2n1n1
$ , ($ p)
sw $t8, ‐4($sp)
addi $sp, $sp, ‐184
return addr
BAA
jal sortnn
Return from sortReturn from sort
l $ ($ )A’A’’ lw $ra, 168($sp)
addi $sp, $sp, 184A1
n’n’B’
jr $ra
A2
A1
n2n2n1n1
return addr
BAA
nn
Further work (lab exercise)Further work (lab exercise)
• Complete the assembly program for recursive mergeComplete the assembly program for recursive merge sort
• Write a pointer version (C and assembly)p ( y)
• Include code to track the max stack size
• Reduce local array size to n and find improvementReduce local array size to n and find improvement
• Write more space efficient program (C and assembly), still recursivey),
Architecture SpaceArchitecture Space • Features of MIPS ISA• Features of MIPS ISA
• Other architectural variationsOther architectural variations
• RISC and CISC• Examples
16
What constitutes ISA?What constitutes ISA?
Main features:Main features:
• Set of basic/primitive operations
• Storage structure – registers/memory
• How addresses are specified• How addresses are specified
• How instructions are encoded
MIPS ISA features ‐ operationsMIPS ISA features operations
• ArithmeticArithmetic
• Logical
l i l• Relational
• Branch/jump
• Data movement
• Procedure linkageProcedure linkage
MIPS ISA features ‐ storageMIPS ISA features storage
Memory
01
04Registers
1
31
230‐4
MIPS ISA features ‐ addressingMIPS ISA features addressing
Addressing modesAddressing modes
• ImmediatePurpose• Register
• Base/index
Purpose
Operand sources• Base/index
• PC relativeResult Destinations
Jump targets• (pseudo) Direct
R i t i di t
Jump targets
• Register indirect
MIPS addressing modes ‐ 1MIPS addressing modes 1
op rs rt constant
Immediate addressingop rs rt constant
Register addressingopop rsrs rtrt rdrd …… funcfunc 0
1
Registers
3131
MIPS addressing modes ‐ 2MIPS addressing modes 2
Base addressingMemory
opop rsrs rtrt constantconstant
Base addressing 04
registerregister + datadata
opop rsrs rtrt constantconstant
PC‐relative addressing
PCPC + instructioninstruction
MIPS addressing modes ‐ 3MIPS addressing modes 3
(pseudo) Direct addressingMemory
opop constantconstant
(pseudo) Direct addressing 04
PCPC + instructioninstruction
opop rsrs rtrt
Register indirect addressingrdrd …… funcfunc
RegisterRegister instructioninstruction
MIPS ISA features ‐ encodingMIPS ISA features encoding
• addi, lui, beq, bne, lw, sw I ‐ format
op rs rt 16 bit numberop rs rt 16 bit number
• j, jal J ‐ format
op 26 bit number
• add, jr R ‐ format
op rs rt rd shamt funct
MIPS ISA features ‐ summaryMIPS ISA features summary
• All instructions of same sizeAll instructions of same size• Only 3 formats• Fair number of GP registers• Simple operations – either arith/logic• Simple operations – either arith/logic or memory access or control transfer
• Limited addressing modes• Separate fields for src1 src2 and destSeparate fields for src1, src2 and dest
Alternative ArchitecturesAlternative Architectures• Provide more powerful operations
–e.g. “J++ and branch to L if J>N, where J is in
memory” or “copy a block of data in memory”memory or copy a block of data in memory
• Goal is to reduce number of instructions
executed
/• Danger is a slower cycle time and/or a
higher CPIhigher CPI
Location of operands – R/MLocation of operands R/M
• R‐R Both operands in registers• R‐R Both operands in registers
• R‐M one operand in register and one in memory
• M‐M Both operands in memoryM M Both operands in memory
• R+M Combines R‐R, R‐M and M‐M
How many operand fields?How many operand fields?
• 3 address machine r1 = r2 + r3• 3 address machine r1 = r2 + r3
• 2 address machine r1 = r1 + r2
• 1 address machine Acc = Acc + x
Acc is implicitAcc is implicit
• 0 address machine add values on
top of stack
Register organizationsRegister organizations
• Register less machine• Register‐less machine
• Accumulator based machine
• A few special purpose registers• Several general purpose registers• Large number of registers / register• Large number of registers / register windows
Additional addressing modesAdditional addressing modes
• Direct• Direct
• Indirect
• Base vs. Index
• Auto increment and auto decrement• Auto increment and auto decrement
• Pre (post) increment/decrement
• Stack
RISC vs. CISCRISC vs. CISC
Reduced (vs. Complex) Instruction Set ( p )
Computer
• Uniformity of instructions
• Simple set of operations and addressing• Simple set of operations and addressing
modes
• Register based architecture with 3 address
instructions
RISC PhilosophyRISC Philosophy• 1970s John Cocke at IBM
• Majority of combinations of orthogonal addressing modes and instructions wereaddressing modes and instructions were not used B t t d b il–By most programs generated by compilers
• Difficult in many cases to write a compiler – To take advantage of the features providedTo take advantage of the features provided by conventional CPUs.
32
RISC examplesRISC examples• Virtually all new instruction sets since 1982 have been RISC– SUN’s SPARC (Scalable Processor ARChitecture)
– HP’s PA‐RISC
– ARM (Advance RISC Machine)
– Motorola’s PowerPC (Performance OptimizationWith Enhanced RISC Performance Computing,)
– DEC’s Alpha
– MIPS
– CDC 6600 (1960’s)