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SUB-TERAHERTZ SIGNAL GENERATION IN CMOS
By
DONGHA SHIM
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2011
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© 2011 Dongha Shim
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To the memory of my father
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ACKNOWLEDGMENTS
I would like to express my deep gratitude and appreciation to my advisor,
Professor Kenneth K. O, for his patient guidance and constant encouragement
throughout my doctoral research. Also much appreciation goes to Professor William R.
Eisenstandt, Professor Jing Guo and Professor David B. Tanner for their helpful
suggestions to my research. I would like to thank them for their interests in this work
and serving in my Ph.D. supervisory committee. I would like to thank all the former and
current colleagues in the SiMICS research group for their helpful discussions, advice
and friendship. Some names are listed here: Chikuang Yu, Haifeng Xu, Jau-Jr Lin, Yu
Su, Changhua Cao, Yanping Ding, Eun-Young Seok, Kwangchun Jung, Swaminathan
Sankaran, Hsin-ta Wu, Chuying Mao, Ning Zhang, Seon-Ho Hwang, Nallani Shashank
Kiron, Myoung Hwan Hwang, Zhe Wang, Wuttichai Lerdsitsomboon, Kyujin Oh, Tie Sun,
Minsoon Hwang, Ruonan Han, Gayathri Devi Sridharan, Choong-yul Cha, Yanghun
Yoon, Chieh-Lin Wu, Gyungsun Sul, Te-yu Kao, Yaming Zhang, Jing Zhang. Special
thanks go to Dr. Chih-Ming Hung at TI and Dr. Brian A. Floyd at IBM for their support on
chip design and fabrication. I am also thankful for those following peoples who greatly
helped my measurements: Dr. Daniel J. Arenas, Dimitrios Koukis, Dr. Jung-sik Hwang,
Professor Stephen Hill, Changhyun Koo, Saiti Datta, Professor Elliott R. Brown,
Jonathan Suen, Zachary D. Taylor, Dr. Vesselin Vassilev, Al Ogden. I am greatly
indebted to my family for their endless love, caring, and encouragement. Last but
foremost, I would like to thank God who gives me wisdom and strength to complete this
dissertation.
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TABLE OF CONTENTS page
ACKNOWLEDGMENTS.................................................................................................. 4
LIST OF TABLES............................................................................................................ 7
LIST OF FIGURES.......................................................................................................... 8
ABSTRACT ................................................................................................................... 12
CHAPTER
1 INTRODUCTION .................................................................................................... 14
1.1 Overview of Sub-terahertz Technology .......................................................... 14
1.2 Sub-terahertz Systems................................................................................... 15
1.3 Sub-terahertz Devices and Integrated Circuits in CMOS Technology............ 18
1.3.1 Sub-Terahertz CMOS Transistors ....................................................... 18
1.3.2 Terahertz Schottky Barrier Diode in CMOS Technology ..................... 20
1.3.3 Sub-terahertz CMOS Integrated Circuits ............................................. 21
1.4 Organization of the Dissertation ..................................................................... 23
2 CMOS SUB-TERAHERTZ DEVICES FOR FREQUENCY MULTIPLICATION....... 25
2.1 Motivation....................................................................................................... 25
2.2 Schottky Diode in CMOS Technology ............................................................ 25
2.3 Anti-Parallel Schottky Diode Pair in CMOS Technology................................. 27
2.3.1 Device Structure .................................................................................. 30
2.3.2 DC Measurements............................................................................... 33
2.3.3 RF Measurements ............................................................................... 33
2.4 Symmetric Varactor in CMOS Technology..................................................... 35
2.4.1 Device Structure .................................................................................. 38
2.4.2 Measurements and Results ................................................................. 41
2.5 Summary........................................................................................................ 49
3 CMOS SUB-TERAHERTZ DEVICES UNDER EXTREME ENVIRONMENTS........ 50
3.1 Motivation....................................................................................................... 50
3.2 Experiment Overview ..................................................................................... 52
3.3 Experimental Results ..................................................................................... 56
3.3.1 Low Temperature Dependence of CMOS devices .............................. 56
3.3.2 High Field Dependence of CMOS Devices at Liquid-Helium Temperature ........................................................................................ 65
3.4 Summary........................................................................................................ 66
4 CMOS SUB-TERAHERTZ FREQUENCY MULTIPLIER......................................... 70
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4.1 Motivation....................................................................................................... 70
4.2 150-GHz Frequency Tripler Using C-APDP ................................................... 70
4.2.1 Design Considerations ........................................................................ 70
4.2.2 Measurement Results.......................................................................... 74
4.3 Summary........................................................................................................ 80
5 CMOS SUB-TERAHERTZ FREQUENCY DIVIDER ............................................... 81
5.1 Motivation....................................................................................................... 81
5.2 194-GHz Injection Locked Frequency Divider ................................................ 81
5.2.1 Design Considerations ........................................................................ 81
5.2.2 Measurement Results.......................................................................... 91
5.3 Summary........................................................................................................ 92
6 CMOS SUB-TERAHERTZ FREQUENCY SOURCE .............................................. 96
6.1 Motivation....................................................................................................... 96
6.2 553-GHz Quadruple-push Oscillator .............................................................. 96
6.2.1 Design Considerations ........................................................................ 96
6.2.2 Measurement Results........................................................................ 105
6.3 Summary...................................................................................................... 112
7 SUMMARY AND FUTURE WORKS..................................................................... 113
7.1 Summary...................................................................................................... 113
7.2 Future Works................................................................................................ 115
APPENDIX
FTIR MEASUREMENT PARAMETERS...................................................................... 117
LIST OF REFERENCES ............................................................................................. 118
BIOGRAPHICAL SKETCH.......................................................................................... 126
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LIST OF TABLES
Table page 2-1 Performance Comparison................................................................................... 47
3-1 Summary of NMOS test structures ..................................................................... 55
3-2 Summary of diode test structures ....................................................................... 55
3-3 Summary of Van der Pauw and Kelvin test structures........................................ 55
3-4 Measured ideality factor of p-n junction diode (PND) and Schottky barrier diode (SBD)........................................................................................................ 65
4-1 Performance comparison ................................................................................... 80
5-1 Transistor sizes (L = 40 nm) ............................................................................... 86
5-2 Core inductor design parameters (µm) ............................................................... 86
5-3 Tuning varactor widths (L = 0.11 µm) ................................................................. 87
5-4 Transmission line lengths (µm)........................................................................... 87
5-5 194-GHz ÷4 frequency divider summary ........................................................... 92
6-1 Performance summary of sub-THz quadruple-push oscillator .......................... 111
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LIST OF FIGURES
Figure page 1-1 Terahertz gap [11]. ............................................................................................. 16
1-2 Sub-THz wave applications [12], [13]. ................................................................ 16
1-3 (a) Conventional optoelectronic spectrometer [14]. (b) Conventional electronic spectrometer [15]. .............................................................................. 17
1-4 Conceptual diagram of the sub-THz on-chip spectrometer in CMOS. ................ 19
1-5 Sub-THz signal generator................................................................................... 19
1-6 Projected performance requirements of NMOS transistors from 2008 International Road Map for Semiconductors [5] and the data from the literature. ............................................................................................................ 20
2-1 (a) Shallow trench separated Schottky barrier diode (STS SBD). (b) Polysilicon gate separated Schottky barrier diode (PGS SBD)........................... 26
2-2 Small signal equivalent circuit model of an n-type Schottky barrier diode. ......... 28
2-3 Simulated n-well resistance of unit-cell STS SBD. ............................................. 28
2-4 Simulated n-well resistance of unit-cell PGS SBD.............................................. 29
2-5 Scaling of STI thickness (tSTI) and gate length (Lg). ............................................ 29
2-6 Simplified nonlinear I-V characteristic of APDP. ................................................. 31
2-7 Schematic cross-section and configuration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d)), respectively. .............................................. 32
2-8 (a) Measured I-V characteristics of a C-APDP and SBDs. (b) Measured I-V and current mismatch factor (∆) of a C-APDP around zero bias voltage............ 34
2-9 (a) Test setup for harmonic power measurements. (b) The second and third harmonic powers generated by a C-APDP and an n-SBD. ................................ 36
2-10 Typical C-V characteristic of HBV diode varactor [39]. ....................................... 39
2-11 (a) Cross-section and (b) schematic of SVAR. (c) C-V characteristics of p-VAR, n-VAR, and SVAR..................................................................................... 40
2-12 Top view of unit-cell MOS varactor..................................................................... 42
2-13 Measured C-V characteristics of (a) MOS varactors and (b) MOS SVAR. ......... 43
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2-14 Test setup for harmonic power measurements................................................... 43
2-15 RF output power versus PIN at VNW = 2.8 V. ....................................................... 46
2-16 Third order harmonic output powers versus VNW. ............................................... 46
2-17 Fifth order harmonic output power versus VNW. .................................................. 48
2-18 SVAR operation conditions for different n-well bias voltages (VNW).................... 48
3-1 Basic principle of electron paramagnetic resonance (EPR) spectroscopy.......... 51
3-2 Cryostat with a superconducting magnet (Quantum Design PPMS) for millimeter-wave EPR spectroscopy [53]. ............................................................ 51
3-3 Van der Pauw (a) and Kelvin (b) test structure. .................................................. 53
3-4 Measurement setup............................................................................................ 54
3-5 Test chip mounted on a sample puck. ................................................................ 54
3-6 Two field orientations for the field dependence measurements.......................... 57
3-7 (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at different temperatures. ................................................... 58
3-8 NMOS drain current versus temperature............................................................ 58
3-9 (a) NMOS Transconductance (gm) versus gate voltage at varying temperatures. (b) Maximum transconductance (gm_max) versus temperature. .... 60
3-10 NMOS threshold voltage (Vt) versus temperature (VDS = 50 mV)....................... 61
3-11 Effective mobility versus temperature................................................................. 61
3-12 (a) Sheet resistance versus temperature. (b) Normalized sheet resistance versus temperature............................................................................................. 63
3-13 Contact resistance versus temperature. ............................................................. 64
3-14 I-V characteristics of p-n junction diode (PND) Schottky barrier diode (SBD) at varying temperatures...................................................................................... 64
3-15 Normalized drain current of NMOS versus magnetic field. ................................. 67
3-16 Normalized maximum transconductance versus magnetic field. ........................ 67
3-17 Normalized threshold voltage versus magnetic field........................................... 68
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3-18 Normalized effective mobility of NMOS versus magnetic field............................ 68
3-19 Cyclotron motion of electrons in the channel of NMOS. ..................................... 69
4-1 Operation principle of frequency multiplier. ........................................................ 72
4-2 Frequency tripler schematic................................................................................ 72
4-3 Cross-section (a) and layout (b) of C-APDP....................................................... 73
4-4 Measured and simulated I-V characteristic of the C-APDP. ............................... 73
4-5 Cross-section of GCPW. .................................................................................... 75
4-6 Top view of the bandpass filter. .......................................................................... 75
4-7 Die photograph of the frequency tripler. ............................................................. 75
4-8 Measured and simulated S-parameters.............................................................. 76
4-9 Measured output spectrum (PIN = 11 dBm at 50 GHz). ...................................... 76
4-10 On-wafer test setup for output power measurements......................................... 78
4-11 Measured conversion loss (CL) and output power (POUT) versus output frequency............................................................................................................ 79
4-12 Measured and simulated conversion loss (CL) and output power (POUT) at 150 GHz versus input power (PIN). ..................................................................... 79
5-1 Diagram of 194-GHz frequency divider with an input signal generator............... 82
5-2 Schematic of 194-GHz input signal generator. ................................................... 82
5-3 Schematic of 194-GHz ÷4 frequency divider. .................................................... 84
5-4 Core inductor of DIV1 (L3/L4). ............................................................................. 84
5-5 Floating dummy fills in the core inductor of DIV1................................................ 85
5-6 Cross-section of GCPW. .................................................................................... 85
5-7 Simulated input sensitivity curves of the frequency divider................................. 88
5-8 Die photograph of the frequency divider with the signal generator. .................... 88
5-9 Test board photograph. ...................................................................................... 89
5-10 On-wafer test setup for the frequency divider. .................................................... 90
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5-11 Frequency tuning ranges of DIV1 and DIV2 versus tuning voltages................... 90
5-12 Measured tuning range of SG, DIV1, and DIV2.................................................. 93
5-13 Measured locking range of the frequency divider. .............................................. 93
5-14 Measured phase noise of (a) the free-running and (b) injection locked divider. . 94
5-15 Measured spectrum of the injection pulled frequency divider. ............................ 95
6-1 (a) Simulated frequency response of Gmax and |h21|. (b) Simulated fmax and ft versus Vg. ........................................................................................................... 97
6-2 Simplified linear model of a quadrature oscillator. .............................................. 99
6-3 Schematic of quadruple-push oscillator schematic with an on-chip antenna...... 99
6-4 Simulated current waveforms in the oscillator. ................................................. 100
6-5 Quadruple-push operation. ............................................................................... 100
6-6 Simulated normalized output power (POUT/POUT(m0)) and frequency (fOUT) versus m (WCPL/WC). ........................................................................................ 102
6-7 Simulated return loss of the on-chip microstrip patch antenna. ........................ 102
6-8 Simulated peak gain and efficiency of the microstrip patch antenna for varying frequency. ............................................................................................ 103
6-9 Simulated gain pattern of the antenna.............................................................. 103
6-10 Quadruple-push oscillator die photograph........................................................ 104
6-11 Layout of interconnects between the core and coupling transistors. ................ 104
6-12 Test board photograph. .................................................................................... 106
6-13 FTIR setup for the output spectrum measurement. .......................................... 107
6-14 FTIR spectrum of a Mercury arc lamp in the atmosphere and vacuum. ........... 109
6-15 Measured spectrum of the radiated power. ...................................................... 109
6-16 Output power measurement setup. .................................................................. 110
6-17 Measured radiated power (PRAD) and output frequency (fOUT) versus bias current. ............................................................................................................. 111
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Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
SUB-TERAHERTZ SIGNAL GENERATION IN CMOS
By
Dongha Shim
May 2011
Chair: Kenneth K. O Major: Electrical and Computer Engineering
This dissertation investigates the feasibility of sub-terahertz (sub-THz) signal
generation using CMOS (Complementary Metal Oxide Semiconductor) technology. The
sub-THz portion of spectrum has remarkable properties especially suitable for sensing,
imaging, and communication applications. The recent progress of high-frequency
capability for CMOS has made it possible to consider the process as a new means to
overcome the limitations of cost and integration level of conventional sub-terahertz
systems.
Two novel non-linear devices, complementary anti-parallel diode pair (C-APDP)
and symmetric varactor (SVAR), were implemented in 130-nm digital CMOS process for
sub-THz frequency multiplier applications. The C-APDP employs both n-type SBD
(n-SBD) and p-type SBD (p-SBD) to eliminate the deleterious effects of substrate
parasitics. The device exhibited an extrapolated cutoff frequency of ~470 GHz. The
SVAR consists of a p- and n-type accumulation-mode varactor connected in parallel to
achieve symmetric C-V characteristics. The device showed the maximum cutoff
frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power
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measurements showed the effective generation of odd order harmonic powers while
suppressing even order ones.
To investigate the feasibility of operation of a sub-THz CMOS circuit in harsh
spectroscopy environments, CMOS devices are characterized under the low
temperature and high magnetic field. The temperature dependences of devices
including NMOS transistors, and p-n junction, and Schottky barrier diodes were
measured at 300, 150, 77, and 4.2 K. The field dependence of NMOS transistors is also
measured under magnetic fields up to 6 T at the liquid helium temperature. The
measured results indicated that CMOS circuits should have acceptable characteristics
in the cryogenic and high field spectroscopy environment.
The first sub-THz CMOS frequency tripler has been demonstrated using a
C-APDP. The tripler exhibited ~34-dB minimum conversion loss, -24-dBm maximum
output power at 150 GHz, and 3-dB output frequency range of ~10 GHz, which is ~10X
wider than that of a 140-GHz CMOS oscillator fabricated in 90-nm CMOS. To
demonstrate sub-THz frequency division in CMOS, a 194-GHz ÷4 frequency divider
has been implemented in 45-nm logic CMOS technology. Two cascaded ÷2 ILFD
stages are employed to divide ~194-GHz input signal in to ~48.5-GHz. A sub-THz
quadruple-push oscillator has been implemented using low leakage transistors in 45-nm
CMOS. Quasi-optical measurements showed that the circuit generates 4th harmonic
signal at 553 GHz with the power level of 220 nW, while suppressing unwanted
harmonic signals. These results provide the foundation for the eventual realization of
compact and affordable sub-THz systems using CMOS integrated circuits.
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CHAPTER 1 INTRODUCTION
1.1 Overview of Sub-terahertz Technology
The sub-terahertz (sub-THz) region is typically defined the portion of an
electromagnetic spectrum in the frequency range of ~100 GHz to ~1 THz. The waves in
this frequency range have remarkable properties especially suitable for sensing,
imaging, and communication applications [1], [2]. Until recently, however, the frequency
region has remained as a part of the last unexplored territory (so-called “THz gap” in
Figure 1-1) due to the lack of practical sources and detectors. With the advances of
photonic and electronic components, this part of spectrum is becoming more accessible
and newer applications for imaging, medical, industry, security, and communication are
emerging.
Sub-THz waves can penetrate through clothing, leather, papers, plastic, and many
other non-metallic materials. It is a suitable candidate for the detection of hidden
weapons including non-metallic ones. Unlike X-rays, sub-THz radiation is non-ionizing,
and should be safer for medical imaging and therapy applications. These technologies
are more accurate and economical compared to the other scanning methods such as
MRI (Magnetic Resonance Imaging), and PET (Positron Emission Tomography). This
emerging technology has the potential to revolutionize the way many diseases are
diagnosed and cured. Sub-THz wave is also useful for non-destructive and fast
inspections for industrial applications including those for pharmaceutical and
semiconductor industries.
Numerous organic molecules exhibit strong absorption and dispersion of sub-THz
radiation due to rotational and vibrational transitions. The ability of sub-THz to probe
15
intermolecular interactions makes sub-THz a unique spectroscopic tool for the
measurement of the unique spectral fingerprints of different chemical and physical
forms, permitting them to be imaged, identified, and analyzed. The ability has been
used to spectrally identify explosives and dangerous chemicals through clothing [2].
This is enabling a new paradigm in the fight against terrorism and detection of
suspicious or controlled substances.
The wide bandwidth offered by sub-THz wave links can also be used for short
range and high data rate indoor communication applications. The sub-THz
communications within rooms or buildings should be quite secure and exhibit strong
interference immunity. The beamlike properties of sub-THz wave can protect
communication signals from intercept. Battlefield communications among soldiers might
be interesting if sub-THz communication equipments can be made sufficiently compact,
light, and low-power consuming. Sub-THz wave applications are summarized in Figure
1-2.
1.2 Sub-terahertz Systems
As mentioned, spectroscopy is an important sub-THz application. Existing sub-
THz spectroscopy systems rely on complex assemblies of optical components or
discrete electronic components where the electronic devices are coupled together using
a bulky waveguide assembly as shown in Figure 1-3. For this reason, the systems cost
many tens to several hundreds of thousands of dollars. The use of CMOS technology to
implement highly integrated sub-THz systems can radically lower the cost and size by
eliminating the costly optical and discrete electronic components. The Integration of
transmitters, detectors, and on-chip antennas [3], as well as, baseband digital signal
processing (DSP) circuits, in CMOS should allow single-chip realization of compact and
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OpticsElectronics
Terahertz Gap
Figure 1-1. Terahertz gap [11].
Security
Medical
AstronomySpectroscopy
Industry
Communication
Imaging Sensing
Communication
Sub-THz
Figure 1-2. Sub-THz wave applications [12], [13].
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(a)
Circulator
Down Converter
Up Converter
Isolator
Waveguide
FrequencyDivider
Oscillator
PLL
Coupler
(b)
Figure 1-3. (a) Conventional optoelectronic spectrometer [14]. (b) Conventional electronic spectrometer [15].
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affordable THz systems. This should provide the engine that can drive the emergence
of moderate-to-high volume and low-to-moderate cost sub-THz applications.
A conceptual diagram of proposed frequency domain sub-THz CMOS
spectrometer is shown in Figure 1-4. A transmitter consists of a tunable sub-THz
frequency generator and an on-chip antenna. A receiver includes an on-chip antenna, a
detector or a mixer followed by a low noise amplifier/filter and an A/D converter (ADC).
Figure 1-5 shows a schematic of the sub-THz frequency generator that can be used in
the spectrometer. A high spectral purity sub-THz signal can be generated by a phase
locked loop (PLL) followed by a sub-THz frequency multiplier. A sub-THz frequency
divider, phase frequency detector (PFD), and low pass filter (LPF) comprise the phase
locked loop (PLL).
1.3 Sub-terahertz Devices and Integrated Circuits in CMOS Technology
1.3.1 Sub-Terahertz CMOS Transistors
Traditionally, digital CMOS technologies have not been seriously considered for
sub-THz frequency applications due to its limited maximum operation frequency. The
scaling of CMOS technology has resulted transistors in production which have cutoff
frequency (fT) and unity maximum available power gain frequency (fmax) of 360 and 450
GHz [4]. Figure 1-6 shows the projected requirements of fT’s and fmax’s for MOS, SiGe
Hetero-Junction bipolar (HBT), and III-V based transistors in current technologies. The
data have been extracted from the 2008 International Roadmap for Semiconductors [5].
The roadmap projects that the required performances of MOS transistors in
manufacturing will surpass those of production SiGe HBTs and III-V based transistors
despite the poorer intrinsic electronic properties of silicon. By year 2013, the projected
NMOS unity power gain frequency (fmax) requirement is ~510 GHz. Such transistors
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Sample
On-ChipAntenna/Resonator
OutputSpectrum
t
f0 f1 f2 f3 f4…
OutputSpectrum
t
f0 f1 f2 f3 f4…Schottky
DiodeHarmonic
Mixer
InputSpectrum
t
f0 f1 f2 f3 f4…
InputSpectrum
t
f0 f1 f2 f3 f4…
Low PassAmplifierSpectrum
Display
ADC
Sub-THz SignalGenerator
CMOS Technology
Figure 1-4. Conceptual diagram of the sub-THz on-chip spectrometer in CMOS.
PFD LPF
÷ N
REF X M
Sub-THzSignal Source
Sub-THzFreq Multiplier
Sub-THzFreq Divider
fREF
fOUT(N×M fREF)
PhaseFreq
DetectorReference
LowPassFilter
Figure 1-5. Sub-THz signal generator.
20
will provide greater flexibility to implement and improve circuits and systems operating
at sub-THz frequencies.
However, there has been a concern whether the CMOS technology scaling can
continue. The reports of a bulk transistor of a 65-nm technology [4] with fmax of 420 GHz
in 2006, and an SOI transistor of a 45-nm process with fT of 450 GHz [6] in 2007
suggest that the industry is keeping up with the ITRS.
1.3.2 Terahertz Schottky Barrier Diode in CMOS Technology
In the near term, at frequencies higher than ~400 GHz, it will be difficult to achieve
amplification using NMOS transistors. A way to deal with this is to use passive detectors
and frequency multipliers as routinely done in the sub-millimeter and THz communities
Figure 1-6. Projected performance requirements of NMOS transistors from 2008 International Road Map for Semiconductors [5] and the data from the literature.
21
[7]. Schottky barrier diodes (SBDs) are a promising candidate due to their high
operating frequencies and a low forward-voltage drop. The carrier transport in Schottky
diodes relies on the majority carrier conduction, in contrast to that in p-n junction diodes
where the carrier transport involves both the minority and majority carriers. Since there
are no minority carrier storage effects, SBDs are potentially capable of operation up to
the frequencies approaching the reciprocal of dielectric relaxation time of the
semiconductor crystal [8]. However the extrinsic series resistance and junction
capacitance typically limit the high frequency capability before reaching the limit set by
the dielectric relaxation.
Schottky diodes with cutoff frequency greater than 1 THz have been demonstrated
in 130-nm CMOS [9] and bipolar-CMOS (BiCMOS) technologies [10]. In the CMOS
implementation, the high cutoff frequency has been achieved by exploiting the device
scaling. The continued technology scaling provides opportunities to increase the diode
cutoff frequency up to several THz [9]. This has led to the exploration of diode detectors
[16], mixers, and frequency multipliers [17] fabricated in CMOS technology, which can
operate up to 1 THz.
1.3.3 Sub-terahertz CMOS Integrated Circuits
The viability of sub-THz operation of CMOS circuits has been shown by
demonstration of several components including oscillators, detectors, and phase-locked
loops. To overcome the limitation of maximum oscillation frequency (fmax) of CMOS
transistors, push-push techniques have been adopted to generate sub-THz signals.
Huang et al. [19] and Cao et al. [20] have utilized this technique to realize oscillators at
131 GHz and 192 GHz, respectively in 130-nm CMOS technology. Seok, et al. have
reported the generation of 410 GHz signal in 45- nm CMOS process [21]. The output
22
frequency of 410 GHz is the highest frequency for signals generated using transistors in
any technology, including those based on compound semiconductors. The operation
frequency can be increased further above fmax by linearly superimposing quadruple
phase shifted fundamental signals at one fourth of the output frequency. A 324-GHz
frequency generator in 90-nm CMOS process has been implemented using the
technique [22].
To examine the feasibility of a sub-THz CMOS detector, a 182-GHz Schottky
diode detector was implemented in 130-nm foundry CMOS [16]. The detector test signal
was generated on-chip by modulating the bias current of a push-push VCO. The
detector consists of a ~180-GHz RF matching network, a Schottky barrier diode, a low
pass filter with ~10-GHz corner frequency, and an amplifier for driving a 50-Ω load. THz
signals can also be detected by exciting plasma waves in the inversion layer of MOS
transistors [23]. An important advantage of plasma-wave THz detection is that its
operating frequency can exceed the frequency at which the transistor current gain is
unity. 780-GHz signals were detected by an NMOS plasma-wave detector [24]. The
responsivity is greater than 200 V/W. The minimum power of a signal with 1-Hz
bandwidth that can be detected is around 100 pW for a detector using NMOS
transistors fabricated in 130-nm CMOS.
Generation of free running high frequency signals by itself is not sufficient. The
signal must be stabilized using a phased locked loop (PLL). A fully integrated PLL
tunable from 45.9 to 50.5 GHz fabricated in 130-nm CMOS, which also outputs the
second order harmonic at frequencies between 91.8 and 101 GHz, has been
demonstrated in a 130-nm logic CMOS process [25]. The circuit utilizes an injection-
23
locked frequency divider (÷2) (ILFD) followed by a ÷512 static frequency divider to
achieve high-speed frequency division up to 50.5 GHz. The PLL including buffers
consumes 57 mW from 1.5/0.8-V supplies with the output power level around -10 dBm.
The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is 63.5, 72, and
99 dBc/Hz, respectively. Lee et al. has reported a 75-GHz phase-locked loop (PLL)
fabricated in 90-nm CMOS technology [26]. The circuit incorporates three-quarter
wavelength oscillators to achieve the high-frequency operation and a novel phase-
frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough.
The PLL demonstrates an operation range of 320 MHz and reference sidebands of less
than 72 dBc while consuming 88 mW from a 1.45-V supply. The operation frequency of
PLL could be pushed up further by using multiple ILFDs in a frequency divider chain. A
96-GHz PLL is fabricated in a 65nm CMOS process with a low power consumption of
43.7 mW from a 1.2 V supply. The PLL locks from 95.1 to 96.5 GHz [27]. The
demonstration of key components together with the continued scaling of CMOS
suggests the possibility for affordable CMOS THz systems in the near future.
1.4 Organization of the Dissertation
The solid blocks of the sub-THz generator in Figure 1-5 are demonstrated in the
dissertation. Two novel CMOS devices, complementary anti-parallel diode pair
(C-APDP) and symmetric varactor (SVAR), for sub-THz frequency multiplication are
demonstrated in Chapter 2. Non-linear behaviors of the devices are characterized by
DC, RF, and harmonic power measurements. Chapter 3 discusses the characterization
of CMOS devices in a magnet cryostat to investigate the feasibility of the operation of
sub-THz CMOS circuits in an extreme spectroscopy environment. The low temperature
24
and high field dependences of devices are characterized down 4.2 K and magnetic
fields up to 6 T. A 150-GHz frequency tripler implemented using a C-APDP in a 130-nm
CMOS technology is presented in Chapter 4. In Chapter 5, 194-GHz ÷4 frequency
divider is demonstrated in 45-nm logic CMOS using two cascaded injection locked
frequency dividers. Chapter 6 presents 553-GHz quadruple-push oscillator implemented
in 45-nm CMOS technology. The oscillator increases both the radiated power and
output frequency over the 410 GHz signal generation circuit [21]. Finally, the
dissertation is summarized and future works are suggested in Chapter 7.
25
CHAPTER 2 CMOS SUB-TERAHERTZ DEVICES FOR FREQUENCY MULTIPLICATION
2.1 Motivation
Two novel non-linear devices, complementary anti-parallel diode pairs (C-APDP)
and symmetric varactor (SVAR), were implemented in a 130-nm digital CMOS process
for sub-THz frequency multiplier applications. The C-APDP employs both n-type SBD
(n-SBD) and p-type SBD (p-SBD) to eliminate the deleterious effects from the substrate
parasitics. The device exhibited an extrapolated cutoff frequency of ~470 GHz. The
SVAR consists of a p- and n-type accumulation-mode varactor connected in parallel to
achieve symmetric C-V characteristics. The device showed the maximum cutoff
frequency of ~320 GHz and dynamic cutoff frequency of ~125 GHz. Harmonic power
measurements showed the effective generation of odd order harmonic powers while
suppressing even order ones.
2.2 Schottky Diode in CMOS Technology
Recently, two SBDs with a different configuration have been reported in logic
CMOS without any process modifications [18]. The cross-section of shallow trench
separated (STS) and poly-gate separated (PGS) SBD is shown in Figures 2-1(a) and
(b), respectively. The Schottky contact is formed on diffusion regions where there are no
source/drain implants. An ohmic contact placed on an n+ implanted n-well region form a
cathode. The cathode and anode of STS and PGS SBD is separated by a shallow
trench and polysilicon gate ring, respectively. A CoSi2-silicon Schottky junction has
been employed in a 130-nm CMOS process for both SBDs [9], [18]. Figure 2-2 shows a
small signal equivalent circuit of the n-type SBDs. The measured cutoff frequency
(fc = 1/2πRsCj0) of STS and PGS SBD is ~1.5 and ~2 THz, respectively. To minimize
26
STI STIn+
ILD
n+
p-substrate
ILD ILD ILD
n+ n+
n-well
STISTI
ILD
SchottkyJunction
STISeparator
CathodeAnode
wSTI
tSTI
Lj
tNW
Current
Contact
(a)
STI STIn+
ILD
CathodeAnode
n+
p-substrate
ILD ILD ILDILD
n+ n+
n-well
SchottkyJunction
Poly-SiSeparator
Lg
Current
Lj
Contact
(b)
Figure 2-1. (a) Shallow trench separated Schottky barrier diode (STS SBD). (b) Polysilicon gate separated Schottky barrier diode (PGS SBD).
27
Rs at given Cj0, the diode is formed by minimum area Schottky diode cells connected in
parallel. The unit-cell area of STS and PGS SBD is 0.32×0.32 and 0.4×0.4 µm2,
respectively. The cutoff frequencies of ~2 THz should allow fabrication of diode
detectors [16], mixers, and frequency multipliers [17] operating at 1 THz and higher in
CMOS.
Measurements show STS SBD has ~2-3X higher series resistance (RS) than PGS
SBD [9]. The n-well resistance of SBDs is responsible for a large portion of RS [9].
HFSS simulations have been performed to understand the cause of the difference in the
resistance. Figure 2-3 shows the unit-cell n-well resistance (rNW) of STS SBD for varying
thickness (tSTI) and width (wSTI) of the STI-ring. The simulated rNW shows strong
dependence on tSTI while slightly increasing with wSTI. Figure 2-4 shows the simulated
rNW of PGS SBD for a varying gate length (Lg). A smaller Lg results in shorter current
path through the n-well to reduce rNW as expected. The simulated rNW is 2.7 and 0.44 kΩ
for STS and PGS SBD, respectively for real design parameters. The smaller rNW of PGS
SBD would significantly reduce RS and improve the cutoff frequency. Figure 2-5 shows
scaling of gate length (Lg) and STI thickness for different technology nodes in bulk
CMOS. Unlike the gate length, STI thickness does not scale down with technology. For
this reason, the cutoff frequency of PGS SBD should scale better with technology
scaling due to the elimination of n-well region surrounded by the STI-ring in STS SBD.
2.3 Anti-Parallel Schottky Diode Pair in CMOS Technology
Anti-parallel diode pairs (APDPs) have been a critical component in circuits for
millimeter and sub-millimeter wave applications including frequency multipliers and
harmonic mixers [28]-[31]. A simplified nonlinear I-V characteristic of APDP is shown in
Figure 2-6. To implement a high frequency APDP, Schottky barrier diodes (SBDs) have
28
Figure 2-2. Small signal equivalent circuit model of an n-type Schottky barrier diode.
wSTI [µm]tSTI [µm]
r NW
[kΩ
]
Lj = 0.32 µmtNW = 1.5 µmσNW = 1750 S/m
Design: rNW = 2.7 kΩ @ tSTI = 0.35 µm, wSTI = 0.22 µm
HFSS Model
AnodeCathod
N-well
STI Ring
Figure 2-3. Simulated n-well resistance of unit-cell STS SBD.
29
0.3
0.4
0.5
0.6
0 0.2 0.4 0.6 0.8
Lj = 0.4 µmtNW = 1.5 µmσNW = 1750 S/m
Design: rNW = 0.44 kΩ @ Lg = 0.12 µm
r NW
[kΩ
]
Lg [µm]
HFSS model
Anode Cathod
N-well
Poly Ring
Figure 2-4. Simulated n-well resistance of unit-cell PGS SBD.
0.0
0.1
0.2
0.3
0.4
0.5
30 60 90 120 1500
50
100
150
t_STILg
Technology [nm]
t STI
[µm
]
L g[n
m]
tSTI
Lg
Figure 2-5. Scaling of STI thickness (tSTI) and gate length (Lg).
30
been widely used due to their high switching speed and lower forward voltage drop [32].
SBDs have often been fabricated with highly optimized processes on GaAs, InP, and
SiC substrates [33], [34].
Two types of SBDs, n- and p-type, depending on the doping type of semiconductor
are possible in CMOS. N-type SBDs (n-SBDs) have been used almost exclusively for
APDPs because electron mobility is higher in most of the widely studied semiconductors.
However, CMOS n-SBDs are not well suited for millimeter-wave APDPs due to the
associated parasitic n-well-to-substrate junction diode and its capacitance and
resistance in Figure 2-2. To mitigate this, a complementary APDP (C-APDP) using both
n- and p-SBD of CMOS is proposed to overcome the limitation of APDPs using only
n-SBDs (n-APDPs). The C-APDPs fabricated in a foundry 0.13-µm logic CMOS process
exhibit a third order harmonic generation capability that is ~25 dB higher than that of an
n-SBD.
2.3.1 Device Structure
Figures 2-7(a) and (c) show the cross-section and configuration of an n-APDP that
can be fabricated in CMOS. The n-well-to-substrate capacitance CSUB and the substrate
resistances RSUB can significantly degrade the harmonic conversion characteristics of
APDP especially at millimeter and sub-millimeter wave frequencies due to the
attenuation of a fundamental driving signal as well as generated harmonics. This
degradation due to CSUB and RSUB can be avoided by replacing the n-SBD2 responsible
for the parasitics with a p-SBD. The cutoff frequency of p-SBDs is ~80% of that for
n-SBDs [9], and use of a p-SBD in C-APDP should not significantly degrade the high-
frequency performance. The cross-section and configuration of C-APDP are shown in
Figure 2-7(b) and (d), respectively. Each n- and p-type SBD of C-APDP is composed of
31
V
I
VIN
(t)
IIN (t)V
I
VIN
(t)
IIN (t)
Figure 2-6. Simplified nonlinear I-V characteristic of APDP.
(a)
Figure 2-7. Schematic cross-section and configuration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d)), respectively. (Figure continues in the next page.)
32
(b)
(c) (d)
Figure 2-7. Schematic cross-section and configuration of an n-APDP ((a) and (c)) and the proposed C-APDP ((b) and (d)), respectively.
33
8 parallel cells. The area of unit Schottky diode cell is set to the minimum contacted
diffusion area of 0.32×0.32-µm2 allowed by the process. The other design and layout
details of the Schottky diodes are similar to that described in [9] except for the well
overlap.
2.3.2 DC Measurements
Figure 2-8(a) shows measured I-V (current-voltage) characteristics of a C-APDP,
and 8-cell n- and p-type SBDs. For both types of the SBDs, the ideality factor is about
1.1, and the reverse leakage currents are less than 0.5 µA at 2-V reverse bias. The
n-SBD has a turn-on voltage of 0.35 V, which is slightly higher than the absolute value
of turn-on voltage of 0.3 V for the p-SBD. Figure 2-8(b) shows I-V and current mismatch
around zero bias voltage. The current mismatch factor (∆ in Figure 2-8(b)) is defined as
the difference to sum ratio of the magnitude of currents at positive and negative voltage,
VC-APDP and –VC-APDP. The C-APDP has a good anti-symmetric characteristic with
modest current mismatch. An ideal APDP should have zero current mismatch. The
C-APDP has current mismatch less than 10%. This mismatch can be reduced by
optimizing the ratios of n- and p-SBD sizes.
2.3.3 RF Measurements
The one-port S-parameters of C-APDP were measured between 15 and 20 GHz
using an 8510C vector network analyzer [9]. The measured capacitances are around
7.3 fF, and the resistances increase from ~40 to ~55 Ω over the frequency range with
an average of 46 Ω. The cutoff frequency of C-APDP extrapolated from the
measurements [36], [37] is greater than 470 GHz, which should be sufficient for
millimeter-wave applications. This is lower than ~1 THz expected from [9] due to the use
of the logic instead of the mixed-mode technology and the smaller well overlaps for
34
10-2
10-4
10-6
10-8
10-10
-2 -1 0 1 2
C-APDPp-SBDn-SBD
VDIODE [V]
Abs
olut
e C
urre
nt [A
]
(a)
-10
-5
0
5
10
-0.3 -0.2 -0.1 0 0.1 0.2 0.3-20
-10
0
10
20
CurrentCurrent Mismatch
)()()()(
)(APDPCAPDPC
APDPCAPDPCAPDPC VIVI
VIVIV
−−
−−− −+
−−=∆
VC-APDP [V]
Cur
rent
(I) [
µA]
Cur
rent
Mis
mat
ch (Δ
) [%
]
))
APDPCAPDP-C
APDPCAPDP-CAPDPC VI()I(V
VI()I(V)∆(V
−
−− −+
−−=
(b)
Figure 2-8. (a) Measured I-V characteristics of a C-APDP and SBDs. (b) Measured I-V and current mismatch factor (∆) of a C-APDP around zero bias voltage.
35
C-APDP [9]. The n-APDP has an extrapolated cutoff frequency around 120 GHz with
measured CSUB of 41 fF and RSUB of 33 Ω [38].
To evaluate the harmonic generation of C-APDPs, the second and third harmonic
powers generated from a C-APDP and 16-cell n-SBD are compared at zero bias. As
mentioned the C-APDP utilizes 8-cell n- and p-SBDs. Figure 2-9(a) shows the
measurement setup. Due to the availability of components and instruments, the
harmonic generation was evaluated using a 900-MHz fundamental signal from an
Agilent 4421B signal generator. The generated harmonic power was measured using an
Agilent 8563E spectrum analyzer. The input and output are isolated using a diplexer
OML DPL.26 with a low (LPF) and high pass filter (HPF)
Figure 2-9(b) shows the measured power levels of second and third harmonics
generated by the C-APDP and n-SBD versus input power levels (Pin). As expected from
its I-V characteristics, the C-APDP generates more than 25 dB higher order third
harmonic power (Pout) than the n-SBD. An ideal APDP is not expected to generate even
order harmonics. However, the second harmonic powers are observed due to the
mismatch between n- and p-SBDs discussed earlier. A C-APDP using PGS SBDs is
also fabricated. The structure exhibits cut off frequency of ~660 GHz. Details of those
structures are presented in section 4.2 on a C-APDP frequency tripler.
2.4 Symmetric Varactor in CMOS Technology
Symmetric varactors (SVARs) have been a critical component for millimeter- and
sub-millimeter wave frequency multiplication [39]-[41]. The design of a frequency
multiplier is simplified using an SVAR since only odd harmonics of the pump signal are
generated, which makes even order harmonic idler circuits unnecessary [39]-[41].
36
(a)
-70
-50
-30
-10
-15 -10 -5 0 5 10
2fo, C-APDP3fo, C-APDP2fo, n-SBD3fo, n-SBD
2f0, C-APDP3f0, C-APDP2f0, n-SBD3f0, n-SBD
PIN [dBm]
f0 = 900 MHz
P OU
T[d
Bm
]
(b)
Figure 2-9. (a) Test setup for harmonic power measurements. (b) The second and third harmonic powers generated by a C-APDP and an n-SBD.
37
SVARs have often been implemented with highly optimized III-V devices such as
heterostructure barrier varactor (HBV) [39], [40] and anti-series Schottky diode varactor
(ASV) [41].
An accumulation-mode MOS (A-MOS) varactor has been extensively employed as
a tuning element especially in an LC-tank of a CMOS voltage controlled oscillator (VCO).
Increasing Q-factor of this varactor structure has received a great deal of attention [43]-
[45]. Recently, an A-MOS varactor with a cutoff frequency (fc = 1/2πRsCvar) greater than
2 THz has been reported in a foundry CMOS process [45].
SVARs in CMOS technology have been utilized as a differential tuning element for
common-mode noise rejection in VCOs [46], [47]. However, harmonic generation using
an SVAR has not been investigated. This section demonstrates an SVAR formed with
complementary A-MOS varactors can be used to generate third and fifth order
harmonics while suppressing even order generation. The device was fabricated in the
UMC 130-nm logic CMOS without any process modification. The varistor mode
operation of the C-APDP leads significant loss and could limit the efficiency of
frequency triplers. The use of MOS varactors for frequency multiplier applications is
investigated because reactive multipliers have a higher theoretical maximum efficiency
of 100%. This make the MOS varactor diodes potentially better suited for frequency
multiplier applications.
Figure 2-10 shows a typical C-V characteristic of HBV symmetric varactor (SVAR)
[48]. The symmetric varactor has symmetric capacitance-voltage (C-V) and anti-
symmetric current-voltage (I-V) characteristics [39]-[41]. Frequency multiplication or
harmonic generation occurs due to the nonlinear voltage dependent capacitance [49].
38
Mathematically, the C-V characteristic can be expressed as a power series given by
(2.1). The bias point is normally set to zero and only even order terms remain because
of the symmetry. With the current given in (2.2), only the odd order harmonic reactive
currents are generated in the device when driven by a sinusoidal voltage source. Once
again, the absence of even order harmonic currents can substantially simplify the
design of input and output filtering/matching networks in frequency multipliers.
t)cos(ωV∆V 0 0= (2.1)
+++++=
+∂
∂+
∂∂
+∂
∂+≅∆
===
K
K
66
44
220
6
0V6V
64
0V4V
42
0V2V
2
VV
∆VC∆VC∆VCC
∆VVC∆V
VC∆V
VC(0)CV)(C
(2.2)
dt
dV(t)(t)Cdtdt
dV(t)(V(t))Cdtd(V)dVC
dtd
atdQ(t)i(t) V
tV
VV ==== ∫∫ (2.3)
K
K
K
+++=+++=
+++≈
t5ωsinAt3ωsinAtωsinAtωsinVω)tωcosVCtωcosVC(C
dtdV(t))∆VC∆VC(Ci(t)
050301
000044
04022
020
44
220
(2.4)
where
...ωVC161A
...ωVC163ωVC
41A
...ωVC81ωVC
41ωVCA
05
045
05
0403
023
05
0403
020001
+=
++=
+++=
(2.5)
2.4.1 Device Structure
Figure 2-11(a) shows the cross-section of proposed SVAR in CMOS. A p-type (p-
VAR) and n-type A-MOS varactor (n-VAR) are connected in parallel to form the SVAR.
An on-chip bypass capacitor (CBP) and bias resistor (RBIAS) are used to bias the n-well of
39
CV
VIN∆V0
Cmin
-Vmax Vmax
Q(∆V)
Cmax
Figure 2-10. Typical C-V characteristic of HBV diode varactor [39].
(a)
Figure 2-11. (a) Cross-section and (b) schematic of SVAR. (c) C-V characteristics of p-
VAR, n-VAR, and SVAR. (Figure continues in the next page.)
40
(b)
(c)
Figure 2-11. (a) Cross-section and (b) schematic of SVAR. (c) C-V characteristics of p-VAR, n-VAR, and SVAR.
41
n-VAR. The schematic of the SVAR is shown in Figure 2-11(b). The p-VAR and n-VAR
have a monotonic transition in the C-V curves when the gate voltage (VG) is near 0 V
and the n-well bias voltage (VNW), respectively (Figure 2-11(c)). The symmetric C-V
curve is realized by combining the C-V curves of the p- and n-VAR. The C-V curve of
the SVAR is symmetric about VG = ~VNW/2, which is DC gate bias of the SVAR (VG_DC).
The shape of C-V curves can be varied by adjusting VNW to shift the C-V curve of n-VAR.
2.4.2 Measurements and Results
Test structures for p- and n-VAR of the SVAR composed of 12 parallel varactor
cells, as well as that for SVR using the n- and p-VARs are fabricated. A unit cell
varactor has a gate length of 0.18 µm and a finger width of 1.2 µm as shown in Figure
2-12 [45].
The measured C-V curves of p- and n-VARs are shown in Figure 2-13(a). The
one-port small-signal S-parameters of varactors were measured between 15 and 20
GHz using an 8510C vector network analyzer [50]. The measured tuning range
(maximum to minimum capacitance ratio) was 2.6 and 2.4 for the p- and n-varactor,
respectively. The capacitance mismatch (∆ in Figure 2-13(a)) of the varactors is less
than 4%. The measured breakdown voltage of the p- and n-VAR was greater than 4.8
and 4.4 V, respectively.
Figure 2-13(b) shows the measured C-V characteristics of the SVAR at varying n-
well bias voltages. For small VNW (VNW < 1.2 V), the dip in the C-V becomes deeper with
VNW until its bottom approaches the minimum capacitance of the SVAR (Cmin), which is
the sum of the minimum capacitance of p- and n-VARs. Further increases of the voltage
(VNW > 1.6 V) makes the dip wider with flat bottom capacitance of Cmin. The minimum
(Cmin) and maximum capacitance (Cmax) of the SVAR at VNW = 2.8 V is 31 and
42
Diffusion
Poly-SiContact/Via
Metal
L
W
L = 0.18 µmW = 1.2 µm
Figure 2-12. Top view of unit-cell MOS varactor.
10
20
30
40
50
-1.0 -0.5 0.0 0.5 1.0VG [V]
CV
AR [f
F]
-10
-5
0
5
10
Mis
mat
ch
n-VARp-VARMismatch
VG [V]
Cap
acita
nce
[fF] M
ismatch (∆) [%
]
n-VAR
( ))V(C)(VC)V(C)(VC
V∆GVAR-nGVAR-p
GVAR-nGVAR-pG −+
−−=
p-VAR
(a)
Figure 2-13. Measured C-V characteristics of (a) MOS varactors and (b) MOS SVAR. (Figure continues in the next page.)
43
30
40
50
60
70
-1 0 1 2 3Vg, V
Csv
ar, f
F
Vnw=0V Vnw=0.4VVnw=0.8V Vnw=1.2VVnw=1.6V Vnw=2.0VVnw=2.4V Vnw=2.8V
VG [V]
CS
VA
R[fF
]
VNW = 0.0 VVNW = 0.8 VVNW = 1.6 VVNW = 2.4 V
VNW = 0.4 VVNW = 1.2 VVNW = 2.0 VVNW = 2.8 V
30
40
50
60
70
-1 0 1 2 3Vg, V
Csv
ar, f
F
Vnw=0V Vnw=0.4VVnw=0.8V Vnw=1.2VVnw=1.6V Vnw=2.0VVnw=2.4V Vnw=2.8V
VG [V]
CS
VA
R[fF
]
VNW = 0.0 VVNW = 0.8 VVNW = 1.6 VVNW = 2.4 V
VNW = 0.4 VVNW = 1.2 VVNW = 2.0 VVNW = 2.8 V
(b)
Figure 2-13. Measured C-V characteristics of (a) MOS varactors and (b) MOS SVAR.
Figure 2-14. Test setup for harmonic power measurements.
44
53 fF, respectively with the complementary tuning range of 1.7. The maximum cutoff
frequency (fc,max = 1/2πRsCmin) is measured to be ~320 GHz with Cmin of 31 fF and
series resistance (Rs) of 16 Ω at VG_DC = 1.4 V and VNW =2.8 V. For a varactor multiplier,
the maximum conversion efficiency (η) can be estimated from the empirical expression
in (2.4) [51]. α and β are correlation factors extracted from detailed large-signal
simulations for a wide range of devices and circuit conditions. The efficiency is related
to the ratio of the pump frequency (fp) and the dynamic cutoff frequency (fcd) given in
(2.5). To maximize the efficiency, fcd should be maximized. The measured fcd of the
SVAR at VNW = 2.8 V is ~125 GHz with the average Rs of 17 Ω. The measured cutoff
frequencies suggest that the SVAR can operate up to millimeter-wave/sub-THz
frequencies.
%
ff
α1
100η β
td
p⎟⎟⎠
⎞⎜⎜⎝
⎛+
≈ (2.4)
minc,maxc,maxminS
cd ffC
1C
1Rπ2
1f −=⎟⎟⎠
⎞⎜⎜⎝
⎛−= (2.5)
Due to the limitations of instrumentation, the harmonic power generation was
evaluated at 900-MHz pumping frequency using a 50-Ω RF measurement set-up in
Figure 2-14 [50]. VG_DC was set to 1.4 V which is a half of applied VNW of 2.8 V. Figure
2-15 shows the measured output harmonic power (POUT) generated by the SVAR versus
input power levels (PIN). A larger SVAR with 216-cell p- and n-VAR is used to increase
the output harmonic power levels. The mismatch loss has been de-embedded to
compute PIN. As expected from its C-V characteristics, the generated third harmonic
powers are more than 25 dB higher than that of the even order harmonics. The SVAR
45
also generates considerable fifth order harmonic power which approaches that of the
third order ones at input power levels above 15 dBm. An ideal SVAR is not expected to
generate even order harmonics. However, the second and fourth order harmonics are
observed due to the mismatches in the C-V characteristic for p- and n-VARs. The
harmonic balance simulations were carried out using a model constructed with the
measurements of SVAR with 12-cell p- and n-VAR. The simulated third and fifth
harmonic powers in Agilent ADS showed reasonable agreement with the measurements
(Figure 2-15). The peak voltage across the gate oxide is estimated to be 1.5 V at PIN =
14 dBm in the simulation. The conversion loss can be reduced by properly impedance
matching the SVAR with the 50-Ω measurement set-up. Multi-harmonic load-pull
simulations [52] show that the minimum conversion loss (CLmin) of SVAR itself is 3.1 dB
at PIN = 2.6 dBm with the optimal termination impedance of 4.5+ j245 and 9.5+ j73 Ω at
900 MHz (f0) and 2700 MHz (3f0), respectively.
To better understand the applicability of A-MOS SVAR in the millimeter-wave
frequency range, additional simulations [52] were performed at the pumping frequency
(f0) of 50 GHz. VG_DC and VNW were set to 1.4 and 2.8 V, respectively. CLmin of 15.8 dB
was achieved for the third order harmonic power at PIN = 7.4 dBm with the optimal
termination impedance of 19.6+ j69.4 and 18.2+j26.0 Ω at 50 (f0) and 150 GHz (3f0),
respectively. CLmin for fifth order harmonic generation is 23.2 dB at PIN = 9.6 dBm. The
optimal termination impedance is 18.8+j82.1, +j40.0, and 16.7+j16.1 Ω at 50 (f0), 150
(3f0), and 250 GHz (5f0), respectively.
Figure 2-16 plots the third harmonic output power versus VNW at varying input
power levels. Optimal VNW bias to generate the maximum output harmonic power exists
46
-80
-60
-40
-20
0
-5 0 5 10 15
P2 P3P4 P5P3_sim P5_sim
PIN [dBm]
PO
UT
[dB
m]
2f03f04f05f0
Measurement (f0 = 900 MHz)
Simulation3f05f0
Figure 2-15. RF output power versus PIN at VNW = 2.8 V.
PIN = -8 dBmPIN = +4 dBm
PIN = -4 dBmPIN = +8 dBm
PIN = 0 dBmPIN = +12 dBm
PIN = -8 dBmPIN = +4 dBm
PIN = -4 dBmPIN = +8 dBm
PIN = 0 dBmPIN = +12 dBm
VNW [V]
PO
UT
[dB
m] @
3f0
-80
-60
-40
-20
0
0 1 2 3
f0 = 900 MHz
Figure 2-16. Third order harmonic output powers versus VNW.
47
for each input RF power level. A maximum POUT occurs at higher VNW as PIN increases.
The measured fifth order harmonic power showed similar behaviors (Figure 2-17). This
can be explained using the illustration in Figure 2-18 with a given RF input swing. For
small VNW (VNW = VL), the dip in the C-V curve increases with VNW, and this increases
the output harmonic powers. With a further increase of VNW, the dip reaches the
maximum depth, and has steep sidewalls and flat bottom (VNW = VM). The input RF
voltage should be sufficient to swing across the highly nonlinear C-V regions to
generate the maximum output harmonic powers. When VNW is further raised to make
the dip wider than the input RF voltage swing (VNW = VH), the generated harmonic
output power drops due to smaller capacitance variation (flat bottom portion of C-V
curve) over the RF input voltage. The optimal VNW for the maximum harmonic power
generation is about the half of peak to peak voltage swing across the SVAR in
simulations. The performance of AMOS SVAR is compared with that of the previously
reported frequency triplers using various SVARs in Table 2-1.
Table 2-1. Performance Comparison This Work [39] [40] [41]
Approach A-MOS HBV HBV ASV Cmax/Cmin 1.7 N/A 2.6 3.6 fcd [GHz] 125 1000 N/A N/A
CLmin [dB] 15.8* 10.5 8.2 < 15.2 fout [GHz] 150 141 113 210
Technology 130-nm CMOS GaAs InP GaAs * The minimum conversion loss of this work was estimated based on simulations [52].
48
-80
-60
-40
-20
0
0 1 2 3Vnw, V
P5,
dB
m
-4 dbm 0 dbm 4dbm8dbm 12dbm
VNW [V]
PO
UT
[dB
m] @
5f0
PIN = -4 dBmPIN = +8 dBm
PIN = 0 dBmPIN = +12 dBm
PIN = +4 dBmPIN = -4 dBmPIN = +8 dBm
PIN = 0 dBmPIN = +12 dBm
PIN = +4 dBm
f0 = 900 MHz
Figure 2-17. Fifth order harmonic output power versus VNW.
Figure 2-18. SVAR operation conditions for different n-well bias voltages (VNW).
49
2.5 Summary
Two novel CMOS devices for sub-THz frequency multiplication were proposed and
demonstrated in a foundry CMOS process. The C-APDP eliminates the deleterious
effects of parasitic n-well-to-substrate junction of n-APDPs. A C-APDP consisting of 8
cells of 0.32×0.32-µm2 n- and p-type SBDs exhibits an extrapolated cutoff frequency of
~470 GHz. The series resistance and capacitance of C-APDP is ~46 Ω and 7.3 fF. The
third order harmonic generation by the C-APDP is ~25 dB higher than that for an n-SBD.
As will be described in Chapter 4, the cutoff frequency of C-APDP is increased to ~660
GHz using poly-gate separated Schottky diodes.
A symmetric varactor for harmonic power generation was implemented in a
130-nm CMOS process. It consists of accumulation-mode p- and n-type MOS varactors
connected in parallel. The SVAR exhibits symmetric C-V characteristics with a
maximum cutoff frequency of ~320 GHz, and dynamic cutoff frequency of ~125 GHz.
The generated third order harmonic power levels are more than 25 dB higher than that
of the even order harmonics. The SVAR also generates significant fifth order harmonic
power at input power levels greater than 10 dBm. These suggest that the CMOS SVAR
is a good candidate device for implementation of X3 and X5 millimeter-wave frequency
multipliers that can be used to increase the output frequency range and lower phase
noise of millimeter wave signal sources. These suggest that CMOS C-APDP and SVAR
are good candidate devices for implementation of higher order sub-THz frequency
multipliers such as triplers (X3) and quintuplers (X5).
50
CHAPTER 3 CMOS SUB-TERAHERTZ DEVICES UNDER EXTREME ENVIRONMENTS
3.1 Motivation
An important sub-THz application is spectroscopy. Spectroscopy environments are
diverse, ranging from extremely low temperature lab environments, to outer space,
battlefields, etc. Building spectrometers operating in such extreme and remote
environments addresses a lot of challenges in engineering designs.
Electron Paramagnetic Resonance (EPR) spectroscopy is a good example of
spectroscopy in extreme environments [53]. It is one of the most popular techniques
with a wide range of applications in chemistry, physics, biology, and medicine. Figure
3-1 shows the basic principle of EPR spectroscopy. An unpaired electron can move
between the two energy levels by either absorbing or emitting electromagnetic radiation
of energy ∆E = hν. The energy gap is proportional to the applied magnetic field, and
higher magnetic field is used to resolve more resonances by widening the energy gap.
For this reason, the frequency (or energy) of microwave source should be high enough
to excite EPR transitions. The high-field/high-frequency EPR instrumentation provides
the ability to study very small samples and often provides extraordinary resolution and
discrimination among similar species.
In EPR spectroscopy, samples are often cooled down close to 0 K to get stable
spectra and study their temperature dependence. Therefore, EPR spectroscopy
employs a special cryostat with a superconducting magnet shown in Figure 3-2 [53].
Long rigid waveguides are used to deliver millimeter-wave power into a sample cavity
inside the cryostat. Because of this, a considerable transmission loss is unavoidable
due to the distance between the sample cavity in the magnetic field center and the top
51
Magnetic Field (B0)
Ener
gy (E
)
Absorption
h = Plank’s constantv = Frequencyg = g-factorβ = Bohr magnetonB0 = Magnetic filed
0Bβghν∆E ==
Figure 3-1. Basic principle of electron paramagnetic resonance (EPR) spectroscopy.
Millimeter-waveSource
Millimeter-waveDetector
Rigid Waveguides
Cavity Resonator
Figure 3-2. Cryostat with a superconducting magnet (Quantum Design PPMS) for millimeter-wave EPR spectroscopy [53].
52
of cryostat. The losses in waveguides account for a major part of the transmission loss
of the system. If the spectrometer can be miniaturized and deployed near a sample, the
EPR sensitivity can be significantly enhanced by reducing the transmission loss inside
the cryostat. This is an important advantage of on-chip spectrometers. However, those
extreme environments potentially can disturb the normal functionality of the
spectrometers. To examine the feasibility of sub-THz CMOS on-chip spectrometer
under extreme spectroscopy environments, the behaviors of devices available in CMOS
are characterized in an EPR spectroscopy environment. The temperature dependence
of the devices was measured at temperatures down to 4.2 K. To understand the field
dependence of NMOS transistors, measurements were also performed under magnetic
fields up to 6 T at the liquid helium temperature.
3.2 Experiment Overview
The measurements are performed at four different temperatures: 4.2, 77, 150, and
300 K. Table 3-1 shows the summary of NMOS test structures with three different gate
lengths (L). The summary of diode test structures is listed in Table 3-2. Table 3-3 shows
the summary of Van der Pauw and Kelvin test structures to measure sheet and contact
resistance, respectively. All the test structures are fabricated in a 90-nm foundry CMOS
process.
Figure 3-3(a) shows the Van der Pauw test structure used to measure the sheet
resistance (R ). The sheet resistance can be obtained using equation (3.1). IAB is
applied current between the pad A and B. VCD is the measured voltage between the pad
C and D. Figure 3-3(b) shows the Kelvin test structure used to measure the contact
resistance (RC). The size of n+/M1and M1/M2 contact (via) is 0.12×0.12 µm2 and
0.14×0.14 µm2, respectively. The sheet resistance can be obtained using equation (3.2).
53
A B
CD
E F
GH
Via/Contact
(a) (b)
Figure 3-3. Van der Pauw (a) and Kelvin (b) test structure.
Sample Puck
PPMS Magnet
Probe
Liquid He Reservoir
Computer
PPMS Dewar
SemiconductorParameterAnalyzer
(HP4155A)
PPMSController
MagneticField
A
B
D
C
Figure 3-4. Measurement setup. (Figure continues in the next page.)
54
A
B
D
Figure 3-4. Measurement setup.
C
Figure 3-5. Test chip mounted on a sample puck.
55
Table 3-1. Summary of NMOS test structures Test structure L [µm] W [µm]
NMOS-1 0.08 10.0 NMOS-2 0.5 10.0 NMOS-3 1.0 10.0
Table 3-2. Summary of diode test structures Test structure Cell Area [µm2] Ncell Area [µm2]
p-n junction diode (p+nn+) 0.4 x 0.4 12 1.92 Schottky barrier diode (PGS SBD) 0.28 x 0.28 16 1.25
Table 3-3. Summary of Van der Pauw and Kelvin test structures Test structure Conductor/Contact Thickness [µm]
Non-silicide poly 0.15 Non-silicide N+ N/A Silicide N-poly 0.15
Van der Pauw
M2 0.22 N+/M1 contact N/A
Kelvin M1/M2 contact (via) N/A
AB
DC
IV
ln2πR = (3.1)
FH
EGC I
VR = (3.2)
The measurement setup is shown in Figure 3-4. The Quantum Design PPMS
(Physical Property Measurement System) provides the low-temperature and high-
magnetic environment for the measurement. A test chip mounted on a sample puck is
shown in Figure 3-5. I-V characteristics of devices were measured using an HP 4155A
semiconductor parameter analyzer.
56
To characterize the magnetic field dependence of CMOS devices, NMOS
transistors are characterized in applied magnetic fields up to 6 T at the liquid helium
temperature (4.2 K). The measurements are performed for two different field
orientations shown in Figure 3-6. The vertical magnetic field (BV) is perpendicular to the
substrate while the horizontal one (BH) is parallel to the gate fingers and substrate.
3.3 Experimental Results
3.3.1 Low Temperature Dependence of CMOS devices
The low temperature characteristics of deep-submicron CMOS devices are
measured. Figure 3-7 shows the measured drain current (ID) versus drain voltage (VDS)
of NMOS transistors at different temperatures. Their current drive capability increases
for the same bias condition as the temperature decreases, indicating considerable
performance improvement at low temperature. It should be noted that obvious
anomalous kink phenomena and impurity freeze-out were not observed down to 4.2 K
due to the high doping level used in the sources and drains of deep submicron CMOS
transistors [54].
Figure 3-8 shows the temperature dependence of NMOS drain current at VG-Vt =
0.6 V for different gate lengths. Effective mobility (µeff) and saturation velocity (vsat) are
two important parameters that determine the drain current. The velocity saturation is
more dominant in a shorter channel device. Since µeff increases faster than vsat with
decreasing temperature, the drain current of a shorter channel NMOS shows less
temperature dependence. For the longest gate transistor (L = 1 µm), ID increases up to
~200% at 4.2 K.
57
Figure 3-6. Two field orientations for the field dependence measurements.
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0
Drain-Source Voltage (VDS) [V]
Dra
in C
urre
nt (I
D) [
mA
/µm
]
L = 0.08 µm
T = 300, 150, 77, and 4.2 KVG = 1V
T decrease
T decrease
L = 0.5 µm L = 1.0 µm
(a)
Figure 3-7. (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at different temperatures. (Figure continues in the next page.)
58
0.0
0.2
0.4
0.6
0.8
0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (VG) [V]
Dra
in C
urre
nt (I
D) [
mA
/µm
]T decrease
T decrease
L = 0.08 µmL = 0.5 µmL = 1.0 µm
T = 300, 150, 77, and 4.2 K VDS = 1V
(b)
Figure 3-7. (a) NMOS drain current (ID) versus drain voltage (VDS) and (b) drain current versus gate voltage at different temperatures.
0.0
0.5
1.0
1.5
2.0
0 100 200 3000
1
2
3
Dra
in C
urre
nt (I
D) [
mA
/µm
] Norm
alized Drain C
urrent(ID /ID
@300K )
VDS = 1 VVG-Vt = 0.6 V
Temperature [K]
L = 0.08 µmL = 1 µm
L = 0.5 µm
Figure 3-8. NMOS drain current versus temperature.
59
Figure 3-9(a) shows the temperature dependence of the NMOS transconductance
(gm) for different gate lengths. The transconductance of NMOS was obtained from the
slope of the ID-VG curves. Figure 3-9(b) shows the temperature dependence of the
maximum transconductance (gm_max). A longer channel device shows larger increase in
gm_max with decreasing temperature. For the longest gate transistor (L = 1 µm), gm_max
increases up to ~200% at 4.2 K compared to that at 300 K, which is similar to the drain
current increase.
Figure 3-10 shows the temperature dependence of NMOS threshold voltage (Vt).
The extrapolation in the linear region method is used for the extraction of Vt at VDS = 50
mV [55]. Vt changes with temperature due to the temperature dependence of Fermi
potential. Normally, the short-channel effect (SCE) decreases the MOSFET threshold
voltage as the channel length is reduced. However, a longer channel device is
measured to have a lower Vt due to halo or pocket implants that reduces SCE [56]. For
the longest gate transistor (L = 1 µm), Vt increased up to 80% at 4.2 K from that at
300 K.
Figure 3-11 shows the temperature dependence of the NMOS effective mobility
versus temperature in the strong inversion region. The mobility is extracted using the
method described in [57]. The mobility increases with decreasing temperature all the
way down to 4.2 K by a factor of ~3.5.
Figure 3-12(a) plots the temperature dependence of R for various conductors in
CMOS. The measured sheet resistances decrease with decreasing temperature for all
layers. In general, a layer with a smaller sheet resistance shows larger temperature
dependence. Figure 3-12(b) shows the temperature dependence of normalized sheet
60
0.0
0.5
1.0
1.5
0.0 0.2 0.4 0.6 0.8 1.0
Gate Voltage (VG) [V]
T decrease
T decrease
T = 300, 150, 77, and 4.2 KVDS = 1V
L = 0.08 µmL = 0.5 µmL = 1.0 µm
Tran
scon
duct
ance
(gm
) [m
S/µ
m]
(a)
0
1
2
3
0 100 200 300
T K
g,
0
1
2
gmno
rm
Temperature [K]
Norm
alized Max. Transconductance
(gm
_max /g
m_m
ax@300K )
Max
. Tra
nsco
nduc
tanc
e (g
m_m
ax) [
mS
/µm
]
VDS = 1 V
L = 0.08 µmL = 1 µm
L = 0.5 µm
(b)
Figure 3-9. (a) NMOS Transconductance (gm) versus gate voltage at varying temperatures. (b) Maximum transconductance (gm_max) versus temperature.
61
0.0
0.1
0.2
0.3
0.4
0.5
0 100 200 3001
2
3L=0.08um_Vt L=0.5um_VtL=1um_Vt L=0.08um_Vt_normL=0.5um_Vt_norm L=1um_Vt_norm
Temperature [K]
Thre
shol
d V
olta
ge (V
t) [V
]N
ormalized Threshold V
oltage(V
t /Vt@
300K )
L = 0.08 µmL = 0.5 µmL = 1 µm
VDS = 50 mV
Figure 3-10. NMOS threshold voltage (Vt) versus temperature (VDS = 50 mV).
0
200
400
600
800
1000
1200
0 100 200 3001
2
3
4
5
Temperature [K]
Effe
ctiv
e M
obilit
y (µ
eff)
[cm
2 /Vs] N
ormalized Effective M
obility (µ
eff /µeff@
300K )
VG-Vt = 0.6 V, VDS = 50 mV
Figure 3-11. Effective mobility versus temperature.
62
resistance. The silicided polysilicon and copper layers exhibit a typical temperature
dependence of a metal. The resistance of a metal increases linearly with temperature
above about 15 K due to the increase of electron-phonon interaction. As the
temperature is sufficiently reduced to freeze all the phonons, the resistance usually
reaches a constant value, known as the residual resistivity due to the effect of impurities
and crystal defects [58].
Figure 3-13 shows the resistances versus temperature. Both resistances decrease
with decreasing temperature. With decreasing temperature the contact resistance
decreased up to 30% at 4.2 K. The resistances should be acceptable for the 4.2 K
operation. These, however, indicate that the contact and other series resistance will
become more significant part of on resistance of a transistor at lower temperatures.
Figure 3-14 shows I-V curves of p-n junction diode (PND) and Schottky barrier
diodes (SBD) at varying temperatures. Ideality factors in Table 3-4 are calculated from
the slope of the curves in the low-injection region. The PND (p+nn+) shows typical
characteristic down to 77 K with an ideality factor (η) close to one. The ideality factor of
PND at 4.2 K is 40.5. This is perhaps due to the fact that the forward I-V characteristic
of Si p-n junction below 30 K is dominated by the thermionic emission of carriers over a
small energy barrier [60].
The SBD exhibits the higher ideality factors as listed in Table 3-4. Thermionic
emission is not the only mechanism for electrons to cross the potential barrier at a
Schottky junction. The quantum mechanical tunneling through the barrier has a
significant effect on I-V characteristic of a highly-doped SBD especially at low
temperatures [59]. It is particular significance in devices designed for cryogenic
63
0
20
40
60
80
100
120
0 100 200 3000.0
0.1
0.2
0.3
0.4
Non-silicide PolyNon-silicide N+ DiffSilicide PolyMetal
Temperature [K]
She
et R
esis
tanc
e (R
) [Ω
/] S
heet Resistance (R
) [Ω/
]Non-silicided polyNon-silicided n+ diffNon-silicided polyNon-silicided n+ diff
Silicided polyCopperSilicided polyCopper
(a)
0
0.2
0.4
0.6
0.8
1
1.2
0 100 200 300
Temp, K
Rsq
/Rsq
_300
K
Non-silicide PolyNon-silicide N+ DiffSilicide PolyCopper
Temperature [K]
Nor
mal
ized
She
et R
esis
tanc
e(R
/R@
300K
)
Non-silicided polyNon-silicided n+ diffSilicided polyCopper
(b)
Figure 3-12. (a) Sheet resistance versus temperature. (b) Normalized sheet resistance versus temperature.
64
0
10
20
30
0 100 200 3000.0
0.2
0.4
0.6
0.8
1.0
RcontRviaRcont/Rcont_300KRvia/Rvia_300K
Temperature [K]
Con
tact
(Via
) Res
ista
nce
(RC
(V))
[Ω]
Norm
alized Resistance
(RC
(V) /R
C(V
)@300K )
RCONT RVIARCONT/RCONT@300KRVIA/RVIA@300K
Figure 3-13. Contact resistance versus temperature.
1.E-08
1.E-06
1.E-04
1.E-02
1.E+00
1.E+02
0 0.5 1 1.5 2
Vf, V
Jf, m
A/u
m2 PND_300K
PND_150KPND_77KPND_4.2KSBD_300KSBD_300KSBD_77KSBD_4.2K
Voltage [V]
Cur
rent
Den
sity
[mA
/µm
2 ]
102
100
10-2
10-4
10-6
10-8
T decrease
T decrease
Figure 3-14. I-V characteristics of p-n junction diode (PND) Schottky barrier diode (SBD) at varying temperatures.
65
operation because as temperatures are lowered, the tunneling current component
becomes the dominant.
3.3.2 High Field Dependence of CMOS Devices at Liquid-Helium Temperature
Figure 3-15 shows the field dependence of the drain current normalized to the
zero-field value (ID/ID@0T). The current decreases with increasing vertical magnetic field.
The variation is larger in a longer channel device. However, negligible changes are
observed under the horizontal magnetic field (BH). For the longest gate transistor (L =
1 µm), the current decreased by ~15% at 6 T of vertical field. Figure 3-16 and 3-17
show the field dependence of the maximum transconductance (gm_max/gm_max@0T) and
the normalized threshold voltage (Vt/Vt@0T) with the maximum shift of ~8% and ~6%,
respectively at 6 T of vertical field. The normalized field dependence of the effective
mobility in a strong inversion region is shown in Figure 3-18. The mobility is reduced by
~25% at 6 T of the vertical field. These field dependences can be understood in terms of
the magnetoresistance associated with the cyclotron motion of electrons shown in
Figure 3-19 [61], [62]. The negligible field dependence at the horizontal field is due to
the strong gate electric field preventing the cyclotron motion. The field dependence of
NMOS can be avoided by positioning the integrated circuits along the orientation of
magnetic field.
Table 3-4. Measured ideality factor of p-n junction diode (PND) and Schottky barrier diode (SBD)
Temperature [K] Ideality factor (PND) Ideality factor (SBD) 300 1.04 1.57 150 1.04 2.70 77 1.05 4.79 4.2 40.5 106
66
3.4 Summary
Devices available in a 90-nm CMOS technology are characterized at the cryogenic
temperatures and high magnetic field levels of EPR spectroscopy environment. The
temperature dependences of NMOS transistors, diodes, sheet and contact resistances
were measured at 300, 150, 77, and 4.2 K. The list of measured device parameters
includes the drain current, transconductance, threshold voltage, and effective mobility.
The NMOS transistors showed no noticeable anomalous kink phenomena or impurity
freeze-out. Larger temperature dependences are observed in a longer channel device.
The p-n junction diodes showed the expected behavior down to 77 K with an ideality
factor close to one. Schottky barrier diodes have a high ideality factor due to the
significant tunneling current through the barrier. The temperature dependence of sheet
and contact resistances were characterized using Van der Pauw and Kelvin structures,
respectively. The magnetic field dependence of NMOS transistors is also characterized
at high magnetic fields up to 6 T at 4.2 K. Larger field dependences were observed in a
longer channel device. The cyclotron motion of the carriers under the magnetic field
accounts for the field dependent magnetoresistance.
The change of device characteristics is tolerable for implementation of CMOS
circuits operating in cryogenic temperature and high magnetic field environment. For
example, a compact on-chip EPR spectrometer in Figure 1-4 could be implemented
using sub-THz CMOS circuits.
67
0.85
0.90
0.95
1.00
1.05
0 2 4 60.90
0.95
1.00
1.05
1.10
1um_Bv 0.08um_Bv
0.5um_Bv 0.08um_Bh
0.5um_Bh 1um_Bh
Magnetic Field [T]
Norm
alized Drain C
urrent(ID /ID
@0T )
Nor
mal
ized
Dra
in C
urre
nt(I D
/I D@
0T)
L = 0.08 µmBH
L = 0.5 µmL = 1.0 µm
BV
L = 0.08 µmBH
L = 0.5 µmL = 1.0 µm
BV
VG-Vt = 0.6 V, VDS = 1 V
Figure 3-15. Normalized drain current of NMOS versus magnetic field.
0.92
0.94
0.96
0.98
1.00
1.02
0 2 4 60.96
0.98
1.00
1.02
1.04
1.06
gmm
axno
rm
0.08um_Bv 0.5um_Bv1um_Bv 0.08um_Bh0.5um_Bh 1um_Bh
Magnetic Field [T]
Norm
alized Max. Transconductance
(gm
_max /g
m_m
ax@0T )
Nor
mal
ized
Max
. Tra
nsco
nduc
tanc
e(g
m_m
ax/g
m_m
ax@
0T)
L = 0.08 µmBH
L = 0.5 µmL = 1.0 µm
BVL = 0.08 µm
BH
L = 0.5 µmL = 1.0 µm
BV
VDS = 1 V
Figure 3-16. Normalized maximum transconductance versus magnetic field.
68
0.92
0.94
0.96
0.98
1.00
1.02
0 2 4 60.96
0.98
1.00
1.02
1.04
1.06
0.08um_Bv 0.5um_Bv
1um_Bv 0.08um_Bh0.5um_Bh 1um_Bh
Magnetic Field [T]
Norm
alized Threshold Voltage
(Vt /V
t@0T )
Nor
mal
ized
Thr
esho
ld V
olta
ge(V
t/Vt@
0T)
L = 0.08 µmBH
L = 0.5 µmL = 1.0 µm
BVL = 0.08 µm
BH
L = 0.5 µmL = 1.0 µm
BV
VDS = 50 mV
Figure 3-17. Normalized threshold voltage versus magnetic field.
0.7
0.8
0.9
1.0
1.1
0 2 4 6
B, T
ueff_
norm
4.2K_Bv
4.2K_Bh
Magnetic Field [T]
Nor
mal
ized
Effe
ctiv
e M
obilit
y ( µ
eff/µ
eff@
0T)
BV
BH
VG-Vt = 0.6 V, VDS = 50 mV
Figure 3-18. Normalized effective mobility of NMOS versus magnetic field.
69
GateSource Drain
Magnetic field downward through the gate
Figure 3-19. Cyclotron motion of electrons in the channel of NMOS.
70
CHAPTER 4 CMOS SUB-TERAHERTZ FREQUENCY MULTIPLIER
4.1 Motivation
One of the common approaches for signal generation in the sub-THz frequency
range is use of a single or cascaded frequency multiplier(s) pumped by a high-power
oscillator [63] or amplifier operating at lower frequencies due to the difficulty of directly
generating the signals. Frequency triplers using an anti-parallel diode pair (APDP) have
been widely adopted for sub-THz signal generation [31], [64], [65]. Typically, frequency
triplers employ highly optimized compound semiconductor devices [31], [64], [65] often
mounted in bulky waveguide structures [65]. As mentioned, Schottky barrier diodes
(SBDs) with a cutoff frequency (fc) near 2 THz [18] and a complementary anti-parallel
diode pair (C-APDP) with fc of ~470 GHz [50] have been reported in foundry CMOS.
This chapter describes a polysilicon gate separated (PGS) C-APDP with cutoff
frequency of ~660 GHz. The C-APDP was utilized in a fully integrated frequency tripler
in 130-nm CMOS with output frequency of 150 GHz and a 10-GHz 3-dB output
frequency range. The output frequency range is ~10X larger than that of CMOS
oscillator circuits [20] and ~1.5X larger than that of a Schottky diode frequency doubler
fabricated in CMOS operating in the similar frequency range [17]. The 150-GHz output
frequency has been chosen for ease of accurate measurements using a calibrated
power sensor.
4.2 150-GHz Frequency Tripler Using C-APDP
4.2.1 Design Considerations
A frequency multiplier is composed of a nonlinear device and matching/filtering
networks at input and output as shown in Figure 4-1.The nonlinear device is driven by
71
an input signal source to generate harmonic powers. The input network should deliver
maximum fundamental power (P1) to the nonlinear device while blocking the generated
harmonic powers into the input port. Only desired harmonic power (PN) is transferred to
the output load through the output matching/filtering network.
A schematic of the C-APDP frequency tripler is shown in Figure 4-2. The tripler is
composed of a C-APDP and RF passive networks. Both n-type SBD (n-SBD) and
p-type SBD (p-SBD) are used in the C-APDP to eliminate the deleterious substrate
parasitic effects in an APDP using n-SBDs [50]. The C-APDP generates odd order
harmonics powers efficiently as demonstrated in Chapter 2. The passive networks
include grounded coplanar waveguides (GCPWs) [66] and an output bandpass filter
(BPF) to select the third order harmonic signal.
Figure 4-3(a) shows a cross-section of the PGS C-APDP [18]. The 0.4×0.4-µm2
unit cell Schottky contact is bounded by a 120-nm-wide polysilicon gate ring. To
maximize conversion efficiency, the size of C-APDP was optimized using harmonic
load-pull simulations [52]. The optimized C-APDP includes 48 n-SBD unit cells and 144
p-SBD cells connected in parallel as shown in Figure 4-3(b). The minimum conversion
loss of C-APDP itself is ~27 dB with the optimal termination impedance for the C-APDP
of 6.7+j22.0 and 3.5+j7.3 Ω at the input (f0) and output frequency (3f0), respectively.
Figure 4-4 plots the measured and simulated I-V curves of C-APDP. The measurements
and simulations agree well. The one-port S-parameters of C-APDP were measured
between 15-20 GHz using an 8510C vector network analyzer. The measured series
resistance (Rs) and zero-bias junction capacitances (Cjo) is 2.3 Ω and 105 fF,
respectively. This structure has fc of ~660 GHz compared to ~470 GHz of that using
72
Figure 4-1. Operation principle of frequency multiplier.
Figure 4-2. Frequency tripler schematic.
(a)
Figure 4-3. Cross-section (a) and layout (b) of C-APDP. (Figure continues in the next page.)
73
(b)
Figure 4-3. Cross-section (a) and layout (b) of C-APDP.
-30
-20
-10
0
10
20
30
-2 -1 0 1 21.E-06
1.E-04
1.E-02
1.E+00
1.E+02
I_fitI_measAbs(I_meas)Abs(I_fit)
VC-APDP [V]
10-6
10-4
10-2
100
102
I C-A
PD
P[m
A]
AB
S (IC
-AP
DP ) [m
A]
Rs = 2.3 ΩCjo = 105 fFfc = 660 GHzIs, n-SBD = 23 nAIs, p-SBD = 35 nAη n-SBD = 1.40η p-SBD = 1.35
MeasurementSimulationMeasurementSimulation
Figure 4-4. Measured and simulated I-V characteristic of the C-APDP.
74
shallow trench separated SBDs [50].
All transmission lines (t-lines) are implemented using a GCPW with characteristic
impedance of 48 Ω. The GCPW structure was chosen to isolate transmission lines from
a lossy silicon substrate and to reduce coupling between adjacent t-lines in the
networks. The cross-section of the GCPW is illustrated in Figure 4-5. The signal line is
formed by shunting an Al bond pad layer and a top copper layer (M8) together to reduce
the signal line loss [66]. 3-D EM simulations using HFSS show that the GCPW has an
effective permittivity (εeff) of ~3.2 with 0.6- and 1.2-dB/mm loss at 50 and 150 GHz,
respectively. A quarter-wave open-end stub (TL2) was used to reject the generated third
harmonic signal into the input port. The transmission lines, TL3, TL4 and TL5, were
designed to match the optimal input impedances of the C-APDP.
The output BPF was implemented using an open-end series stub [67]. The filter
exhibits 3.1-dB maximum loss between 140-160 GHz with the rejection better than 8.5
dB for signals below 50 GHz in HFSS simulations. The geometry and dimensions are
summarized in Figure 4-6. Figure 4-7 shows a die photograph of the chip fabricated in
the UMC 130-nm logic CMOS technology without any process modifications. The
GCPWs were folded to achieve a compact layout. A swept bend is employed to
minimize the effect of an excess parasitic capacitance at the bend [68]. The overall chip
size is 740×470 µm2 including bond pads.
4.2.2 Measurement Results
Figure 4-8 plots the measured and simulated small-signal S-parameters of the
frequency tripler from 40 to 110 GHz. An Agilent E8361A network analyzer was used for
the measurements. The measured input return loss (|S11|) is better than -8 dB between
75
Figure 4-5. Cross-section of GCPW.
Figure 4-6. Top view of the bandpass filter.
BPF
TL1TL2
C-APDPP1
P2TL3
TL4TL5
BPF
TL1TL2
C-APDPP1
P2TL3
TL4TL5
Figure 4-7. Die photograph of the frequency tripler.
76
-20
-15
-10
-5
0
40 50 60 70 80 90 100 110
Frequency [GHz]
S-p
aram
eter
[dB
]
S11_measurement S22_measurementS21_measurement S11_simulationS22_simulation S21_simulation
MeasurementSimulation
S11
S21
S22
-20
-15
-10
-5
0
40 50 60 70 80 90 100 110
Frequency [GHz]
S-p
aram
eter
[dB
]
S11_measurement S22_measurementS21_measurement S11_simulationS22_simulation S21_simulation
MeasurementSimulationMeasurementSimulation
S11
S21
S22
Figure 4-8. Measured and simulated S-parameters.
Figure 4-9. Measured output spectrum (PIN = 11 dBm at 50 GHz).
77
49 and 54 GHz. The output spectrum was measured using an OML G-band harmonic
mixer (M05HWD) and an Agilent E4448A spectrum analyzer. Figure 4-9 shows the
measured output spectrum at 150 GHz when the input power level at 50 GHz is 11 dBm.
Figure 4-10 shows the on-wafer test setup for output power measurements. The
input signal from the network analyzer (Agilent E8361A) in CW mode was amplified with
a Terabeam power amplifier chain, and then fed into the tripler through a GGB probe
(67A-GS-150P). The output powers were measured using GGB waveguide probes
(220-GSG-150 and 120-GS-150) and ELVA-1 power meters (DPM-06 and DPM-10).
Figure 4-11 shows conversion loss (CL) and output power (POUT) versus frequency for
three different input power levels (PIN).
The minimum CL of 34 dB and maximum output power of -24 dBm occur around
150 GHz. The 3-dB output frequency range is ~10 GHz between 145 and 155 GHz
when the input power level is higher than ~5 dBm. Figure 4-12 shows CL and the
second and third harmonic output powers versus PIN at 50-GHz input frequency. The
third harmonic output power (POUT @3f0) can be further raised above -24 dBm by
increasing the PIN above 11 dBm. The harmonic balance simulations of CL and output
powers in Agilent ADS show a reasonable agreement with the measurements (Figure
4-12). Due to the mismatch of anti-symmetric I-V of the C-APDP, an unwanted second
order harmonic (POUT @2f0) with a power level 10-13 dB below that of the third order
was observed. A second harmonic idler in a frequency tripler plays a critical role in
conversion of the energy from the fundamental to the third order harmonic frequency
[49]. The low conversion efficiency can be partially explained by the non-optimal
termination of the C-APDP at the idler frequency and the absence of the embedded
78
idler circuits [31]. Simulations show that a C-APDP with an optimal termination and idler
circuits can generate up to ~9-dB higher output powers. The forward conduction loss of
the C-APDP, which is inherent in a varistor mode operation [69], and the mistuned
PowerAmplifier
Chain
SignalSource
PowerMeter
DUT
G-BandWaveguide
Probe
V-bandCoaxialProbe
NetworkAnalyzer
A B C D
ABC
D
Figure 4-10. On-wafer test setup for output power measurements.
79
20
25
30
35
40
45
140 145 150 155 160 165
Output Frequency [GHz]
CL
[dB
]
-50
-40
-30
-20
-10
0
10
PO
UT [dB
m]
CL_1 dBmCL_5 dBmCL_9 dBmPout_1 dBmPout_9 dBmPout_8 dBm
PIN = 2 dBmPIN = 6 dBmPIN = 10 dBm
CL
[dB]
PO
UT
[dBm
]
20
25
30
35
40
45
140 145 150 155 160 165
Output Frequency [GHz]
CL
[dB
]
-50
-40
-30
-20
-10
0
10
PO
UT [dB
m]
CL_1 dBmCL_5 dBmCL_9 dBmPout_1 dBmPout_9 dBmPout_8 dBm
PIN = 2 dBmPIN = 6 dBmPIN = 10 dBm
PIN = 2 dBmPIN = 6 dBmPIN = 10 dBm
CL
[dB]
PO
UT
[dBm
]
Figure 4-11. Measured conversion loss (CL) and output power (POUT) versus output frequency.
30
35
40
45
50
-2 0 2 4 6 8 10 12-50
-40
-30
-20CL_MeasurementCL_SimulationPout_MeasurementPout_SimulationPout@2fo_MeasurementPout Simulation
CL
[dB
]P
OU
T[dB
m]
PIN [dBm]
MeasurementSimulation
POUT @3f0
POUT @2f0
30
35
40
45
50
-2 0 2 4 6 8 10 12-50
-40
-30
-20CL_MeasurementCL_SimulationPout_MeasurementPout_SimulationPout@2fo_MeasurementPout Simulation
CL
[dB
]P
OU
T[dB
m]
PIN [dBm]
MeasurementSimulation
POUT @3f0
POUT @2f0
Figure 4-12. Measured and simulated conversion loss (CL) and output power (POUT) at 150 GHz versus input power (PIN).
80
passive networks are also responsible for the high conversion loss. Due to the low
barrier height of SBDs, the output power starts to saturate at a lower input power level
[70]. The performance comparison with the previously reported frequency generators is
summarized in Table 4-1.
Table 4-1. Performance comparison This Work [64] [20] [17]
Approach Frequency Tripler
Frequency Tripler Oscillator Frequency
Doubler fOUT [GHz] 145-155 a 84-103 a 139-140.2 b 120-125 a
Min. CL [dB] 34 18 N/A 10 Max. POUT
[dBm] -25
( PIN = 11 ) -3
( PIN = 16 ) -19
-1.5 ( PIN = 8.5 )
Technology 130-nm CMOS GaAs 90-nm
CMOS 130-nm CMOS
Area [µm2] 740×470 1500×1000 540×360 1100×700 a 3-dB output frequency range and b Tuning range.
4.3 Summary
This chapter described the first C-APDP frequency tripler fabricated in a standard
digital CMOS process without any process modifications. The C-APDP was
implemented with the PGS SBDs and exhibited a cutoff frequency (fc) of ~660 GHz. A
maximum output power of -24 dBm was generated by the frequency tripler with 34-dB
minimum conversion loss at 150 GHz. The 3-dB output frequency range was measured
to be ~10 GHz. In the near term, Schottky diodes in CMOS can be used to generate
signals at sub-THz frequencies with a wider output frequency range well beyond that
can be supported using MOS transistor oscillators.
81
CHAPTER 5 CMOS SUB-TERAHERTZ FREQUENCY DIVIDER
5.1 Motivation
A frequency divider plays a critical block in the implementation of phase locked
loops (PLLs) for wireless and wireline communication systems. Generally, it can be
classified into three groups: flip-flop-based digital, regenerative, and injection-locked
frequency divider (ILFD). A conventional digital frequency divider is not suitable for sub-
THz frequency operation due to their moderate maximum operating frequency even
under high power consumption. A maximum speed of ~60 GHz has been reported in
65-nm CMOS [71]. A regenerative divider has not been popular in CMOS technology
due to complexities in implementation [72]. A 40-GHz Miller regenerative divider has
been demonstrated in 0.18-µm CMOS technology using resonance techniques but with
high power consumption [73]. An LC-based ILFD features high-frequency capability at
low power consumption [74]. Recently, direct ILFDs in CMOS boasted their high
operation capability at millimeter-wave frequencies [52], [75], [76]. A drawback of ILFDs
is narrow locking range due to the reliance on circuit oscillation. To demonstrate sub-
THz frequency division in CMOS technology, a 194-GHz ÷4 frequency divider using two
cascaded ILFDs has been implemented.
5.2 194-GHz Injection Locked Frequency Divider
5.2.1 Design Considerations
The diagram of the 194-GHz frequency divider is shown in Figure 5-1. It is
composed of two cascaded ÷2 ILFD stages to divide ~194-GHz signal in to ~48.5-GHz
one. Due to the limitations of instrumentation, a 194-GHz signal generator (SG) is
82
Figure 5-1. Diagram of 194-GHz frequency divider with an input signal generator.
Figure 5-2. Schematic of 194-GHz input signal generator.
83
integrated together to provide the input signal for the divider. A frequency doubled (~388
GHz) signal is also generated and radiated through an on-chip antenna. The radiated
signal could be detected using quasi-optical measurement [21].
Figure 5-2 shows the schematic of the signal generator implemented using a
cross-coupled differential LC-oscillator. One of the differential outputs is connected to
the input of divider for injection of a ~194-GHz signal. Two-stage buffers are used to
isolate the oscillator from external loads. The transistor sizes are listed in Table 5-1.
Matching and bias networks in the circuit are implemented using transmission lines (t-
lines). The shunt bypass capacitors connected to t-lines, CBP1, CBP2, and CBP3, are
implemented with the woven metal-oxide-metal structure [77]. Second order harmonic
currents in the oscillator are constructively added at the center tap of the inductor. The
push-push node (n0) is connected to an on-chip microstrip patch antenna for a quasi-
optical measurements [21].
Figure 5-3 shows the schematic of the 194-GHz ÷4 frequency divider. The first
(DIV1) and second ILFD (DIV2) are cascaded via an inter-stage buffer (ISF). The free-
running oscillation frequency of the first (DIV1) and second ILFD (DIV2) is ~97 and
~48.5 GHz, respectively. A differential inductor and cross-coupled transistor pair are
employed for LC-based oscillation. The size of all transistors in Figure 5-3 is listed in
Table 5-1. A single-turn circular inductor using the ~2.5-µm-thick Metal 7 layer (M7) is
employed for each ILFD. Figure 5-4 shows the layout of the differential inductor for DIV1.
In modern CMOS technologies, metal dummy fills are used to achieve a uniform metal
density for the CMP (Chemical Mechanical Polishing) process. Dummy fills adjacent to
an inductor line have a strong impact on Q-factor and SRF (Self Resonant Frequency)
84
Figure 5-3. Schematic of 194-GHz ÷4 frequency divider.
P3
Dummy Dummy
Dummy Dummy
P1 P2
Dummy
Dummy
dL
wL
Figure 5-4. Core inductor of DIV1 (L3/L4).
85
M1-M6Dummy
Poly-SiDummy
M7 Dummy
Figure 5-5. Floating dummy fills in the core inductor of DIV1.
Figure 5-6. Cross-section of GCPW.
86
[78]. A custom dummy filling technique is employed to block out dummy fills near the
inductor line. The inductor has a higher-density region around the center to meet the
metal density rules. Poly-silicon dummy fills are uniformly spread under the inductor.
Each dummy fill has a minimum area allowed by design rules. The size and density of
the dummy fills in M1-M6 layers is 0.4×0.4 µm2 and ~30%, respectively. Figure 5-5
shows the dummy fill patterns around the inductor line. HFSS simulations are performed
to model the inductor. A differential inductance (Ldiff) and Q-factor (Qdiff) of the inductor
are obtained from the simulated S-parameters using (5.1)-(5.4) [79]. The parameters of
the differential inductors, L3/L4 and L5/L6, are listed in Table 5-2.
2
S-S-SSS 21122211diff
+= (5.1)
⎟⎟⎠
⎞⎜⎜⎝
⎛ +=
diff
diff0dff S-1
S1Z2Z (5.2)
ω(Z ImL diff
diff)
= (5.3)
))
diff
diffdiff (Z Re
(Z ImQ = (5.4)
Table 5-1. Transistor sizes (L = 40 nm) M1/M2 M3 M4 M7/M8 M9 M11 M12/M13 M14
W [µm] 9.5 3.0 9.1 13.7 6.8 3.0 21.3 12.9
Table 5-2. Core inductor design parameters (µm) dL [µm] wL [um] Ldiff [pH] Qdiff SRF [GHz]
L3/L4 46 4 ~85 @100GHz
~15 @100GHz ~350
L5/L6 84 6 ~180 @50GHz
~20 @50GHz ~200
87
The injection transistors, M9 and M14, are biased through 4.5-kΩ silicide-block poly
resistors, RB1 and RB2. The coupling capacitors, CC1 and CC2, are implemented using
60-fF parallel plate capacitors. Two parallel binary-scaled varactor pairs for each ILFD
are tuned to enhance their locking range [25]. An accumulation-mode MOS structure is
employed with a non-minimum gate length (L = 0.11 µm) with a higher tuning ratio [43].
The varactor widths are listed in Table 5-3. The inter-stage buffer (ISB) between DIV1
and DIV2 is matched using t-line networks. All t-lines are implemented using GCPW
(Grounded Coplaner Waveguide) structure with characteristic impedance of 45 Ω [66].
The signal line is formed by an Al bond pad layer [66]. 3-D EM simulations using HFSS
show that the GCPW has an effective permittivity (εeff) of ~3.4 with 1.3-dB/mm loss at
100 GHz. The cross-section of the GCPW is illustrated in Figure 5-6. The t-line lengths
in the design are listed in Table 5-4. Two-stage output buffers are used to drive 50-Ω
measurement equipments. Figure 5-7 shows simulated input sensitivity curves of DIV1
for different bias voltages of the injection signal (VINJ_DC1). The divider has 4.4 GHz
(2.0%) at the injection power level of 0 dBm and VINJ_DC1 = 1.0 V. Figure 5-8 shows a
die photograph of the divider with the signal generator fabricated in a 45-nm digital
CMOS technology. The overall chip size is 1.1×1.3 mm2 including bond pads. The
frequency divider alone occupies 340×310 µm2.
Table 5-3. Tuning varactor widths (L = 0.11 µm) CV11/12 CV21/22 CV31/32 CV41/42
W [µm] 2.7 5.4 8.0 16.1
Table 5-4. Transmission line lengths (µm) TL1/TL2 TL3 TL4 TL5 TL6 TL7 TL8 TL9 TL10
95 110 100 70 70 80 70 120 110
88
-20
-10
0
10
210 215 220 225
Vg=1.0VVg=0.8VVg=0.9V
Frequency [GHz]
Inje
ctio
n Po
wer
[dBm
]
VINJ_DC1 = 1.0 V
VINJ_DC1 = 0.9 V
VINJ_DC1 = 0.8 V
VDD_DIV1 = 1.0 V
IB_DIV1 = 3.8 mA
Figure 5-7. Simulated input sensitivity curves of the frequency divider.
SignalGen.
On-ChipAntenna
DIV1
DC Bond Pads
fIN
fDIV1
fDIV2
DIV2
340 µm
310
µm
Figure 5-8. Die photograph of the frequency divider with the signal generator.
89
Chip
Bypass Capacitor
Figure 5-9. Test board photograph.
B
E F
SpectrumAnalyzer
SpectrumAnalyzerSpectrumAnalyzer
SpectrumAnalyzer
DC BiasBoard
DC PowerSupply
C
D
A
DUT
HM1HM3
HM2
PRB
1
PRB2
PRB
3
GGB 120-GS-150W-Band Waveguide ProbePRB2GGB 220-GSG-150G-Band Waveguide ProbePRB1Agilent 11970UU-Band Harmonic MixerHM3
GGB 67A-GS-150PV-Band Coaxial ProbePRB3
Agilent 11970WW-Band Harmonic MixerHM2OML M05HWDG-Band Harmonic MixerHM1
GGB 120-GS-150W-Band Waveguide ProbePRB2GGB 220-GSG-150G-Band Waveguide ProbePRB1Agilent 11970UU-Band Harmonic MixerHM3
GGB 67A-GS-150PV-Band Coaxial ProbePRB3
Agilent 11970WW-Band Harmonic MixerHM2OML M05HWDG-Band Harmonic MixerHM1
fIN
fDIV1
fDIV2
Figure 5-10. On-wafer test setup for the frequency divider. (Figure continues in the next page.)
90
E
F
B
AD
C
Figure 5-10. On-wafer test setup for the frequency divider.
46
48
50
52
54
0.0 0.2 0.4 0.6 0.8 1.092
94
96
98
100VCTRL31=0VVCTRL31=1VVCTRL21=0VVCTRL21=1V
f DIV
2[G
Hz]
f DIV
1[G
Hz]
fDIV2@VT3= 0VfDIV2@VT3= 1VfDIV1@VT1= 0VfDIV1@VT1= 1V
VT2 and VT4 [V]
Figure 5-11. Frequency tuning ranges of DIV1 and DIV2 versus tuning voltages.
91
5.2.2 Measurement Results
The chip is mounted and wirebonded to a test board as shown in Figure 5-9.
Figure 5-10 shows the detail on-wafer measurement setup. The output frequency of SG,
DIV1, and DIV2 (fIN, fDIV1, and fDIV2, respectively) was measured using millimeter-wave
probes and harmonic mixers followed by spectrum analyzers. Figure 5-11 shows the
measured free-running frequency of DIV1 and DIV2 for varying tuning voltages (VT’s).
The tuning range of SG, DIV1, and DIV2 is summarized in Figure 5-12. The figure
demonstrates that the tuning ranges of two dividers are well-aligned to cover the output
frequency range of the signal generation. Each divider block, DIV1, ISB, and DIV2,
draws 3.1, 0.7, 2.2 mA of current, respectively from a 1.0-V supply. The bias voltages of
injection signals, VINJ_DC1 and VINJ_DC2, are set to 1.0 V. The divider consumes 6 mW
excluding the output buffers.
The locking range of the frequency divider is measured by changing the output
frequency of the signal generator. The injection signal frequency could be tuned from
192.4 to 196.6 GHz. The free-running frequency of DIV1 and DIV2 (fDIV1_FR and fDIV2_FR)
is set to 97.0 and 48.5 GHz, respectively. The frequency divider loses lock as the
injection signal frequency is tuned above195.5 GHz. The frequency divider exhibited the
locking range of 3.1 GHz from 192.4 to 195.5 GHz as shown in Figure 5-13.
The phase noise of the frequency divider is dominated by that of the injection
signal for a small offset frequency from a carrier [80]. Figure 5-14 shows the measured
output phase noise of DIV2 with and without the injection signal. Both SG and DIV1
were turned-off to measure the phase noise of the free-running DIV2 in Figure 5-14(a).
The injection locked divider (Figure 5-14(b)) exhibits ~5-dB lower phase noise at 10
MHz offset.
92
Injection pulling occurs in LC-based ILFD if the injection signal frequency is close
to the limit of the locking range [81]. Figure 5-15 shows the measured spectrum of the
injection pulled frequency divider with the injection signal frequency slightly above the
locking range. The spectrum exhibits the typical fast beat behavior in an injection pulled
oscillator [81]. The performance of the divider is summarized in Table 5-5.
Table 5-5. 194-GHz ÷4 frequency divider summary Supply voltage 1.0 V
Power consumption* 6.0 mW
(6.0 mA/Total = 3.1 mA/DIV1 + 0.7 mA/ISB + 2.2 mA/DIV2
Locking range 192.4–195.5 GHz (1.6%)
Technology 45-nm Logic CMOS
(7 Metal layers) Area 340×310 µm2
* Excluding output buffers.
5.3 Summary
A 194-GHz frequency divider was implemented in 45-nm logic CMOS. Two ILFDs
are cascaded to perform ÷4 frequency division for the sub-THz input signal provided by
a built-in signal generator. The frequency divider exhibits a locking range of 3.1 GHz at
~194 GHz. The injection locking is also verified by observing the phase noise change
and injection pulling. These results suggest the feasibility of sub-THz phase locking at
low power consumption in CMOS.
93
185 190 195 200 205 210Frequency [GHz]
00 01 10 11
01 10 11
fIN
2fDIV1
4fDIV2
Frequency [GHz]
00
VT1(VT2)VT2(VT4)
1 V1 V110 V1 V101 V0 V010 V0 V00
VT1(VT2)VT2(VT4)
1 V1 V110 V1 V101 V0 V010 V0 V00
VT4VT3 =
VT2VT1 =
Figure 5-12. Measured tuning range of SG, DIV1, and DIV2.
192
194
196
198
3 6 9 1248.0
48.5
49.0
49.5fINfDIV2
Bias Current (IB_SG) [mA]
f IN[G
Hz]
f DIV
2[G
Hz]
fINfDIV2
VDD_SG = 1.4 VfDIV1_FR = 97.0 GHzfDIV2_FR = 48.5 GHz
Figure 5-13. Measured locking range of the frequency divider.
94
Carrier Freq = 48.47 GHzPN= -103.8 dBc/Hz @10MHz
(a)
Carrier Freq = 48.52 GHzPN= -108.7 dBc/Hz @10MHz
(b)
Figure 5-14. Measured phase noise of (a) the free-running and (b) injection locked divider.
95
fIN/4 = 48.84 GHz
Figure 5-15. Measured spectrum of the injection pulled frequency divider.
96
CHAPTER 6 CMOS SUB-TERAHERTZ FREQUENCY SOURCE
6.1 Motivation
N-push techniques have been employed to generate signals above the unity
maximum available gain frequency (fmax) of devices [21], [22], [82], [83]. Recently, a
1.3-THz signal has been generated in CMOS using the 6th harmonic of a 4-push
oscillator [83]. The signal is one of the unexpected harmonics. None of the power levels
of the circuit were available. In addition, the fourth order output power level was lower
than those of the first three harmonics.
This chapter reports a quadruple-push oscillator fabricated using low leakage
transistors of a 45-nm CMOS technology with improved 4th harmonic current generation
and suppression of unwanted harmonics. It radiates 220 nW of power at 553 GHz. The
output power is ~4X that radiated at 410 GHz in [21] which has been the highest
radiated from a CMOS circuit at frequencies above 400 GHz.
6.2 553-GHz Quadruple-push Oscillator
6.2.1 Design Considerations
A maximum operation frequency of an oscillator is limited by the unity maximum
available power gain frequency (fmax) of a transistor [84]. Figure 6-1(a) shows the
simulated frequency response of the maximum available power gain (Gmax) and unity
current gain (|h21|) of a 45-nm CMOS transistor. The peak fmax and ft of the device is
estimated to be 362 and 243 GHz, respectively. A simulated fmax and ft for various gate
bias voltages is plotted in Figure 6-1(b). A quadruple-push (4-push) technique is
devised to push output frequency substantially above the fmax of this device.
97
0
10
20
30
40
50
1 10 100 1000
Gmaxh21
Frequency [GHz]
Gai
n [d
B]
Gmax @ VG = 0.85 V|h21| @ VG = 1.1 V
fmax = 362 GHzft = 243 GHz
ft
NMOSW = 0.6×20 µmL = 40 nmVDS = 1.1 V
fmax
(a)
0
100
200
300
400
0.4 0.6 0.8 1.0 1.2
fmax ft
NMOSW = 0.6×20 µmL = 40 nmVDS = 1.1 V
Freq
uenc
y [G
Hz]
VG [V]
fmax ft
(b)
Figure 6-1. (a) Simulated frequency response of Gmax and |h21|. (b) Simulated fmax and ft versus Vg.
98
The 4-push signal generator is based on a quadrature oscillator [85]. Figure 6-2
shows a linear model of the quadrature oscillator. Gm and Gmc represents the
transconductance of cross-coupled core transistors (MC) and coupling transistors (MCPL),
respectively. Due to the combination of direct and inverted connection between two
oscillators, the output signals should have a quadrature phase offset to satisfy
Barkhausen criteria. Figure 6-3 shows the schematic of proposed 4-push oscillator with
an on-chip antenna. The harmonic currents ICPL in MCPL are added by a passive
combining network implemented with transmission lines. Instead of using a separate
linear phase combiner [22], this circuit utilizes the quadrature coupling transistors in the
oscillator core as the combiner. This reduces the capacitive loading of the LC tanks by
the gates of phase combiner circuit, which in turn allows the size of transistors in the
quadrature oscillator core to be increased for higher output power.
All transmission lines (t-lines) are once again implemented using grounded
coplanar waveguide (GCPW) with characteristic impedance of ~45 Ω [66]. The signal
line is formed using the Al bond pad layer with thickness of ~1.2 µm, and Metal 1 to
Metal 3 layers are shunted together for the bottom ground plane. 3-D EM simulations
using HFSS show that the GCPW has an effective permittivity (εeff) of 3.2 with 3-dB/mm
loss at 600 GHz. A single-turn circular inductor using ~2.5-µm thick Metal 7 layer (M7) is
employed for the LC tanks. The inductor has the outer diameter (dL) of 31.0 µm and
width (wL) of 2.8 µm. The custom floating dummy fills discussed in Chapter 5 are
employed for the inductor. HFSS simulations show the differential inductance (Ldiff) of 56
pH and Q-factor (Qdiff) of 14 at 150 GHz. The sources of MCPL (n1 node) are terminated
with a t-line matching network to maximize the power output at the 4th harmonic
99
Figure 6-2. Simplified linear model of a quadrature oscillator.
Figure 6-3. Schematic of quadruple-push oscillator schematic with an on-chip antenna.
100
frequency. The nodes n2 and n3 are potentially another nodes at which the 4th order
harmonic could be extracted. Simulations showed that the 4-push harmonic combining
at the node n2 and n3 results ~30 and ~50% lower output power, respectively than that
generated at the node n1. The node n3 would need long interconnects to the combining
network in a typical symmetric layout of a quadrature oscillator to keep core and
coupling transistors close together. The interconnects introduce additional losses and
increase the layout complexity of the circuit.
-5
0
5
10
15
1400 1405 1410 1415 1420-0.8
-0.4
0.0
0.4
0.8
I CP
L[m
A]
ICPL_I+ ICPL_I- ICPL_Q+ ICPL_Q- IOUT
I OU
T[m
A]
Time [ps]
VDD = 1.4 V IBIAS = 44mA
Figure 6-4. Simulated current waveforms in the oscillator.
I-
I+
I+
Q-Q+
Q- I+ I-
Q+ Q- I-
Q+I+
Q-Q+
I-
Fundamental(f0)
2nd harmonic(2f0)
3rd harmonic(3f0)
4th harmonic(4f0)
Figure 6-5. Quadruple-push operation.
101
Figure 6-4 shows simulated individual current waveform through MCPL and the
output node. They contain higher order harmonics due to the nonlinearities in the
oscillator. In the 4-push oscillator, only 4n-th (n = 1, 2, 3, …) order harmonics are
constructively combined while other harmonics cancel out as illustrated in Figure 6-5.
Increasing the coupling transistor width raises the output power and lowers output
frequency because of increased LC tank capacitance. Figure 6-6 shows the tradeoff
between POUT (power delivered to the on-chip antenna) and fOUT as function of WCPL to
WC ratio, m. The output power (POUT) saturates as m approaches one. The width of MC
and MCPL is set to be ~12 and ~7.5 µm, respectively with the minimum gate length of
40 nm. Device mismatches, parasitic inductive coupling, and layout asymmetries lead to
departure from the ideal quadrature generation in a quadrature oscillator [86]. The
phase error degrades image suppression capability of a wireless receiver with an
image-reject architecture. In the case of 4-push oscillator, the phase error reduces the
output power. To analyze the effect of phase error to the output power, additional
simulations are performed for the oscillator with 2% mismatch in the tank resonant
frequency of the I- and Q-oscillators. The output power degrades less than 2% for m
higher than 0.5 as shown in Figure 6-6. The level of frequency mismatch in real
quadrature oscillators is expected to be < 0.1%. The 4-push oscillator should have an
outstanding immunity to the phase error.
The on-chip antenna was implemented using a microstrip patch antenna [21]. The
aluminum pad layer is used to form the patch. The ground plane is formed by shunting
Metal 1 to Metal 6 layer. The thickness of each metal layer is ~0.2 µm. The separation
between the patch and ground plane is ~4 µm. HFSS simulations were performed to
102
0.0
0.5
1.0
1.5
0.0 0.5 1.0 1.5580
590
600
610
620
630
m (WCPL/WC)
w/o mismatchw/ mismatch
PO
UT/
PO
UT(
m0)
Design
f OU
T[G
Hz]
m = m0
Figure 6-6. Simulated normalized output power (POUT/POUT(m0)) and frequency (fOUT)
versus m (WCPL/WC).
-25
-20
-15
-10
-5
0
540 560 580 600 620 640 660
Frequency [GHz]
Ret
urn
Loss
[dB
]
HFSS Model
120 µm
160 µm
Figure 6-7. Simulated return loss of the on-chip microstrip patch antenna.
103
-4
-2
0
2
540 560 580 600 620 640 660
Frequency [GHz]
Peak
Gai
n [d
Bi]
0
10
20
30
Effic
ienc
y [%
]
Peak GainEfficiency
Figure 6-8. Simulated peak gain and efficiency of the microstrip patch antenna around the resonant frequency.
E-plane
H-plane
[dBi]
Figure 6-9. Simulated gain pattern of the antenna.
104
PatchAntenna
VDD
4-Push Oscillator
GND GNDVB
540 µm
530
µm
Figure 6-10. Quadruple-push oscillator die photograph.
MC1/MC2 MC3/MC4
MCPL2
MCPL1
MCPL4
MCPL3
Interconnects
Figure 6-11. Layout of interconnects between the core and coupling transistors.
105
analyze antenna performance. The antenna exhibits a good input match around 600
GHz as shown in Figure 6-7. Figure 6-8 shows a simulated peak gain and efficiency
around the resonant frequency. The peak gain and efficiency of the antenna is -0.2 dB
and 28%, respectively around 600 GHz. Simulated E- and H-plane gain pattern of the
antenna are plotted in Figure 6-9. An inset-feed structure is used for input impedance
matching. The patch size is 160×120 µm2. Figure 6-10 shows a die photograph of the
fabricated oscillator. The layout was optimized for symmetry to minimize mismatches.
Figure 6-11 shows the layout of interconnects between the core and coupling transistors
with an identical length. The overall chip size is 540×530 µm2 including bond pads. The
chip is mounted and wirebonded to a test board as shown in Figure 6-12.
6.2.2 Measurement Results
It is challenging to detect sub-microwatt signals above 500 GHz using electronic
instrumentation due to excessive loss [22]. Furthermore, no electronic probe is
presently available. In this work, a quasi-optical setup using the on-chip antenna and a
Fourier transform infrared (FTIR) spectrometer (Bruker ISF 113v) in Figure 6-13 is
employed [21]. A 23-µm-thick Mylar beam splitter was used in the FTIR. Detailed
measurement parameters are listed in Appendix. The oscillator spectrum is measured in
the atmosphere at room temperature. Due to the intense molecular rotational transitions
of water molecules, THz signals exhibit a strong atmospheric attenuation depending on
frequencies [90], [91]. The attenuation is corrected using the Mercury arc lamp
spectrum data measured in the atmosphere and vacuum (Figure 6-14). A strong
attenuation is observed at the typical water vapor absorption lines including ~558, ~753,
and ~989 GHz [92]. The atmosphere attenuation is measured to be ~50% at the output
frequency of the oscillator (553 GHz).
106
Chip
BypassCapacitor
Figure 6-12. Test board photograph.
Fixed Mirror
Bolometer
MovableMirror
Beam Splitter
FFT
ffOSC
fOSCIn
tens
ity
OSCfcλ =
On-chipPatch
Antenna
Michelson
Interferoemeter
4-PushOscillator
A
B
C
δ
δλ/2
Figure 6-13. FTIR setup for the output spectrum measurement. (Figure continues in the next page.)
107
C
B
AB
A
Figure 6-13. FTIR setup for the output spectrum measurement.
108
Figure 6-15 plots the measured output spectrum and radiated power (PRAD). The
oscillator generated an output signal at 553 GHz with the power level of 220 nW.
Harmonics up to 6th order (829.2 GHz) were observed. The power levels of all unwanted
harmonics are suppressed below 50 nW. The target operating frequency of the on-chip
antenna is ~47-GHz higher than the measured output frequency of the oscillator. The
frequency mismatch degrades input return loss and radiation efficiency of the antenna.
The radiated power is estimated to be 1.29 µW with an on-chip antenna tuned at the
measured oscillation frequency. The oscillator draws 46 mA of current from a 1.4-V
supply. The radiated power is measured using a liquid helium-cooled Si bolometer
(Infrared Laboratories HD-3) with responsivity of 4.0×104 V/W. A detail measurement
setup is shown in Figure 6-16. The oscillator was powered by 10-Hz square wave from
a waveform generator to modulate the radiated power. The output signal from the
bolometer was measured using a lock-in amplifier (Ithaco 393). Figure 6-17 plots the
measured radiated power and frequency versus bias current. The circuit starts to
oscillate at 12 mA and the radiated power monotonically increases with the bias current.
The output frequency varied ~0.5 GHz over the bias range. The performances of the
4-push oscillator are summarized in Table 6-1.
109
0
1
2
3
4
5
200 400 600 800 1000 1200
Frequency [GHz]
Inte
nsity
[a.u
.]VacuumAtmosphere
558.2
752.6
988.5988.
5 G
Hz
752.
6 G
Hz
558.
2 G
Hz
Figure 6-14. FTIR spectrum of a Mercury arc lamp in the atmosphere and vacuum.
0
50
100
150
200
250
100 300 500 700 900
5f0
552.8 GHz
2f0 3f0f0
Frequency [GHz]
P RA
D[n
W]
6f0
VDD = 1.4 VIBIAS = 46 mA
4f0
138.
2 G
Hz
276.
4 G
Hz
414.
6 G
Hz
691.
0 G
Hz
829.
2 G
Hz
Figure 6-15. Measured spectrum of the radiated power.
110
SignalGenerator
Bolometer
10 Hz
Oscilloscope4-Push
Oscillator
VDD
0V
A
BC
D
E
Lock-inAmplifier
VIN
VOUT
A
B
C D
E
VIN
VOUT
Figure 6-16. Output power measurement setup.
111
0
50
100
150
200
250
10 20 30 40 50552.0
552.5
553.0
PradFreq
Bias Current [mA]
f OU
T[G
Hz]
PR
AD
[nW
]
VDD = 1.4 V
Figure 6-17. Measured radiated power (PRAD) and output frequency (fOUT) versus bias current.
Table 6-1. Performance summary of sub-THz quadruple-push oscillator Output frequency 553 GHz Supply voltage 1.4 V
Radiated power (PRAD) 220 nW Antenna peak efficiency 28% (simulation)
Antenna peak gain -0.2 dBi (simulation) Estimated radiated power (PRAD)
w/ a tuned on-chip antenna 1.29 µW
Power consumption 64 mW
Technology 45nm Logic CMOS (7 Metal layers)
Chip area 540×530 µm2
112
6.3 Summary
A half-THz continuous wave signal was generated by a CMOS 4-push oscillator.
Since the forth harmonic current in a quadrature oscillator is directly added up by an
embedded combining network, the oscillator does not need a separate active harmonic
power combiner. The output signal is coupled to an optical instrument by an on-chip
antenna to detect 220-nW radiated power at 553 GHz. The well-suppressed unwanted
harmonic powers suggest that sufficient quadrature accuracy has been achieved in the
oscillator.
113
CHAPTER 7 SUMMARY AND FUTURE WORKS
7.1 Summary
This dissertation investigated the implementation of devices and building blocks
for sub-THz signal generation using digital CMOS (Complementary Metal Oxide
Semiconductor) technology. [42], [89].
Two novel non-linear devices, C-APDP [50] and SVAR [87], were implemented in
130-nm CMOS process for sub-THz frequency multiplier applications. Both devices
predominantly produce odd harmonics of an applied signal due to the anti-symmetric I-V
characteristics. To eliminate the deleterious effects from substrate parasitics both n-type
SBD (n-SBD) and p-type SBD (p-SBD) are used in the C-APDP. The C-APDP exhibited
the maximum extrapolated cutoff frequency of ~470 and ~660 GHz using STS and PGS
SBDs. The SVAR consists of p- and n-type accumulation-mode varactors connected in
parallel and shows symmetric C-V characteristics. The maximum and minimum cutoff
frequency is measured to be ~295 and ~175 GHz, respectively with a dynamic cutoff
frequency of ~120 GHz. Measurements of generated harmonic power showed the
absence of even order harmonics and presence of high levels of third and fifth
harmonics. This suggests that frequency triplers and quintuplers can be implemented
using the structure.
To investigate the feasibility of operation of CMOS circuit in EPR spectroscopy
applications, CMOS devices are characterized under the low temperature and high
magnetic field. The temperature dependences of NMOS transistors, diodes, sheet and
contact resistances are measured at 300, 150, 77, and 4.2 K. The NMOS transistors
exhibited no anomalous kink phenomena or impurity freeze-out. Larger temperature
114
dependences were observed in a longer channel device. A p-n junction diode exhibited
a expected behavior down to 77 K with the ideality factor close to one. Higher ideality
factors were measured in the Schottky barrier diodes due to the significant tunneling
current component through the barrier typical in a Schottky junction formed on a highly
doped semiconductor. Van der Pauw and Kelvin structures were used to measure the
temperature dependence of sheet and contact resistances, respectively. The magnetic
field dependence of NMOS transistors is also measured under high magnetic fields up
to 6 T at the liquid helium temperature. Larger field dependences were observed in a
longer channel device for the magnetic field perpendicular to the channel direction.
However, these indicate that CMOS circuits should have acceptable characteristics in
the cryogenic and high field environment for EPR spectroscopy.
The first complementary anti-parallel Schottky diode frequency tripler in CMOS
has been demonstrated in Chapter 4 [88]. The tripler exhibited ~34-dB minimum
conversion loss and -24-dBm maximum output power at 150 GHz. The measured 3-dB
output frequency range is ~10X wider than that of a 140-GHz CMOS oscillator
fabricated in 90-nm CMOS [20].
A 194-GHz ÷4 frequency divider using two cascaded injection-locked frequency
dividers (ILFDs) has been demonstrated in 45-nm CMOS. The locking range is
measured to be 3.1 GHz from 192.4 to 195.5 GHz. This circuit is the fastest CMOS
frequency divider with a division modulus greater than two. The frequency divider along
with the built-in signal generator suggests the feasibility of a sub-THz phase-locked loop
at low power consumption in CMOS.
115
A half-THz quadruple-push oscillator has been demonstrated using 45-nm logic
CMOS technology [93]. Quasi-optical measurements showed that the circuit generates
4th harmonic signal at 553 GHz with the power level of 220 nW, while suppressing
unwanted harmonic signals. The oscillator generates ~4X higher power at ~1.5X higher
frequency than the 410 GHz signal generator previously demonstrated in the same
process [21]. This circuit is the highest frequency oscillator with an identified power level
in CMOS.
7.2 Future Works
A varactor-mode sub-THz frequency multiplier would be implemented using the
symmetric varactor demonstrated in Chapter 2. The symmetric C-V characteristic of the
device makes even order harmonic idler circuits unnecessary in frequency tripler or
quintupler designs. Due to the mismatch in the anti-symmetric I-V of C-APDP, the
device generates considerable second harmonic powers. The conversion loss of
C-APDP frequency tripler in Chapter 4 would be improved by proper termination of
C-APDP at the second harmonic idler frequency.
The output power level from the sub-THz oscillator is still low for most real-world
applications. The output power could be increased by further optimization in design and
layout to minimize losses and parasitics in transistors, inductors, and t-lines. The
oscillator generated an output signal at 553 GHz while the on-chip microstrip patch
antenna was tuned to ~585 GHz. Since the antenna has a narrow bandwidth, the
operation at the non-resonant frequency results in a significant drop in radiation
efficiency. More output power should be radiated if the oscillator frequency is matched
to the resonant frequency of antenna. It would be interesting to develop a wideband
sub-THz antenna in CMOS to resolve the mistuning issue.
116
Many sub-THz systems need a signal source with a wide tuning range. The sub-
THz oscillator could incorporate a frequency tuning capability by adding accumulation-
mode MOS (A-MOS) varactors. A-MOS varactor has the highest Q-factor among CMOS
variable capacitors. However, loss of the device increases with operation frequency. An
A-MOS varactor potentially causes severe degradation in Q-factor and tunability of LC-
tank operating in the sub-THz frequency. It is essential to develop a CMOS tunable
device with a high-Q and high tuning range in the sub-THz region to realize a more
useful frequency source.
117
APPENDIX FTIR MEASUREMENT PARAMETERS
Optic Aperture Setting 3; 10 mm Beam splitter Mylar 23 um Detector Setting 1; DTGS/KBr (MIR) or BOLO High Pass Filter Open Low Pass Filter 7; 137 Hz Optical Filter Setting Black Polyethylene Scanner velocity 7; 12.5 KHz Signal Gain 1 Acquisition Acquisition Mode Single sided Delay Before Measurement 0 Stabilization Delay 4 Wanted High Freq Limit 700 Wanted Low Freq Limit 0 Sample Scans 64 Result Spectrum Transmittance Resolution 0.1 FT Apodization Function Norton-Beer, Medium Phase Resolution 10 Phase Correction Mode Mertz Zero Filling Factor 4 Instrument High Folding Limit 987.375 Low Folding Limit 0 Laser Wavenumber 15798 Absolute Peak Pos in Laser 5294 Sample Spacing Gain 1 Scan time (sec) 930.56 Peak Amplitude 919 Peak Location 153 Instrument Type IFS113 Running Sample Number 19568
118
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BIOGRAPHICAL SKETCH
Dongha Shim received his B.S. and M.S. degrees from Seoul National University,
Seoul, Korea, in 1996 and 1998, respectively. In 1998, he joined Samsung Advanced
Institute of Technology (SAIT), where he mainly worked on RF MEMS (Radio-
Frequency Micro-Electro-Mechanical-Systems) applications. Since 2005, he has been
pursuing the Ph.D. degree in electrical and computer engineering at the University of
Florida, Gainesville. His research interests are in the design and analysis of millimeter-
wave and sub-terahertz integrated circuits in CMOS (Complementary Metal Oxide
Semiconductor). He is a member of Eta Kappa Nu (HKN) and Tau Beta Pi (TBP).
