BYTE DATA LINK CONTROLLER (BDLC )

HCS12 Technical Training, Rev 2.0 Module 11- BDLC, Slide 1

MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.

BYTE DATA LINK

CONTROLLER

(BDLC )



Internal Bus

SCI1

256K FLASEEPROM

12K SRAM

ATD 1

HCS12 CPU

BKP INT MMI

CM BDM MEBI

4K BYTESEEPROM

SIM

msCAN3

msCAN2

msCAN1

SCI1

SPI 2or

PWMCH4-7

BDLCor

msCAN0

msCAN4or

IIC

SPI 1or

PWMCH 0-3

SPI 0

ATD 0

PIM PLL PIT

ECT 8CHAN

PWM 8CHAN



BDLCCONTROLLER

• SAE J1850 Compatible

• 10.4Kbps VPW bit format

• Digital noise filter

• Collision detection

• Hardware CRC generation & checking

• Receive and Transmit Block mode supported

• Supports 4X receive mode (41.6 Kbps)

• Digital loopback mode

• In-frame Response (IFR) Types 0, 1, 2, and

3 supported

• Power-Saving Stop and Wait modes with Automatic

Wakeup on Network Activity

• Interrupt Generation with Vector Lookup Table

FEATURES:



BDLC Block Diagram

Protocol Handler: responsible for encoding and decoding of data bits and special message symbols

CPU Interface: contains software addressable registers and provides link between CPU and Buffers

Rx/Tx Buffers: provide storage for data received and transmitted onto the J1850 bus

MUX Interface: provides link between the BDLC digital section and the analog Physical Interface

Physical Interface: performs wave shaping, driving and digitizing of data

To CPU

To J1850 Bus



OPERATING MODES

Power Off

Reset

Run

BDLC Stop BDLC Wait

No MCU reset source asserted

(WAIT instruction and WCM =0)

Network activity or other MCU wake-up

STOP Instruction or (WAIT instruction and WCM =1)

Network Activity or other MCU wake-up

Vdd > Vdd(Min) and any MCU reset source assertedVdd < Vdd(Min)

Any MCU reset source asserted(from any mode)

(COP,CM, RESET, POR)



BDLC BLOCK DIAGRAM

To CPU






To J1850 Bus



CPU Interface: contains software addressable registers and provides link between HCS12 CPU and Buffers

BDLC CPU Interface

BDLC Control Register 1 (DLCBCR1)

BDR Protocol handler (BDR)

User Registers

DLCBDLC Port Register (DLCSCR)

BDLC Analog Roundtrip Delay (DLCBARD)

BDLC Rate Select Register (DLCBRSR)

BDLC Port Direction (DLCBSTAT)

Address Offset $0000

$0001

$0002

$0003

$0004

$0005

$006

$0007

BDLC State Vector Register (DLCBSVR)

BDLC Control Register 2 (DLCBCR2)



–Ignore Message (IMSG)• Disables receiver until new Start of Frame (SOF) is detected• Cleared automatically by reception of SOF symbol or a BREAK symbol It then generates interrupt requests and will allow changes to the status register to occur• All BDLC interrupt requests will be masked when this bit is set

1 = Disable Receiver

0 = Enable Receiver

–Clock Select (CLKS)

• Selects BDLC Nominal Frequency (fbdlc)1 = Binary frequency (1.048576 MHz) is used for fbdlc

0 = Integer frequency (1 MHZ) is used for fbdlc

–Rate Select (R1, R0)• Determines the amount by which the frequency of the MCU system clock signal (fTCLKS) is divided to form the MUX

Interface clock (fbdlc)

³ Defines the basic timing resolution of the MUX Interface

–Interrupt Enable (IE) 1 = Enable Interrupt requests from BDLC0 = Disable Interrupt requests from BDLC

BDLC Control RegistersDLCBCR1 - BDLC Control Register 1

•Wait Clock Module (WCM)

–Determines operation of BDLC during CPU Wait mode1 = Stop BDLC internal clocks during CPU wait mode0 = Wait BDLC internal clocks during CPU wait mode




BDLC Rate Selection

BDLC Rate Selection for Binary FrequenciesBDLC Rate Selection for Integer Frequencies

DLCBRSR - BDLC Rate Select RegisterAddress Offset $0005



–State Machine Reset (SMRST)

1 = Arms the state Machine but does not reset BDLC

0 = Clearing SMRST after it has been set, causes BDLC to reset

–Digital Loopback Mode (DLOOP)

• Determines the source to which RXPD is connected and

can be used to isolate bus fault conditions

1 = RxPD is connected to TxPD, BDLC is now in Digital

Loopback Mode

0 = RxPD is connected to RxPA, BDLC is taken out of Digital

Loopback Mode

–Receive 4X Enable (RX4XE)• Determines if the BDLC operates at normal transmit and receive speed (10.4 kbps) or receive only at 41.6 kbps

1 = BDLC is put in 4X receive only operation0 = BDLC transmits and receives at 10.4 kbps Rx4x4 Defines the basic timing resolution of the MUX Interface

BDLC Control RegistersDLCBCR2 - BDLC Control Register 2

•Normalized Bit Format Select(NBFS)

–Control the format of the Normalization Bit (NB)

1 = NB that is received or transmitted is a ‘0’ when the response part of IN-Frame

Response (IFR) ends with a CRC byte.

0 = NB that is received or transmitted is a ‘1’ when the response part of IN-Frame

Response (IFR) ends with a CRC byte.

•Transmit End of Data (TEOD) –Set by programmer to indicate the end of a

message being sent by the BDLC

1 = Transmit EOD symbol0 = TEOD bit will be automatically cleared at

the rising edge of the first CRC bit that is sent , or if an error is detected




BDLC Frame Format

SOF - Start of Frame Symbol A message Frame always begins with a SOF symbol

Data – In Message Data BytesThe data bytes contained in the message include the messagepriority/type, message I.D. byte, and any actual data being transmittedto the receiving node.

CRC – Cyclical RedundancyThis byte is used by the receiver(s) of each message to determine if anyerrors have occurred during the transmission of the message.

EOD – End of Data SymbolThe EOD symbol is a long passive period on the J1850 bus used tosignify to any recipients of a message that the transmission by theoriginator has completed.

IFR – In Frame Response BytesThe IFR section of the J1850 message format is optional. Users desiringfurther definition of in-frame response should review the “SAE J1850

EOF – End of Frame SymbolThis symbol is a passive period on the J1850 bus, longer than an EOD symbol, which signifies the end of a message. Since an EOF symbol is longer than an EOD symbol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the message is assumed to be completed.The EOF flag is set upon receiving the EOF symbol.

IFS – Inter-Frame Separation SymbolThe IFS symbol is a passive period on the J1850 bus which allows proper synchronization between nodes during continuous message transmission. The IFS symbol is transmitted by a node following the completion of the EOF period.



Transmit In-Frame Response Control (TSIFR, TMIFR1, TMIFR0)

Transmit In-Frame Response Control Bit Priority Encoding

X X

0 0

1 X

0 1

0

0

1

0

0

0

0

1

0

1

0

0

WRITETMIFR1

WRITETMIFR0

ACTUALTSIFR

ACTUALTMIFR1

ACTUALTMIFR0

WRITETSIFR1

0

0

1

0

•Control the type of In-Frame Response being sent•Programmer should not set more than one of these control bits to a one at any given time

–If more than one of these three control bits are set to one, the priority encoding logic will force these register bits to a known value

Types of In-Frame Response



BDLC State Vector Register

BSVR I3 I2 I1 I0 Interrupt Source Priority

$00 0 0 0 0 No Interrupt Pending 0(lowest)$04 0 0 0 1 Received EOF 1$08 0 0 1 0 Received IFR byte (RXIFR) 2$0C 0 0 1 1 Rx Data register full (RDRF) 3$10 0 1 0 0 Tx data register empty (TDRE) 4$14 0 1 0 1 Loss of arbitration 5$18 0 1 1 0 CRC error 6$1C 0 1 1 1 Symbol invalid or out of range 7$20 1 0 0 0 Wakeup 8(highest)

• Decreases CPU overhead associated with servicing interrupts while under operation of a MUX protocol•It provides a index offset that is directly related to the BDLC’s current state, which can be used with a user

supplied jump table to rapidly enter an interrupt service routine

•Eliminates the need for the user to maintain a duplicate state machine in software.•I0, I1, I2, I3 - indicate the source off the interrupt request that is currently pending


DLCBDLC - State Vector Register



BDLC Data Register•Used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC•Used to pass data received from the J1850 bus to the CPU•DLCBDR is double buffered via a transmit shadow register and receive shadow register

BDLC Data RegisterDLCBDR - BDLC Data Register

DATA IN

DATA OUT

Receive Shadow Register

Rx Shift Register

RECEIVER:

• RDRF Flag sets each time new data is transferred from the Rx shift register to the Receive Shadow Register.

• TDRE Flag sets each time new data is transferred from the Transmit Shadow Register to the transmit Tx shift register.

Transmit Shadow Register

Tx Shift Register

DATA IN

DATA OUT

TRANSMITTER:




BDLC Analog Round Trip Register

BARD Offset Expected Delay [B3:B0] (us) 0000 9 0001 10 - - - - 1110 23 1111 24

RxPOL - Receive Pin Polarity 0 = Select Inverted Polarity 1 = Select Normal Polarity

DLCSCR - BDLC Control Register

BDLCE - BDLC Enable 0 = BDLC Pins are set for GPI/O 1 = BDLC Pins are set for BDLC Function



$0007

BO[3:0] Bit Encoding

DLCBSTAT - BDLC Status Register

IDLE 1 = BDLC received IFS (No Data being transmitted or received) 0 = BDLC is either transmitting or receiving

DLCBARD - BDLC Round Trip Delay Register



BDLC BLOCK DIAGRAM






To CPU

To J1850 Bus

BDLC Protocol Handler: Responsible for framing, collision detection,arbitration, CRC generation/checking, and error detection. It conforms to SAE J1850 - Class B Data Communications Network Interface.



State Machine

Rx Shift Register Tx Shift Register

Rx Shadow Register Tx Shadow Register

LoopbackMultiplexer

RxPTxP

DLOOP from BCR2loopback control Control

ControlTx Data

8

Rx Data

RxP TxP

8

PROTOCOL ARCHITECTURE

To Physical Interface

To CPU Interface & Rx/Tx Buffer’s



Error Condition BDLC Function

Bus short to Vbatt. The BDLC will not transmit until the bus is idle

Bus short to Gnd. Thermal overload will shutdown physical interface. Fault condition is reflected in BSVR as invalid symbol.

Invalid Symbol:BDLC receives invalid bits(noise)

The BDLC will abort transmission immediately. Invalid symbol interrupt will be generated

Framing Error

CRC error interrupt will be generated. The BDLC will wait for SOF.CRC Error

Invalid Symbol interrupt will be generated. The BDLC will wait for SOF.

BDLC Receives Break symbol The BDLC will wait for the next valid SOF. Invalid symbol interrupt will be generated

Invalid Symbol:BDLC send an EOD but receives

an active symbol.

Invalid symbol interrupt will be generated. The BDLC will wait for SOF.

BDLC J1850 BUS ERROR SUMMARY

Documents

BYTE DATA LINK CONTROLLER (BDLC )