CAO Pipelining Lecture

Appendix A - Pipelining *IntroductionA.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards Data Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations

Appendix A - Pipelining

Appendix A - Pipelining *What Is PipeliningLaundry ExampleAnn, Brian, Cathy, Dave each have one load of clothes to wash, dry, and foldWasher takes 30 minutes

Dryer takes 40 minutes

Folder takes 20 minutes


Appendix A - Pipelining *What Is PipeliningSequential laundry takes 6 hours for 4 loadsIf they learned pipelining, how long would laundry take? 3040203040203040203040206 PM7891011MidnightTask

OrderTime


Appendix A - Pipelining *What Is Pipelining Start work ASAPPipelined laundry takes 3.5 hours for 4 loads 6 PM7891011MidnightTask

OrderTime


Appendix A - Pipelining *Pipelining LessonsPipelining doesnt help latency of single task, it helps throughput of entire workloadPipeline rate limited by slowest pipeline stageMultiple tasks operating simultaneouslyPotential speedup = Number pipe stagesUnbalanced lengths of pipe stages reduces speedupTime to fill pipeline and time to drain it reduces speedup6 PM789Task

OrderTimeWhat Is Pipelining


Appendix A - Pipelining *MIPS Without PipeliningWhat Is PipeliningMemoryAccessWriteBackInstructionFetchInstr. DecodeReg. FetchExecuteAddr. CalcIRLMD


Appendix A - Pipelining *The Basic Pipeline For MIPSLatches between each stage provide pipelining.


Appendix A - Pipelining *The Basic Pipeline For MIPSInstr.

OrderFigure 3.3


Appendix A - Pipelining *Pipeline HurdlesA.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards -- Structural HazardsData Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle OperationsLimits to pipelining: Hazards prevent next instruction from executing during its designated clock cycleStructural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away)Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)Control hazards: Pipelining of branches & other instructions that change the PC Common solution is to stall the pipeline until the hazard is resolved, inserting one or more bubbles in the pipeline


Appendix A - Pipelining *Pipeline HurdlesDefinitionconditions that lead to incorrect behavior if not fixed Structural hazard two different instructions use same h/w in same cycle Data hazard two different instructions use same storage must appear as if the instructions execute in correct order Control hazard one instruction affects which instruction is next

Resolution Pipeline interlock logic detects hazards and fixes them simple solution: stall increases CPI, decreases performance better solution: partial stall some instruction stall, others proceed better to stall early than late


Appendix A - Pipelining *Structural HazardsWhen two or more different instructions want to use same hardware resource in same cycle

e.g., MEM uses the same memory port as IF as shown in this slide.

Figure 3.6


Appendix A - Pipelining *Structural HazardsThis is another way of looking at the effect of a stall.Figure 3.7


Appendix A - Pipelining *Structural HazardsThis is another way to represent the stall we saw on the last few pages.


Appendix A - Pipelining *Structural HazardsDealing with Structural Hazards Stall low cost, simple Increases CPI use for rare case since stalling has performance effectPipeline hardware resource useful for multi-cycle resources good performance sometimes complex e.g., RAM Replicate resource good performance increases cost (+ maybe interconnect delay) useful for cheap or divisible resources


Appendix A - Pipelining *Structural HazardsStructural hazards are reduced with these rules:Each instruction uses a resource at most once Always use the resource in the same pipeline stage Use the resource for one cycle onlyMany RISC ISAa designed with this in mind Sometimes very complex to do this. For example, memory of necessity is used in the IF and MEM stages. Some common Structural Hazards:Memory - weve already mentioned this one.Floating point - Since many floating point instructions require many cycles, its easy for them to interfere with each other. Starting up more of one type of instruction than there are resources. For instance, the PA-8600 can support two ALU + two load/store instructions per cycle - thats how much hardware it has available.


Appendix A - Pipelining *Data HazardsThese occur when at any time, there are instructions active that need to access the same data (memory or register) locations.

Where theres real trouble is when we have:

instruction Ainstruction B

and B manipulates (reads or writes) data before A does. This violates the order of the instructions, since the architecture implies that A completes entirely before B is executed.A.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards -- Structural HazardsData Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations


Appendix A - Pipelining *Data HazardsRead After Write (RAW) InstrJ tries to read operand before InstrI writes it

Caused by a Dependence (in compiler nomenclature). This hazard results from an actual need for communication.Execution Order is:InstrIInstrJ

I: add r1,r2,r3J: sub r4,r1,r3


Appendix A - Pipelining *Data HazardsWrite After Read (WAR) InstrJ tries to write operand before InstrI reads iGets wrong operand

Called an anti-dependence by compiler writers. This results from reuse of the name r1. Cant happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5

Execution Order is:InstrIInstrJ


Appendix A - Pipelining *Data HazardsWrite After Write (WAW) InstrJ tries to write operand before InstrI writes it Leaves wrong result ( InstrI not InstrJ )

Called an output dependence by compiler writers This also results from the reuse of name r1.

Cant happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in later more complicated pipesExecution Order is:InstrIInstrJ


Appendix A - Pipelining *Data HazardsSimple Solution to RAW

Hardware detects RAW and stalls Assumes register written then read each cycle + low cost to implement, simple -- reduces IPC Try to minimize stalls

Minimizing RAW stalls

Bypass/forward/shortcircuit (We will use the word forward)Use data before it is in the register + reduces/avoids stalls -- complex Crucial for common RAW hazards


Appendix A - Pipelining *Data HazardsThe use of the result of the ADD instruction in the next three instructions causes a hazard, since the register is not written until after those instructions read it.Figure 3.9


Appendix A - Pipelining *Data HazardsForwarding To AvoidData HazardForwarding is the concept of making data available to the input of the ALU for subsequent instructions, even though the generating instruction hasnt gotten to WB in order to write the memory or registers.Figure 3.10


Appendix A - Pipelining *Data HazardsThere are some instances where hazards occur, even with forwarding.The data isnt loaded until after the MEM stage.Figure 3.12


Appendix A - Pipelining *Data HazardsThere are some instances where hazards occur, even with forwarding.The stall is necessary as shown here.Figure 3.13


Appendix A - Pipelining *Data HazardsThis is another representation of the stall.

LW R1, 0(R2)IFIDEXMEMWBSUB R4, R1, R5IFIDEXMEMWBAND R6, R1, R7IFIDEXMEMWBOR R8, R1, R9IFIDEXMEMWB

LW R1, 0(R2)IFIDEXMEMWB SUB R4, R1, R5IFIDstallEXMEMWBAND R6, R1, R7IFstallIDEXMEMWBOR R8, R1, R9stallIFIDEXMEMWB


Appendix A - Pipelining *Data HazardsInstruction scheduled by compiler - move instruction in order to reduce stall. lw Rb, b code sequence for a = b+c before scheduling lw Rc, c Add Ra, Rb, Rc stall sw a, Ra lw Re, e code sequence for d = e+f before scheduling lw Rf, f sub Rd, Re, Rf stall sw d, Rd

Arrangement of code after scheduling. lw Rb, b lw Rc, c lw Re, e Add Ra, Rb, Rclw Rf, f sw a, Ra sub Rd, Re, Rfsw d, RdPipeline Scheduling


Appendix A - Pipelining *Data HazardsPipeline Scheduling


Appendix A - Pipelining *Control HazardsA control hazard is when we need to find the destination of a branch, and cant fetch any new instructions until we know that destination.A.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards -- Structural HazardsData Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations


Appendix A - Pipelining *Control Hazard on BranchesThree Stage StallControl Hazards


Appendix A - Pipelining *Branch Stall ImpactIf CPI = 1, 30% branch, Stall 3 cycles => new CPI = 1.9!(Whoa! How did we get that 1.9???)Two part solution to this dramatic increase:Determine branch taken or not sooner, ANDCompute taken branch address earlier

MIPS branch tests if register = 0 or ^ 0

MIPS Solution:Move Zero test to ID/RF stageAdder to calculate new PC in ID/RF stagemust be fast can't afford to subtract compares with 0 are simple Greater-than, Less-than test signbit, but not-equal must OR all bits more general compares need ALU 1 clock cycle penalty for branch versus 3

In the next chapter, well look at ways to avoid the branch all together.Control Hazards


Appendix A - Pipelining *Five Branch Hazard Alternatives#1: Stall until branch direction is clear

#2: Predict Branch Not TakenExecute successor instructions in sequenceSquash instructions in pipeline if branch actually takenAdvantage of late pipeline state update47% MIPS branches not taken on averagePC+4 already calculated, so use it to get next instruction

#3: Predict Branch Taken53% MIPS branches taken on averageBut havent calculated branch target address in MIPSMIPS still incurs 1 cycle branch penaltyOther machines: branch target known before outcomeControl Hazards


Appendix A - Pipelining *#4: Execute Both Paths

#5: Delayed BranchDefine branch to take place AFTER a following instruction branch instruction sequential successor1 sequential successor2 ........ sequential successornbranch target if taken 1 slot delay allows proper decision and branch target address in 5 stage pipelineMIPS uses thisBranch delay of length nControl HazardsFive Branch Hazard Alternatives


Appendix A - Pipelining *Delayed BranchWhere to get instructions to fill branch delay slot?Before branch instructionFrom the target address: only valuable when branch takenFrom fall through: only valuable when branch not takenCancelling branches allow more slots to be filled Compiler effectiveness for single branch delay slot:Fills about 60% of branch delay slotsAbout 80% of instructions executed in branch delay slots useful in computationAbout 50% (60% x 80%) of slots usefully filled

Delayed Branch downside: 7-8 stage pipelines, multiple instructions issued per clock (superscalar)Control Hazards


Appendix A - Pipelining *Evaluating Branch AlternativesSchedulingBranchCPI speedup v. Speedup v. scheme penalty unpipelinedstallStall pipeline31.423.51.0Predict taken11.144.41.26Predict not taken11.094.51.29Delayed branch0.51.074.61.31

Conditional & Unconditional = 14%, 65% change PCControl Hazards


Appendix A - Pipelining *Pipelining Introduction SummaryJust overlap tasks, and easy if tasks are independentSpeed Up Pipeline Depth; if ideal CPI is 1, then:

Hazards limit performance on computers:Structural: need more HW resourcesData (RAW,WAR,WAW): need forwarding, compiler schedulingControl: delayed branch, prediction

Speedup =Pipeline Depth1 + Pipeline stall CPIXClock Cycle UnpipelinedClock Cycle PipelinedControl Hazards


Appendix A - Pipelining *Compiler Static Prediction ofTaken/Untaken BranchesAlways takenTaken backwardsNot Taken ForwardsControl HazardsThe compiler can program what it thinks the branch direction will be. Here are the results when it does so.


Appendix A - Pipelining *Compiler Static Prediction ofTaken/Untaken BranchesImproves strategy for placing instructions in delay slot

Two strategiesBackward branch predict taken, forward branch not takenProfile-based prediction: record branch behavior, predict branch based on prior runControl Hazards


Appendix A - Pipelining *Evaluating Static Branch Prediction StrategiesMisprediction ignores frequency of branchInstructions between mispredicted branches is a better metricControl Hazards


Appendix A - Pipelining *What Makes Pipelining Hard?A.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards Data Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations


Appendix A - Pipelining *What Makes Pipelining Hard?Examples of interrupts:Power failing, Arithmetic overflow, I/O device request, OS call, Page fault

Interrupts (also known as: faults, exceptions, traps) often require surprise jump (to vectored address) linking return address saving of PSW (including CCs) state change (e.g., to kernel mode) Interrupts cause great havoc!There are 5 instructions executing in 5 stage pipeline when an interrupt occurs:How to stop the pipeline?How to restart the pipeline?Who caused the interrupt?


Appendix A - Pipelining *What Makes Pipelining Hard?Interrupts cause great havoc!What happens on interrupt while in delay slot ?Next instruction is not sequential solution #1: save multiple PCs Save current and next PC Special return sequence, more complex hardware solution #2: single PC plus Branch delay bit PC points to branch instruction

StageProblem that causes the interruptIFPage fault on instruction fetch; misaligned memory access; memory-protection violationIDUndefined or illegal opcodeEXArithmetic interruptMEMPage fault on data fetch; misaligned memory access; memory-protection violation


Appendix A - Pipelining *What Makes Pipelining Hard?Simultaneous exceptions in more than one pipeline stage, e.g.,Load with data page fault in MEM stageAdd with instruction page fault in IF stageAdd fault will happen BEFORE load faultSolution #1Interrupt status vector per instructionDefer check until last stage, kill state update if exceptionSolution #2Interrupt ASAPRestart everything that is incompleteAnother advantage for state update late in pipeline!Interrupts cause great havoc!


Appendix A - Pipelining *What Makes Pipelining Hard?Heres what happens on a data page fault. 1 2 3 4 5 6 7 8 9 i F D X M W i+1 F D X M W

Appendix A - Pipelining *What Makes Pipelining Hard?Complex Addressing Modes and InstructionsAddress modes: Autoincrement causes register change during instruction executionInterrupts? Need to restore register stateAdds WAR and WAW hazards since writes are no longer the last stage.

Memory-Memory Move InstructionsMust be able to handle multiple page faultsLong-lived instructions: partial state save on interrupt

Condition CodesComplex Instructions


Appendix A - Pipelining *Handling Multi-cycle OperationsMulti-cycle instructions also lead to pipeline complexity.

A very lengthy instruction causes everything else in the pipeline to wait for it.A.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards Data Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations


Appendix A - Pipelining *Multi-Cycle OperationsFloating point gives long execution time.This causes a stall of the pipeline.Its possible to pipeline the FP execution unit so it can initiate new instructions without waiting full latency. Can also have multiple FP units.

FP InstructionLatency Initiation Rate Add, Subtract43Multiply84Divide3635Square root112111Negate21Absolute value21FP compare32Floating Point


Appendix A - Pipelining *Divide, Square Root take 10X to 30X longer than AddInterrupts?Adds WAR and WAW hazards since pipelines are no longer same lengthMulti-Cycle OperationsFloating PointNotes:I + 2: no WAW, but this complicates an interruptI + 4: no WB conflictI + 5: stall forced by structural hazardI + 6: stall forced by in-order issue


1

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i

IF

ID

EX

MEM

WB

I + 1

IF

ID

EX

EX

EX

EX

MEM

WB

I + 2

IF

ID

EX

MEM

WB

I + 3

IF

ID

EX

EX

EX

EX

MEM

WB

I + 4

IF

ID

EX

MEM

WB

I + 5

IF

ID

--

--

EX

EX

I + 6

IF

--

--

ID

EX

Appendix A - Pipelining *Summary of Pipelining BasicsHazards limit performanceStructural: need more HW resourcesData: need forwarding, compiler schedulingControl: early evaluation & PC, delayed branch, predictionIncreasing length of pipe increases impact of hazards; pipelining helps instruction bandwidth, not latencyInterrupts, Instruction Set, FP makes pipelining harderCompilers reduce cost of data and control hazardsLoad delay slotsBranch delay slotsBranch prediction


Appendix A - Pipelining *CreditsI have not written these notes by myself. Theres a great deal of fancy artwork here that takes considerable time to prepare.

I have borrowed from:Wen-mei & Patel: http://courses.ece.uiuc.edu/ece511/lectures/lecture3.pptPatterson: http://www.cs.berkeley.edu/~pattrsn/252S98/index.htmlRabaey: (He used lots of Patterson material):http://bwrc.eecs.berkeley.edu/Classes/CS252/index.htmKatz: (Again, he borrowed heavily from Patterson):http://http.cs.berkeley.edu/~randy/Courses/CS252.F95/CS252.Intro.html

Mark Hill: (Follows text fairly well): http://www.cs.wisc.edu/~markhill/cs752/


Appendix A - Pipelining *SummaryA.1 What is Pipelining? A.2 The Major Hurdle of Pipelining-Structural Hazards Data Hazards Control Hazards A.3 How is Pipelining ImplementedA.4 What Makes Pipelining Hard to Implement? A.5 Extending the MIPS Pipeline to Handle Multi-cycle Operations


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CAO Pipelining Lecture