carrier phase synchronization

8/10/2019 carrier phase synchronization

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carrier phase synchronization-Introduct A successful communication system must establish synchroniza

.

Synchronization is required at several levels.

.

At the physical-layer level the receiver needs to know or estimaparameters:

:

1. the incoming carrier frequency, fc (hertz).

2. for coherent demodulation any phase shift or phase drift, (t3. the bit (symbol) timing.

Frequency, phase, symbol, and frame synchronization are donereceiver.

.


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IntroductionEx

The bit sequence needs to be segmented typically into eigheach word representing a voice sample.

.

time-division multiple access where the communication chashared. In this case the time slots need to be properly segmenthe information from the different users properly. Such synchtypically calledframe synchronization.

...

In a mobile cellular environment where two (or more) base sbe involved in transmitting to (or receiving from) a mobile rtransmitters need to be synchronized for satisfactory opersynchronization is usually called network synchronization (by p

()().().


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Introduction

Digital communication systems using coherent modulationthree levels of synchronization.

(

)

1-Phase, 2-Symbol, 3-Frame.

Digital communication systems using non-coherent modulrequire two levels of synchronization

(

)

1-Symbol, 2-Frame.


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Introduction the effect of improper phase or symbol timing on the syste

performance.

.

Effect of a phase error on BPSK signal constellations and

received sufficient statistics.


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the bit error probabilities in AWGN are:

Effect of a phase erro

error probabilities of B

AWGN.


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Introduction Since the modulation is not coherent, accurate phaselockis not required

coherentrequire frequencysynchronization.

.

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Frequency synchronization differs from phase synchronization in that the

carrier that is generated by the receiver is allowed to have arbitrary constaoffset from the received carrier.

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Receiver designs can be simplified by removing the requirement to determvalue of the incoming carrier phase.

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The receiver, in digital communication systems, has accurate knowledge asymbol started and when it is over. This knowledge is required in order to proper symbol integration interval (the interval over which energy is integmaking symbol decision).

.

(

.)


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Introduction It can be seen that symbol synchronization and phase

synchronization are similarin that both involve producing receiver a replica of a portion of the transmitted signal.

For phase synchronization, it is an accurate replica of the c

For symbol synchronization, it is a square wave at the symtransition rate (the receiver must be able to produce a squfor each incoming signals transitions between symbols). A that is able to do this can be said to have symbol synchron

to be in symbol lock. Similar to symbol synchronization, frame synchronization i

equivalent to being able to generate a square wave at the with the zero crossing coincident with the transitions fromto the next.


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Synchronization costs and benefits

1-The most obvious costs is in the need for additional hardwsoftware in the receiver for acquisition and tracking.

2-Extra time is required to achieve synchronization before

commencing communications.

3-Error control coding is used.


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Phase Locked Loop

The heart of all synchronization circuits is the phase lo(PLL). A schematic diagram of the basic PLL is shown in fig

PLL is a servo control loop, whose controlled parameter is

of a locally generated replica of the incoming carrier signa

PLL has three basic components:-


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PLL-components Phase detector: is a device that produce a measure of the

in phase between an incoming signal and the local replicaincoming signal and the local replica change with respect t

other, the phase difference (or phase error) becomes a timsignal into the loop filter.

Loop filter: is the device governsthe PLL response to thesein the error signal.

VCO: is the device that produces the carrier replica. The VC

sinusoidal oscillator whose frequency is controlledby a voat the device input.


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PLL-VCO&PD A VCO is an oscillator whose output frequency is a linear f

its input voltage over a certain range.

Figure below shows what is called a sinusoid phase detect

A sinusoid phase detector. Here

or operating point of the voltage

oscillator (VCO), which determ

running frequency, i, of the V

frequency when out(t) = 0.


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PLL-LF

Figurebelowpresents four possible loop filters

Four possible loop filters: (a

allpass filter, (b) lowpass fil

(c) leadlag filter, (d) active

filter.


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PLL- Modeling Let us consider the input signal to the PLL is given by

= + () -------(1)

Where is the nominal carrier frequency and ()is a slvarying phase. Similarly, consider a normalized VCO outpuform .

= 2 + () -------(2)

Where ()is the estimated phase. These signals will pro

output error signal at the phase detector output of the for = 2 + () * + ()

= () + 2 + + (


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PLL- Modeling Assuming that the loop filter is low pass filter, the second term

be filtered out. Thus the low pass filter provides error signal that

a function of the difference phases between input and the outpu

only.

This error signal is applied to the input VCO.

The VCO output frequency is the time derivative of the argumeof the sine function in eq(2).

If we assume that is the output frequency of the VCO when

is zero, we can express the difference in the VCO output frequeas the differential of the phase term ().

Therefore, since an input voltage of zero produces an output fr, the difference in the output frequency form will be prothe value of the input voltage y(t).


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_____(3)

Where(t)=the frequency difference

*=the convolution

Ko=the gain of the VCO

f(t)=the loop filter impulse response

PLL- Modeling

linearized

loop equation


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PLL- Modeling

This linear differential equation in () (if small angle approximation) is known as the linearized loop equation. Idetermine the loop behavior during normal operation (whphase error is small). Consider the Fourier transform of eq

Where H jW)is t

loop transfer fun

the PLL

loop

fu

E l


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Example EX: Show that for appropriately chosen Ko, Koand f(t) the lin

loop equation (for PLL) demonstrates a tendency toward phthat is, the phase difference between the incoming signal anoutput tends to decrease.

Solution:

------(4)

1-Consider the case where the phase of the input signal ()varying with time.

2-If the phase difference on the right hand side of eq(4) is pos()> ], so that will increase with time, which will reduce the magnitude of the difference ()- .

3-If ()= , then eq(4) indicates that will not changtime ,and the equality will be maintained.

St d t t t ki h t i ti


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Steady state tracking characteristic By using eq(5), we can obtain an expression for the Fourier t

of the phase error E(w)

________(5)

__________(6)

eq(6) can be used to determine the steady state errorrespoloop to a variety of possible input characteristics. The steadyerror is the residualerror after all transients have died away


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PLL f i i


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PLL performance in noise As before, the loop filter eliminates the twice carrier freque

terms. Denoting the second and third terms of eq(8) as

Consider the auto correlation function of ()

PLL f i i


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PLL performance in noise Where E[.] denotes the expected value.

The cross terms on the right hand side of eq(9) are equbecause ns and ncare mutually independent and have zero m

Eq(9) can be written as:-

______(10)

Where =t1-t2. Taking Fourier transforms, the power spectra

of

()is seen to be

PLL performance in noise


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PLL performance in noise Where Gc(w) and Gs(w) are the Fourier transforms of

respectively. But from eq(7), it can be seen that the spectrGs(w) are made of shifted versions of the spectra of the ori

process n(t). Therefore, because-----(11)

Where ()is the spectral density of the original bandpassprocess n(t). Eq(10) can be rewritten as

_____(12)



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PLL performance in noise For the special case of white noise, we have = /2

where No is the signal sided spectral density of the white nfrom Eq(12), for this special case

---------(13)

The spectral density of the VCO phase, is related to t

density of the noise process through the loop transfer funct

---------(14)

-------(15)

-------(16)



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PLL performance in noise The variance of the output phase is then

____(17)

For special case of white noise

______(18)

The integral in eq(18) is called the two sided loop bandwidt



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PLL performance in noise The single sided loop bandwidth is termed BL. The definitio

terms are

-----(19)

Thus if the noise process is white and the small angle appholds, the phase variance is given by

---------(20)

The phase variance is a measure of the amount of jitter output due to noise at the input. Eq(20) and Eq(6) highlimany tradeoffs in communication theory.



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PLL performance in noise If

is small, the loop bandwidth is small. But the narrower

bandwidth of H(w), the poorer will be the loop ability to traincoming signal phase response.

Suppressed of carrier loops


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Suppressed of carrier loops Suppressed of carrier loops: In the case of a phase modulat

carrier phase variation due to the modulation less than /2there will be positive energy at the carrier frequency. This

system design that has a residual carrier component. A diagsignal space for a binary phase modulated with a residual cacomponents is shown in fig(A), for modulating angle of However, the residual component is wasted energy, it is nottransmit the information, only to transmit the carrier. Thus mmodern phase modulated systems are suppressed carrier sy

This means that there is no average energy transmitted at thfrequency also there is no longer any signal for the basic PL


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Suppressed of carrier loops Where m(t)=1 with equal probability. This is suppressed ca

the average energy at radian frequency is zero. This reprgraphically in fig (A) when To acquire and track the phase of

carrier, the effects of the modulation must be eliminated. Oeliminate the modulation is to square the signal.

if m2(t)=1, the second term on the right hand side of eq(21) related term(at twice the original carrier frequency) that canacquired and tracked with a basic PLL



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Suppressed of carrier loops Such an arrangement is illustrated in fig(B). The problems w

schematic are:-

a) All phase angles have been doubled. Thus, the phase nois

phase jitter have been doubled. b) Larger S/N is required for this PLL to overcome this larger

variation of the noise.

c) False lock. This additional loss due to the terms in eq(21)

is called the loop squaring lo

given by _____(22)



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Suppressed of carrier loops Where S is the signal power

Bi is the filter bandwidth

Nois the single sided power spectral density of the prefiltereGaussian noise process.

Fig (B)



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Suppressed of carrier loops Eq(22) can be expressed as

Where Piis the signal to noise ratio

Costas loop


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Costas loop Costas loop

-Fig (C) shows the Costas loop. This loop design is importantit eliminatesthe square law device, which can be difficult to

implement at carrier frequencies, and replaces it with a murelatively simple low pass filters. The problem in this loop isimplement the two LPF identical. This problem can be solvethe digital filter.

-The decision as to whether to implement a Costas loop or t

classical design of fig(B) amounts to a design decision betwedifficulty of implementing the squaring device and the difficimplementing closely matched arm filters.

Costas loop


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Costas loop

Fig(C)

Higher order suppressed carrier loo


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Higher order suppressed carrier loo Higher order suppressed carrier loops

Sequaring the signal a second time (equivalent to takingoriginal signal to the fourth power) can be seen to produce

with a carrier component at four times the transmuted carrfrequency. The loss for fourth power loop is


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Higher order suppressed carrier loo


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g pp Thus, an input signal to noise ratio of 10dB is suitable to kee

small for the squaring loop, the same signal to noise ratio msignificant losses for the fourth power loop.

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carrier phase synchronization