CH6-Parallel IO Port

7/29/2019 CH6-Parallel IO Port

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Parallel I/O Port


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Introduction

A parallel I/O port is used for interfacing with external peripherals

Writes (output) data and reads (input) data I/O devices

LEDs

Seven-segment display

Switches


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Introduction

An I/O port consists of a set of I/O pins and the registers required to

control its operation An I/O pin can be configured for input or output

An I/O pin usually serves multiple functions

When it is not used as a peripheral function, it can be used as ageneral-purpose I/O pin.


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Port B

Port A


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HCS12 I/O Ports & Pin Names

Table 4.5 N umbe r of pins available in each paralle port

Port Name No. of Pins Pin Name

A

B

E

H

J

K

M

P

S

T

PAD1, PAD0

L

U

V

W

8

8

8

8

4

7

8

8

8

8

16

8

8

8

8

PA7~PA0

PB7~PB0

PE7~PE0

PH7~PH0

PJ7~PJ0

PK4~PK0

PM7~PM0

PP7~PP0

PS3~PS0

PT7~PT0

PAD15~PAD0

PL7~PL0

PU7~PU0

PV7~PV0

PW7~PW0

8-bit I/O ports


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I/O Port Direction Configuration

Data direction register (DDR) is used to configure the direction of

each pin (8 pins) of I/O port Input

Output

DDR is 8-bit register

Setting a bit of the DDR to1, the corresponding I/O pin is configuredas output

Setting a bit of the DDR to 0, the corresponding I/O pin is configuredas input


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b7

b6

b5

b4

b3

b2

b1

b0

0 0 0 0 0 0 0 0DDRA

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

All pins are input


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b7

b6

b5

b4

b3

b2

b1

b0

1 1 1 1 1 1 1 1DDRA

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

All pins are output


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b7

b6

b5

b4

b3

b2

b1

b0

0 0 0 0 1 1 1 1DDRA

Port A

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA0-PA3 are output

PA4-PA7 are input


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Each data direction register is assigned an address

ie. address of Port A DDR is $02

equ directive can be used to represent address of Port A DDR

movb #$FF, $02 ; configure Port A as output

DDRA equ $02

movb #$FF, DDRA ; configure Port A as output


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I/O Port Data Register

Data register is used to send data to or from I/O devices

To perform output (send data to I/O port), write the data register To perform input (receive data from I/O port), read the data register

Each data register is assigned an address

ie. Port A data register is assigned address 0

equ directive can be used to represent address of Port A data register

movb #$35,0 ; address 0 is Port A data register; value of $35 is send to Port A

PORTA equ 0movb #$35, PORTA ; PORTA is address 0


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Example of I/O Operation

movb #$FF, DDRB ; configure Port B as output

staa PORTB ; output A to Port Bmovb #$67, PORTB ; output $67 to Port B

movb #0, DDRA ; configure Port A as input

movb #PORTA, ibuf ; read Port A and save it at

; ibuf memory location


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Electrical Characteristics

Electrical compatibility issues needs to be considered when

interfacing I/O device to the MCU Two major concerns in interfacing IC chips

Voltage-level compatibility

Is the high output level of an IC chip high enough to be consideredas a high for the input of another IC chip? Is the low output level of

an chip low enough to be considered as a low for the input ofanother IC chip?

Current drive capability

Does the output of an IC chip have enough current to drive its load?

Can the output circuit of an IC chip sink the currents of its load?


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Voltagelevel Compatibility Voltage parameter needs to be considered

Input high voltage (VIH): voltage that be treated as a logic 1 when applied to theinput of a digital circuit.

Input low voltage (VIL): the voltage that be treated as a logic 0 when applied tothe input of a digital circuit

Output high voltage (VOH): the voltage level when a digital circuit outputs a logic 1

Output low voltage (VOL): the voltage level when a digital circuit outputs a logic 0

In order for device X to drive device Y correctly, the following condition mustbe satisfied:

Output high voltage of device X (VOHX

) must be higher than input high voltage ofdevice Y (VIHY). VOHX > VIHY

Output low voltage of device X (VOLX) must be lower than the input low voltage ofdevice Y (VILY). VOLX < VILY


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Logic family VCC VIH VOH VIL VOL

HCS123

S4

LS4

AS4

F4

HC3

HCT3

ACT3

ABT5

BCT5

FCT5

5 V

5 V

5 V

5 V

5 V

5 V

5 V5 V

5 V

5 V

5 V

3.25 V

2 V

2 V

2 V

2 V

3.5 V

3.5 V2 V

2 V

2 V

2 V

4.2 V

3.0~3.4 V1

3.0~3.4 V1

3.0~3.4 V1

3.4 V

4.9 V

4.9 V4.9 V

3 V

3.3 V

2.4 V

1.75 V

0.8 V

0.8 V

0.8 V

0.8 V

1.5 V

1.5 V0.8 V

0.8 V

0.8 V

0.8 V

0.8 V

0.4~0.5 V2

0.4~0.5 V2

0.35 V

0.3 V

0.1 V

0.1 V0.1 V

0.55 V

0.42 V

0.55 V

Notes.

1. VOH value will get lower when output current is larger.

2. VOL value will get higher when output current is larger. The VOLvalues of different logic gates are slightly different.

3. HCS12, HC, HCT, ACT are based on the CMOS technology.

4. S, LS, AS and F logic families are based on the bipolar technology.

5. ABT, BCT, and FCT are using the BiCMOS technology.

Table 7.1 Input and output voltage levels of common logic families


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Current Drive Capability

A device that drives other devices must have enough sourcing(supply current) and sinking (absorb current) capability

Current flows out from the driving device when the driving voltage ishigh

Current flows into the driving device when the driving voltage is low

The driving device must be able to supply (or sink) enough currentneeded by those devices being driven for proper operation


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Cont.

If a device cannot source or sink enough current, then using buffer

device is a common solution

The current capabilities of a logic device are determined by thefollowing currents:

Input high current(IIH): The input current (flowing into the input pin)

when the input voltage is high.

Input low current(IIL): the input current (flowing out of the input pin)when the input voltage is low.

Output high current(IOH): The output current (flowing out of the outputpin) when the output voltage is high

Output low current(IOL): The output current (flowing into the output pin)when the output voltage is low.


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Cont.

To determine whether a pin can supply and sink currents to all theperipheral pins that it drives directly, the following requirements need

to be checked:

The IOHof an output pin must be equal to or largerthan the total currentflowing into all the peripheral pins that are connected to directly to theuC I/O pins

The IOL of an output pin must be equal to or largerthan the total currentflowing out from all the peripheral pins that are connected directly to uCI/O pins

Need to make sure that the total current needed to drive the

peripheral signals pins does not exceed the total current that themicrocontroller can supply.

What should be done if an I/O cannot supply or sink the currentneeded to drive the peripheral pins?

Use buffer chips


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Logic family VCC

HCS1223

SLSASF

HC3HCT3

ACT3

ABT3

BCTFCT3

IIH IIL IOH IOL

5 V5 V5 V5 V5 V

5 V5 V5 V5 V5 V5 V

2.5 A50 A20 A20 A20 A1 A1 A1 A1 A

20 A1 A

2.5 A1.0 mA0.2 mA0.5 mA0.5 mA

1 A1 A1 A1 A1 mA1 A

25 mA1 mA15 mA15 mA1 mA

25 mA25 mA24 mA32 mA15 mA15 mA

25 mA20 mA24 mA64 mA20 mA

25 mA25 mA24 mA64 MA64 mA64 mA

Notes.1. Values are based on the 74xx244 of Texas Instrument (xx is the technology name)

2. The total HCS12 supply current is 65 mA.3. The values for IIH and IIL are input leakage currents.

Table 7.4 Current capabilities of common logic families1


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Interfacing with LEDs

Indicate system operation

Power-on, mode indicator etc.

Current required to light an LED is 10 mA Voltage drop across an LED ranging from 1.6V - 2.2 V


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Interfacing with LEDs

Three (3) interfacing methods

74HC04

VCC

Figure 4.15 An LED connected to a CMOS inverter through a current -limiting resistor .

Port

pin

(a) Positive direct drive(c) Buffered drive

R1

R2

R3

VCC

Port

pin

Port

pin(b) Inverse direct drive


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Example 4.12

Write a program to drive the LEDs shown in Figure 4.16 so that oneLED is lighted at a time from top to bottom and then from bottom to

top with each LED lighted for about 200 ms.

Figure 4.16 Circuit connection for Exam ple 4.12

PB3

PB 2

PB 1

PB 0

HCS12

PB7

PB6

PB5

PB4

1.5 K

PJ1


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#include "C:\miniide\hcs12.inc"org $1000

lpcnt ds.b 1

org $1500Start movb #$FF,DDRB ; configure port B for output

bset DDRJ,$02 ; configure PJ1 pin for output

bclr PTJ,$02 ; enable LEDs to light

forever movb #16,lpcnt ; initialize LED pattern count

ldx #led_tab ; Use X as the pointer to LED pattern table

led_lp movb 1,x+,PORTB ; turn on one LED

ldy #5 ; wait for half a second

jsr delayby100ms ; "

dec lpcnt ; reach the end of the table yet?

bne led_lp

bra forever ; start from beginning

led_tab dc.b $80,$40,$20,$10,$08,$04,$02,$01

dc.b $01,$02,$04,$08,$10,$20,$40,$80

#include "C:\miniide\delay.asm"

; org $FFFE ; uncomment this line for CodeWarrior

; dc.w start ; uncomment this line for CodeWarrior

end


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Seven-Segment Display

A common necessity for many different digital devices is a visualnumeric display

Individual LEDs can display the binary states of a set of latches orflip-flops

However human more used to dealing with decimal numbers -clearly represent decimal numbers without translating binary todecimal


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Seven-Segment Display

One possibility is to arrange the minimum possible number of LEDsin such a way as to represent only numbers in a simple fashion

Seven LEDs (plus an eighth one for the decimal point, if needed) Seven bars are laid out as a squared-off figure "8 and is known as a

seven-segment display

Use to display decimal digits, small subset of letters


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Interfacing with Seven-segment

I/O port can drive a seven-segment display directly

Buffer chips are used mainly to save excessive current draw from

the HCS12


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Interfacing with Seven-segment

HCS12 I/O port drives seven-segment display through a buffer chip74HC244

74HC244

PB6

PB5

PB4

PB3

PB2

PB1

PB0

a

bc

d

e

fg

comm on cathode

a

b

c

d

e

f

g

HCS12

Figure 4.17 D riving a single seven -segm ent display

47 0 each


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Decimal to 7-segment Decoder

Values for displaying decimal digits depends on how seven-segments a-g are connected to the I/O pins

Dragon12 demo board segments a-g are connected to from thepin PB0 ~ PB6

Decimaldigit

a b c d e f g

Segments Corresponding Hex Number

0

1

2

3

4

5

6

7

8

9

1

0

1

1

0

1

1

1

1

1

1

1

1

1

1

0

0

1

1

1

1

1

0

1

1

1

1

1

1

1

1

0

1

1

0

1

1

0

1

1

1

0

1

0

0

0

1

0

1

0

1

0

0

0

1

1

1

0

1

1

0

0

1

1

1

1

1

0

1

1

$7E

$30

$6D

$79

$33

$5B

$5F

$70

$7F

$7B

Table 4 .7 Decimal to seven-segm ent decoder

Figure 4.17 circuit Dragon12 demo board

$3F

$06

$5B

$4F

$66

$6D

$7D

$07

$7F

$67


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Multiple 7-segment Display

A time-multiplexing technique is often used to display multiple digits

.

.

.

a

b

g

PB

6

PB

1

PB

0

Figure 4.18 Port B and Port P together drive six seven -segment displays (MC9S12DG256)

. . .

. . .

. . .

74HC244

HCS12

a

b

g

.

.

.

common

cathode

common

cathode

common

cathode

a

b

g

.

.

.

800

PP5

PP4

PP0

800

#5#1#0

74HC367

PP3

PP2

PP1

A5

Y0A0

Y5

A4

Y1

A3

A2

A1

Y2

Y3

Y4


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Multiple 7-segment Display

The circuit can display up to six digits simultaneous using the time-multiplexing technique

The HCS12 lights one digit for a short period of time and thenswitches to the next digit

Within one second, each digit is lighted in turn many times

Due to the persistence of vision, all six digits appear to be lightedat the same time


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Example 4.13

Write an instruction sequence to display 7 on the seven-segmentdisplay #5


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seven equ $07

org $1500movb #$FF,DDRB ; configure Port B for output

movb #$3F,DDRP ; configure Port P for output

movb #$1F,PTP ; enable display #5 to be lighted

movb #seven,PTB ; send out the segment pattern of 7

end


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Example 4.14

Write a program to display 123456 on the six seven-segmentdisplays


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#include "c:\miniide\hcs12.inc"org $1500

start lds #$1500

movb #$FF,DDRBmovb #$3F,DDRP

forever ldx #DispTab ; set X to point to the display table

loopi movb 1,x+,PTB ; output segment pattern

movb 1,x+,PTP ; output display select

ldy #1

jsr delayby1ms ; wait for 1 ms

cpx #DispTab+12 ; reach the end of the table?

bne loopi

bra forever

#include "c:\miniide\delay.asm"

DispTab dc.b $06,$1F

dc.b $5B,$2Fdc.b $4F,$37

dc.b $66,$3B

dc.b $6D,$3D

dc.b $7D,$3E

; org $FFFE ; uncomment this line for CodeWarrior

; dc.w start ; uncomment this line for CodeWarrior

end


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DIP Switch

A set of manual electric switches that are packaged in a group in astandard dual in-line package (DIP)

Commonly used to customize the behavior of an electronic devicefor specific situations store setting/configuration


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Interfacing with DIP Switch

A dual-in-line package can be connected any port with 8 pins

A set of pull-up resistors are needed to pull the voltage to high on

one side of the DIP

VCC

10 K

PA0

PA1PA2

PA3

PA4

PA5

PA6

PA7

HCS12

Figure 4.19 Connecting a set of eight DIP switches to Port A of the HCS 12

SW DIP-8


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Keypad

Keypad is input device that is constructed by arranging an array ofswitches mechanical, membrane, capacitive or Hall effect

Mechanical switches have a problem called contact bounce. Mechanical switch generates a series of pulses because the switch

contacts do not come to rest immediately.

A human cannot press and release a key switch in less than 20ms

During this interval, microprocessor can scan the same key switch

closure tens or even hundreds of thousands of times Debouncing is needed to solve the disparity in speed between the

microprocessor and human key pressing

Re-scan the key switch closure to make sure a key is indeed pressed


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Keypad scanning

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

10 K

VCC

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

HCS12 MCU

Figure 7.32 Sixteen-key keypad connected to the HCS12

PA7 PA6 PA5 PA4 Selected Keys

1

1

10

1

1

01

1

0

11

0

1

11

0,

4,

8,C,

1,

5,

9,D,

2,

6,

A,E,

and 3

and 7

and Band F

Table 7.12 Sixteen-key keypad row selections

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CH6-Parallel IO Port