Challenges in Low‐Power Analog

Challenges in Low Power AnalogChallenges in Low‐Power Analog Circuit Design for sub‐28nm CMOS

Technologies

Amr Fahim

S t h C tiSemtech Corporation

International Symposium on Low Power Electronics and Design

Outline• Scaling Effects• Design MethodologyCh ll i b 28 CMOS• Challenges in sub‐28nm CMOS

• Analog Design for sub‐28nm CMOS• Design Examples• Design Examples• Conclusions

2

Scaling Effects• Transistor cross section:

Vs Vd

Where:

Ileakage more in deep substrate

• Known as drain induced barrier lowering (DIBL)• As L scales: 1) Cox 2) W (body doping)

3

• As L scales: 1) Cox 2) Wdep (body doping)

Scaling Effects• Leakage current scaling (W=1um)

6.00E-09

4.00E-09

5.00E-09

(A)

2.00E-09

3.00E-09

I,ds

(

65nm40nm28nm

0.00E+00

1.00E-09

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

VDS (V)

4

Scaling Effects• Intrinsic Transistor Gain: Av = gmro

26

Introduction of HK/MG

20

22

24

26

dB)

14

16

18

20

Av=g

m*r

o (d

65nm40nm28nm

10

12

14

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

A

5

Ids (mA)


• Analog Design for Sub‐28nm CMOS• Design Examples• Design Examples• Conclusions

6

Design Methodology• Important Figure‐of‐merit in analog design is the Gm/IDS ratio

Towards weako a ds eainversion

Towards linearregion

7

Design Methodology• Other important metrics in analog design include:

• Noise: limits the minimum detectable signal (MDS) th t th l i it(MDS) that the analog circuit can process

• Linearity: limits the maximum possible signal that the analog circuit can processthe analog circuit can process

d f h “d ”• Noise+Linearity define the “dynamic range” (DR) of the signal that the circuit can handle

MDSIIPDR 32

8

MDSIIPDR 332

Design Methodology• Other important metrics in analog design include:

• Gain (gm), Bandwidth (Ft), power consumption

• Define a “figure‐of‐merit” (FOM) to take into account dynamic range and bandwidthdynamic range and bandwidth• This FOM describes maximum performance without regard to power consumptiong

dfvIIPfFOM 2log1032log10 dfvIIPfFOM nT log1033

log10

Dynamic range

9

Bandwidth Dynamic range

Design Methodology• FOM plot over current consumption:

dfvIIPfFOM nT2log103

32log10

10

3

Design Methodology• Define another “figure‐of‐merit” (FOM2) to take into account current consumption as well

FOM2 t k i t t th t ffi i i• FOM2 takes into account the current efficiency in obtaining a certain performance level

dfvIIPf

IgFOM nTds

m 2log10332log10log102

PowerEfficiency Bandwidth

Dynamic Range

11

Design Methodology• FOM2 plot over current consumption

gm 22

12

dfvIIPf

IgFOM nTds

m 2log10332log10log102

Design Methodology• Overall design methodology:

1. Generate parametric curves based on FOM or FOM2 (Ids and W are parameters)

2. Choose Ids and W that meet desired specificationsspecifications

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Challenges in sub‐28nm CMOSff ( l )• Stress effects (isolation proximity):

• Stress = Force / Area• Stress scenarios:• Stress scenarios:

1. Force = q * E

2. Stress is also induced by interface boundaries between material with different dopantdensities (adjacent NFETs or NFET/PFET boundary)boundary)

• Effect of stress carrier mobility shifts (current!)• Mitigate by use of dummies & equally spaced

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Mitigate by use of dummies & equally spaced devices

Challenges in sub‐28nm CMOS• Diffusion proximity (well proximity)

• Dopant atoms scattered from adjacent photoresist

Scattering variability in doping profileVT variation in order to 10’s mV

- Mitigate by use of dummies

16

Source: Freescale Semiconductor (0.13um 3.3V NFET)

Challenges in sub‐28nm CMOS• Device gate leakage:

• Gate leakage caused by quantum tunneling effect

1.00E-08

1.00E-07

1.00E-10

1.00E-09

eaka

ge (A

)

1 00E 12

1.00E-11

I,le

1.00E-12180nm 130nm 90nm 65nm 45nm 28nm

Technology node

17

Introduction of HK/MGgateoxGS fLWCi

Challenges in sub‐28nm CMOS• Gate leakage introduce low‐frequency pole:

tunnelgf

h l f b d l

in

tunnelgate C

gf2

• This creates a low‐frequency bound on sample‐and‐hold (S/H) circuits as well as low‐frequency RC filters (such as PLL loop filters)

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RC filters (such as PLL loop filters)

Challenges in sub‐28nm CMOS• Gate leakage causes mismatch in current mirrors:

Gate leakage causes current mismatchGate leakage causes current mismatch

Classical mismatch: Mismatch with gate tunneling:22

Ig

WLA

II mVT

222

Ii

WLX

Ig

WLA

II GIGSmVT

19


• Analog Circuit Design for Sub‐28nm CMOS• Design Examples• Design Examples• Conclusions

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Sub‐28nm CMOS Circuit Design• Stack devices

• Ensure no stressed oxides during off modeU d i I/O d i• Used in I/O drivers

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Sub‐28nm CMOS Circuit Design• Digitally assisted analog circuit design

• Use trimming/calibration loops to sense i f ti i l i it i t himperfections in analog circuits mismatches, center frequency, etc.

• Data converters (DAC/ADC):• Data converters (DAC/ADC):• Use a higher resolution, lower frequency ADC/DAC to sense imperfections

• Input voltage (or digital word) is a saw‐tooth waveform during calibration

• VCO:• Trim center frequency• Trim LC tank amplitude

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• Trim LC tank amplitude

Sub‐28nm CMOS Circuit Design• Design techniques:

• Digital temperature sensor use to adjust analog ttisettings Multiple programmable PFETs

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Design Examples• 9‐bit SAR ADC in 28nm CMOS

Metric ValuePerformance Summary:Input offset voltage

lib t d t t t Metric Value# bits 9VDD 0.9

calibrated at startup(DC calibration loop)

fCLK 900MHzArea 200um x 100um

Power 382uW

25

ENOB 8.51

Design Examplesb• 10‐bit current steering DAC in 28nm CMOS

• One Slice:Metric ValuePerformance Summary:Metric Value# bits 10VDD 0.9fCLK 200MHzArea 200um x 100um

Power 330uA

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ENOB 8.8 bits

Design Examples• VCO in 28nm CMOS:

PFET current mirror with embedded PSR

P f SMetric Value

Fosc,center 3GHz

Performance Summary:

Tuning range 800MHzPN @ 1MHz -134.3dBc/Hz

Power 9mA

Current amplitude loopto suppress LO harmonics in LC tank.

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Power 9mA



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Conclusions• Scaling Effects Reviewed• Design Methodology

B d /ID d i th d l• Based on gm/ID design methodology• Extended to include DR & BW

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Conclusions• Challenges in sub‐28nm CMOS analog design

DSM effect Analog Circuit ImplicationStress effects (isolation Mobility variation (BW currentStress effects (isolation proximity)

Mobility variation (BW, currentmismatch, gain)

Diffusion proximity VT variation (mismatch)Gate leakage Noise mismatch low frequencyGate leakage Noise, mismatch, low-frequency

limit

• Analog circuit design techniquesDesign Technique Reason / ApplicationFET ki Hi h l i

• Design examples: DAC ADC VCO

FET stacking High voltage swingDigital assist / temp sensor Trimming analog

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• Design examples: DAC, ADC, VCO

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Challenges in Low‐Power Analog