1

Chapter 12 Power Amplifiers

2

Sections to be covered

• 12.1 General Considerations• 12.2 Classification of Power Amplifiers• 12.10 Design Examples (Lee)

3

Chapter Outline

Basic PA Classes

Class A PAs Class B PAs Class C PAs

4

Motivations

• Power amplifiers are the most power-hungry building block of RF transceivers and pose difficult design challenges.

• In the past ten years, the design of PAs has evolved complex transmitter architectures to improve the trade-off between linearity and efficiency.

Class A Power Amplifiers Class B Power Amplifiers Class C Power Amplifiers

Di

t

Illustration

6

Efficiency

The “drain efficiency” (for FET implementations) or “collector efficiency” (for bipolar implementations) is defined as:

PL denotes the average power delivered to the load Psupp the average power drawn from the supply voltage.

Suppose a 1-W PA with 50% efficiency draws 2W from the battery—much more than the rest of the transceiver does.

7

General power amplifier model

• The resistor RL represents the load.

• A “big, fat” inductance, BFL, feeds DC power to the drain, and is assumed large enough so that the current through it is substantially constant.

• The drain is connected to a tank circuit through capacitor BFC to prevent any DC dissipation in the load.

• To simplify analysis, we assume that the tank has a high enough Q that the voltage across the tank is well approximated by a sinusoid.

DDV

BFL

L CINv L

R

OUTv

BFC

8

Saturation Region

• Biased voltage

• Drain current is controlled only by vGS

• Drain current is independent of vDS and behaves as an ideal current source.

GS th

DS GS th

v Vv v V

>≥ −

21 ' )2D n GS th

Wi k v VL

= −（

9

Saturation Region

The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation

Vth = 1 V, k’n W/L = 1.0 mA/V2

Square law of iD–vGS characteristic curve.

10

Classification of Power Amplifiers

• There are four classic types of power amplifiers, distinguished primarily by bias conditions.Class AClass AB Class BClass C

11

Classification of Power Amplifiers: Class A Power Amplifiers

Class A amplifiers are defined as circuits in which the transistor(s) remain on and operate linearly across the full input and output range.

The bias levels are chosen so that the transistor operates linearly. For a biploar realization, this condition is satisfied by avoiding cutoff and saturation; For MOS implementations, the transistor is kept in the saturation region of operation;

If linearity is required, then class A operation is necessary.

12

Impedance of LC tank for harmonics

( )

( )

( )( ) ( )

p

p

2p

2

11 1

when 1 then and 1

1

p

p n

p n

p

Z Q L R

Zj n C

R n LQ

n L R LC

Z njZ n Q

ω

ω

ω

ω

ω

ωω

ω ω

= =

= + −

=

= −−

The impedance of LC tank: For fundamental: ((Zp)ω) .

For high-order harmonics: ((Zp)nω) can be regarded as zero

( )( ) ( )2 1

p n

p

Z nZ n Q

ω

ω

=−

iD

13

Drain voltage and current for ideal class A amplifier

IDC is the bias current; irf is the amplitude of the signal component

of the drain current; ω0 is the signal frequency (also the resonant

frequency);

• The output voltage is the product of a signal current and the load resistance.

• The drain voltage is the sum of the DC voltage and the output voltage.

• There is a 1800 phase shift between the drain voltage and current .

rf 0sinD DCi I i tω= +

out rf p 0sinv i R tω= −

iD

outDS DDv V v= +

Di

DCI rfi

DSv

DDV

t

14

Efficiency of Class A Power Amplifiers

irfRp can have the maximum value as VDD. Thus, the maximum drain efficiency of class A amplifiers is just 50%. For practical Class A amplifiers, drain efficiency is usually between 30-35%.

The signal power delivered to the resistor R:

Suppose the drain bias current is large enough to guarantee the transistor does not cut off (iD>0) :

The input DC power:

The ratio of RF output power to DC input power is given by:

22rf pout

outp

P2 2

i RvR

= =

DC rfI i=

DC DC rfDD DDP I V i V= =

2rf p rf pout

DC rf

( 2)2DD DD

i R i RPP i V V

η = = =

DSv

DDV

t

Di

DCI rfi

t

iD

15

Observations----Class A PA The drain (collector) peak-to-peak voltage swing

is equal to twice the supply voltage,

i.e., the transistor can withstand a drain-source (or collector-emitter) voltage of 2VDD with no reliability or breakdown issues;

the device must be able to withstand peak voltagesand currents of these magnitudes,

even though both maxima do not occur simultaneously;

iD

DSv

DDV

t

16

Conduction angle (导通角)

Distinguish PA classes by the “conduction angle” of their output transistor(s).

The conduction angle is defined as the percentage of the signal period during which the transistor(s) remain on multiplied by 3600.

In class A stages, the conduction angle is 3600 because the output transistor is always on.

DSv

DDV

t

t

Di

DCI

17

How to improve efficiency?

To raise η, we can try to reduce PDS/PDC. Since PDC is given, it comes true when PDS is reduced.

We expect a gross departure from linear operation. (Bias is changed.)

out DC DS DS

DC DC DC

1P P P PP P P

η −= = = −

Drain voltage and current for ideal Class B amplifier

DSv

DDV

t

t

Di

DCI

t

rfit

DSv

DDV

Di

18

Efficiency of Class B Power Amplifiers (1) We assume that the drain current

is sinusoidal for one half-cycle and zero for the other half-cycle:

To compute the output voltage vout:1. find the fundamental component of the drain current; 2. multiply this current by the load resistance;

rf 0sin for 0.D Di i t iω= >

2 rffund rf 0 00

2 (sin )(sin ) ,2

T ii i t t dtT

ω ω= =∫

rfout p 0sin2

iv R tω≈ −

The output tank removes the harmonics; leaving a sinusoidal drain voltages vout

as in the Class A amplifier.

t

rfiDi

t

DSv

DDV

iD

outDS DDv V v= +

19

Efficiency of Class B Power Amplifiers (2)

The output power:

The maximum possible value of vout

The maximum output power:

The average drain current:

fundp

DDViR

=

2out

outp2

vPR

=

2 2out,max

out,maxp p2 2

DDv VPR R

= =

0p

/

0p

2 2 21 sinDD DDDT V Vi tdt

T R Rω

π= =∫

2

DCp

2 DDD DD

VP i VRπ

= × =

,max

DC

0.7854

outPP

πη = = ≈

t

rfi

DSv

DDV

Di

DC power:

Maximum drain efficiency:

the corresponding value of ifund

out,max DDv V=

rfp

2 DDViR

=

Set a proper resistance Rp

20

Class B Power Amplifier The traditional class B PA employs two parallel stages each of which conducts

for only 180°, achieving a higher efficiency than the class A counterpart.

The drain currents of M1 and M2 are combined by transformer T1.

quasi-differential stage a balun driving the single-

ended load

Each transistor turn off for half of the period (i.e., the conduction angle is 1800).

The gate bias voltage of the devices is chosen approximately equal to their threshold voltage VTH.

21

Example of Class B Amplifier

Explain how T1 combines the half-cycle current waveforms generated by M1 and M2

Solution:

Using superposition, we draw the output network in the two half cycles as shown here.

When M1 is on, ID1 flows from node X,

producing a current in the secondary that flows into RL and generates a positive Vout .

When M2 is on and draws current from node Y ,

the secondary current flows out of RL and generates a negative Vout.

22

Observations---Class B PA

The drain efficiency for Class B PA is higher than for the Class A PA;

The actual efficiency of any practical implementation will be lower than given by this analysis owing to effects that we have neglected;

With the Class B amplifier, we have accepted distortion in exchange for a significant improvement in efficiency;

This tradeoff is effected by reducing the fraction of a period that the transistor conducts current.

Here comes the question, is it possible to further improve the efficiency by reducing the conduction angle?

23

Class C Power Amplifiers: Overview

In class C stages, the conduction angle is further reduced. In order to avoid large harmonic levels at the antenna, the matching

network must provide some filtering. As θ decreases, the transistor is on for a smaller fraction of the period,

dissipating less power; however, the transistor delivers less power to the load.

24

Example of Class C Stage Harmonic CalculationDetermine the amplitude of the first harmonic of the transistor drain current Class C stage for a conduction angle of θ.

Conduction A →B.

The angle of the sinusoid reaches α at A and π-α at B π-α-α= θ → α = (π-θ)/2.

The Fourier coefficients of the first harmonic :

The first harmonic is expressed as

Note that a1 → 0 as α → π/2. For example, if α = π/4, then a1 ≈ 0.41irf, the transistor must therefore be about 2.4 times as large as in a class-A stage for the

same output power.Upon multiplication by RL, this harmonic must yield a drain voltage swing of nearly 2VDD.

( )

( )

0

0

0

0

/

1 rf 0 0/0

/

1 rf 0 0/0

2 (sin )(sin )

2 (sin )(cos )

a i t t dtT

b i t t dtT

π α ω

α ω

π α ω

α ω

ω ω

ω ω

−

−

=

=

∫

∫

( )rf1

1

sin20

ia

b

θ θπ

= −

=

irf

0 1 0( ) sinI t a tω ω=

25

Efficiency of Class C Power Amplifiers (1)• In a Class C PA, the gate bias is

arranged to cause the transistor to conduct less than half the time.

rf 0cos , 0D DC Di I i t iω= + >

1 DC

rf

cos2

Ii

θ − = −

( )rffund D 002 (cos ) sin

2T ii i t dt

Tω θ θ

π= = −∫

• Setting the current equal to zero and solving or the total conduction angle θ yields:

DC rf cos 2I i θ= −

( )2

DC rf2

rf

1 cos2

sin cos2 2 2

Di I i d

i

θ

θφ φ

πθ θ θ

π

−= +

= −

∫

• The average drain current: • The fundamental component of the drain current:

( )rfout p 0sin sin2iv R tθ θ ωπ

≈ − −

t

DC rfI i+Di

2θDCI

26

Efficiency of Class C Power Amplifiers (2) The maximum possible value of vout

is VDD

t

DSv

DDV

t

DC rfI i+Di

2θDCI

thus, the corresponding value of irf is

( )pout,max rf sin2 DDR

v i Vθ θπ

= − =

( )rf p2

sinDDVi

Rπθ θ

=−

DC D DDP i V=

( ) ( ) ( )( )1 sin4 sin 2 2 cos 2

θ θηθ θ θ

−=

−

fundout,max 2

DDi VP =

The relation suggests an efficiency of 100% as θ approaches zero.

outDS DDv V v= +

27

Efficiency of Class C Power Amplifiers (3) Efficiency of 100% as θ approaches zero. Pout falls to zero as θ approaches zero.

In modern RF design, class C operation has been replaced by other efficient amplification techniques that do not require such large transistors (because of its less gain).

L1 L1

C1 C2Eb1

L2

C3 L3 C4T1

L4

C5 C6

L5

C7

C8L6

L7

C9

L8

CA

rA

T2

EcEb2 Ec

28

Example

Load of T2: C9, L8, L7, L6, C8, antenna (matching network); Load of T1: C3, L3, (coupling) Coupling+DC blocking: C4, C7 Bias: Eb1(C1+L1), Ec(C2+L2), Eb2(C5+L4+C4 ), Ec(C6+L5+C7)

L2

L1

L4

L5

Load + matching network (输出回路)

Load + coupling (级间回路)

C1 C2C5 C6

C4

C7

Eb1Eb2

EcEc

T1 T2

BFL: known as an RF choke because it “chokes off” the flow of RF current through it

BFC: DC blocking capacitor

L1

29

The Trade-Off between the Output Power and the Voltage Swing

① The product of the breakdown voltage and fT of silicon devices is around 200 GHz·V. Transistors with fT of 200GHz need a voltage swing of less than 1V.

② We should -----------control the voltage swing on transistor ------------provide enough output power.

Consider a transmitter delivering 1W (+30 dBm) of power to a 50-Ω antenna. The peak-to-peak voltage swing, Vpp, at the antenna reaches 20V and the peak

current through the load, 200 mA.

For a common-source stage todrive the load directly,

supply voltage VDD greater than Vpp.

If the load is realized as an inductor (LC tank) the drain ac voltage exceeds VDD, even

reaching 2VDD (or higher).

The maximum drain-source voltage experienced by M1 is at least 20 V.

30

Interposing a Matching Network

The above PA must deliver 1 W to RL = 50 Ω with a supply voltage of 1 V. Estimate the value of RT.

The peak-to-peak voltage swing, Vpp, at the drain of M1 is approximately equal to 2 V.

In order to reduce the peak voltage experienced by the output transistor, a “matching network” is interposed between the PA and the load.

The matching network must therefore transform RL down by a factor of 100.

Low voltage swing but high ac current!

This network transforms the load resistance to a lower value, RT , smaller voltage swings still deliver the required power.

Example: a lossless transformer having a turns ratio of 1:10 converts a 2-Vpp swing at the drain of M1 to a 20-Vpp swing across RL.

31

PAs with Power Combining: Transformer-Based Matching

The on-chip realization of 1-to-n transformers poses many difficulties, especially if the primary and/or secondary must carry

large currents. As explained in Chapter 7,

stacked transformers contain various parasitics, multi-turn planar transformers can hardly achieve a

turns ratio of greater than 2. Thus, It is desirable to employ only 1-to-1 transformers.

Is it possible to directly add the output voltages of several stages so as to generate a large output power?

the primaries of two 1-to-1 transformers are placed in parallel while their secondaries are tied in series.

The circuit amplifies the voltage swing by a factor of 2 because V1=V2=Vin.

1-to-1 transformers more easily lend themselves to integration.

32

Examples of Output Swing and Matching Network How is an actual output stage connected to the double-transformer topology?

In (b), we “slice” the amplifier into two equal sections; place each in the close vicinity of its

respective primary.

Extended to a multitude of 1-to-1 transformers to obtain a greater RL/Rin ratio

2.4-GHz class E example employing four differential branches

33

PAs with Power Combining: a Multitude of 1-to-1 Transformers

Extended to a multitude of 1-to-1 transformers so as to obtain a greater RL/Rin ratio

2.4-GHz class E example employing four differential branches

The multiple amplifiers driving the 1-to-1 transformers in these topologies can also be turned off“individually”；

allowing output power control.

34

Class A amplifier design example (1)• Design a linear amplifier for use in

a 1-GHz communications system. • Requirements:

– supply 1W into 50Ω.– 3.3-V DC power supply

• w/o impedance transformation:

• Thus, impedance transformation is required.

• In practice, the 50Ω load resistance would have to be transformed to an even lower value. Here we use 4Ω.

• The peak RF current is

• The DC drain current bias must be set to approximately this value. Then

• When the amplifier is supplying 1W to the load, the transistor will be dissipating about 1.7W.

50LR = Ω

ov

DRIVEv

3.3V825mA

>6.4nH

11.7pF

0.6nH 32pF

2 2

max(3.3) 0.1W

2 2 50DDVPR

= = ≈⋅

2 2

maxmax

(3.3) 5.42 2 1

DDVRP

= = ≈ Ω⋅

out 3.3 4 825mADDv R V R= = =

1 37%0.825A 3.3V

o o

DC DC DD

P PP I V

η = = = ≈⋅

35

Class A amplifier design example (2)• We need to specify component

values for the output filter and matching network.

• Output filter:– a parallel LC tank with Q≈10 – 100MHz bandwidth at center

frequency of 1GHz

• The size of inductor, BFL (RF choke)– Its reactance is large enough (10

times as large as 4Ω resistance)

• Provide a DC blocking capacitor and an impedance-transforming network:

– High-pass L-match network– Q ≈3.4 (Q2=10)

• The inductor of the L-match can be combined with the tank inductor, yielding a 0.6nH inductor.

50LR = Ω

ov

DRIVEv

3.3V825mA

>6.4nH

11.7pF

0.6nH 32pF

55 0.80nH2 1GHzL

X Lπ

= ⇒ = =⋅

15 31.8pF5 2 1GHzC

X Cπ

= ⇒ = =⋅ ⋅

10 4 6.4nHBFLX BFL≥ ⋅ Ω⇒ ≥

1 90

2.3nH2 10 3.4

50LLQ

Rω π

= ≈ ≈⋅

1 90

1 1 11.7pF2 10 3.4 4SR

CQω π

= ≈ ≈⋅ Ω⋅

Lp L p

p

RQ R CL

ωω

= =

1ss

s

LQR R Cω

ω= =

36

Class A amplifier design example (3)

• Bias condition:– With the use of a current

mirror

• The signal to be amplified (vDRIVE) coupled to the circuit through another DC blocking capacitor.

50LR = Ω

OUTv

DRIVEv3.3V

825mA>6.4nH

11.7pF0.6nH 32pF

BIAS /I I n=

A/n A

37

Class C amplifier design example If we consider only the single-

ended implementation, then Class AB, B, and C amplifiers look extremely similar.

For Class B amplifier, bias would result in θ=1800, but not practical. Actually, they are Class AB or

C amplifiers; Even less drain current; A smaller gain (be a factor of

about 2 relative to Class A amplifier).

For Class C amplifier, the common practice in most semiconductor designs is to use a zero gate bias.

For Class AB amplifier, bias would result in 1800

Feeding circuit

38

Series mode Parallel mode

outDS DDv V v= +

𝑉𝑉𝐷𝐷𝐷𝐷

𝑉𝑉𝐷𝐷𝐷𝐷

vout

vout

Chapter 12 Power AmplifiersSections to be coveredChapter OutlineMotivations 幻灯片编号 5幻灯片编号 6General power amplifier modelSaturation RegionSaturation RegionClassification of Power AmplifiersClassification of Power Amplifiers: Class A Power AmplifiersImpedance of LC tank for harmonics Drain voltage and current for ideal class A amplifier幻灯片编号 14 Observations----Class A PA Conduction angle (导通角)How to improve efficiency? Efficiency of Class B Power Amplifiers (1)Efficiency of Class B Power Amplifiers (2)Class B Power Amplifier幻灯片编号 21Observations---Class B PA Class C Power Amplifiers: Overview幻灯片编号 24Efficiency of Class C Power Amplifiers (1)Efficiency of Class C Power Amplifiers (2)Efficiency of Class C Power Amplifiers (3)Example The Trade-Off between the Output Power and the Voltage Swing幻灯片编号 30PAs with Power Combining: Transformer-Based MatchingExamples of Output Swing and Matching NetworkPAs with Power Combining: a Multitude of 1-to-1 TransformersClass A amplifier design example (1)Class A amplifier design example (2)Class A amplifier design example (3)Class C amplifier design exampleFeeding circuit