Wei Wu Electrical Engineering Department

University of California, Los Angeles

Chapter 2

Interconnect Analysis

Delay Modeling

S2P and Effective Capacitance

2

Outline

Delay models

Review of Elmore Delay

Second Order Analysis (S2P algorithm)

Gate delay

3

( ) 1

t

RCV t e

R

C

V(t) 1v

How about more complex circuits?

Review of Elmore Delay

1

0.5

50% delay

RCt

e RC

t

69.0

5.0

50% Delay for lumped RC model

R1

C1

s

C3

R3

Ci

Ri

1

2

3

4

i

4

Example

Elmore delay at node i is

))()( iii433i43211

ii314313312111

iii4i43i32i21i1Di

CRCCCCCCCC0.69(R

))CRR(R)CR(R)CR(RCRC0.69(R

)CRCRCRCRC0.69(Rτ

R

R1

C1

s

C3

R3

Ci

Ri

1

2

3

4

i

5

Elmore Delay Approximation

The Elmore delay is the metric of choice for performance-driven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated

However, for deep submicron technologies (DSM), the

accuracy of the Elmore delay is insufficient

6

Outline

Delay models

Review of Elmore Delay

Second Order Analysis (S2P algorithm)

Gate delay

7

Second Order Analysis (Stable 2-Pole Delay Algorithm) General Idea: MOR Original RC network: 2 poles Model: (Model Order Reduction: AWE) Generate the time domain single from 2P model: eg:

Alternative solution: S2P Algorithm

( ), ( ) 0

1

qknH s Y s k

s pnn

0 1 1 2

21 2 1 2

( )1

b b s k kh s

s p s pa s a s

1 2ˆImpulse Response: ( ) ( ) ( )1 2p t p t

h t k e k e u t

Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi. 1999. “S2P: A Stable 2-

Pole RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great Lakes Symposium on

VLSI(GLS '99).

8

Moments of H(s)

Moments of H(s) are coefficients of the Taylor’s Expansion of H(s) about s=0

0

1( ) ( )! s

jdjm H sjj ds

0 0 0

2 31 12 3( ) ( ) ( ) ( ) ...0 2 32! 3!s s s

d d dH s H s H s s H s s H s

ds ds ds

(0) (1) 2 (2) 3 (3) ...m sm s m s m

9

Let Y(s) be an driving point admittance function of a general RC circuit. Consider its representation in terms poles and residues

where q is the exact order of the circuit

Moments of Y(s) can be written as:

( ) 0

1

qknY s k

s pnn

01

1

qknm ii ipnn

Driving Point Admittance

10

Compute m1, m2, m3 and m4 for Y(s) Find the two poles at the driving point admittance as follows: To match the voltage moments at the response nodes, choose and the S2P approximation is then expressed as:

Note that m0* and m1* are the moments of H(s). m0* is the Elmore delay.

S2P Algorithm

Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi. 1999. “S2P: A Stable 2-

Pole RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great Lakes Symposium on

VLSI(GLS '99).

11

S2P Vs. Elmore Delay

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0.4

0.5

0.6

0.7

0.8

0.9

1

t

Voltage

SPICE

Elmore

S2P

12

Outline

Delay models

Review of Elmore Delay

Second Order Analysis (S2P algorithm)

Gate delay

13

Gate Delay

BCABAC DelayDelayDelay

A B C

Inv 1 Inv 2

Overall flow of delay calculation

DelayAB: Gate delay DelayBC: RC network delay

14

General Model of a Gate

15

Definitions

Vin Vout

Time

Gate Delay

90%

10%

Output Transition Time

Gate/Cell

T in

Cloadt

in

16

The gate delay and the output transition time are functions of both input slew and the output load

Gate/Cell

T in

Cload

( , )in loadGate Delay f T C

( , )in loadOutput Transition Time f T C

Gate Delay and Output Transition Time

17

Output Response for Different Loads

18

Three approaches for gate propagation delay computation are based on: – Delay look-up tables – K-factor approximation Effective capacitance

Delay look-up table is currently in wide use especially in the ASIC design flow

Effective capacitance promises to be more accurate when the load is not purely capacitive

ASIC Cell Delay Model

19

What is the delay when Cload is 505f F and Tin is 90pS?

Cload (fF)

Tin

(pS)

0 5 10 500 505 510

50

70

90

110

310

330

115pS

Table Look-Up Method

20

We can fit the output transition time v.s. input

transition time and output load as a polynomial function, e.g.

A similar equation gives the gate delay

2( )1 2 3 4 5T k k C T k k C k Coutput load in load load

K-factor Approximation

2 2.4 2.8 3.2 3.6 4

x 10-10

5

6

7

8

9

10

11x 10

-11

Size=69 Cout=23fF

Size=48 Cout=15fF

Size=90 Cout=18fF

Input Transition Time (s)

Ou

tpu

t T

ran

siti

on

tim

e (s

)

10-10

1 1.4 1.8 2.2 2.6 3

x 10-14

6

7

8

9

10

11x 10

-11

Size=60 Tin=300pS

Size=81 Tin=350pS

Size=45 Tin=200pS

Ou

tpu

t T

ran

siti

on

tim

e (s

)

CLoad (F) 10-14

21

The gate delay and the output transition time are functions of both input slew and the output load

Gate/Cell

T in

Cload

( , )in loadGate Delay f T C

( , )in loadOutput Transition Time f T C

How to calculate the Cload??

22

Gate /Cell

T in

2 31 2 3( ) .....inY s A s A s A s

2 2 2 3 31 2 2 2( ) ( ) .....inY s C C s R C s R C s

22 232 2

1 1 233 32

AA AC A R C

A AA

Gate /Cell

Tin R

C1

C2

Using Taylor Expansion around s = 0

Second-order RC- Model

23

Gate /Cell

Tin R

C1

C2

1 2( , , , )inGate Delay f T C R C

This equation requires creation of a four-dimensional table to achieve high accuracy

This is however costly in terms of memory space and computational requirements

Second-order RC- Model (Cont’d)

24

The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC- load such that both circuits behave similarly during transition

What’s the value of Ceff, C1+C2???

Gate /Cell

Tin R

C1

C2

Gate /Cell

T in

Ceff

Effective Capacitance Approach

25

Output Response for Effective Capacitance

26

Effective Capacitance (Cont’d)

27

0<k<1

Gate /Cell

Tin R

C1

C2

21 kCCCeff

Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C2

R 0 k = 1

R ∞ k = 0

Gate /Cell

T in

Ceff

Effective Capacitance (Cont’d)

28

Effective Capacitance for Different Resistive Shielding

29

Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same

=> the effective capacitance is only a function of the output transition time and the load

GATE 2

Tin2 R

C1

C2

GATE 1

Tin1 R

C1

C2

Macy’s Approach

R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep

Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp. 313-316

30

1. Compute a from C1 and C2 2. Choose an initial value for

Ceff 3. Compute Tout for the given

Ceff and Tin

4. Compute b

5. Compute g from a and b 6. Find new Ceff 7. Go to step 3 until Ceff

converges

GATE 1

Tin1 R

C1

C2

21

1

CC

C

a

2CR

Tout

b

21 CC

Ceff

g

Macy’s Iterative Solution

R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep

Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp. 313-316

31

Summary

31

Delay model – Elmore Delay model – S2P model Reduce the RC network to a 2-pole model AWE is adopted for MOR

– Gate delay: look-up table, k-factor approximation, effective capacitance

A B C

Inv 1 Inv 2

32

References

32

R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep

Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp. 313-316

J. Qian, S. Pullela, and L. T. Pileggi, "Modeling the "effective capacitance" for the RC interconnect

of CMOS gates," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.

13, pp. 1526-1535, Dec. 1994.

Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI

interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996 (Section 2.1-2.2)

W. C. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to

Wideband Amplifiers”, Journal of Applied Physics, 1948.

Jorge Rubinstein, and etc. “Signal Delay in RC Tree Networks”, TCAD'83

Emrah Acar, Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi. 1999. “S2P: A Stable 2-Pole

RC Delay and Coupling Noise Metric”. In Proceedings of the Ninth Great Lakes Symposium on

VLSI(GLS '99).