Class 5 Timer Handout

8/7/2019 Class 5 Timer Handout

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C8051F020/1/2/3

Rev. 1.4 225

22. TIMERS

The C8051F020/1/2/3 devices contain 5 counter/timers: three are 16-bit counter/timers compatible with those found

in the standard 8051, and two are 16-bit auto-reload timers for use with the ADCs, SMBus, UART1, or for general

purpose use. These can be used to measure time intervals, count external events and generate periodic interrupt

requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timer 2 offers addi-tional capabilities not available in Timers 0 and 1. Timer 3 is similar to Timer 2, but without the capture or Baud Rate

Generator modes. Timer 4 is identical to Timer 2, and can supply baud-rate generation capabilities to UART1.

When functioning as a timer, the counter/timer registers are incremented on each clock tick. Clock ticks are derived

from the system clock divided by either one or twelve as specified by the Timer Clock Select bits (T4M-T0M) in

CKCON, shown in Figure 22.1. The twelve-clocks-per-tick option provides compatibility with the older generation

of the 8051 family. Applications that require a faster timer can use the one-clock-per-tick option.

When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected

input pin. Events with a frequency of up to one-fourth the system clock's frequency can be counted. The input signal

need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level

is sampled.

Timer 0 and Timer 1: Timer 2: Timer 3: Timer 4

13-bit counter/timer16-bit counter/timer with

auto-reload

16-bit timer with auto-

reload

16-bit counter/timer with

auto-reload

16-bit counter/timer16-bit counter/timer with

capture


capture


auto-reload

Baud rate generator for

UART0

Baud rate generator for

UART1

Two 8-bit counter/timers

(Timer 0 only)
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C8051F020/1/2/3

226 Rev. 1.4

Figure 22.1. CKCON: Clock Control Register

Bit7: UNUSED. Read = 0b, Write = dont care.

Bit6: T4M: Timer 4 Clock Select.

This bit controls the division of the system clock supplied to Timer 4. This bit is ignored when the

timer is in baud rate generator mode or counter mode (i.e. C/T4 = 1).

0: Timer 4 uses the system clock divided by 12.

1: Timer 4 uses the system clock.


This bit controls the division of the system clock supplied to Timer 2. This bit is ignored when the

timer is in baud rate generator mode or counter mode (i.e. C/T2 = 1).0: Timer 2 uses the system clock divided by 12.



This bit controls the division of the system clock supplied to Timer 1.

0: Timer 1 uses the system clock divided by 12.



This bit controls the division of the system clock supplied to Counter/Timer 0.

0: Counter/Timer uses the system clock divided by 12.

1: Counter/Timer uses the system clock.

Bits2-0: Reserved. Read = 000b, Must Write = 000.

R/W R/W R/W R/W R/W R/W R/W R/W Reset Value

- T4M T2M T1M T0M Reserved Reserved Reserved 00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:

0x8E


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C8051F020/1/2/3

Rev. 1.4 227

22.1. Timer 0 and Timer 1

Timer 0 and Timer 1 are accessed and controlled through SFRs. Each counter/timer is implemented as a 16-bit regis-

ter accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Con-

trol (TCON) register is used to enable Timer 0 and Timer 1 as well as indicate their status. Both counter/timers

operate in one of four primary modes selected by setting the Mode Select bits M1-M0 in the Counter/Timer Mode(TMOD) register. Each timer can be configured independently. Following is a detailed description of each operating

mode.

22.1.1. Mode 0: 13-bit Counter/Timer

Timer 0 and Timer 1 operate as a 13-bit counter/timer in Mode 0. The following describes the configuration and oper-

ation of Timer 0. However, both timers operate identically and Timer 1 is configured in the same manner as described

for Timer 0.

The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-

TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when read-

ing. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag

TF0 (TCON.5) is set and an interrupt will occur if enabled.

The C/T0 bit (TMOD.2) selects the counter/timer's clock source. Clearing C/T selects the system clock as the input

for the timer. When C/T0 is set to logic 1, high-to-low transitions at the selected input pin (T0) increment the timer

register. (Refer to Section 17.1. Ports 0 through 3 and the Priority Crossbar Decoder on page 163 for informa-

tion on selecting and configuring external I/O pins for digital peripherals.)

Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is 0 or the input signal /INT0 is

logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0, facili-

tating pulse width measurements.

Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value before

enabling the timer.

TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1

is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.

TR0 GATE0 /INT0 Counter/Timer

0 X X Disabled

1 0 X Enabled1 1 0 Disabled

1 1 1 Enabled

X = Don't Care


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C8051F020/1/2/3

228 Rev. 1.4

22.1.2. Mode 1: 16-bit Counter/Timer

Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are

enabled and configured in Mode 1 in the same manner as for Mode 0.

Figure 22.2. T0 Mode 0 Block Diagram

TCLK TL0

(5 bits)

TH0

(8 bits)

TCO

N

TF0TR0

TR1TF1

IE1

IT1IE0IT0

Interrupt

/INT0 TR0

T0

Crossbar

0

1

0

1

TMOD

T1

M

1

T1

M

0

C/

T

1

GA

T

E

1

GA

T

E

0

C/

T

0

T0

M

1

T0

M

0

SYSCLK

12

CKCON

T4

M

T2

M

T1

M

T0

M

GATE0


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C8051F020/1/2/3

Rev. 1.4 229

22.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload

Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value.

The TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00,

the timer overflow flag TF0 (TCON.5) is set and the counter value in TL0 is reloaded from TH0. If enabled, an inter-

rupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to thedesired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically

to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0.

Figure 22.3. T0 Mode 2 (8-bit Auto-Reload) Block Diagram

TCLK

TMOD

T1M1

T1M0

C/T1

GATE1

GATE0

C/T0

T0M1

T0M0

TCON

TF0TR0

TR1TF1

IE1IT1IE0IT0

InterruptTL0

(8 bits)

ReloadTH0

(8 bits)

/INT0 TR0

T0

Crossbar

0

1

0

1

CKCON

T

4

M

T

2

M

T

1

M

T

0

M

SYSCLK

12

GATE0


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C8051F020/1/2/3

230 Rev. 1.4

22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)

Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held in

TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD:

TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The timer

in the TH0 register is restricted to a timer function sourced by the system clock. TH0 is enabled using the Timer 1 runcontrol bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt.

Timer 1 is inactive in Mode 3, so with Timer 0 in Mode 3, Timer 1 can be turned off and on by switching it into and

out of its Mode 3. When Timer 0 is in Mode 3, Timer 1 can be operated in Modes 0, 1 or 2, but cannot be clocked by

external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to gener-

ate the baud clock for UART0 and/or UART1. Refer to Section 20. UART0 on page 205 and Section

21. UART1 on page 215 for information on configuring Timer 1 for baud rate generation.

Figure 22.4. T0 Mode 3 (Two 8-bit Timers) Block Diagram

TL0(8 bits)

TMOD

/INT0 TR0

T0

Crossbar

0

1

TCON

TF0TR0

TR1TF1

IE1IT1IE0IT0

Interrupt

Interrupt

TR1 TH0(8 bits)

T1M1

T1M0

C/T1

GATE1

GATE0

C/T0

T0M1

T0M0

CKCON

T4

M

T2

M

T1

M

T0

M

0

1

SYSCLK

12

GATE0


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C8051F020/1/2/3

232 Rev. 1.4

Figure 22.6. TMOD: Timer Mode Register

Bit7: GATE1: Timer 1 Gate Control.

0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.

1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic 1.

Bit6: C/T1: Counter/Timer 1 Select.

0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).

1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin (T1).

Bits5-4: T1M1-T1M0: Timer 1 Mode Select.

These bits select the Timer 1 operation mode.

Bit3: GATE0: Timer 0 Gate Control.

0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.

1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic 1.

Bit2: C/T0: Counter/Timer Select.

0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).

1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin (T0).

Bits1-0: T0M1-T0M0: Timer 0 Mode Select.These bits select the Timer 0 operation mode.


GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000


0x89

T1M1 T1M0 Mode0 0 Mode 0: 13-bit counter/timer

0 1 Mode 1: 16-bit counter/timer

1 0 Mode 2: 8-bit counter/timer with auto-reload

1 1 Mode 3: Timer 1 inactive

T0M1 T0M0 Mode



1 0 Mode 2: 8-bit counter/timer with auto-reload

1 1 Mode 3: Two 8-bit counter/timers


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C8051F020/1/2/3

Rev. 1.4 233

Figure 22.7. TL0: Timer 0 Low Byte

Bits 7-0: TL0: Timer 0 Low Byte.

The TL0 register is the low byte of the 16-bit Timer 0.


00000000


0x8A

Figure 22.8. TL1: Timer 1 Low Byte

Bits 7-0: TH0: Timer 0 High Byte.

The TH0 register is the low byte of the 16-bit Timer 1.


00000000

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:0x8B


The TH0 register is the high byte of the 16-bit Timer 0.


00000000


0x8C

Figure 22.9. TH0 Timer 0 High Byte

Figure 22.10. TH1: Timer 1 High Byte


The TH1 register is the high byte of the 16-bit Timer 1.


00000000


0x8D


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C8051F020/1/2/3

Rev. 1.4 117

Table 12.4. Interrupt Summary

Interrupt SourceInterrupt

Vector

Priority

OrderPending Flag

Bitaddressable?

Cleared

byHW?

Enable

Flag

Priority

Control

Reset 0x0000 Top None N/A N/AAlways

Enabled

Always

Highest

External Interrupt 0 (/INT0) 0x0003 0 IE0 (TCON.1) Y Y EX0 (IE.0) PX0 (IP.0)

Timer 0 Overflow 0x000B 1 TF0 (TCON.5) Y Y ET0 (IE.1) PT0 (IP.1)

External Interrupt 1 (/INT1) 0x0013 2 IE1 (TCON.3) Y Y EX1 (IE.2) PX1 (IP.2)

Timer 1 Overflow 0x001B 3 TF1 (TCON.7) Y Y ET1 (IE.3) PT1 (IP.3)

UART0 0x0023 4RI0 (SCON0.0)

TI0 (SCON0.1)Y ES0 (IE.4) PS0 (IP.4)

Timer 2 Overflow (or EXF2) 0x002B 5 TF2 (T2CON.7) Y ET2 (IE.5) PT2 (IP.5)

Serial Peripheral Interface 0x0033 6 SPIF (SPI0CN.7) Y ESPI0(EIE1.0)

PSPI0(EIP1.0)

SMBus Interface 0x003B 7 SI (SMB0CN.3) YESMB0

(EIE1.1)

PSMB0

(EIP1.1)

ADC0 Window Comparator 0x0043 8AD0WINT

(ADC0CN.2)Y

EWADC0

(EIE1.2)

PWADC0

(EIP1.2)

Programmable Counter Array 0x004B 9

CF (PCA0CN.7)

CCFn

(PCA0CN.n)

YEPCA0

(EIE1.3)

PPCA0

(EIP1.3)

Comparator 0 Falling Edge 0x0053 10CP0FIF

(CPT0CN.4)

ECP0F

(EIE1.4)

PCP0F

(EIP1.4)

Comparator 0 Rising Edge 0x005B 11CP0RIF

(CPT0CN.5)

ECP0R

(EIE1.5)

PCP0R

(EIP1.5)

Comparator 1 Falling Edge 0x0063 12CP1FIF

(CPT1CN.4)

ECP1F

(EIE1.6)

PCP1F

(EIP1.6)

Comparator 1 Rising Edge 0x006B 13CP1RIF

(CPT1CN.5)

ECP1R

(EIE1.7)

PCP1F

(EIP1.7)

Timer 3 Overflow 0x0073 14 TF3 (TMR3CN.7)ET3

(EIE2.0)

PT3

(EIP2.0)

ADC0 End of Conversion 0x007B 15AD0INT

(ADC0CN.5)Y

EADC0

(EIE2.1)

PADC0

(EIP2.1)

Timer 4 Overflow 0x0083 16 TF4 (T4CON.7)ET4

(EIE2.2)

PT4

(EIP2.2)

ADC1 End of Conversion 0x008B 17AD1INT

(ADC1CN.5)

EADC1

(EIE2.3)

PADC1

(EIP2.3)External Interrupt 6 0x0093 18 IE6 (P3IF.5)

EX6

(EIE2.4)

PX6

(EIP2.4)

External Interrupt 7 0x009B 19 IE7 (P3IF.6)EX7

(EIE2.5)

PX7

(EIP2.5)

UART1 0x00A3 20RI1 (SCON1.0)

TI1 (SCON1.1)ES1 PS1

External Crystal OSC Ready 0x00AB 21XTLVLD

(OSCXCN.7)

EXVLD

(EIE2.7)

PXVLD

(EIP2.7)


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C8051F020/1/2/3

118 Rev. 1.4

12.3.3. Interrupt Priorities

Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter-

rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be preempted. Each

interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority level. Low priority

is the default. If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. Ifboth interrupts have the same priority level, a fixed priority order is used to arbitrate, given in Table 12.4.

12.3.4. Interrupt Latency

Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled

and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock cycles:

1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is pending

when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending interrupt.

Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the

new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as the

next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock

cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL

to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be

serviced until the current ISR completes, including the RETI and following instruction.
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C8051F020/1/2/3

Rev. 1.4 119

12.3.5. Interrupt Register Descriptions

The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet

section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the

peripheral and the behavior of its interrupt-pending flag(s).

Figure 12.9. IE: Interrupt Enable

Bit7: EA: Enable All Interrupts.

This bit globally enables/disables all interrupts. When set to 0, individual interrupt mask settings are

overridden.

0: Disable all interrupt sources.

1: Enable each interrupt according to its individual mask setting.Bit6: IEGF0: General Purpose Flag 0.

This is a general purpose flag for use under software control.

Bit5: ET2: Enabler Timer 2 Interrupt.

This bit sets the masking of the Timer 2 interrupt.

0: Disable Timer 2 interrupt.

1: Enable interrupt requests generated by the TF2 flag (T2CON.7).

Bit4: ES0: Enable UART0 Interrupt.

This bit sets the masking of the UART0 interrupt.

0: Disable UART0 interrupt.

1: Enable UART0 interrupt.

Bit3: ET1: Enable Timer 1 Interrupt.


0: Disable all Timer 1 interrupt.

1: Enable interrupt requests generated by the TF1 flag (TCON.7).

Bit2: EX1: Enable External Interrupt 1.

This bit sets the masking of external interrupt 1.

0: Disable external interrupt 1.

1: Enable interrupt requests generated by the /INT1 pin.

Bit1: ET0: Enable Timer 0 Interrupt.


0: Disable all Timer 0 interrupt.

1: Enable interrupt requests generated by the TF0 flag (TCON.5).

Bit0: EX0: Enable External Interrupt 0.

This bit sets the masking of external interrupt 0.

0: Disable external interrupt 0.1: Enable interrupt requests generated by the /INT0 pin.


EA IEGF0 ET2 ES0 ET1 EX1 ET0 EX0 00000000


(bit addressable) 0xA8

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Class 5 Timer Handout