Class Note on Digital Electronics

1.0 Bipolar Transistor Switching Characteristics:

-Surendra ShresthaDepartment of Electronics and Computer

EngineeringPulchowk Campus, Institute of Engineering,

T.U.

1.1 The Ebers-Moll equation

1.2 Depletion region charge and delay time

1.3 Base region charge and the succession of steady states model

1.4 Rise storage and fall time calculations

Department of Electronics and Computer Engineering

Pulchowk Campus, Institute of Engineering, T.U.

1.1 The Ebers-Moll equation

- Basis on the equivalent circuit model of Bipolar junction transistor (BJT)

- Model develop by Ebers and Moll in 1954 (also known as earliest ac model)

- looks like a ‘T’ on its side, the equivalent circuit is also called T-model and as well as also called “coupled diode model”.























Depletion region charge and Delay Time

Cross section of npn junction transistor



Base width modulation

As the voltages applied to the base-emitter and base-collector junctions are changed, the depletion layer widths and the quasi-neutral regions vary as well. This causes the collector current to vary with the collector-emitter voltage as illustrated in Figure 1.

Figure 1. Variation of the minority-carrier distribution in the base quasi-neutral region due to a variation of the base-collector voltage



A variation of the base-collector voltage results in a variation of

the quasi-neutral width in the base. The gradient of the

minority-carrier density in the base therefore changes, yielding

an increased collector current as the collector-base current is

increased. This effect is referred to as the Early effect. The

Early effect is observed as an increase in the collector current

with increasing collector-emitter voltage as illustrated with

Figure 2. The Early voltage, VA, is obtained by drawing a line

tangential to the transistor I-V characteristic at the point of

interest. The Early voltage equals the horizontal distance

between the point chosen on the I-V characteristics and the

intersection between the tangential line and the horizontal axis.

It is indicated on the figure by the horizontal arrow.



Collector current increase with an increase of the collector-emitter voltage due to the Early effect. The Early voltage, VA, is also indicated on the figure



The change of the collector current when changing the

collector-emitter voltage is primarily due to the variation of the

base-collector voltage, since the base-emitter junction is

forward biased and a constant base current is applied. The

collector current depends on the base-collector voltage since the

base-collector depletion layer width varies, which also causes

the quasi-neutral width, wB', in the base to vary. This variation

can be calculated for a piece-wise uniformly-doped transistor

using the ideal transistor mode:

(1)



This variation can be expressed by the Early voltage, VA,

which quantifies what voltage variation would result in

zero collector current.

(2)



It can be shown that the Early voltage also equals the

majority carrier charge in the base, QB, divided by the base-

collector junction capacitance, Cj,BC = s/(xp,BC + xn,BC), where

xp,BC and xn,BC are given by



The Early voltage can also be linked to the output conductance,

r0, which equals:

(4)

(3)



In addition to the Early effect, there is a less pronounced effect

due to the variation of the base-emitter voltage, which changes

the ideality factor of the collector current. However, the effect

at the base-emitter junction is much smaller since the base-

emitter junction capacitance is larger and the base-emitter

voltage variation is very limited since the junction is forward

biased. This effect does lead to a variation of the ideality factor,

n, given by:

(5)



(6)

The collector current is therefore of the following form:

where, IC,s is the collector saturation current.



# Consider a bipolar transistor with a base doping of 1017 cm-3 and a quasi-neutral base width of 0.2 mm. Calculate the Early voltage and collector current ideality factor given that the base-emitter capacitance and the base-collector capacitance are 0.2 nF and 0.2 pF. The collector area equals 10-4 cm-2.

The Early voltage equals:

The saturation voltage equals:



So far, we have ignored the recombination in the depletion

region. As in a p-n diode, the recombination in the depletion

region causes an additional diode current. We can identify

this contribution to the current because of the different

voltage dependence. Shown are the collector and base

current of a silicon bipolar transistor, biased in the forward

active mode of operation with VBC = -12 V, as a function of

the base-emitter voltage. This type of plot is also called a

Gummel plot.

Recombination in the depletion region



The current due to recombination in the depletion region can be observed as an additional base current between VBE = 0.2 and 0.4 V. The collector current does not include this additional current, since recombination in the depletion region does not affect the flow of electrons through the base.



Recombination in the depletion region

Gummel plot: Collector current (top curve) and base current (bottom curve) of a silicon bipolar transistor versus the base-emitter voltage.

http://ece-www.colorado.edu/~bart/book/book/chapter5/xls/fig5_4_3.xls

Department of Electronics and Computer EngineeringPulchowk Campus, Institute of Engineering, T.U.

1.4 Rise Storage and Fall time (BJT Switching Time)

basic BJT switch and its load line

Department of Electronics and Computer EngineeringPulchowk Campus, Institute of Engineering, T.U.

1.4 Rise Storage and Fall time (BJT Switching Time)

In figure a, an ideal waveform applied to the base (input) of a

BJT switch.

In figure b

and c, show

the resulting

Collector

(output)

Current

and

Voltage

waveforms.



The overall time delay between input and output transitions

(measured at the 50% points) is called propagation delay. There

are four transistor switching times that contribute to

propagation delay. These times can be defined as follows:

1. Delay time ( td ) is the time required for the BJT to

come out of cutoff. As shown in Figure, this is the time

required for VC to drop to 90% of its high-state value.



2. Rise time ( tr ) is the time required for the

BJT to make the transition from cutoff to

saturation. As shown in Figure, rise time is

measured from the 90% to the 10% points on

the VC waveform.

3. Storage time ( ts ) is the time required for the

BJT to come out of saturation. As shown in

Figure, this is the time required for the VC

to reach 10% of its high-state value.



4. Fall time ( tf ) is the time required for the BJT to

make the transition from saturation to cutoff. As

shown in Figure, fall time is measured from the

10% to the 90% points on the VC waveform.

The times are defined (above) in terms of transistor

collector voltage because they are commonly measured

with an oscilloscope.



Improving BJT Switching Time

Reducing delay time. When a BJT is in cutoff, the depletion layer is at its maximum width and IC 0 A. When the input to the BJT goes positive, the depletion layer starts to dissolve, allowing IC to begin increasing. Delay time ( td ) is the time required for IC to rise to 10% of IC

(max) . There are three factors that affect how long this takes:1. The physical characteristics of the BJT. 2. The amount of reverse bias initially applied to the device. 3. The value of that the input signal generates when it goes positive.

Rise time. Rise time ( tr ) is the time required for the collector current to rise from 10% to 90 % of IC (max) . This is caused by the time required for the depletion layer to fully dissolve. It is a function of the physical characteristics of the device and there is nothing we can do to reduce its value.

Reducing storage time. The biggest overall delay is storage time ( ts ). When a BJT is in saturation, the base region is flooded with charge carriers. When the input goes low, it takes a long time for these charge carriers to leave the region and allow the depletion layer to begin to form. The amount of time this takes is a function of three factors:

4. The physical characteristics of the device. 2. The initial value of IC . 3. The initial value of reverse bias voltage applied at the base.

Fall time. Like rise time, fall time ( tf ) is a function of the physical characteristics of the transistor, and there is nothing we can do to reduce its value.

Putting all these statements together, we see that delay and storage time can be reduced by:

1. Applying a high initial value of IB (to decrease delay time) that settles down to some value lower than that required to saturate the transistor (to reduce storage time).

2. Applying a high initial reverse bias (to reduce storage time) that settles down to the minimum value required to keep the transistor in cutoff (to reduce delay time).



Improving BJT Switching TimeReducing delay time.

When a BJT is in cutoff, the depletion layer is at its maximum width and IC 0 A. When the input to the BJT goes positive, the

depletion layer starts to dissolve, allowing IC to begin

increasing. Delay time ( td ) is the time required for IC to rise to

10% of IC (max) . There are three factors that affect how long this

takes:

1. The physical characteristics of the BJT. 2. The amount of reverse bias initially applied to the

device.3. The value of that the input signal generates when it

goes positive.




Rise time:

Rise time ( tr ) is the time required

for the collector current to rise

from 10% to 90 % of IC (max) .

This is caused by the time required for the depletion layer to

fully dissolve. It is a function of the physical characteristics

of the device and there is nothing we can do to reduce its

value.




Reducing storage time.

The biggest overall delay is storage time ( ts ). When a BJT is in

saturation, the base region is flooded with charge carriers. When

the input goes low, it takes a long time for these charge carriers to

leave the region and allow the depletion layer to begin to form.

The amount of time this takes is a function of three factors:

1. The physical characteristics of the device.

2. The initial value of IC .

3. The initial value of reverse bias voltage applied at the base.




Fall time. Like rise time, fall time ( tf ) is a function of the physical characteristics of the transistor, and there is nothing we can do to reduce its value.

Putting all these statements together, we see that delay and storage time can be reduced by:

1. Applying a high initial value of IB (to decrease delay time) that settles down to some value lower than that required to saturate the transistor (to reduce storage time).

2. Applying a high initial reverse bias (to reduce storage time) that settles down to the minimum value required to keep the

transistor in cutoff (to reduce delay time).



Figure: Speed-up capacitor and resulting waveforms

This capacitor, called a speed-up capacitor, CS is connected across the base resistor. The VB waveforms in the figure are the result of adding the capacitor to the circuit.



When the input first goes negative, the charge on the

speed-up capacitor briefly drives the base to –5 V. This drives the

transistor quickly into cutoff. As soon as the capacitor discharges,

the base voltage returns to 0 V. This ensures that the base-emitter

junction is not heavily reverse biased. In this way, all of the

desired criteria for reducing switching time are met.

When Vin initially goes high, the capacitor acts like a short circuit

around RB . As a result, the input signal is coupled directly to the

base for a brief instant. This results in a high initial voltage spike

being applied to the base, generating a high initial value of IB . As

the capacitor charges, IB decreases to the point where IC is held

just below the saturation point.

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Class Note on Digital Electronics