Closed Loop Compensation of a Synchronous Switching Charger

Application ReportSLUA371–September 2006

Closed-Loop Compensation Design of a SynchronousSwitching Charger Using bq2472x/3x

Lingyin Zhao........................................................................................................ PMP Portable Power

ABSTRACT

Design of the loop compensator is one of the key challenges in the circuit design of aswitching charger. This application report presents the internal control loop operation ofthe bq2472x/3x as well as the external compensator design guideline. The modeling ofthe nonlinear behavior of a switching charger is based on the state space averagemodel. A design example based on practical specifications is demonstrated.

Contents1 Buck-Type Charger Power Stage Small-Signal Model ........................................ 22 bq2472x/3x Control-Loop Model and Compensation Design ................................. 63 Design Example .................................................................................... 94 Reference .......................................................................................... 19

List of Figures

1 The Power Stage of a Buck-Type Charger ..................................................... 22 Three-Terminal Model of a PWM Switch in CCM .............................................. 23 Control-to-Output Small-Signal Model in CCM ................................................. 34 Three-Terminal Model of a PWM Switch in DCM .............................................. 45 Control-to-Output Small-Signal Model in DCM ................................................. 56 PWM and Error Amplifiers Block of bq2472x/3x................................................ 67 Simplified Control-Loop Block Diagram.......................................................... 78 A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions ... 89 A Type III Compensator ........................................................................... 810 Bode Plot of a Typical Type III Compensator................................................... 811 Control-to-Output-Voltage Transfer Function.................................................. 1012 Control-to-Charge-Current Transfer Function ................................................. 1113 Control-to-Input-Current Transfer Function .................................................... 1214 Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain .......... 1315 Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)................................. 1416 Output-Voltage Loop Gain TV (CCM)........................................................... 1517 Charge-Current Loop Gain Tis (CCM) .......................................................... 1618 Input-Current Loop Gain Tii (CCM).............................................................. 1719 Output-Voltage Loop Gain TV (DCM)........................................................... 1820 Input-Current Loop Gain Tii (DCM) ............................................................. 19

SLUA371–September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 1Submit Documentation Feedback

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1 Buck-Type Charger Power Stage Small-Signal Model

Q2

VIN

ISL

Q1

RC2 Z

L

RL VORSNS

C2

IL

RC1

C1

1.1 Continuous Conduction Mode (CCM) Small-Signal Model

Q1

Q2

ca

p

(a) a PWM Switch

a c

p

1 D1I dC

^

(b) Small-Signal Model

Vap

Dˆd

Buck-Type Charger Power Stage Small-Signal Model

A typical stage of a synchronous buck-type switching battery charger is shown in Figure 1.

Figure 1. The Power Stage of a Buck-Type Charger

The small-signal model is obtained from the relationships among the perturbation in average terminalquantities at a given dc operating point. The model is different under continuous conduction mode (CCM)and discontinuous conduction mode (DCM).

The average values of the switch network terminal waveforms can be determined in terms of the converterstate variables and the converter independent inputs. The basic assumption is made that the natural timeconstants of the converter network are much longer than the switching period Ts. This assumptioncoincides with the requirement for small switching ripple. The resulting averaged model predicts thelow-frequency behavior of the system, while neglecting the high-frequency switching harmonics [1]. Thethree-terminal model for a PWM switch network in CCM is illustrated in Figure 2.

Figure 2. Three-Terminal Model of a PWM Switch in CCM

To perform the CCM small-signal analysis, the PWM switch in the buck converter is substituted with thethree-terminal model in CCM and Vin is shorted, as shown in Figure 3.

2 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371–September 2006Submit Documentation Feedback


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L

C2C1

RC1 RC2

RSNS

ZL

RLL

is

i ov

1 D

dD

Vin

ii L

C2C1

RC1 RC2

RSNS

ZL

RLL

is

i ov

1 D

dD

Vin

ii

Gvd(s) V

o

d Vin ZL

sz1

1 sz2

13s3 2s2 1s 0 (1)

Gisd(s) i

s

d Vin

sz1

1 sz3

13s3 2s2 1s 0 (2)

Giid(s)i

i

d IL Vin

2s2 1s 1

3s3 2s2 1s 0 (3)

z11

RC1 C1 (4)

z21

RC2 C2 (5)

z3 1RC1 ZL

C2 (6)

3 RC2 ZL RSNS RC1RC2 ZL

L C1 C2 (7)

2 RL RC1RC2 ZL RSNS RC1

RC2 ZL C1 C2 ZL RSNS RC1

L C1 RC2 ZL L R2

C1 C1 C2 (8)

1 RC2 ZL RSNS RLRC2 ZL

C2 ZL RSNS RL RL RC1

C1 L R2L C1

0 ZL RSNS RL (10)

2 RC2 ZL RSNS RC1 RC2 ZL

C1 C2 (11)

1 ZL RSNS RC1 C1 RC2 ZL

C2 (12)


Figure 3. Control-to-Output Small-Signal Model in CCM

The open-loop control-to-output-voltage transfer function is given as:

Compared to a regular buck-type converter, this topology results in one more zero and one more pole,both at high frequencies under normal conditions.

The open-loop control-to-charge-current transfer function is given as:

The open-loop control-to-input-current transfer function is given as:

in which,

(9)

Approximately, Gvd (s) and Gisd (s) can be presented as



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Gvd(s) Vin ZL

ZL RSNS RL

sz1

1 sz2

1

s2

20 s0Q

1 sp1

1(13)

G isd(s) Vin 1

ZL RSNS RL

sz1

1 sz3

1

s2

20 s0Q

1 sp1

1(14)

p1 ZL RSNS RL

C1 C2

RC2 ZL RSNS RC1 RC2 ZL

C1 C2 (15)

0 1L C1 C2

(16)

Q 10 RL RC1

C1 C2

(17)

1.2 Discontinuous Conduction Mode (DCM) Small-Signal Model

MVoVin (18)

D 2(M2)2

M2 1

K(M 2)2

M2 1

(19)

K2L fs

VoIo (20)

Q1

Q2

ca

p

(a) a PWM Switch

a c

p

dko

acv

ogacfvg cpv

dki

ig

a c

p

dko

acv

ogacfvg cpv

dki

ig

(b) Small-Signal Model


in which,

Under DCM conditions, assume the dc voltage gain is

The duty cycle is given by

in which,

The three-terminal model for a PWM switch network in CCM is illustrated in Figure 4.

Figure 4. Three-Terminal Model of a PWM Switch in DCM



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ki2IaD (21)

ko2IpD (22)

giIa

Vac (23)

goIp

Vcp (24)

gf2IpVac (25)

dko og

ig

fg

dki L

C2C1

RC1 RC2

RSNS

ZL

RL Li si ov

ii dko og

ig

fg

dki L

C2C1

RC1 RC2

RSNS

ZL

RL Li si ov

ii

giD2

2L fs (26)

ki2IoM

D (27)

kd ki ko2IoD (28)

r 1gi go gf

VoIo

(I M)(29)

Gvd_DCM(s) v

o

d kd ZL

sz1

1 sz2

13s3 2s2 1s 0 (30)

G iid_DCM(s)i

i

d ki gi kd r gi Kd r

2s2 1s 13s3 2s2 1s 0 (31)

3 L C1 C2

r RC2 ZL RSNS RC1RC2 ZL

(32)


To perform the DCM small-signal analysis, the PWM switch in the buck converter is substituted with thethree-terminal model in DCM and Vin is shorted, as shown in Figure 5.

Figure 5. Control-to-Output Small-Signal Model in DCM

In a buck converter operating in DCM, the following equations can be obtained:

The open-loop, control-to-output-voltage transfer function is given as:

The open-loop, control-to-input-current transfer function is given as:

in which,



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2 C1 C2

r RC2 ZL RSNS RC1RC2 ZL

RC1 RSNS RC2 ZL

LrRSNS RC1 ZL

C1 RC2 ZL C2

(33)

1 C1r RL r RSNS RC1 ZL

RC1 RSNS RC1 ZL

RL r RSNS RC2 ZL

RC2 ZL L

r (34)

0RL r RSNS ZL

r (35)

2 C1 C2 RC2 ZL RSNS RC1RC2 ZL

(36)

1 RSNS RC1 ZL C1 RC2 ZL

C2 (37)

2 bq2472x/3x Control-Loop Model and Compensation Design

2.1 bq2472x/3x Control-Loop Model

bq2472x/3x Control-Loop Model and Compensation Design

The PWM and error amplifiers block of bq2472x/3x is illustrated in Figure 6. It consists of three feedbackloops: output-voltage loop, charge-current loop, and input-current loop (DPM loop). However, only one ofthem dominates at one time. The simplified control-loop block diagram is depicted in Figure 7.

Figure 6. PWM and Error Amplifiers Block of bq2472x/3x



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d

ii

ov

Power Stage

G vd, G isd, G iid

-A(s ) FGFM

si

dˆ

cv

iv

d

ii

ov

Power Stage

G vd, G isd, G iid

-A(s ) FGFM

si

dˆ

cv

iv

FG grd gv

16 6 1 (for 3 cell)

18 6 0.75 (for 4 cell)

(38)

FG RSNS gSR Tdamp1 40 RSNS Tdamp1 (39)

Tdamp1(s) 1

shfp1

1 shfp2

1(40)

FG RSNS gAC Tdamp2 40 RSNS Tdamp2 (41)

Tdamp2(s) Tdamp1(s)(42)

FM 1Vp (43)

Tv Gvd FG A(s) FM (44)T is Gisd FG A(s) FM (45)T ii Giid FG A(s) FM (46)


Figure 7. Simplified Control-Loop Block Diagram

In Figure 7, FG is the feedback gain whose value depends on which loop is operating.

For the output-voltage loop,

in which grd and gv are the resistor divider gain and the voltage amplifier gain, respectively. For thecharge-current loop,

in which RSNS and gSR are the charge-current-sense resistor value and the charge-current amplifier gain,respectively. Tdamp1 is the transfer function of the network added to damp the high-frequency harmonicsfor this loop. It contains a pole at 60 kHz and another at 150 kHz.

For the DPM loop,

in which RSNA and gAC are the adapter input current-sense resistor value and the input current amplifiergain, respectively. Tdamp2 is the transfer function of the network added to damp the high-frequencyharmonics for this loop. It contains a pole at 60 kHz and another at 150 kHz.

In Figure 7, A(s) is the compensator transfer function and FM is the control voltage to duty-cycle transferfunction. To generate a PWM drive signal, the control voltage Vc is compared with a ramp waveform, asshown in Figure 6. The ramp peak voltage Vp = Vcc/10. Thus, the value of FM can be obtained as:

The three loop gains are given by



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2.2 bq2472x/3x Compensator Design

f - Frequency

Ma

gn

itu

de

- d

B

C3_com

R1_com

C2_com

1_com R3_com

R2_com

FBOEAI3_com

1_com

2_com

C1_com 3_com

2_com

EAO

f - Frequency

Magnitude -

dB

Integrator

Zero 1 Zero 2

Pole 1 Pole 2

Integrator

Zero 1 Zero 2

Pole 1 Pole 2


From Equation 13 and Equation 14, it can be seen that the power stage CCM open-loop transfer functionsare basically a three-pole-two-zero system. A typical Bode plot of the converter control to output gainunder CCM conditions is shown in Figure 8. However, it can be simplified as a double-pole systembecause ωz1, ωz2, and ωp1 are normally located at high frequencies where the average model is not validany longer.

Figure 8. A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions

A Type III compensator is a promising candidate for this application. The typical realization of a Type IIIcompensator is demonstrated in Figure 9. Its typical frequency response is depicted in Figure 10.

Figure 9. A Type III Compensator

Figure 10. Bode Plot of a Typical Type III Compensator



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A(s) K

sz1_com

1 sz2_com

1

s sp1_com

1 sp2_com

1(47)

K 1

R1_com C1_com C3_com (48)

z1_com1

R3_com C1_com (49)

z2_com 1R1_com R2_com C2_com (50)

p1_com1

R2_com C2_com (51)

p2_com1

R3_comC1_comC3_com

C1_comC3_com (52)

3 Design Example

3.1 Specifications

Design Example

An integrator is needed for a high dc gain. Two zeroes need to be put below the loop gain crossoverfrequency fc to compensate the excessive phase lag due to the integrator and the power stage complexpole pair. In order to attenuate the high-frequency noise, two high frequency poles are added to ensurethe magnitude of the loop gain keeps decreasing after the 0-dB crossover. The two poles must be placedbelow half of the switching frequency.

The transfer function of the compensator is given as:

where

Vin = 19 V, L = 10 µH, C1 = C2 = 20 µF, RSNS = RSNA = 10 mΩ, RC1 = RC2 = 10 mΩ, RL = 20mΩ,Vbat = 9 V – 12.6 V (3s2p), Ichrg = 4 A, fs = 300 kHz



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3.2 Power Stage Open-Loop Transfer Functions (CCM)

20

60

0

-20

-60

1 10 100 1 k 10 k 100 k 1 M

f - Frequency - Hz(a) Gain

Ma

gn

itu

de

- d

B

Z = 17.8L W

Z = 2.25L W

f - Frequency - Hz(b) Phase

1 10 100 1 k 10 k 100 k 1 M

180

0

-180

Z = 17.8L W

Z = 2.25L W

Ph

as

e -

De

g

Design Example

The transfer functions of the converter in CCM are illustrated in Figure 11, Figure 12, and Figure 13.

Figure 11. Control-to-Output-Voltage Transfer Function



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100

0

-100

1 10 100 1 k 100 k10 k 1 M


Ma

gn

itu

de

- d

B

Z = 2.25L W

Z = 17.8L W

Z = 17.8L W

Z = 2.25L W

1 10 100 1 k 100 k10 k 1 M


100

0

-180

Ph

as

e -

de

g

Design Example

Figure 12. Control-to-Charge-Current Transfer Function



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100

20

0

-20

-100

1 10 100 1 k 10 k 100 1 M

Z = 2.25L W

Z = 17.8L W

Ma

gn

itu

de

- d

B


Z = 2.25L W

Z = 17.8L W

1 10 100 1 k 10 k 100 1 M


180

0

-180

Ph

as

e -

de

g

3.3 Compensator Design Procedure

z11

RC1 C1 796 kHz

(53)

z21

RC2 C2 796 kHz

(54)

0 1L C1 C2

8 kHz

(55)

Design Example

Figure 13. Control-to-Input-Current Transfer Function

From the preceding calculation, the following parameters can be obtained:

Place the two compensator zeros before the resonant frequency of the converter (f0) to improve the DCMstability.



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z1_com 2 0.5 f0 25 kHz(56)

p1_com p2_com12

2fs 943 kHz(57)

p1_com p2_com12

2fs 943 kHz(58)

TV(S)

Gvd(S)

A(S)

80

0

-80

1 10 1 k100 10 k 100 1 M


Ma

gn

itu

de

- d

B

TV(S)

Gvd(S)

A(S)

1 10 1 k100 10 k 100 1 M


180

0

-180

Ph

as

e -

de

g

Design Example

Select

Because ωz1, ωz2 are higher than half of the switching frequency, place the two high-frequency poles at0.5fs:

Set a crossover frequency fc (voltage loop) of 10 kHz – 20 kHz. Select K = 2500 to make fc≈ 15 kHz withabout 60° phase margin. Normally, a phase margin greater than 40° is desirable. The transfer function ofGvd, the compensator and the entire voltage loop gain Tv are shown in Figure 14.

Figure 14. Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain



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3.4 Check Loop Gains With Various Loads

3.4.1 Li-Ion Battery Equivalent Circuit Model

L C1RSER

Rhf R1 R2

C2

NOTE: R = 13.77 m , C = 0.337672 F, R = 47.15 m ,

C = 1.79935 F, R = 65.18 m , R = 5.8 , L = 0.637 H

1 1 2

2 SER hf

W W

W W m

3.4.2 CCM Loop Gains With Various Loads (Including Battery Load)

Design Example

Assuming R1_com = 200k, based on equations (48)–(52), the preliminary compensator component valuescan be determined as:

R1_com = 200kΩ, R2_com = 7.5kΩ, R3_com = 20kΩ, C1_com = 2000pF, C2_com = 130pF, C3_com = 51pF.

Figure 15 shows the typical Li-ion battery equivalent circuit model used for the small-signal analysis. lt isapproximately correct for charged state from 100% of SOC to 20% of SOC. Impedance varies frommanufacturer to manufacturer up to two times and from cell to cell up to ±15%. For a discharged statebelow 20% of SOC, the impedance starts to increase rapidly. The particular value the impedance reachesdepends on manufacturer, but it can be roughly modeling by multiplying R1 and R2 by 3.

NOTE: R1=13.77 mΩ, C1=0.337672 F, R2=47.15 mΩ, C2=1.79935 F, RSER= 65.18 mΩ, Rhf=5.8 Ω, L=0.637 µH

Figure 15. Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)

Plot the output-voltage loop gain, and check the stability and bandwidth with a 3s2p battery load, asshown in Figure 16.

Plot the charge-current and input-current loop gains, and check the stability and bandwidth. The entirecharge-current and input-current loop gains Tis and Tii are shown in Figure 17 and Figure 18, respectively.



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100

0

-1001 10 100 1 k 10 k 100 k 1 M

Z = 17.8L W

Z =2.25L W

Z = Zbat(s)L


Ma

gn

itu

de

- d

B

100

0

-100

Ph

as

e -

de

g

1 10 100 1 k 10 k 100 k 1 Mf - Frequency - Hz

(b) Phase

Z = 17.8L W

Z =2.25L W

Z = Zbat(s)L

Design Example

Figure 16. Output-Voltage Loop Gain TV (CCM)



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Design Example

Figure 17. Charge-Current Loop Gain Tis (CCM)



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100

0

-100

Ma

gn

itu

de

- d

B


(a) Gain

Z = 17.8L W

Z =2.25L W

Z = Zbat(s)L

180

0

-180

Ph

as

e -

de

g

Z = 17.8L W

Z =2.25L W

Z = Zbat(s)L


(b) Phase

Design Example

Figure 18. Input-Current Loop Gain Tii (CCM)



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3.5 Check Loop Gains Under DCM Condition

100

0

-100

Ma

gn

itu

de

- d

B


(a) Gain

I = 40 mA

Z =315

O

L W

I = 40 mA

Z = Zbat(s)O

L

I = 700 mA

Z = 17.8

O

L W

180

0

-180

Ma

gn

itu

de

- d

B

I = 40 mA

Z =315

O

L W

I = 40 mA

Z = Zbat(s)O

L

I = 700 mA

Z = 17.8

O

L W

10 100 1 k 10 k 100 k 1 Mf - Frequency - Hz

(a) Gain

1

Design Example

Plot the output-voltage and input-current loop gains, and check the stability and bandwidth. The entireoutput-voltage and input-current loop gains Tv and Tii are shown in Figure 19 and Figure 20, respectively.

Figure 19. Output-Voltage Loop Gain TV (DCM)



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I = 40 mA

Z =315

O

L W

I = 40 mA

Z = Zbat(s)O

L

I = 700 mA

Z = 17.8

O

L W

50

0

-100

Ma

gn

itu

de

- d

B


(a) Gain

180

0

-180

Ma

gn

itu

de

- d

B


(b) Phase

I = 40 mA

Z =315

O

L W

I = 40 mA

Z = Zbat(s)O

L

I = 700 mA

Z = 17.8

O

L W

4 Reference

Reference

Figure 20. Input-Current Loop Gain Tii (DCM)

From the transfer function Bode plots obtained, it is seen that this compensator design offers adequatephase margins and bandwidths for all three loops. If not, the parameters (K, ωz1_com, ωz2_com) can beadjusted to get a reasonable design.

1. R. W. Erickson, D. Maksimvić, Fundamentals of Power Electronics (Second Edition), Kluwer AcademicPublishers, Sixth Printing 2004.

2. Fred C. Lee, Modeling and Control Design of DC/DC Converters, CPES Lecture Notes, Virginia Tech,2004.



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Documents

Closed Loop Compensation of a Synchronous Switching Charger