Cmos Inverter Characterization

7/25/2019 Cmos Inverter Characterization

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CIRCUIT CHARACTERIZATION

AND PERFORMANCE

ESTIMATION CONTD

Prof. N.S.Murthy,

PPKKP/UNIMAP

[email protected]

02/09/1 1!M"2#1$NSM$09
mailto:[email protected]:[email protected]


2/54

"he %M&S In'erter( A )ir*t

+an-e

Vin Vout

CL

VDD


3/54

%M&S In'erter

Polysilicon

In Out

VDD

GND

PMOS2

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well


4/54

"o In'erter*

Connect in Metal

Share power and ground

Abut cells

VDD


5/54

%M&S In'erter

)ir*t&rder % Anay*i*

VOL= 0

VOH= VDDVM= f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp


6/54

%M&S In'erter oad %hara-teri*ti-*

IDn

Vout

Vin= 2.5

Vin

= 2

Vin

= 1.5

Vin

= 0

Vin

= 0.5

Vin

= 1

NMOS

Vin

= 0

Vin

= 0.5

Vin

= 1Vin= 1.5

Vin= 2

Vin

= 2.5

Vin= 1V

in= 1.5

PMOS


7/54

%M&S In'erter "%

Vout

Vin0 . 5 1 1 . 5 2 2 . 5

0.

5

1

1.

5

2

2.

5

NMOS res

PMOS off

NMOS sat

PMOS sat

NMOS off

PMOS res

NMOS sat

PMOS res

NMOS res

PMOS sat


8/54

eterminin3 I4and I

VOH

VOLVin

Vout

VM

VIL VIH

A simplifed approach


9/54

+ain a* a fun-tion of

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin(V)

Vout

(V)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vi(V)

Vout(V)

Gain=-1


10/54

Simuated "%

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin(V)

Vout(V

)


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Impa-t of Pro-e** ariation*

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5

Vin(V)

Vout(V

)

Good PMOSBad NMOS

Good NMOSBad PMOS

Nominal


12/54

Propa3ation

eay


13/54

%M&S In'erter Propa3ation eay

VDD

Vout

Vin= VDD

Ron

CL

tpHL= f(Ron.CL

= !."# RonCL

t

out

5on%

1

0.#

n60.#7

0.8


14/54

%M&S In'erter*

Polysilicon

InOut

Met$l%

VDD

GND

PMOS

NMOS

%.2&=2


15/54

0 0.5 1 1.5 2 2.5

-10

-0.5

0

0.5

1

1.5

2

2.5

3

t (sec)

Vout(V)

"ran*ient 5e*pon*e

tp= 0.69 CL

(Reqn+Reqp)/2

?

tpL tpL


16/54

e*i3n for Performan-e

Keep -apa-itan-e* *ma

In-rea*e tran*i*tor *i:e*

;at-h out for *efoadin30.2#m

A**ume that for WP> 2WN =2W

*ame puup and pudon -urrent*

appro?. eua re*i*tan-e* RN> RPappro?. eua ri*e tpLHand fa tpHLdeay*

Anay:e a* an 5% netor

WN

unit

Nunit

unit

PunitP RR

W

WR

W

WRR ==

=

11

tpHL= (ln 2) RNCL tpLH= (ln 2) RPCLeay 6D7(

2W

W

unit

unit

gin C

W

WC 3=oad for the ne?t *ta3e(


23/54

In'erter ith oad

oad 6CL7

eay

A**umption*( no oad B :ero deay

CL

tp= kRWCL

RW

RW

Wunit

> 1

ki* a -on*tant, eua to 0.9


24/54

In'erter ith oad

oad

eay

Cint CL

eay > kRW6CintC CL7 > kRWCintC kRWCL = kRW Cint61C CL/Cint7

= eay 6Interna7 C eay 6oad7

CN= Cunit

CP= 2Cunit

2W

W


25/54

!?ampe

CL= 8 C1

In &ut

C11 f f2

283 ==f

CL/C1ha* to De e'eny di*triDuted a-ro** N> 8 *ta3e*(


26/54

&ptimum NumDer of Sta3e*

)or a 3i'en oad, CLand 3i'en input -apa-itan-e Cin)ind optima *i:in3 f

f

FNCfCFC in

N

inL

ln

ln wit ===


27/54

Euffer e*i3n

1

1

1

1

F

G

G

G

G

G

2.F F

1

22.

N f tp

% "' "

2 ) %)

* ' %

' 2.) %.*


28/54

Poer

i**ipation


29/54

Hhere oe* Poer +o in %M&S=

+ D,n$&-. Po/e0 Con12&pt-on

+ S3o0t C-0.2-t C200ent1

+ Le$4$5e

C3$05-n5 $n6 D-1.3$05-n5 C$p$.-to01

S3o0t C-0.2-t P$t3 7et/een S2ppl, R$-l1 620-n5 S/-t.3-n5

Le$4-n5 6-o6e1 $n6 t0$n1-1to01


30/54

ynami- Poer i**ipation

Energy/transition = CL * Vdd

Power = Energy/transition *f = CL* Vdd* f

!eed to reduce CL" Vdd" andfto reduce power#

Vin Vout

CL

V!!

!ot a $unction o$ transistor si%es&


31/54

Modification for Circuits with Reduced Swing

CL

Vdd

Vdd

Vdd -Vt

E0 1 CL Vdd Vdd Vt( )=

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)


32/54

Short Circuit CurrentsShort Circuit Currents

Vin Vout

CL

Vdd

IVDD(

mA)

0.15

0.10

0.05

Vin(V)5.04.03.02.01.00.0


33/54

How to keep Short-Circuit Currents Low?How to keep Short-Circuit Currents Low?

Sort "ir"uit "urrent #oes to $ero if tfall%% trise&

'ut "ant !o tis for "as"a!e lo#i"& so ...


34/54

Minimizing Short-Circuit PowerMinimizing Short-Circuit Power

0 1 2 3 4 50

1

2

3

4

5

6

7

8

tsin/t

sout

Pnorm

V!! =1.5

V!! =2.5

V!! =3.3


35/54

LeakageLeakage

Vout

Vdd

Sub-ThresholdCurrent

Drain JunctionLeakage

SuDthre*hod -urrent one of mo*t -ompein3 i**ue*

in oener3y -ir-uit de*i3nene0$l S$l-n5

-6e$l &o6el 6-&en1-on1 $n6 Bolt$5e 1$le

to5et3e0 7, t3e 1$&e f$to0 S

&o1t o&&on &o6el nt-l 0eentl,

onl, 6-&en1-on1 1$le@ Bolt$5e1 0e&$-n on1t$nt

&o1t 0e$l-1t- fo0 to6$,1 1-t$t-on Bolt$5e1 $n6 6-&en1-on1 1$le /-t3 6-ffe0ent f$to01


49/54

e'i-e*


50/54

Pro-e**or S-ain3

P/Gelsin%er' Processors "or the Ne Milleni.m (SS22 300


51/54

Pro-e**or Poer



52/54

Pro-e**or Performan-e



53/54

2010 &utoo

Performan-e 2L/1 month*; 1 "IP 6terra in*tru-tion*/*7

; 80 +4: -o-

Si:e; No of tran*i*tor*( 2 Eiion; ie( G0G0 mm

Poer

; 10H


54/54

Some intere*tin3 ue*tion*

Hhat i -au*e thi* mode to Drea=

Hhen i it Drea=

Hi the mode 3raduay *o don=; Poer and poer den*ity

; eaa3e

; Pro-e** ariation

Documents

Cmos Inverter Characterization