Bill W. Haynes

Slide 1

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Common Design for Multiple Timing Applications Available PLD Based SERDES Devices Time to Digital Converter (TDC) w/ PLD Based SERDES Timing Distribution System (TDS) w/ PLD Based SERDES Other PLD Based SERDES Potential Applications

Simulation Results of TDC w/ 400ps Resolution

Prototype TDC/TDS Card Status

Simulation Only

Bill W. Haynes

Slide 2

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Available PLD Based SERDES Devices Cypress Programmable Serial Interface (PSI)

CPLD w/ a single channel 2.5Gbs SERDES device Cost ~ $140

CPLD w/ a quad channel 1.5Gbs SERDES device Cost ~ $200

Both devices in production

Xilinx-II Pro FPGA Up to 16-channel FPGA w/ 3.125 Gbs SERDES devices Not in production & Cost is UNK

Altera Stratix FPGA Up to 80-channel FPGA w/ 800 Mbs SERDES devices Not in production & Cost is UNK

Bill W. Haynes

Slide 3

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

High-Resolution TDC Block Diagram

DetectorOutput(CML)

156 MHzRef Clk

Serdes Control

16bit Data

FPGA/CPLD( Cypress / Xilinx )

SerialReceiver(Cypress

/ Xilinx)

General I/O

General I/O

Gen

eral

I/O

Bill W. Haynes

Slide 4

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Programmable TDC Features Resolution of 400ps (or better) is possible

Single channel Cypress PSI w/ 2.5 Gbs SERDES (in production) Multiple channel FPGAs planned by several vendors Single & Multiple channel dedicated SERDES

Available or Planned by several vendors

8 channel TDC at lower resolution (666 ps) 4-channel Cypress device (in production) 8-channel Cypress device (planned)

80 channels at lower resolution (1.25 ns) Altera Stratix FPGA

Not in production

Fully Programmable (VHDL) Backend Timing compensation Interface to external world (PCI, CPCI, etc.) Transmit TDC data over one of the serial links

Bill W. Haynes

Slide 5

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = FFFF F800 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps

Input Prop. Delay = 29.200075ns + T Ref Offset = 29.200075ns 105.6ns

FFFF

Bill W. Haynes

Slide 6

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 7FFF FC00 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 1 x 400ps = 400ps

Input Prop. Delay = 28.800075ns + T Ref Offset = 28.800075ns +400ps =

7FFF

29.200075ns

105.6ns

Bill W. Haynes

Slide 7

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 3FFF FE00 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 2 x 400ps = 800ps

Input Prop. Delay = 28.400075ns + T Ref Offset = 28.400075ns +800ps =

3FFF

29.200075ns

105.6ns

Bill W. Haynes

Slide 8

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0FFF FF80 0000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps

Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =

0FFF

29.200075ns

105.6ns

Bill W. Haynes

Slide 9

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0001 FFFF F000-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 15 x 400ps = 6000ps

Input Prop. Delay = 23.200075ns + T Ref Offset = 23.200075ns +6000ps =

0001

29.200075ns

105.6ns

Bill W. Haynes

Slide 10

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0000 FFFF F800-> 21bits x 6.4ns/16 = 21 x 400ps = 8.4ns Reference Counter Time = T Ref = 105.6ns + 6.4ns = 112.0 ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 0 x 400ps = 0ps

Input Prop. Delay = 29.200075ns + T Ref Offset = 29.200075ns +0ps =

FFFF

29.200075ns

112.0ns

Bill W. Haynes

Slide 11

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0000 0FFE 0000-> 11bits x 6.4ns/16 = 11 x 400ps = 4.4ns +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps

Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =

0FFE

29.200075ns

105.6ns

Bill W. Haynes

Slide 12

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0000 0E00 0000-> 3bits x 6.4ns/16 = 3 x 400ps = 1.2ns +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps

Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =

0E00

29.200075ns

105.6ns

1.0ns

Bill W. Haynes

Slide 13

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDC w/ 400ps Resolution Input Pulse Width = 0000 0800 0000-> 1bits x 6.4ns/16 = 1 x 400ps = 400ps +/-200ps Reference Counter Time = T Ref = 105.6ns + 0ns = 105.6 ns

T Ref Offset = # of 0 bits from T Ref x 400ps = 4 x 400ps = 1600ps

Input Prop. Delay = 27.600075ns + T Ref Offset = 27.600075ns +1600ps =

0800

29.200075ns

105.6ns

400ps

Bill W. Haynes

Slide 14

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Prototype TDC/TDS Card Status

4 –PCI Card w/ a 1.5Gbs Resolution TDC/TDS Design near completion PC board layout will start in March Prototype Testing in May/June Beam Testing in November Test Beam

Bill W. Haynes

Slide 15

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Timing (or Clock) Distribution System (TDS) Discussed at the CKM Ann Arbor Workshop Uses a 2-channel 2.5 Gbs Cypress device Can be converted to a high resolution TDC by:

Setting lock to reference rather than lock to data

Bill W. Haynes

Slide 16

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Timing (or Clock) Distribution System (TDS) The Far-End of the Cable is a Common Reference for all Receivers Reference can be Determined by: T = (Round Trip Time)/2 Or The Time from Incident Wave to the Reflected Wave Divided by Two

I-Wave

R-Wave

Round Trip Time = 2T

I-WaveR-Wave

TfarEnd= (TI-Wave – TR-Wave)/2

I-Wave

R-Wave

TfarEnd= (TI-Wave – TR-Wave)/2

TfarEnd= (TI-Wave – TR-Wave)/2

Bill W. Haynes

Slide 17

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

TDS Simpified Block Diagram

Bill W. Haynes

Slide 18

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Other PLD Based SERDES Potential Applications Data Links for DAQ Control & Monitoring Links

Bill W. Haynes

Slide 19

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

PCI Test Adapter (PTA)

Bill W. Haynes

Slide 20

February 26, 2002

CKM Precision Timing

CKM Workshop In San Luis Potosi, Mexico

Cypress CPLD