Compact Modeling of Carbon Nanotube Thin Film Transistors for Flexible Circuit Design

Leilai Shao1,4∗, Tsung-Ching Huang4, Ting Lei3, Zhenan Bao3, Raymond Beausoleil4, and Kwang-Ting Cheng1,2

1 Department of Electrical & Computer Engineering, University of California, Santa Barbara, CA, USA2School of Engineering, Hong Kong University of Science and Technology, Hong Kong, China

3 Department of Chemical Engineering, Stanford University, Stanford, CA, USA4 Hewlett Packard Labs, Palo Alto, CA, USA

∗lshao@ece.ucsb.edu

Abstract—Carbon nanotube thin film transistor (CNT-TFT) isa promising candidate for flexible electronics, because of its highcarrier mobility and great mechanical flexibility. An accurateand trustworthy device model for CNT-TFTs, however, is stillmissing. In this paper, we present a SPICE-compatible compactmodel for CNT-TFT circuit simulation and validate the proposedmodel based on fabricated CNT-TFTs and Pseudo-CMOS circuits[1][2]. The proposed CNT-TFT model enables circuit designersto explore design space by adjusting device parameters, supplyvoltages and transistor sizes to optimize the noise margin (NM)and power-delay product (PDP), which are the key merits forlarger scale CNT-TFT circuits. We further propose a designframework to effectively optimize the NM and PDP to facilitategreater automation of flexible circuit design based on CNT-TFTs.

Index Terms—Carbon nanotube, thin-film transistors, SPICE,Pseudo-CMOS, robust design, design automation.

I. INTRODUCTION

Carbon nanotube (CNT) random network is promisingfor high-performance flexible thin film transistors (TFTs),as shown in Fig. 1, because of its high carrier mobility(25 cm2/V s), mechanical flexibility, and solution-compatibleprocesses [3]. Recently developed CNT sorting methodologiesin [4][5] enable high-purity semiconducting CNTs and denseCNT networks, which leads to a higher carrier mobility andlower operation voltages. Comparisons among different TFTtechnologies are shown in Table I, which indicates that CNT-TFT is promising for high-performance low-power flexibleapplications [6][7][8]. In addition to merits of low-cost man-ufacturing such as low-temperature and solution-compatibleprocesses, CNT-TFT is recently emerging as an ideal candidatefor low-cost wearables and internet of things (IoT) nodes [9].1

While CNT-TFT is promising for a wide range of appli-cations, an accurate and yet simple compact model for CNT-TFTs is still missing. Previously reported analysis for CNT-TFTs [3] only focuses on the linear region and does not reflectmobility dependency on the gate voltage and contact effect atsource/drain terminals. For CNT random network, the chargetransport characteristic is dominated by tube-tube junctions[3][10]. Due to the complexity of the CNT random network,it is infeasible to model all tube-tube junctions using MonteCarlo simulations [11]. In this paper, we propose a compactmodel based on the measurement data and provide validationresults of the model with fabricated CNT-TFT devices as

1CNT TFT Verilog-A Model and Design Examples are available on Github:https://github.com/llshao/CNT-TFT-Verilog-A

TABLE I: Comparisons among different TFT technologies

Device Type(TFT)

AmorphousSi

Metal-Oxide

SAMOrganic

PolymerOrganic

CarbonNanotube

ProcessTemperature ∼ 250C ∼ 150C ∼ 100C

Roomtempera-ture

Roomtempera-ture

ProcessTechnology Lithography

Lithography/Roll-to-roll

Shadowmask Ink-jet

Solution/shadowmask/roll-to-roll

Feature Size(µm) ∼ 8 ∼ 2-5 ∼ 50 ∼ 50 ∼ 2-5

StableDevice Type N-type N-type P-type P-type P-type

Supply Volt-age (V) ∼ 20 ∼ 5 ∼ 2 ∼ 40 ∼ 1-2

Mobility(cm2/Vs) ∼ 1 ∼ 10 ∼ 0.5 ∼ 0.05 ∼ 25

1.6 1.8 2 2.2 2.4 2.6 2.8

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Si or glass substrateFlexible substrate

Al2O3

CNT active layer Metal-1

GateVia-1Metal-2

Interlayerdielectric

RandomNetwork

Fig. 1: Flexible CNT TFT Circuits [12].

well as Pseudo-CMOS logic circuits. The proposed model isimplemented in the Verilog-A language, and is compatiblewith SPICE to explore the design space for Pseudo-CMOScircuit implementations [1][2]. We plan to release this modelto allow designers to explore CNT-TFT based flexible circuitsand evaluate their potentials. The main contributions of thispaper are summarized as follows:

• Developing an accurate SPICE-compatible compactmodel for CNT-TFTs, which is thoroughly validatedusing transistor and circuit measurements

• Exploring the design space based on the developed modelto analyze the noise margin (NM) and power-delay prod-uct (PDP) for flexible circuit design

• Proposing an optimization framework, which enableseffective optimization of the NM and PDP for large-scaleCNT-TFT flexible circuits

The rest of this paper is organized as follows: Section IIprovides device details and model derivations for CNT-TFTs;

Section III elaborates CNT-TFT model validation againsttransistor and circuit measurements; Section IV analyzes CNT-TFT circuits and explores the design spaces for NM and PDPoptimization; Section V draws the conclusion.

II. COMPACT MODELING OF CNT-TFTA. CNT-TFT Properties

The cross section of the CNT-TFT is illustrated in Fig.1,where a bottom gate structure is used. The bottom gate struc-ture enables a denser CNT network for better performance.For TFT technologies, there is only either N or P type ofstable devices, as illustrated in Table I. CNT-TFTs usuallyexhibit P-type characteristics and the fabrication of stable N-type CNT-TFTs remains a longstanding challenge [13]. In ouranalysis, therefore, we focus on P-type CNT-TFTs and mono-type circuit design such as Pseudo-CMOS to accommodatematerial and device limitations of CNT-TFTs.

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)10-9

10-8

10-7

10-6

10-5

10-4

I S (A

)

Measured I-V Curve VD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

1

2

3

Gm

(S)

10-5

TransconductanceVD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

10

20

30

(cm

2 /Vs) Mobility=25.7cm2/Vs

VD=-0.5

Contact Degeneration

Contact Degeneration

Mobility Enhancement

Gm Enhancement

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)10-9

10-8

10-7

10-6

10-5

10-4

I S (A

)

Measured I-V Curve VD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

1

2

3

Gm

(S)

10-5

TransconductanceVD=-0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5

Vg(V)0

10

20

30

(cm

2 /Vs) Mobility=25.7cm2/Vs

VD=-0.5

Linear Region Sub-thresholdRegion

|𝑽𝑮𝑺 −𝑽𝒕𝒉| = 𝟏

Fig. 2: Measured CNT-TFT I-V curve and mobility dependency ongate voltages.

B. ObservationsTo investigate the effective mobility of the CNT-TFT, a

low source drain voltage (VS = 0V and VD = −0.5V )is chosen to make sure that the device is in the linearregion. The measured I-V curve is shown in the top partof Fig. 2. The bottom part of Fig. 2 shows the effectivemobility µeff , where the p-type MOSFET model is usedto perform its derivation: µeff = gmL/(WCoxVSD) andgm = ∂ISD/∂VSG = µeffCoxVSDW/L , where W isthe gate width, L is the gate length, Cox is the gate unitcapacitance, VSG is the source gate voltage and VSD is thesource drain voltage. Notice that the polarities of voltages andcurrents are opposite to those used in conventional N-typeanalysis. From Fig. 2, we observed that the effective mobilityµeff is enhanced as the VSG increases (with VS fixed andVG decreasing), when VSG is relative small. However, as VSGbecomes larger, µeff starts to degrade.C. Analysis and Assumptions

Similar mobility dependency phenomenon has been ob-served in OTFT and a-Si TFT [14], and the most acceptedtheories are based on charge drift in the presence of tail-distributed traps (TDTs) and variable range hopping (VRH)[10][15]. We therefore establish the CNT-TFT model based on

Fig. 3: CNT-TFT intrinsic model with contact resistances.

TDTs and VRH theories which, to be shown in the following,can well capture the behaviors of CNT-TFTs.

1) Mobility Enhancement: Both theories indicate the fieldenhancement of the mobility :

µ =

µ0(VG − Vth)γ , N-type TFTµ0(Vth − VG)γ , P-type TFT

(1)

, where Vth is the threshold voltage, γ is the field enhancementfactor for mobility and µ0 is defined as the effective mobilitywhen |VG − Vth| = 1, as illustrated in Fig. 2. This mobilityenhancement assumption explains the increase of the effectivemobility at a low VSG.

2) Contact Effect: The degeneration of mobility at highVSG can be explained by the contact resistances RS and RDat source/drain terminals, as shown in Fig. 3. These resistancesresult in effective source-gate voltage/source-drain voltagedrops: VSG = VSG−RS ISD, VSD = VSD−(RS+RD)ISD =VSD − RC ISD, where RC = RS + RD and the currentwith contact effect is denoted as ISD. The derivations arenot presented here for simplicity and the contact effect canbe illustrated as follows:

ISD ≈WCoxµ

L1 + kRC(Vth + VSG)(Vth + VSG)−

1

2VSDVSD

(2)

ISDISD

≈ µ

µ=

1

1 + kRC(Vth + VSG); k =

W

LCoxµ (3)

From Eq. (3), we can conclude that contact resistances lead toa mobility reduction with a factor of 1/(1+kRC(Vth+VSG))and it becomes more significant as VSG increases, whichexplains the degeneration of the effective mobility with a highVSG as shown in Fig. 2.

D. Model Derivations

We first establish the intrinsic current model based on themobility enhancement assumption, then extend the model tocapture parasitics and second order effects.

1) Intrinsic Current Model: We therefore integrate themobility enhancement assumption Eq. (6) into the p typecharge drift model Eqs. (4)-(5) to derive the intrinsic currentmodel inspired by [14]:

ISD(x) = QCH(x)v; v = ueff∂V (x)

∂x(4)

QCH(x) =WCox(Vth − VG + V (x)) (5)ueff = µ0(Vth − VG + V (x))γ (6)

Since the current is constant in the channel [16], integratingalong the channel

∫ x=Lx=0

ISD(x)dx yields:

ISD =k

(γ + 2)(Vth − VGS)γ+2 − (Vth − VGD)γ+2 (7)

where k is defined as WCoxµ0

L . Similar to MOSFET, we divideEq. (7) into two regions: 1) linear region, and 2) saturationregion. Applying the Taylor expansion and keep the first andsecond order terms, we can then simplify the formula as:

ISD ≈

k′(Vth − VGS)− 1+γ

2VSDVSD, VDS > VGT

k′

(γ+2)(Vth − VGS)2, VDS ≤ VGT

(8)

k′ = k(Vth − VGS)γ ; VGT = VGS − Vth (9)

Notice that Eq. (8) becomes a conventional MOSFET modelwhen γ = 0. This is because the main difference between theCNT-TFT intrinsic model, Eq. (7) and the MOSFET modelis the mobility enhancement dependency on the gate voltage.This inherent connection between Eq. (7) and the MOSFETmodel leads to a major advantage: we can readily includesecond-order effects, such as channel length modulation, intoEq. (7) taking advantage of mature MOSFET theories.

2) Extending the Intrinsic Model: To further enrich thecapability of the CNT-TFT intrinsic model, we incorporatethe channel length modulation 1 + λVSD into Eq. (7) andthe limiting function flim(VG, V ) is added to provide smoothtransitions between the sub-threhold region and the above-threshold region [16] :

ISD =k

γ + 2(f(VG, VS)

γ+2 − f(VG, VD)γ+2)(1 + λVSD) (10)

flim(VG, V ) = SS ln[1 + exp(Vth − VG + V

SS)] (11)

where λ is the channel length modulation factor and SS isrelated to the sub-threshold slope. We also summarize thesimplified analytical model in Table II, which can be usedto analyze CNT-TFT based circuits and provide more designintuitions.

TABLE II: Simplified Analytical Model for CNT-TFTs

VGS ≤ Vth VGS > Vth

VDS ≤ VGT k′

(γ+2)(Vth − VGS)2 k

(γ+2)(SS exp(Vth−VGS

SS))γ+2

−(SS exp(Vth−VGDSS

))γ+2VDS > VGT k′(Vth − VGS)VSD − k′

(γ+2)(Vth − VGD)2

− 1+γ2V 2SD

3) Contact Resistance and Gate Capacitance: We add twoseries resistances RS and RD to account for the contact effectas shown in Fig. 3. Two lumped capacitors CGS and CGDare added as well to characterize the transient behavior of theCNT-TFT circuits. Due to the large device sizes (hundredsof µm scale), two lumped capacitors are sufficient accurateto capture the transient responses of CNT-TFT circuits. Gatesource/drain parasitic capacitors CGSO and CGDO are alsoincluded to improve the accuracy.

CGS = CGCS + CGSO; CGD = CGCD + CGDO; (12)CGSO = CGDO = CoxWLov; (13)

CGCD = ∂QCH/∂VGD ≈1/2CoxWL Linear0 Saturation/Cutoff

(14)

CGCS = ∂QCH/∂VGS ≈

1/2CoxWL Linear2/3CoxWL Saturation0 Cutoff

(15)

where Lov is the gate source/drain overlap. CGCS and CGCDare implemented as voltage controlled capacitors in Verilog-A. The final equivalent circuit model is shown in Fig. 3 and

all equations can be implemented in Verilog-A for the SPICEsimulation.

III. MODEL VALIDATIONIn this section, we compare the SPICE CNT-TFT simulation

results with measured source-drain current versus gate voltages(I-V) curves, Pseudo-CMOS inverters’ voltage transfer curves(VTCs) and ring-oscillator’s transient waveforms.

A. Device Validation

-2 -1 0 1VGS

10-10

10-8

10-6

10-4

I SD (A

)

Transfer Curve VS=0V, VD=-0.5V

MeasureModel

-2 -1 0 1 2

VGS

-2

0

2

4

6

I SD (A

)

10-5

MeasureModel

-2 -1 0 1VGS

10-7

10-6

10-5

10-4

g m (S

)

gm Transconductance

MeasureModel

-2 -1 0 1 2VGS

0

1

2

3

g m (S

)

10-5

MeasureModel

Fig. 4: Model validation for I − V and transconductance curves.

1) I-V Validation: We first examined the proposed modelwith the measured I-V and transconductance curves. Bothlinear and logarithmic scales are shown in Fig. 4. The modelprediction well matches the device measurement reflectingboth the mobility enhancement and contact resistance causeddegeneration as shown in the Fig. 4. A wide range of VGS ∈[−2, 0]V and VDS ∈ [−4, 0]V , covering sub-threshold, linearand saturation, are investigated, as illustrated in Fig. 5. Theexcellent match between model predictions and measurementdata further confirm the validity of the above-mentioned modelderivations and assumptions.

-2 -1.5 -1 -0.5 0VGS

0

0.5

1

1.5

2

2.5

-ID

(A)

10-4

VDS = 0, -0.5, ..., -4V

MeasurementsModel

-2 -1.5 -1 -0.5 0VDS

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-ID

(A)

10-4

VGS = 0, -0.5, ..., -2V

MeasurementsModel

Fig. 5: Model validation for I − V curves.

2) Parameter Extraction: We extract model parameters outof 52 fabricated CNT-TFTs, where a Gaussian distribution isassumed for process variations. All extracted parameters aresummarized in Table III, where the mean value µ and standarddeviation σ are provided.

TABLE III: Parameters extracted from 52 fabricated CNT-TFTs

Model Parameter Notation [µ, σ] UnitChannel Length L [25, -] umChannel Width W [125, -] um

Gate S/D Overlap Lov [10, -] umGate Unit Capacitance Cox [200, -] nF/cm2

Threshold voltage Vth [0.5, 0.102] VSub-threshold Swing SS [0.28, 0.0388] V/dec

Effective Mobility µ0 [25.69, 0.19] cm2/V sContact Resistance RC [1531, 291] Ω

Channel Length Modulation λ [0.064, 0.0185] V −1

Factor of Gate Dependent mobility γ [0.20, 0.116] (-)

B. Circuits Validation

Beside single devices, the model must be able to predict thecircuit level behaviors with a sufficient accuracy. We thereforecompare the SPICE simulation results with the measuredvoltage transfer curves (VTC) and ring-oscillator’s waveform.

1) Introduction to Pseudo-CMOS: Pseudo-CMOS is a de-sign style proposed to address design challenges of mono-type TFT circuit design [1][2], which has been proven arobust design style and has been widely used for flexibledigital, analog, and power circuits [17][18][19]. Comparedto conventional mono-type digital design styles, such as thediode-load or resistive-load designs, Pseudo-CMOS offersbetter noise margin and provides post-fabrication tunabilityat the cost of an additional power rail VSS . There are twotopologies of Pseudo-CMOS: depletion (Pseudo-D) type andenhancement (Pseudo-E) type. We focus on the Pseudo-Dtype since it is more suitable for our depletion devices [2].A Pseudo-D inverter consists of three power rails, VDD, VSSand GND, and four transistors M1−4, as shown in Fig. 6.

Stage1 Stage2VSS

VDD

GND

VOUT

VINM1

M2

M3

M4

VIM

Fig. 6: Pseudo-D inverter.

𝑽𝑰𝑵 = 𝑽𝑶𝑼𝑻

(𝑽𝑺𝑷, 𝑽𝑫𝑫/𝟐)

(𝑽𝑰𝑯,𝑽𝑶𝑳)

Output, V

Input, V

(𝑽𝑰𝑳,𝑽𝑶𝑯)

Fig. 7: Typical VTC.

2) VTC Validation: A typical voltage transfer curve (VTC)of an inverter is shown in Fig. 7 and here we focus onVSP , VI/OH and VI/OL, which determine the noise margin(NM) for digital circuits. In Fig. 8 (Left), we compare theSPICE simulated voltage transfer curves (VTCs) and smallsignal gain with actual measurements, where solid lines areSPICE simulations and dots are measurements. Both VTC andsmall signal gain simulations match closely with the circuitmeasurements over a wide range of supply voltages VDD,from 0.8V to 1.6V. Despite minor discrepancies in low supplyvoltages, the proposed model accurately predicts the VSP ,VI/OH and VI/OL. Furthermore, Monte Carlo simulation isperformed to illustrate various VTCs under process variations,based on extracted device parameters as shown in Table III.From Fig. 8 (Right), we can see that the SPICE simulationcan accurately predict the variation of the VSP of the VTCs,where bold lines are simulation results using the mean valuesin Table III.

3) Transient Validation: We validated our transient modelusing the Pseudo-D based five-stage ring-oscillator’s measuredwaveform. As shown in Fig. (9), the SPICE simulation resultwell captures the oscillation frequency and the amplitudecompared with the measurement data.

In summary, the results of both DC and transient simula-tions indicate that the proposed SPICE CNT-TFT model canaccurately predict both device and circuit level behaviors.

0 0.5 1 1.5Vin (V)

0

0.5

1

1.5

V out (V

)

0 0.5 1 1.5Vin (V)

0

50

100

150

200

Gai

n

Sim 0.8VSim 1VSim 1.2VSim 1.8Vdd 1.6VVdd 1.2VVdd 1VVdd 0.8V

0 0.5 1 1.5Vin (V)

0

0.5

1

1.5

Vou

t (V)

Monte Carlo Simulation

0 0.5 1 1.5Vin (V)

0

0.5

1

1.5

V out (V

)

𝝈

Fig. 8: Left: Measured and simulated VTCs and small signal gains;Right: 26 measured VTCs and Monte Carlo simulation.

0 20 40 60 80 100Time( S)

0

1

2

3

V out(V

)

Measurement

0 20 40 60 80 100Time( S)

0

1

2

3

V out(V

)

SPICE Simulation

Fig. 9: Ring-oscillator. Fig. 10: Load Capacitance.

IV. NOISE MARGIN, POWER-DELAY ANALYSIS ANDDESIGN EXPLORATION

To further enable large-scale flexible circuit design, wethoroughly analyze the key merits for digital circuits, includ-ing NM, power and delay, and develop a systematic designmethodology to facilitate design automation for CNT-TFTflexible circuits. In this section, we first analyze how deviceparameters, transistor sizes and supply voltages affect NM andPDP for Pseudo-D digital circuits. Based on insights derivedfrom this analysis, we propose a design framework to optimizethe NM and PDP.

A. Noise Margin Analysis

A Pseudo-D inverter consists of two stages, as illustratedin Fig. 6. Since the first stage dominates the overall inverterVTC, for simplicity our NM analysis focuses on the first stage.

a) Derivation: A typical VTC of an inverter is shownin Fig. 7 and the NM is defined as NM = min(VOH −VIH , VIL − VOL). We use the following approximations tosimply the derivations: 1) VOH ≈ VDD, VOL ≈ GND;2) VIH/L ≈ VSP ± VDD

2Gain ≈ VSP . Such simplifications arereasonable resulting in negligible errors. As shown in Fig. 8,the VTCs are almost rail to rail and the gains are very high(≥ 50) even with a VDD at 0.8V , which leads to a negligibleVDD

2Gain . Therefor, the simplified analytical NM model can beexpressed as:

NM = min(VOH − VIH , VIL − VOL)≈ min(VDD − VSP , VSP )

(16)

VSP = VDD + Vth(1−γ+2 √α), α =W2/W1. (17)

(VDD − VSS)/2 ≥γ+2 √αVth; (18)

where α =W2/W1 is the transistor size ratio of M2/M1 andVSP is derived through the current equivalent at the switchingpoint using the saturation model in Table II. Eq. (18) ensuresthat M1/2 are in the saturation region at VSP . Compared to themean value of 26 measured VTCs, the analytical NM modelcan predict the NM for Pseudo-D inverters within an error≤ 6.25%VDD even at a low supply voltage VDD = 0.8V .

0 5 10 15 20Ratio

0

0.2

0.4

0.6

0.8

1

NM

(V)

NM (V) V th=0.5 VSS=-2

VDD=1VDD=1.5VDD=2

Fig. 11: NM vs. Ratio α.

0.8 1 1.2 1.4 1.6 1.8 2VDD (V)

0

5

10

15

20

25

30

Rat

io

Optimal ratio V SS=-2

Vth=0.3Vth=0.4Vth=0.5Vth=0.6

Fig. 12: Optimal α.

b) Analysis: In Figs. 11 and 12, we analyze the relation-ship among NM, transistor sizes, Vth and supply voltages. Thesimulation results show that: 1) properly adjusting transistorsizes can effectively improve the NM ; 2) an optimal ratio αoptto assure the maximum NM can be accurately predicted byEq. (19) which is determined by the ratio of VDD/Vth; 3) themaximum achievable NM is slightly less than VDD/2 due tothe imperfect VOL/H . To ensure VOL ≈ 0 and VOH ≈ VDD,the constraints for VDD and VSS are given in Eq. (20).Simulation results further confirm our analysis results, whereVDD − VOH ≤ 0.05V and VOL ≤ 0.05V with Eq. (20) beingsatisfied.

αopt = (1 +VDD2Vth

)γ+2 (19)

VDD−VOH≈0VOL≈0 ⇔ VDD≥2Vth

−VSS≥2Vth(20)

B. Power and Delay (P&D) Analysis

In this section, we analyze the trade-offs among power,delay and NM for Pseudo-D circuits [20]. According to [2],we use the following default transistor sizes: W1 = Wmin =5µm, W2 = W3 = W4 = 15µm in the analysis. And, wedefine tp0 as the propagation delay of a Pseudo-D inverterwith these default sizes.

a) Power Analysis: For the total power Ptot, it consistsof two parts: static power Pstat and dynamic power Pdyn. Weignore the direct path power dissipation during switching Pdp,which is negligible comparing to Pstat and Pdyn.

Ptot ≈ Pstat + Pdyn; ki =WiCoxµ0

L(21)

Pstat ≈

Output High︷ ︸︸ ︷DH2V γ+2th k2(VDD − VSS) + k4VDD

+

Output Low︷ ︸︸ ︷DL2V γ+2th k1(VDD − VSS) + k3VDD

(22)

Pdyn ≈ f

Stage1︷ ︸︸ ︷CL,1(VDD − VSS)2 +

Stage2︷ ︸︸ ︷CL,2(VDD)

2 (23)

where f is the frequency, DL/H ≈ 1/2 is the fraction of theduration when output is low/high in each period and CL,1/2is the equivalent load capacitance at node VIM/VOUT , asindicated in Fig. 10. To improve accuracy, Miller effects areincorporated as well:

CL,1 =

Miller Effect︷ ︸︸ ︷2CGDO,1 +CGDO,2 + CG,4;CL,2 =

Miller Effect︷ ︸︸ ︷2CGDO,3 +CG,1 + CG,3

(24)CG ≈ CGSO + CGDO + 2/3CoxWL (25)

Since CNT-TFTs are in the depletion model, the leakagecurrent Ileak ∝ V γ+2

th is determined by Vth, which dominatesthe static power. The dynamic power is a function of thefrequency, supply voltage and total capacitance [21].

b) Delay Analysis: For the propagation delay tp, we usethe equivalent RC approximation [20]:

tp =0.69

2

Stage1︷ ︸︸ ︷CL,1(Req,1 +Req,2)+

Stage2︷ ︸︸ ︷CL,2(Req,3 +Req,4) (26)

Req,1 ≈3

4k1

VDD − VSS(VDD + Vth)2+γ

; Req,2 ≈3

4k2

VDD

V γ+2th

(27)

By setting the k1 to k3/4 and VSS = 0 in Req,M1, we canget Req,M3/4. Notice that Req,M1/3/4 decreases as the supplyvoltage VDD increases; however, Req,M2 behaves opposite.This is because zero-Vgs connection will limit the current to asmall value (IM,2 = k2V

γ+2th ) during switching, leading to a

large equivalent resistance. This also confirms the validity ofignoring Pdp.

1 1.5 2 2.5 3VDD (V)

1.6

1.8

2

2.2

2.4

2.6

2.8

3

Prop

agat

ion

Del

ay (s

)

10-6

0

1

2

3

4

5

6

Pow

er (W

)

10-6

W1 = 5 m, W2,3,4 =15 m, f=1/(4tp0)

VSS 0 to -2V

Fig. 13: VDD vs. P&D.

0.5 1 1.5 2VDD (V)

0

20

40

60

80

100

120

Nor

mal

ized

Req

W1 = 5 m, W2 =5 m, VSS=0 VReq,M1 Vth=0.2

Req,M1 Vth=0.3Req,M1 Vth=0.5

Req,M2 Vth=0.2Req,M2 Vth=0.3

Req,M2 Vth=0.5

Req,M2

>10XReq,M1

Fig. 14: VDD vs. Req .c) Design Space Exploration: First, we investigate how

supply voltages affect the delay and power. We observed thatsimply increase the VDD cannot improve the propagationdelay as shown in Fig. 13, which is counter-intuitive toconventional wisdom. This is because Req,M2 increases asthe supply voltage and Req,M2 is much larger (∼ 10X) thanReq,M1/3/4, as shown in Fig. 14, preventing from furtherimproving of the stage delay. As a result, the delay increasesas VDD becomes higher, due to the dominant Req,M2. This

0 20 40 60 80 100W2 ( m)

4

6

8

10

12

14

16PD

P (p

J)

0

0.2

0.4

0.6

0.8

1

NM

(V)

W1=5 m, W3=W4=15 m, VDD=2 V

VSS 0 to -2V

Fig. 15: W2 vs. PDP and NM .

0 20 40 60 80 100W2 ( m)

1

2

3

4

5

Prop

agat

ion

Del

ay (s

)

10-6

0

0.2

0.4

0.6

0.8

1

Pow

er (W

)

10-5

W1=5 m, W3=W4=15 m, VDD=2 V

VSS 0 to -2V

Fig. 16: W2 vs. P&D.

phenomenon indicates that Pseudo-D is more suitable for lowvoltage design, which can benefit from a better PDP . ForVSS , a large negative VSS will increase the delay and power;however, it leads to a better NM as illustrated in Fig. 15.

After identifying Req,M2 as a critical part for power anddelay, we analyze the impact of W2 on power, delay and NM .We observed that W2 can be used to explore the trade-offbetween power and delay as show in in Fig. 16. A larger W2

can lead to a smaller delay but higher power consumption.Furthermore, W2 will also affect the NM , as shown in Fig.15, and the optimal values of W2 for NM and PDP aredifferent. Thus, trade-off between NM and PDP should beevaluated during the circuit design stage.

C. NM and PDP OptimizationBased on the analysis in Section IV-B, we conclude that

supply voltages and transistor sizes influence the PDP sig-nificantly for Pseudo-D circuits. Furthermore, to assure a goodNM, transistor sizes and supply voltages have to satisfy certainconstraints stated in Section IV-A. Hence, we can formulate aconstrained optimization problem to optimize the PDP whilemeeting the NM requirement for Pseudo-D circuits:

minimize PDP (W1−4, VSS) given NM0, Vth, VDD

subject to min(VDD − VSP , VSP ) ≥ NM0 ⇔ Eq. (16)(VDD − VSS)/2 ≥γ+2

√αVth; ⇔ Eq. (18)

VDD − VOH ≤ δ, VOL ≤ δ; ⇔ Eq. (20)Wi ≥Wmin = 5 µm

The above optimization determines transistor sizes and VSSgiven specific NM0, Vth and VDD. Using Lagrange multipli-ers and gradient decent, we can solve the above constrainedoptimization and optimized results for different NM0 aresummarized in Table IV. Compared to the default design inFig. 15, the optimized results show ∼ 3X improvement forPDP with the same NM = 0.3 V and supply voltages.Considering Vth and VDD as design parameters, we canachieve ∼ 6X improvement with device and circuit co-optimization. Although our exemplar formulation above usesthe PDP as the optimization target, it can be easily modifiedfor power or delay optimization. In summary, this proposeddesign framework can effectively optimize the PDP (or justpower or delay) while satisfying the NM specification.TABLE IV: Pseudo-D Optimization VDD = 2 V , Vth = 0.5 V ,δ = 0.05

NM0 W1 W2 W3 W4 VSS PDP0.3V 5.0µm 19.4µm 5.0µm 5.0µm -1.00V 1.97pJ0.5V 5.0µm 27.4µm 5.0µm 5.0µm -0.97V 2.03pJ0.8V 5.0µm 44.0µm 5.2µm 5.4µm -0.76V 2.24pJ

V. CONCLUSION

In this paper, we present a SPICE-compatible CNT-TFTmodel to support CNT-TFT flexible circuit design. The modelhas been derived and validated based on 52 fabricated CNT-TFTs and 26 Pseudo-D inverters. Based on the proposedmodel, we further analyze how device parameters, supplyvoltages and transistor sizes affect the NM and PDP of Pseudo-D circuits. Finally, a constrained optimization procedure isproposed to optimize the PDP while meeting the NM specifi-cation. The proposed optimization methodology can be easilyextended to more complicated logic gates and library cells,which can further enable greater automation of large-scaleflexible circuit design based on CNT TFTs.

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